Apple J2 Schematics
820-2996-11-BOT MLB 0908
C5708
R5700
L5763
C3803
R8216
L5762
DZ5752
C5760
C5753
R5753
R3700
C3750
C3712
R3712
C3751
C3711
R3711
R3701
R3702
C3702
C3701
C3713
R3713
U3700U3710
C3752
C3753
C3703
R3703
C21
L6
L7
J1
L9
R3
C11
C5703
R5740
DZ5712
C5712
D5703
DZ5710
C3801
L5760
L5716
R3800
R3801
C5710
L5761
C5711
DZ5711
C3802
C6
C89
L2
C5
L43
U3
C45
C69
C4
C41
L23
FL1
C38
C20C18
L5
C76
FL10
C84
L22
C75
FL5707
D5700 D5701
L5700
C5802
L24
C44
L17
C39
U9
C73
C5707
C5706
R5905
R5904
R5916
FL5711
U5700
R5917
R5908
FL5708
C5701 C5700
C5705
C5702
R5909
D5702
L5701
C5804
C5805
C5803
C43
C42
R14
R15
R2
U6
L15
L20
L16
C32
C34
R13
C36
R7
U10
L12
L21
C35 C83
C72
C71
L5702
C5811
R5907
C5810
R5906
C5766
DZ5790
FL5750
C5765
DZ5751
DZ5750
C5754
C5755
R5823
C5752
R5751
R5820
DZ5753
R5750
R5720
R5721
C5806
C5807
L5714
C5751
C5782
R5911
R5910
R5900
R5730
R5901
R5914
C5808
R5912
R5913
C5809
R5915
R5731
R5902
R5903
Q8104
R31
C67
C68
C66
C64
FL8
L14
R29
C74
FL7
C50
C3
R33
C65
C63
U4
C37
C85
C33
L10
L11
C60
C61
L46
C87
C7
U1
C8
C77
C10
R10
C46
R9
C47
C62
Y1
R35
C82
C86
R32
FL9
R34
R11
R4
R12
R76
R27
R26
C81
U8
C80
R28
R8100
C8170
C8101
C8171
C8100
R8116
R8130
DZ8120
C8141
C8281
C8282
R8222
C5780
C8221
C8223
C8217
C8215
C8206
C8140
C8137
C8138
C8156
C8220
C8131
C8158
C8159
C8139
R8219
DZ5720
R5710
C8163
C8207
R8260
C8266
C8201
C8251
C8210
D8230
C8267
R8270
R8262
R8269
C8172
C8151
C8240
C8238
C8145
C8148
R8240
R8231
R8235
C8152
R8265
R8227
R8232
R8261
R8257
R8239
R9001
C8164
C8162
C8157
R8173
R8172
C8161
C8135
C8209
C8214
R5752
C8212
C8130
C8153
C8147
C8149
C8204
C8169
R8203
C8160
C8136
C8146
C8167
C8150
C8168
C8144
U1600
C1193
R1620
C1652
R1652
C1190
C1022
C1661
R1651
C0934
R0911
C0932
C0933
C0930
C0927
C1251
R1251
C1250
R1250
C0924
C0909
C0960
C1184
R0957
C1135
C1138
C0957
C1103C1117C1121
C1100
R0921
C0931
C0923
C0910
C1102
C0950
R0910
C0926
R0920
R1253
C1176
C0935
R1252
C0961
FL0600
C0925
C0621
C0903
R0612
C0622
C1199
C0908
C0620
C1197
C1196
C0632
C0633
C0956
C0608
C0952
FL0910
C0631
R0955
C0951
R0956
R1261
R0609
DZ0600
C1710
C1020
R1020
R1621
R1606
C1650
R1605
C1660
C1191
C1195
C1021
R1720
R10234
R1751
C1761
C1752
R1752
C1194
C0953
U1700
R2211
R2205
C1107
C1750
R1706
C1132
C1131
C1124
R8218
C1136
C1137
C1126
C1111
C1108
C1150
C1159
C1161
C1105
R1206
C1129
R1204
R1205
C1143
C1122
C1162
C1125
C1160
C1106C0612
C1110
C1140
C1181
C0635
C0630
C0604
C0615
R0605
R0606
R0607
C1163
C1166
C1133
C1141
C1104
C1164
C1152
C1134
C1109
C1165
C1156
C1130
C1198
C0614
C0609
C0634
C0603
C1172
R0613
C0607
C0601
C0602
C0600
R0601
R0603
R0604
R0602
R1030
C1760
R1180
C1023
R1209
C1154 C1153 C1155 C1158
C1188
C1151
R1207
C1174
C1173
C1170
C1171
R0834
R0831
R0832
R1705
R0715
R1202
R0712
C1146
C1182
C1144
R1203
R0701
C1177
R0930
R0931
R0720
R0900
C0907
R0621
R1260
R1210
C1183
R0608
C1142
C1145
C1175
R1100
R1101
R0836
C1715
R9000
R0713
R1201
R0714
R1200
R0722
R0731
R0933
R0932
R0730
R0885
R0704
R0703
R1211
R0940
R0700
R0622
R0620
R0652
C0640
R0643
R0642
R0641
R0640
C1413
C1412
C1400
C1405
C1402
C1404
C1422
R1401
R1400
C1411
C1433
C1430
C3053
R3066
C3005
C1450
C1451
C1414
R1455
C1425
C3007
C1410
C1401
C1406
R3025
U3009 U3010
C1432
C3050
R1452
C3006
U3007
C3041
R1454
R3033
R1453
C3031
C3030
C3112
C3110
C3111
C3109
C3108
C3106
R3030
R3101
R3031
U3101
R3107
C3191
C3192
R3190
R3173
R3160
C3107
U3100
U3003
C1470
R1475
C1434
C1471
C1431
R0801
R0803
C1426
C1424
C1421
R3180
R3171
C1420
C3105
R0813
R1473
R0811
R0812
R0800
R3120
R3032
R0810
R3604
R1474
R3605
R0802
C4213
C4211
R0702
R4212
R4213
R1472
R3621
R3608
C4217
C3609
C3611
U3600
C3616
C3604
C3603
C3607
C3615
C3608
R3071
R3070
C3070
L4308
L4302
FL7500
R7541
C3613
C3614
R3603
R3601
R3602
C3601
C3602
R4312
C3600
C4310
C3605
C3617
C3618
R3850
R3851
C3606
C3852
C3853
C3854
C3851
C3850
R5510
R5511
L4303
L4306
L4304
L4307
L4301
U5600
L5500
R5513
C7523
C7522
L2200
R4204
C4202
C4201
R4201
R4205
L5501
R5512
U5500
C7524
C7525
C2233
C2253
L2210
C2220
C2270
R4203
R4202
U4200
C4216
C4212
C4200
L5601
R5613
R5612
U5502 U5601
C2249
C2247
C2248
C2246
R2287
R2284
R2283
R2286
R2285
C2203
C2204
Q2200
R2250
R2204
R2210
C2240
R2203
C2230
C2241
C5500
C2202
R5602
R5600
R4210
R4211
R5621
C5501
R5603
R5601
R5501
U5501U5503
R2242
C2245
C2243
C2244
C2242
R2281
R2282
R2280
L2212 L2222 L2232 L2202
R2240
C2206
L2242
R2241
C2250
C2251
C2232
L2201
L5612
C5615
R2290
C5616
C5623
C5614
R0706
R0705
R8282
C5602
L5610
R6100
L5600 L5620
R5611
R5610
R5620
C5601
R6101
C563
C6100
L5611
R5502
C5612
C5620
C5613
L5613
C5617
C5621
C5618
J6000
J7500
U1410
J2200
C3101
C3102
R3181
R3155
J5400 J5401 J3011J3010
820-2996-11-TOP MLB 0908
DZ5760
C5783
C5722
C5750
C5721
R5790
L5757
C8124
L8112
D8100
C8236
L8255
C1
L1
C2
C55
C70C58
35C 87C
C59
R5
R8280
C49
C57
C79
FL2
R1
C48
R16
C17
C29
C54
C56
C52
FL6
FL4
C8165
C8125
L8229
C8237
C8264
C8263
C8226
J5900
LED9000
R9002
C3714
J3700
C3704
L3700
C3700
J2
C8143
C8117
C8118
L8105
L8100
C8154
L8115
L8116
C8122
C8121
L8225
Q8123
L8121
U8100
C8235
C8233
C8232
C8155
L8119
D8228
D8258
C8265
C8234
C8262
C8107
Q2201
C1705
C1727
C1714
U1400
C3103
C3104
R8281
C3008
R3009
C1723
C1707
C1703
R1022
R1721
C1729 C1728
R1208
R0708
R0710
R0711
C3000
D3000
L3000
C3001
C3009
U3000
C3002
R3012
C1720
C1721
C1701
C1763
R1755
C1724
R1095
C1095
R0709
C1702
C1706
C1762
R1753
C1726
R1754
C1754
C1731
C1733
R1756
C1756
C1719
C1735
C1730
C1718
C1708
C1734
C1096
R1096
U5730
C5730
C1716
C1717
C1732
C1722
R5796
R5795
R1083
C1711
C1713
C1712
C1725
C1709
R1084
C1084
C1704
C0650
R0650
R0651
C0651
Y0602
R0804
C1628C1629
C1624
C1058
R1055
C1085
C1634
C1608
C1618
C1056
R1056
U0600
C1614
C1627
C1615
C1607
C1610
C1623
C1603
C1663
R1655
C1621
C1633
R1656
C1635
C1619
C1630
C1631
C1656
R1653
C1662
C1654
R1654
C1632
C1622
C1604
C1625
C1612
C1609
C1613
C1611
C1054
R1054
C1101
C1123
C1157
C0955
R0950
R1212
C1601
C1620
L8110
C1605
C8102
C1626
C1606
C1602
C1192
C1616 C1617
R1053
C1057
R1021
C8120
C8119
R1213
R1214
R1360
R1361
R1362
C1370
U1300
R1320
R1372
R1315
C1300
C1301
C8108
L8107
C8103
L8101
L8128
C8142
Y8138
C8166
C8256
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PROPRIETARY PROPERTY OF APPLE INC.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
DESCRIPTION OF REVISION
CK
APPD
21
1245678
B
D
6543
C
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
THE INFORMATION CONTAINED HEREIN IS THE
C
A
D
DATE
R
SHEET
Apple Inc.
THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING TITLE
D
SIZE
REVISION
DRAWING NUMBER
BRANCH
REV ECN
7
B
3
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
IV ALL RIGHTS RESERVED
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
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J2 MLB - DVT OK2FAB
Schematic / PCB #’s
1 OF 48
2011-09-06
ENGINEERING RELEASED
1 OF 157
10.0.0
051-8773
10
0001231154
LAST_MODIFIED=Tue Sep 6 17:35:11 2011
X26_WIFI_MIKE_BT 09/01/2011
61
31
WLAN BB & POWER
JOE
01/19/2011
60
30
CONNECTOR: X26
JOE
01/19/2011
59
29
IO FLEX: B2B CONNECTOR
JOE
01/19/2011
58
28
DISPLAY PORT MISC
JOE
01/19/2011
57
27
IO FLEX: DOCK COMPONENTS
MARK
01/11/2011
56
26
SENSOR PANEL FILTERS 2
MARK
01/11/2011
55
25
SENSOR PANEL FILTERS 1
MARK
01/11/2011
54
24
CONNECTOR: SENSOR
KAVITHA 02/03/2011
43
23
AUDIO: HP/MIC FILTERS
KAVITHA 02/03/2011
42
22
AUDIO: DETECT/MIC BIAS
KAVITHA 02/03/2011
38
21
AUDIO: HEADPHONE OUT
KAVITHA 02/03/2011
37
20
AUDIO: SPEAKER AMP
KAVITHA 02/03/2011
36
19
AUDIO: L63B CODEC
RAMSIN
12/17/2010
31
18
GRAPE: Z1, Z2
RAMSIN
12/17/2010
30
17
GRAPE: GROUNDHOG,CONN,BOOST
JOE
01/19/2011
22
16
VIDEO: EDP CONNECTOR
ALEX
09/30/2010
21
15
MLB ALIASES/CONNECTIONS
MIKE
06/21/2010
17
14
DDR 2 AND 3
MIKE
06/21/2010
16
13
DDR 0 AND 1
MIKE
N/A
14
12 NAND
CHOPIN
12/10/2010
13
11
AP: VIDEO BUFFER,BB USB MUXES
ALEX
N/A
12
10
AP: MISC & ALIASES
MIKE
N/A
11
9
AP: POWER
MIKE
N/A
10
8
AP: DDR
JOE
01/13/2011
9
7
AP: TV,DP,MIPI
MIKE
N/A
8
6
AP: NAND
JOE N/A
7
5
AP: I/Os
MIKE
N/A
6
4
AP: MAIN
MIKE
N/A
4
3
BOM TABLES
J2DEV
N/A
2
2
BLOCK DIAGRAM: SYSTEM
157
48
01/21/2011
FUNC TEST POINTS
MIKE
156
47
01/21/2011
FUNC TEST POINTS
MIKE
155
46
01/21/2011
CONSTRAINTS: DEBUG
MIKE
154
45
01/21/2011
CONSTRAINTS: POWER / GND
MIKE
153
44
01/21/2011
CONSTRAINTS: DDR/FMI
MIKE
152
43
01/21/2011
CONSTRAINTS: DISPLAY/AUDIO
MIKE
151
42
01/21/2011
CONSTRAINTS: LOW SPEED BUS
MIKE
150
41
01/21/2011
CONSTRAINTS: MLB RULES
MIKE
93
40
10/04/2010
FCT/ICT TEST/BRACKETS
ALEX
90
39
10/04/2010
DEBUG AND MISC
ALEX
83
38
01/13/2011
POWER: AMELIA VSS
MADHAVI
82
37
01/14/2011
POWER: AMELIA PMU
MLB
81
36
01/13/2011
POWER: AMELIA PMU
MADHAVI
80
35
01/13/2011
POWER ALIASES
MADHAVI
75
34
01/13/2011
POWER: BATTERY CONNECTOR
MADHAVI
63
33
09/01/2011
WLAN 5GHZ AND TEST POINTS
X26_WIFI_MIKE_BT
SYNC MASTER
DATE
CONTENTS
CSAPDF
DRAWING
MLB
MIKE
NA
1
1
Table of Contents
62
32
09/01/2011
WLAN 2.4GHZ AND ANT
X26_WIFI_MIKE_BT
PDF
CONTENTS
CSA
DATE
SYNC MASTER
SYNC_MASTER=MIKE
SCH,J2,MLB
SYNC_DATE=NA
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
FF CAMERA
VGA FLEX
REAR CAMERA
AUDIO
UART3
UART6
MIPI1C
DUAL-CORE ARM
CORTEX-A9 W/ SMP
HSIC1_1
ISP_I2C1
LPDDR2
HSIC0_1
AMP
AMP
BT_I2S
CSA 61-64
CSA 60
VA5/8 FLEX
VGA FLEX
BUTTON FLEX
HALL EFF
PROX SENSOR
AE2
GPU
ARM A5 CPU
QUAD-CORE IMG
SGX543-MP2
400MHZ/800MB/S
4X32-BIT
1 GBYTE
EDP
MIMO
WIFI/BT ANT 2
WIFI ANT 1
FMI2
FMI1
HSIC1
CELLULAR/GPS
X26
950 MHZ
H4G
DWI
UART5
DISPLAYPORT
CSA 31
CSA 31CSA 30
CSA 75
CSA 14CSA 14
I2S2
VIDEO DAC
FMI0
USB2.0
I2C0
I2C2
DOCK
30-PIN
GYRO
ACCELEROMETER
ALS
ISP_I2C0
SPI1
WIFI/BT
MIPI0C
USART
IPCSPI2
I2C1
UART1
AMP
ASP
LINEOUT
I2S0
Z2
AUDIO CODEC
L63B
TOUCH PANEL
RESOLUTION: 2048X1536
GROUNDHOG
Z1
VSP
FMI3
XSP
CSA 36
I2S3
I2C 8’H94
I2C 8’H76
PPN1.0 PPN1.0
NAND FLASHNAND FLASH
CSA 57
UART0
SPEAKER
PRIMARY CELLULAR ANT
DIVERSITY CELLULAR ANT
GPS ANT
PMU
AMELIA
BATTERY
DISPLAY/
BACKLIGHT
SENSOR PANELSENSOR PANEL
SENSOR PANEL SENSOR PANEL
COMPASS
CSA 81,82
I2C 8’H1C
I2C 8’H78
I2C 8’H58
I2C 8’H72I2C 8’H32I2C 8’HD0
MIC
EXT MIC
MUX
US/CHINA
SYNC_DATE=N/A
SYNC_MASTER=J2DEV
BLOCK DIAGRAM: SYSTEM
051-8773
10.0.0
2 OF 157
2 OF 48
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
NAND
SDRAM
SCH AND BOARD P/N
DEVELOPMENT_JTAG_TAP
Power aliases required by this page:
INTERNAL_MIC
DEVELOPMENT_JTAG
16GB_PROD
(NONE)
32GB_PROD
JTAG_DAP
SPEAKER
(NONE)
ALTERNATE
COMMON
64GB_PROD
128GB_PROD
J2
MLB
DEV
NAND_IO_1V8
NAND_IO-3V3
SNOTE
MECHANICAL PARTS
BOM options provided by this page:
BARCODE LABEL/EEEE CODES
PMU
32GB FLASH CONFIGURATIONS
16GB FLASH CONFIGURATIONS
64GB FLASH CONFIGURATIONS
128GB FLASH CONFIGURATIONS
Page Notes
Signal aliases required by this page:
ALL AVAIL BOM OPTIONS
SOC
DEV1
DEV BOM,MLB,J2
085-3058
?1
PCB1
PCBF,MLB,J2
820-2996
?1
CRITICAL
SCH1SCH,MLB,J2051-8773
?1
CRITICAL
U0600
IC,SOC,H4G,FCBGA1225
343S0533 CRITICAL
1 ?
SYNC_MASTER=MIKE
SYNC_DATE=N/A
BOM TABLES
825-7691
CRITICAL
1
EEEE_J2A_64G
EEEE FOR 639-2827 (J2A 64G)
EEEE_DRF5
1
CRITICAL
EEEE FOR 639-2826 (J2A 32G)
EEEE_J2A_32G
825-7691
EEEE_DRF6
EEEE FOR 639-2844 (J2A 16G)
EEEE_DRJQ
EEEE_J2A_16G
825-7691
CRITICAL
1
FENCE,LARGE,TOP,MLB,J2
PD_FENCE_LARGE
806-1857
CRITICAL
1
806-1860
PD_FENCE_BTM1
FENCE,1,BTM,MLB,J2
1
CRITICAL
806-1865
FENCE,2,BTM,MLB,J2
CRITICAL
PD_FENCE_BTM2
1
FENCE,SMALLER,BTM,MLB,J2
CRITICAL
PD_FENCE_BTM3
1
806-2352
AUDIO
SPEAKER,INTERNAL_MIC
U1400,U1410
128GB_PROD335S0806 335S0814
TOSHIBA 24NM PPN1.0
128GB_PROD
U1400,U1410
2
CRITICAL335S0814
HYNIX 26NM PPN1.0 64GB
64GB_PROD
U1400,U1410
335S0805 335S0782
TOSHIBA 24NM PPN1.0
CRITICAL
64GB_PROD
2
U1400,U1410
335S0782
HYNIX 26NM PPN1.0 32GB
U1400,U1410
32GB_PROD
335S0781335S0804
TOSHIBA 24NM PPN1.0
335S0804 335S0781
16GB_PROD
U1400
TOSHIBA 24NM PPN1.0
16GB_PROD
U1400
HYNIX 26NM PPN1.0 16GB
1
335S0781 CRITICAL
HYNIX 26NM PPN1.0 16GB
335S0781 CRITICAL
2
U1400,U1410
32GB_PROD
U1600,U1700
SDRAM,LPDDR2,512MB,SAMSUNG 46NM
2
333S0579
?
CRITICAL
CRITICAL
U8100
IC,PMU,AMELIA,D1974AB
1
343S0561
?
EEEE_J2_128G
EEEE_DKQK
1
CRITICAL
EEEE FOR 639-1870 (J2 128G)
825-7691
825-7691
EEEE FOR 639-2352 (J1 16G)
1
CRITICAL
EEEE_DNKT
EEEE_J1_16G
825-7691
CRITICAL
EEEE_DM2N
EEEE_J1_32G
1
EEEE FOR 639-2058 (J1 32G)
825-7691
EEEE FOR 639-2059 (J1 64G)
1
CRITICAL
EEEE_DM2P
EEEE_J1_64G
825-7691
EEEE FOR 639-2353 (J2 16G)
1
CRITICAL
EEEE_J2_16G
EEEE_DNKV
825-7691
EEEE FOR 639-1572 (J2 32G)
1
CRITICAL
EEEE_J2_32G
EEEE_DHWV
825-7691
EEEE FOR 639-1871 (J2 64G)
1
CRITICAL
EEEE_DKQL
EEEE_J2_64G
COMMON,ALTERNATE
BASIC
CRITICAL
FENCE,NAND,TOP,MLB,J2
806-2105
1
PD_FENCE_NAND
806-2349
1
PD_FENCE_SMALL
CRITICAL
FENCE,SMALLER,TOP,MLB,J2
LPDDR2,HYNIX 44NM
333S0579
U1600,U1700
333S0580
LPDDR2,ELPIDA 45NM
U1600,U1700
333S0579333S0581
051-8773
10.0.0
4 OF 157
3 OF 48
BI
BI
BI
BI
(1 OF 12)
JTAG_TRST*
XO0
XI0
WDOG
USB11_DP1
USB11_DP0
USB11_DM1
USB11_DM0
USB_VDD330
USB_VBUS1
USB_VBUS0
USB_ID1
USB_ID0
USB_DVDD
USB_DP0
USB_DM0
USB_BRICKID1
USB_BRICKID0
USB_ANALOGTEST1
USB_ANALOGTEST0
TST_STPCLK
TST_CLKOUT
TESTMODE
RESET*
PLL5_AVDD11
PLL4_AVDD11
PLL3_AVDD11
PLL2_AVSS11
PLL2_AVDD11
PLL1_AVSS11
PLL1_AVDD11
PLL0_AVSS11
PLL0_AVDD11
PLL_USB_AVSS11
PLL_USB_AVDD11
MIPI1D_VDD11_PLL
JTAG_TRTCK
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG_TCK
JTAG_SEL
HSIC1_VSS122
HSIC1_VSS121
HSIC1_VDD122
HSIC1_VDD121
HSIC1_STB2
HSIC1_STB1
HSIC1_DVSS
HSIC1_DVDD
HSIC1_DATA2
HSIC1_DATA1
HSIC0_VSS122
HSIC0_VSS121
HSIC0_VDD122
HSIC0_VDD121
HSIC0_STB2
HSIC0_STB1
HSIC0_DVSS
HSIC0_DVDD
HSIC0_DATA2
HOLD_RESET
FUSE1_FSRC
FAST_SCAN_CLK
DDR3_CKEIN
DDR2_CKEIN
DDR1_CKEIN
DDR0_CKEIN
CFSB1
HSIC0_DATA1
USB_DM1
USB_DP1
USB_DVSS
USB_VSSA0
USB_VSSAC
PLL5_AVSS11
MIPI_VSS
USB_REXT1
USB_REXT0
PLL4_AVSS11
PLL3_AVSS11
CFSB0
MIPI0D_VDD11_PLL
(11 OF 12)
VSS VSS
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
1 - DAISY CHAIN (FOR USE WITH 5-WIRE JTAG)
34MA
7MA
10MA
7MA
14MA
2.5MA EACH
2.5MA
JTAGSEL
3.16V
1.75V
1.16V
28MA
34MA
BB
WLAN
PER RADAR #6755237
0 - PARALLEL
01005
X5R
6.3V
0.01UF
10%
01005
0.01UF
10%
X5R
6.3V
10%
01005
X5R
0.01UF
6.3V
0.01UF
01005
6.3V
10%
X5R
30 42
30 42
15 40
42
15 40 42
5%
100K
1/32W 01005
5%
01005
100K
1/32W
01005
5%
100K
1/32W
01005
100K
1/32W
MF
1%
1%
10K
MF
01005
1/32W
1000PF
201
16V
X7R
10%
01005
MF
1/32W
0.00
0%
MLB
01005
0.01UF
10%
X5R
6.3V
H4G
FCBGA
OMIT
H4G
FCBGA
OMIT
10
10
10
10
10 42
10 42 45
10
1%
44.2
201
MF
1/20W
201
MF
1/20W
1%
44.2
01005
0%
0.00
MF
1/32W
0%
0.00
MF
01005
1/32W
0.00
1/32W
MF
0%
01005
0.00
0%
1/32W
MF
01005
0.00
0%
1/32W
01005
MF
0%
MF
01005
1/32W
0.00
1/32W
0%
01005
MF
0.00
0201
80-OHM-0.2A-0.4-OHM
GDZ-0201
GDZT2R5.1B
100K
5%
1/32W
MF
01005
DEVELOPMENT_JTAG_TAP
100K
5%
1/32WMF01005
CRITICAL
SM-2
24.000MHZ-16PF-60PPM
01005
1/32W
5%
22
MF
01005
22PF
CERM
16V
5%
01005
5%
22PF
CERM
16V
1.00M
010051/32W
1% MF
42.2K
1%
MF
1/32W
01005
01005
1/32W
MF
1%
82.5K
27 30 37 45
37
37 45
6.3V
X5R
10%
01005
0.01UF
6.3V
CERM
402
1UF
10%
6.3V
X5R
10%
0.01UF
01005
0.01UF
6.3V
X5R
10%
01005
01005
0.01UF
10%
X5R
6.3V 6.3V
402
CERM
10%
1UF
56PF
NP0-C0G
01005
6.3V
5%
6.3V
X5R
10%
0.01UF
01005
6.3V
X5R
01005
10%
0.01UF
6.3V
X5R
10%
0.01UF
01005
0.01UF
10%
6.3V
X5R
01005
0.01UF
6.3V
X5R
01005
10%
10%
X5R
6.3V
0.01UF
01005
0.01UF
6.3V
X5R
01005
10%
01005
0.01UF
6.3V
X5R
10%
SYNC_MASTER=MIKE
AP: MAIN
SYNC_DATE=N/A
PP1V1_PL4_F
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MM
=PP1V1_PLL_H4
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
PP1V1_MIPID_PLL_F
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3MM
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.2MM
VOLTAGE=1.1V
MIN_NECK_WIDTH=0.1MM
PP1V1_PL1_F
MIN_LINE_WIDTH=0.2MM
VOLTAGE=1.1V
MIN_NECK_WIDTH=0.1MM
PP1V1_PL2_F
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MM
PP1V1_PL3_F
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
PP1V1_PL5_F
MIN_LINE_WIDTH=0.2MM
VOLTAGE=1.1V
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3MM
NET_SPACING_TYPE=PWR
PP1V1_PLL_USB_F
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
RST_PMU_IN
=PP1V8_H4
24M_O
PPVBUS_USB
=PP3V3_USB_H4
=PP1V1_PLL_H4
=PP1V1_USB_H4
=PP1V1_MIPI_PLL_H4
=PP1V8_H4
USB_REXT0
USB_REXT1
NC_USB_D1_P
NC_USB_D1_N
HSIC0_BB_DATA1
AP_DDR1_CKEIN_1V2
NC_HSIC0_DATA2
HSIC0_BB_STB1
NC_HSIC0_STB2
HSIC1_WLAN_DATA1
NC_HSIC1_DATA2
HSIC1_WLAN_STB1
NC_HSIC1_STB2
JTAG_AP_SEL
JTAG_AP_TCK
JTAG_AP_TDI
JTAG_AP_TMS
NC_JTAG_AP_TRTCK
NC_USB_ANALOGTEST0
NC_USB_ANALOGTEST1
USB_BRICKID
NC_USB_BRICKID1
USB_DK_D0_N
USB_DK_D0_P
NC_USB_ID0
NC_USB_ID1
USB_AP_VBUS0
USB11_MUX_D0_N
NC_USB11_D1_N
AP_WDOG
XTAL_24M_I
XTAL_24M_O
=PP1V2_HSIC_H4
MIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.1MM
PP1V1_PL0_F
VOLTAGE=1.1V
MAX_NECK_LENGTH=3MM
=PP1V1_HSIC_H4
=PP1V1_USB_H4
=PP3V3_USB_H4
USB_AP_VBUS1
JTAG_AP_TDO
JTAG_AP_TRST_L
TP_AP_TST_CLKOUT
AP_TST_STPCLK
RST_AP_L
AP_FAST_SCAN_CLK
AP_HOLD_RESET
AP_TESTMODE
RST_AP_1V8_L
USB11_MUX_D0_P
NC_USB11_D1_P
C0615
1
2
R0612
1
2
R0613
1
2
R0604
12
R0603
12
R0602
12
R0601
12
R0605
12
R0606
12
R0607
12
FL0600
12
DZ0600
1
2
R0609
1
2
R0608
12
Y0602
24
13
R0651
12
C0651
1
2
C0650
1
2
R0650
12
R0642
1
2
R0643
1
2
C0612
1
2
C0614
1
2
C0608
1
2
C0609
1
2
C0621
1
2
C0622
1
2
C0620
1
2
C0604
1
2
C0603
1
2
C0600
1
2
C0601
1
2
C0602
1
2
C0607
1
2
C0630
1
2
C0631
1
2
C0635
1
2
C0634
1
2
C0633
1
2
C0632
1
2
R0621
12
R0622
12
R0620
12
R0641
1
2
R0640
1
2
C0640
1
2
R0652
12
U0600
W6
AR32
L6
F9
AK10
AF6
AR33
M31
AN28
K35
K33
N31
N30
L35
L33
P29
P31
P28
P30
H35
H33
H32
H31
J35
J33
K30
J30
K29
J29
AK29
AN29
AN30
AP30
AJ27
AR27
AM27
F27
F30
H24
H25
H26
H27
H28
H29
V33
V32
U33
U32
T33
T32
R33
R32
P33
P32
N33
N32
M33
M32
AR30
AH27
AR29
AR28
R34
P35
T34
N35
R30
J28
T28
K31
T35
M34
U35
N34
U29
L30
U28
L31
T31
K32
R31
K28
T30
J32
R28
M28
T29
L28
R29
L29
AP29
W35
Y35
U0600
A1
A2
AA8
AN10
AN13
AN16
AP1
AP2
AP6
AP9
AP12
AP15
AP18
AA10
AP22
AP25
AP28
AP31
AP34
AP35
AR1
AR2
AR5
AR8
AA12
AR11
AR14
AR17
AR19
AR34
AR35
B1
B2
B4
B9
AA14
B12
B15
B34
B35
C7
C10
C13
C16
C30
C31
AA16
C32
C33
D3
D5
D8
D11
D14
D17
D30
D33
AA18
E1
E10
E21
E22
E24
E25
E26
E27
E28
E29
AA20
E30
E33
F2
F5
F16
F17
F21
F22
F24
F33
AA22
G3
G17
G18
G19
G20
G21
AA24
AA26
A5
AA35
AB1
AB4
AB8
AB9
AB11
AB13
AB15
AB17
AB19
A8
AB21
AB23
AB25
AB27
AC3
AC8
AC10
AC18
AC20
AC22
A11
AC24
AC28
AC32
AC34
AD2
AD8
AD9
AD11
AD19
AD21
A14
AD23
AD25
AD27
AD29
AE1
AE8
AE9
AE10
AE18
AE20
A17
AE22
AE24
AE26
AF3
AF8
AF9
AF27
AF30
AF32
AF34
A34
AG2
AG8
AG9
AH1
AH8
AH9
AH10
AH11
AH12
AH17
A35
AH22
AH25
AH26
AJ5
AJ13
AJ20
AJ29
AJ32
AJ34
AK2
AA2
AL1
AM3
AM8
AM19
AM22
AM25
AM28
AM32
AM34
AN7
051-8773
10.0.0
6 OF 157
4 OF 48
45
4
35
45 45
45
45
45
45
4 7
10 35
42
36 45
4
35
4
35
4
35
35
4 7
10 35
42 46
42 46
42 46
42 46
42 46
42
46
10
27 42
10 42
27 42
46
46
46
46
27 42
27 42
46
46
11 42
42 46
42
42
35
45
35
4
35
4
35
45
11 42
42 46
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI
OUT
BI
OUT
BI
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
IN
OUT
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
(2 OF 12)
UART5_RTXD
UART3_TXD
UART3_RXD
UART3_RTSN
UART3_CTSN
UART6_TXD
UART6_RXD
UART6_RTSN
UART6_CTSN
UART4_TXD
UART4_RXD
UART4_RTSN
UART4_CTSN
UART2_TXD
UART2_RXD
UART2_RTSN
UART2_CTSN
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO39
GPIO38
GPIO37
GPIO36
GPIO35
GPIO34
GPIO33
GPIO32
GPIO31
GPIO30
GPIO3
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO2
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO1
GPIO0
GPIO_3V1
GPIO_3V0
UART1_TXD
UART1_RXD
UART1_RTSN
UART0_TXD
UART0_RXD
TMR32_PWM2
TMR32_PWM1
TMR32_PWM0
EHCI_PORT_PWR2
GPIO9
GPIO10
UART1_CTSN
EHCI_PORT_PWR1
EHCI_PORT_PWR0
SPI0_SSIN
SPI0_SCLK
SPI0_MOSI
SPI0_MISO
SWI_DATA
SPI3_SSIN
SPI3_SCLK
SPI3_MOSI
SPI3_MISO
SPI2_SCLK
SPI2_MOSI
SPI1_SSIN
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
SPDIF
SDIO0_DATA3
SDIO0_DATA2
SDIO0_DATA1
SDIO0_DATA0
SDIO0_CMD
SDIO0_CLK
I2S3_MCK
I2S3_LRCK
I2S3_DOUT
I2S3_DIN
I2S3_BCLK
I2S2_MCK
I2S2_BCLK
I2S1_MCK
I2S1_LRCK
I2S1_DIN
I2S1_BCLK
I2S0_MCK
I2S0_DOUT
I2S0_BCLK
I2C2_SDA
I2C2_SCL
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
DWI_DO
DWI_DI
DWI_CLK
I2S2_DOUT
I2S2_DIN
I2S2_LRCK
I2S1_DOUT
I2S0_LRCK
I2S0_DIN
VSSA18_TS
VDDA18_TS
SPI2_SSIN
SPI2_MISO
THERM_RES_EXT
THERM_TEST_OUT
(3 OF 12)
IN
OUT
IN
IN
IN
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CODEC ASP
- BB -> H4G
- BB_DIAGS_READY (RADAR #9179861)
NOTE FOR GPIO12:
- AP_MODEM_WAKE (RADAR #9179861)
NOTE FOR GPIO24:
- H4G -> BB
BUT OPTION IS HERE IN CASE THEY NEED TO BE SEPARATE
DEFAULT IS TO TIE HSIC_HOST_READY TO BOTH DEVICES
TO BB
NEW GPIO FOR J2. FILE A RADAR
TO SENSOR BOARD (ALS)
CODEC VSP & BT
TO SENSOR BOARD
TO CHARLESTON, CODEC AND PMU
CODEC XSP
NOT USED
TO GRAPE
3.0V IO
TO BT UART
TO DOCK MUX
TO BB USART
15 42
15 42
15 42
15 42
34 37
1%
MF
01005
1/32W
33.2
19 42
19 42
19 42
19 42
19 42
15 19 42
15 19 42
15 19 42
15 19 42
19 42
19 42
19 42
19 42
10
10
10
10 19 22 37 42
10 19 22 37 42
10 25 42
10 25 42
25 42
25 42
37 42
37 42
37 42
5%
201
220K
1/20W
MF
5%
MF
220K
1/20W
201
201
5%
220K
1/20W
MF
201
MF
100K
1/20W
5%
MF
100K
1/20W
5%
201
100K
MF
1/20W
5%
201
MF
1/32W
01005
100K
5%5%
201
100K
1/20W
MF
30 42
30 42
30 42
5
30 42
30 42
24
24
30
5
37
30 45
15
37
19
15 30 45
201
100K
5%
1/20W
MF
NOSTUFF
MF
100K
201
1%
1/20W
17 42
17 42
17 42
17 42
1/32W
0%
01005
MF
0.00
10%
X5R
6.3V
0.01UF
01005
01005
MF
1/32W
1%
100K
NOSTUFF
0%
MF
01005
1/32W
0.00
MF
0%
1/32W
01005
0.00
MF
1/20W
5%
100K
201
5
42
OMIT
H4G
FCBGA
OMIT
H4G
FCBGA
5
15 42
15 42
15 42
5
28 37
5
24 37
5
30
30 42
5
26
10
18
30
10
5
5
39
10
10
26
26
26
26
25
11
20
10
10
10
15 42
15 42
30 42
30 42
30 42
30 42
5
24 37
30 45
SYNC_MASTER=JOE
SYNC_DATE=N/A
AP: I/Os
IRQ_CODEC_L
NC_AP_GPIO7
NC_AP_GPIO8
PM_RADIO_ON
RST_DET_L
HSIC_BB_RDY
ONOFF_L
HOME_EMI_L
GPIO42_BRD_REV2
IRQ_ALS_INT_L
AUD_SPKRAMP_MUTE_L
PORT_DOCK_VIDEO_AMP_EN
RST_BB_L
SRL_L
NC_BOARD_ID_3
IRQ_ACCEL_INT1_L
UART0_AP_TXD
UART0_AP_RXD
IRQ_PMU_L
PM_BT_WAKE
=PP1V8_VDDA18_TS
HSIC_HOST_RDY
=PP1V8_VDDIOD_H4
UART1_BB_RTS_L
HSIC_HOST_READY_WLAN
HSIC_HOST_RDY
=PP1V8_S2R_MISC
=PP1V8_ALWAYS
=PP1V8_S2R_MISC
SRL_L
ONOFF_L
HOME_EMI_L
HSIC_WLAN_RDY
HSIC_HOST_READY_WL
GPIO40_BRD_REV0
GPIO41_BRD_REV1
UART1_BB_CTS_L
NC_AP_GPIO185
NC_AP_GPIO186
TP_LED_STROBE_EN
UART1_BB_RXD
UART1_BB_TXD
NC_AP_GPIO11
SPI2_IPC_SRDY
NC_AP_GPIO13
AUD_VOL_DOWN_L
GSM_TXBURST_IND
IRQ_GYRO_INT2
BOOT_CONFIG_0
NC_AP_GPIO19
AUD_VOL_UP_L
IRQ_GRAPE_HOST_INT_L
PM_KEEPACT
BB_EMERGENCY_DWLD
IPC_GPIO_X26
BOOT_CONFIG_1
FORCE_DFU
BOOT_CONFIG_2
BOOT_CONFIG_3
NC_AP_GPIO3
NC_UART2_RXD
NC_UART2_TXD
NC_UART4_CTS_L
NC_UART4_RTS_L
NC_UART4_RXD
NC_UART4_TXD
NC_UART6_CTSN
NC_UART6_RTSN
UART3_BT_CTS_L
UART3_BT_RTS_L
UART3_BT_RXD
UART3_BT_TXD
BATTERY_SWI
TP_THERM_TEST_OUT
THERM_RES_EXT
SPI2_IPC_MISO
PP1V8_VDDA18_TS
NC_I2S1_DOUT
I2S2_VSP_LRCK
I2S2_VSP_DIN
I2S2_VSP_DOUT
DWI_AP_DI
DWI_AP_DO
I2C0_SCL_1V8
I2C0_SDA_1V8
I2C1_SCL_1V8
I2C2_SCL_3V0
I2C2_SDA_3V0
NC_I2S1_BCLK
NC_I2S1_DIN
NC_I2S1_LRCK
NC_I2S1_MCK
I2S2_VSP_BCLK
NC_I2S2_MCK
I2S3_XSP_BCLK
I2S3_XSP_DIN
I2S3_XSP_DOUT
I2S3_XSP_LRCK
NC_I2S3_MCK
NC_SDIO0_WL_CLK
NC_SDIO0_WL_CMD
NC_SDIO0_WL_DATA<0>
NC_SDIO0_WL_DATA<1>
NC_SDIO0_WL_DATA<2>
NC_SDIO0_WL_DATA<3>
NC_AP_GPIO216
SPI1_GRAPE_MISO
SPI1_GRAPE_MOSI
SPI1_GRAPE_SCLK
SPI1_GRAPE_CS_L
SPI2_IPC_MOSI
SPI2_IPC_SCLK
NC_SPI3_MISO
NC_SPI3_MOSI
NC_SPI3_SCLK
NC_SPI3_CS_L
NC_SWI_AP
BOARD_ID_2
BOARD_ID_1
BOARD_ID_0
NC_SPI_FLASH_CS_L
I2C1_SDA_1V8
DWI_AP_CLK
IRQ_GYRO_INT1
IRQ_PROX_INT_L
NC_AP_GPIO31
HSIC_HOST_READY_WL
NC_AP_GPIO35
HSIC_WLAN_RDY
NC_AP_GPIO3V1
DFU_STATUS
IRQ_ACCEL_INT2_L
UART6_WLAN_RXD
UART6_WLAN_TXD
PM_RADIO_ON
DFU_STATUS
FORCE_DFU
IRQ_GYRO_INT2
PM_KEEPACT
I2S0_ASP_MCK_R
I2S0_ASP_BCLK
I2S0_ASP_LRCK
I2S0_ASP_DIN
I2S0_ASP_DOUT
I2S0_ASP_MCK
R0700
12
R0708
12
R0709
12
R0710
12
R0715
1
2
R0714
1
2
R0713
1
2
R0712
1
2
R0711
1
2
R0720
1
2
R0722
1
2
R1180
12
C1188
1
2
R1030
1
2
R0730
12
R0731
12
R0885
1
2
U0600
AG26
AE15
AE16
AJ14
AK15
AG17
AD13
AK17
AE14
AL17
AF17
AL18
AK18
AJ18
AD12
AL16
AH18
AF18
AM18
AN18
AN19
AG18
AP20
AN20
AR20
AR21
AG14
AP21
AK19
AN21
AH19
AG19
AJ19
AR22
AL20
AM20
AN22
AP19
AH13
AH16
AE13
AE12
AH15
AN31
AP32
AD16
AD14
AC12
AH14
AG15
AP23
AL21
AG21
AF21
U5
T7
U8
T5
AG22
AJ21
AR24
AR23
Y6
Y7
W7
Y5
AL22
U9
V6
U7
V7
U0600
AN25
AM24
AG23
AJ23
AK23
AN24
AR25
AH21
AK21
AG24
AK25
AL25
AP26
AR26
AC17
AC16
AF26
AC14
AC15
AF24
AG25
AM26
AN26
AK27
AN27
AK26
AL26
AF25
AP27
AL27
AR31
AK28
AL28
AM29
AM30
AG27
U6
W5
T6
W8
AF20
AF19
AG20
AM21
AF23
AL23
AH23
AM23
AL30
AL29
AN32
AP33
AC13
AK16
AJ16
AF16
AG16
051-8773
10.0.0
7 OF 157
5 OF 48
46
46
46
35
9
35
15 42
5
30 42
5
27 35 39
35
5
27 35 39
5
24 37
5
24 37
5
28 37
5
15 42
5
42
46
46
46
46
46
46
46
46
46
46
46
46
46
46
45
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
5
30
5
5
39
5
26
5
37
42
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
FMI0_ALE
FMI3_IO7
FMI3_IO6
FMI3_IO5
FMI3_IO4
FMI3_IO1
FMI3_IO0
FMI3_DQS
FMI3_CLE
FMI3_CEN7
FMI3_CEN6
FMI3_CEN5
FMI3_CEN4
FMI3_CEN3
FMI3_CEN2
FMI3_CEN1
FMI3_CEN0
FMI2_WEN
FMI2_REN
FMI2_IO7
FMI2_IO6
FMI2_IO5
FMI2_IO4
FMI2_IO3
FMI2_IO2
FMI2_DQS
FMI2_CLE
FMI2_CEN7
FMI2_CEN6
FMI2_CEN4
FMI2_CEN3
FMI2_CEN2
FMI2_CEN1
FMI2_CEN0
FMI2_ALE
FMI1_IO7
FMI1_IO4
FMI1_IO3
FMI1_IO2
FMI1_IO1
FMI1_IO0
FMI1_DQS
FMI1_CLE
FMI1_CEN1
FMI1_CEN0
FMI1_ALE
FMI0_WEN
FMI0_IO7
FMI0_IO6
FMI0_IO5
FMI0_IO4
FMI0_IO3
FMI0_IO2
FMI0_IO1
FMI0_IO0
FMI0_DQS
FMI0_CEN7
FMI0_CEN6
FMI0_CEN5
FMI0_CEN4
FMI0_CEN3
FMI0_CEN1
FMI0_CEN0
FMI1_CEN2
FMI1_CEN3
FMI1_CEN4
FMI1_CEN7
FMI1_CEN6
FMI1_CEN5
FMI2_IO1
FMI2_IO0
FMI0_CEN2
FMI2_CEN5
FMI0_CLE
FMI0_REN
FMI3_ALE
FMI1_IO5
FMI1_IO6
FMI3_IO3
FMI3_IO2
FMI1_REN
FMI1_WEN
FMI3_REN
FMI3_WEN
(4 OF 12)
(12 OF 12)
VSSVSS
IN
OUT
OUT
BI
OUT
OUT
OUT
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CHECK WITH GRAPE ON VOLTAGE FOR THESE TWO SIGNALS
CHECK CONNECTION FOR VSSA18_TS
FMI2-3_CEN IS 3.0V
NEW GPIO FOR J2. FILE A RADAR
12 44
12 44
12 44
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
6
12 44
6
12 44
6
12 44
6
12 44
12 44
12 44
MF
1/32W
5%
100K
01005
NOSTUFF
01005
100K
5%
1/32W
MF
NOSTUFF
MF
1/32W
5%
100K
01005
NOSTUFF
MF
1/32W
5%
100K
01005
NOSTUFF
100K
5%
1/32W
MF
01005
NOSTUFF
01005
100K
5%
1/32W
MF
NOSTUFF
MF
1/32W
5%
100K
01005
NOSTUFF
MF
1/32W
5%
100K
01005
NOSTUFF
OMIT
H4G
FCBGA
H4G
FCBGA
OMIT
100K
5%
1/32W
MF
01005
20
01005
100K
5%
1/32W
MF
01005
100K
5%
1/32W
MF
01005
100K
5%
1/32W
MF
100K
5%
1/32W
MF
01005
17 45
16
12 44
6
12 44
17
6
12 44
12 44
12 44
12 44
SYNC_DATE=N/A
AP: NAND
SYNC_MASTER=MIKE
NC_FMI3_WE_L
FMI1_WE_L
FMI1_CLE
FMI1_AD<7>
FMI1_AD<6>
FMI1_AD<5>
FMI1_AD<4>
NC_FMI2_CE1_L
RST_GRAPE_L
FMI0_ALE
NC_FMI3_AD<7>
NC_FMI3_AD<6>
NC_FMI3_AD<5>
NC_FMI3_AD<4>
NC_FMI3_AD<1>
NC_FMI3_AD<0>
NC_FMI3_DQS
NC_FMI3_CLE
NC_FMI3_CE7_L
NC_FMI3_CE6_L
NC_FMI3_CE5_L
NC_FMI3_CE4_L
NC_FMI3_CE3_L
NC_FMI3_CE2_L
NC_FMI3_CE1_L
NC_FMI3_CE0_L
NC_FMI2_WE_L
NC_FMI2_AD<7>
NC_FMI2_AD<6>
NC_FMI2_AD<5>
NC_FMI2_AD<4>
NC_FMI2_AD<3>
NC_FMI2_AD<2>
NC_FMI2_DQS
NC_FMI2_CLE
NC_FMI2_CE3_L
NC_FMI2_CE2_L
NC_FMI2_ALE
FMI1_AD<3>
FMI1_AD<2>
FMI1_AD<1>
FMI1_AD<0>
FMI1_DQS_P
FMI1_CE1_L
FMI1_CE0_L
FMI1_ALE
FMI0_WE_L
FMI0_AD<7>
FMI0_AD<6>
FMI0_AD<4>
FMI0_AD<3>
FMI0_AD<2>
FMI0_AD<1>
FMI0_AD<0>
FMI0_DQS_P
NC_FMI0_CE7_L
NC_FMI0_CE6_L
NC_FMI0_CE5_L
NC_FMI0_CE4_L
NC_FMI0_CE3_L
FMI0_CE1_L
FMI0_CE0_L
NC_FMI1_CE2_L
NC_FMI1_CE3_L
NC_FMI1_CE4_L
NC_FMI1_CE7_L
NC_FMI1_CE6_L
NC_FMI1_CE5_L
NC_FMI2_AD<1>
NC_FMI0_CE2_L
NC_FMI2_CE5_L
FMI0_CLE
FMI0_RE_N
NC_FMI3_ALE
NC_FMI3_AD<3>
NC_FMI3_AD<2>
FMI1_RE_N
NC_FMI3_RE_L
NC_FMI2_RE_L
GRAPE_FW_DNLD_EN_L
NC_FMI2_AD<0>
FMI0_AD<5>
PM_LCDVDD_PWREN
FMI1_CLE
FMI0_CLE
FMI1_ALE
FMI1_RE_N
FMI1_WE_L
FMI0_RE_N
PPIO_NAND_H4
FMI0_WE_L
FMI0_ALE
SPK_ID
=PP3V0_IO_MISC
FMI1_CE0_L
FMI0_CE0_L
FMI1_CE1_L
PPIO_NAND_H4
FMI0_CE1_L
R0834
1
2
R0831
1
2
R0836
1
2
R0832
1
2
R0803
1
2
R0802
1
2
R0801
1
2
R0800
1
2
R0813
1
2
R0812
1
2
R0811
1
2
R0810
1
2
U0600
AE32
AH31
AF31
AD28
AG29
Y29
AH28
AG28
AM31
AF33
AG33
AG35
AF35
AH35
AH33
AG31
AG32
AG34
AH32
AE33
AH34
AN34
AJ33
AN33
AD30
AE30
AJ31
AJ30
AL31
AK31
AK35
AL34
AL32
AN35
AK32
AK33
AL33
AK34
AM33
AJ35
AL35
AM35
AB34
AE35
AB28
AA28
AB30
AE28
AF28
AA29
AB31
AB32
AC33
AC31
AB33
AC35
AE34
AD34
AD32
AD35
AD31
AD33
AB35
Y33
W31
W28
W29
V30
AG30
AC30
AH30
AE31
W30
Y32
AA34
W33
AA33
V34
AA30
V31
W32
Y30
AA31
AA32
U0600
G22
G23
G30
H1
H4
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H30
H34
J2
J8
J9
J10
J11
J12
J14
J16
J18
J20
J22
J24
J26
J31
J34
K3
K8
K9
K10
K11
K13
K15
K17
K19
K21
K23
K25
K27
K34
L32
L1
L4
L8
L10
L12
L14
L16
L18
L20
L22
L24
L26
M2
M3
M8
M9
M11
M13
M15
M17
M19
M21
M23
M25
M27
M30
L34
N3
N8
N10
N12
N14
N16
N18
N20
N22
N24
N26
M35
P1
P8
P9
P11
P13
P15
P17
P19
P21
P23
P25
P27
R2
R8
R10
R12
R14
R16
R18
R20
R22
R24
R26
P34
T3
T9
T11
T13
T15
T17
T19
T21
T23
T25
T27
R35
U1
U10
U12
U14
U16
U18
U20
U22
U24
U26
U30
U31
V9
V11
V13
V15
V17
V19
V21
V23
V25
V27
V29
U34
V35
W1
W3
W10
W12
W14
W16
W18
W20
W22
W24
W26
W34
Y9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
Y27
Y28
Y31
Y34
R0804
1
2
051-8773
10.0.0
8 OF 157
6 OF 48
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6 9
45
6
12 44
6
12 44
28 35
6
12 44
6
12 44
6
12 44
6 9
45
6
12 44
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
OUT
OUT
OUT
OUT
(5 OF 12)
DAC_VREF
DP_PAD_TX0P
DP_PAD_AUXN
DP_PAD_AUXP
EDP_PAD_TX0P
DP_PAD_AVSS_AUX
EDP_PAD_AVSS
DAC_AVSS30D
DP_PAD_AVDDX
DP_PAD_TX2P
DP_PAD_TX1N
DP_PAD_TX1P
DAC_AVSS30A1
DAC_AVSS30A2
DAC_IREF DAC_OUT1
DAC_OUT3
DP_HPD
DP_PAD_DC_TP
DP_PAD_R_BIAS
DP_PAD_TX2N
DP_PAD_TX3N
DP_PAD_TX3P
EDP_HPD
EDP_PAD_AUXN
EDP_PAD_AUXP
EDP_PAD_AVSSP0
EDP_PAD_AVSSX
EDP_PAD_DVDDEDP_PAD_DVSS
EDP_PAD_R_BIAS
EDP_PAD_TX0N
EDP_PAD_TX1N
EDP_PAD_TX1P
EDP_PAD_TX2N
EDP_PAD_TX2P
EDP_PAD_TX3N
EDP_PAD_TX3P
DP_PAD_AVDDP0
DP_PAD_AVDD
DAC_COMP
EDP_PAD_AVDDX
EDP_PAD_AVDDP0
EDP_PAD_AVDD
EDP_PAD_AVDD_AUX
DP_PAD_DVDD
EDP_PAD_AVSS_AUX
DP_PAD_AVSSP0
DP_PAD_AVSSX
DP_PAD_DVSS
DP_PAD_AVSS
DP_PAD_TX0N
DAC_OUT2
EDP_PAD_DC_TP
DAC_AVDD30D
DAC_AVDD30A
DP_PAD_AVDD_AUX
MIPI_VDD11
MIPI1D_VREG_0P4V
MIPI0D_VREG_0P4V
ISP0_FLASH
SENSOR1_RST
SENSOR1_CLK
SENSOR0_RST
SENSOR0_CLK
MIPI1C_DNDATA0
MIPI_VSYNC
ISP1_SCL
ISP1_PRE_FLASH
ISP1_FLASH
ISP0_SDA
ISP0_SCL
ISP0_PRE_FLASH
MIPI1C_DPDATA0
MIPI1D_VDD18
MIPI0D_VDD18
MIPI0C_DNDATA3
MIPI1C_DNCLK
MIPI1C_DPCLK
MIPI1C_DNDATA1
MIPI1C_DPDATA1
MIPI0C_DPDATA0
MIPI0C_DNDATA0
MIPI0C_DPDATA1
MIPI0C_DPDATA2
MIPI0C_DNDATA2
MIPI0C_DPDATA3
MIPI0C_DPCLK
MIPI0C_DNCLK
MIPI0C_DNDATA1
ISP1_SDA
(6 OF 12)
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
1.2MA
5MA
2MA
332MA
21MA
4MA
DP LANES 2/3 ARE FOR STEVE-NOTE ONLY
NOTE: 0.6V ANALOG REF
NOTE: 0.6V ANALOG REF
6MA
5MA
2MA
5MA
1.2MA
5MA
172MA
14MA
6.3V
0.22UF
20%
X5R
402
1/20W
1%
201
6.34K
MF
10%
6.3V
201
X5R
0.1UF
X5R
6.3V
10%
01005
0.01UF
6.3V
01005
NP0-C0G
56PF
5%
1UF
402
6.3V
10%
CERM
6.3V
10%
0.01UF
X5R
01005
0.22UF
20%
402
X5R
6.3V
402
X5R
6.3V
20%
0.22UF
MF
1/20W
201
0
5%
6.3V
NP0-C0G
01005
56PF
5%
0.1UF
10%
201
X5R
6.3V
1%
201
200
1/20W
MF MF
201
1/20W
1%
200
201
MF
1%
200
1/20W
4.99K
1/32W
1%
MF
01005
0.01UF
01005
X5R
6.3V
10%
NOSTUFF
NP0-C0G
01005
6.3V
56PF
5%
0
201
MF
1/20W
5%
01005
56PF
NP0-C0G
6.3V
5%
6.3V
20%
X5R
402
0.22UF
402
0.22UF
X5R
20%
6.3V
402
0.22UF
20%
X5R
6.3V
10%
6.3V
0.1UF
X5R
201
MF
1/32W
01005
1%
4.99K
01005
X5R
6.3V
10%
0.01UF
NOSTUFF
402
1UF
10%
CERM
6.3V
201
6.3V
X5R
10%
0.1UF
6.3V
X5R
201
10%
0.1UF
0.1UF
X5R
10%
201
6.3V
0.00
MF
01005
0%
1/32W
MF
0.00
01005
0%
1/32W
0201
240-OHM-0.2A-0.8-OHM
201
X5R
10%
10V
2.2NF
10V
X5R
201
10%
2.2NF
28 43
28 43
28 43
28 43
28 43
28 43
37 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
0.1UF
201
X5R
6.3V
10%
11 43
11 43
11 43
25 43
25 43
25 43
25 43
25 43
25 43
25 43
25 43
25 43
25 43
25 42
25 42
25 42
25 42
1/32W
01005
MF
1.00K
5%
1/32W
MF
01005
1.00K
5%
1/32W
MF
01005
1.00K
5%
1/32W
MF
01005
1.00K
5%
28 43
28 43
28 43
28 43
H4G
OMIT
FCBGA
OMIT
H4G
FCBGA
SYNC_MASTER=JOE
SYNC_DATE=01/13/2011
AP: TV,DP,MIPI
132S0279 132S0154
RADAR:9624625
C0960,C0961
NET_SPACING_TYPE=PWR
PP0V4_MIPI1D
VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3MM
=PP1V8_H4
ISP_AP_1_SDA
TP_CAM0_1V2_VDDCORE_EN
ISP_AP_0_SCL
CAM0_RESET_L
ISP_AP_0_SDA
ISP_AP_1_SCL
CLK_CAM_RF
PM_FRONT_CAM_SHUTDOWN
CLK_CAM_FF_R
PM_REAR_CAM_SHUTDOWN
CLK_CAM_RF_R
NC_ISP_AP_1_PRE_FLASH
NC_ISP_AP_1_FLASH
=PP1V8_MIPI_H4
NC_MIPI0C_AP_DATA_N<3>
MIPI1C_AP_CLK_N
MIPI1C_AP_CLK_P
NC_MIPI1C_AP_DATA_N<1>
NC_MIPI1C_AP_DATA_P<1>
MIPI0C_AP_DATA_P<0>
MIPI0C_AP_DATA_N<0>
MIPI0C_AP_DATA_P<1>
NC_MIPI0C_AP_DATA_P<2>
NC_MIPI0C_AP_DATA_N<2>
NC_MIPI0C_AP_DATA_P<3>
MIPI0C_AP_CLK_N
MIPI0C_AP_DATA_N<1>
DAC_AP_VREF
DP_AP_TX_P<0>
DP_AP_AUX_N
DP_AP_AUX_P
EDP_AP_TX_P<0>
DP_AP_TX_P<2>
DP_AP_TX_N<1>
DP_AP_TX_P<1>
DAC_AP_OUT1
DP_AP_HPD
TP_DP_AP_ANALOG_TEST
AP_DP_R_BIAS
DP_AP_TX_N<2>
DP_AP_TX_N<3>
DP_AP_TX_P<3>
EDP_AP_AUX_N
EDP_AP_AUX_P
=PP1V1_EDP_PAD_DVDD_H4
AP_EDP_R_BIAS
EDP_AP_TX_N<0>
EDP_AP_TX_N<1>
EDP_AP_TX_P<2>
EDP_AP_TX_N<3>
EDP_AP_TX_P<3>
DAC_AP_COMP
DP_AP_TX_N<0>
DAC_AP_OUT2
=PP1V8_EDP_H4
DAC_AP_COMP_FTR=PP3V0_VIDEO_H4
CLK_CAM_FF
EDP_AP_HPD
EDP_AP_TX_P<1>
EDP_AP_TX_N<2>
TP_EDP_AP_ANALOG_TEST
MAX_NECK_LENGTH=3MM
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
VOLTAGE=1.8V
PP1V8_EDP_AVDD_AUX
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3MM
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.2MM
VOLTAGE=0.4V
PP0V4_MIPI0D
DAC_AP_IREF
MIPI1C_AP_DATA_N<0>
MIPI0C_AP_CLK_P
DAC_AP_OUT3
=PP3V0_VIDEO_H4
NC_MIPI_VSYNC_H4
=PP1V1_DP_PAD_DVDD_H4
MIPI1C_AP_DATA_P<0>
=PP3V0_IO_H4
=PP1V8_DP_H4
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2MM
PP1V8_DP_AVDD_AUX
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
=PP1V1_MIPI_H4
C0927
1
2
R0950
1
2
C0955
1
2
C0952
1
2
C0924
1
2
C0951
1
2
C0953
1
2
C0926
1
2
C0925
1
2
R0910
12
C0923
1
2
C0909
1
2
R0955
1
2
R0956
1
2
R0957
1
2
R0920
1
2
C0950
1
2
C0930
1
2
R0911
12
C0931
1
2
C0932
1
2
C0933
1
2
C0934
1
2
C0910
1
2
R0921
1
2
C0957
1
2
C0935
1
2
C0903
1
2
C0908
1
2
C0907
1
2
R0900
12
R0940
12
FL0910
12
C0960
1
2
C0961
1
2
C0956
1
2
R0930
1
2
R0931
1
2
R0932
1
2
R0933
1
2
U0600
G31
D32
G32
F32
D31
E32
F31 G35
G34
G33E31
AL15
C27
C28
C26
C25
D24
D23
D28
D27
B29
A26
A25
B24
B23
B28
B27
D29
F23
A29C29
E23
A27
A28
D25
D26
B25
B26
C23
C24
AJ15
A23
A24
B18
A18
E19
E18
D20
D19
C21
D18
C18
F19
F18
B20
B19
A21
F20
C22
A22
E20
D21
D22
B21
B22
C19
C20
A19
A20
U0600
AD17
AF13
AK22
AF22
AF14
AE17
AP24
AN23
A32
C35
B32
B30
A30
A33
D35
B33
B31
A31
F25
F26
E35
E34
C34
F35
F34
D34
F28
F29
G24
G25
G26
G27
G28
G29
AD15
AJ24
AK24
AH24
AL24
051-8773
10.0.0
9 OF 157
7 OF 48
45
4
10 35
26
25 42
25
42
25
42
46
46
35
43 46
43 46
43 46
43 46
43 46
43 46
45
35
35
7
35
25 42
45
45
7
35
46
35
9
35
35
45
35
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
(7 OF 12)
DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CA6
DDR0_CA7
DDR0_CA8
DDR0_CA9
DDR0_CK
DDR0_CKB
DDR0_CKE0
DDR0_CKE1
DDR0_CSN0
DDR0_CSN1
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0
DDR0_DQ1
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ2
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ3
DDR0_DQ30
DDR0_DQ31
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_NDQS0
DDR0_NDQS1
DDR0_NDQS2
DDR0_NDQS3
DDR0_PDQS0
DDR0_PDQS1
DDR0_PDQS2
DDR0_PDQS3
DDR0_VDDQ_CKE
DDR0_VREF_DQ
DDR0_ZQ
DDR1_CA0
DDR1_CA1
DDR1_CA2
DDR1_CA3
DDR1_CA4
DDR1_CA6
DDR1_CA7
DDR1_CA8
DDR1_CA9
DDR1_CK
DDR1_CKB
DDR1_CKE0
DDR1_CSN0
DDR1_CSN1
DDR1_DM0
DDR1_DM1
DDR1_DM2
DDR1_DM3
DDR1_DQ0
DDR1_DQ1
DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR1_DQ16
DDR1_DQ17
DDR1_DQ18
DDR1_DQ19
DDR1_DQ2
DDR1_DQ20
DDR1_DQ21
DDR1_DQ22
DDR1_DQ23
DDR1_DQ24
DDR1_DQ25
DDR1_DQ26
DDR1_DQ27
DDR1_DQ28
DDR1_DQ29
DDR1_DQ3
DDR1_DQ30
DDR1_DQ31
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_NDQS0
DDR1_NDQS1
DDR1_NDQS2
DDR1_NDQS3
DDR1_PDQS0
DDR1_PDQS1
DDR1_PDQS2
DDR1_PDQS3
DDR0_DQ8
DDR0_DQ9
DDR1_CA5
DDR1_VREF_DQ
DDR1_CKE1
DDR1_VDDQ_CKE
DDR1_ZQ
(8 OF 12)
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
DDR2_CA0
DDR2_CA1
DDR2_CA2
DDR2_CA3
DDR2_CA4
DDR2_CA5
DDR2_CA6
DDR2_CA7
DDR2_CA8
DDR2_CA9
DDR2_DM0
DDR2_DM1
DDR2_DM2
DDR2_DM3
DDR2_PDQS0
DDR2_NDQS0
DDR2_PDQS1
DDR2_NDQS1
DDR2_PDQS2
DDR2_NDQS2
DDR2_PDQS3
DDR2_NDQS3
DDR2_VDDQ_CKE
DDR2_VREF_DQ
DDR2_ZQ
DDR2_CK
DDR2_CKB
DDR2_CKE0
DDR2_CKE1
DDR2_CSN0
DDR2_CSN1
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8
DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
DDR3_CA0
DDR3_CA1
DDR3_CA2
DDR3_CA3
DDR3_CA4
DDR3_CA5
DDR3_CA6
DDR3_CA7
DDR3_CA8
DDR3_CA9
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_PDQS0
DDR3_NDQS0
DDR3_PDQS1
DDR3_NDQS1
DDR3_PDQS2
DDR3_NDQS2
DDR3_PDQS3
DDR3_NDQS3
DDR3_VDDQ_CKE
DDR3_VREF_DQ
DDR3_ZQ
DDR3_CK
DDR3_CKB
DDR3_CKE0
DDR3_CKE1
DDR3_CSN0
DDR3_CSN1
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
998-3125 0.5MM PT
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 40 44
13 40 44
13 44
13 44
13 40 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
13 44
13 44
13 44
13 44
13 44
01005
10%
0.01UF
NOSTUFF
6.3V
X5R
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
1.00K
1%
MF
1/32W
01005
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
1/32W
1%
MF
01005
1.00K
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
10%
01005
0.01UF
NOSTUFF
6.3V
X5R
13 44
13 44
13 44
13 44
13 44
13 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
1.00K
1%
1/32W
MF
01005
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
MF
1.00K
1/32W
1%
01005
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
H4G
FCBGA
OMIT
H4G
FCBGA
OMIT
0.01UF
01005
10%
NOSTUFF
6.3V
X5R
1/32W
1.00K
1%
MF
01005
MF
1.00K
1/32W
1%
01005
10%
01005
0.01UF
NOSTUFF
6.3V
X5R
01005
1/32W
MF
1%
1.00K
01005
1.00K
MF
1%
1/32W
0201
6.3V
X5R
0.22UF
20%
0201
6.3V
X5R
0.22UF
20%
0201
6.3V
X5R
0.22UF
20%
0201
6.3V
X5R
0.22UF
20%
MF
1%
1/20W
240
201
1/20W
240
MF
1%
201
240
1%
1/20W
MF
201
240
1%
1/20W
MF
201
10%
01005
0.01UF
6.3V
X5R
NOSTUFF
NOSTUFF
10%
01005
0.01UF
6.3V
X5R
NOSTUFF
0.01UF
10%
01005
6.3V
X5R
10%
01005
0.01UF
NOSTUFF
6.3V
X5R
13 40 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 40 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
SYNC_MASTER=MIKE
AP: DDR
SYNC_DATE=N/A
DDR1_DM<2>
DDR1_DM<0>
H4G_DDR0_ZQ
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
PPVREF_DDR1_DQ_H4
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.6V
NET_SPACING_TYPE=PWR
PPVREF_DDR1_DQ_H4
PPVREF_DDR0_DQ_H4
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
NET_SPACING_TYPE=PWR
PPVREF_DDR0_DQ_H4
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
PPVREF_DDR2_DQ_H4
NET_SPACING_TYPE=PWR
PPVREF_DDR2_DQ_H4
PPVREF_DDR3_DQ_H4
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.6V
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
PPVREF_DDR3_DQ_H4
DDR1_DQ<27>
DDR1_DQ<23>
=PP1V2_VDDIOD_H4
=PP1V2_VDDIOD_H4
=PP1V2_VDDIOD_H4 =PP1V2_VDDIOD_H4
H4G_DDR1_ZQ
=PP1V2_S2R_H4
NC_DDR1_CKE<1>
DDR1_CA<5>
DDR0_DQ<9>
DDR0_DQ<8>
DDR1_DQS_P<3>
DDR1_DQS_P<2>
DDR1_DQS_P<1>
DDR1_DQS_P<0>
DDR1_DQS_N<3>
DDR1_DQS_N<2>
DDR1_DQS_N<1>
DDR1_DQS_N<0>
DDR1_DQ<9>
DDR1_DQ<8>
DDR1_DQ<7>
DDR1_DQ<6>
DDR1_DQ<5>
DDR1_DQ<4>
DDR1_DQ<31>
DDR1_DQ<30>
DDR1_DQ<3>
DDR1_DQ<29>
DDR1_DQ<28>
DDR1_DQ<26>
DDR1_DQ<25>
DDR1_DQ<24>
DDR1_DQ<22>
DDR1_DQ<21>
DDR1_DQ<20>
DDR1_DQ<2>
DDR1_DQ<19>
DDR1_DQ<18>
DDR1_DQ<17>
DDR1_DQ<16>
DDR1_DQ<15>
DDR1_DQ<14>
DDR1_DQ<13>
DDR1_DQ<12>
DDR1_DQ<11>
DDR1_DQ<10>
DDR1_DQ<1>
DDR1_DQ<0>
DDR1_DM<3>
DDR1_DM<1>
NC_DDR1_CSN<1>
DDR1_CSN<0>
DDR1_CKE<0>
DDR1_CK_N
DDR1_CK_P
DDR1_CA<9>
DDR1_CA<8>
DDR1_CA<7>
DDR1_CA<6>
DDR1_CA<4>
DDR1_CA<3>
DDR1_CA<2>
DDR1_CA<1>
DDR1_CA<0>
=PP1V2_S2R_H4
DDR0_DQS_P<3>
DDR0_DQS_P<2>
DDR0_DQS_P<1>
DDR0_DQS_P<0>
DDR0_DQS_N<3>
DDR0_DQS_N<2>
DDR0_DQS_N<1>
DDR0_DQS_N<0>
DDR0_DQ<7>
DDR0_DQ<6>
DDR0_DQ<5>
DDR0_DQ<4>
DDR0_DQ<31>
DDR0_DQ<30>
DDR0_DQ<3>
DDR0_DQ<29>
DDR0_DQ<28>
DDR0_DQ<27>
DDR0_DQ<26>
DDR0_DQ<25>
DDR0_DQ<24>
DDR0_DQ<23>
DDR0_DQ<22>
DDR0_DQ<21>
DDR0_DQ<20>
DDR0_DQ<2>
DDR0_DQ<19>
DDR0_DQ<18>
DDR0_DQ<17>
DDR0_DQ<16>
DDR0_DQ<15>
DDR0_DQ<14>
DDR0_DQ<13>
DDR0_DQ<12>
DDR0_DQ<11>
DDR0_DQ<10>
DDR0_DQ<1>
DDR0_DQ<0>
DDR0_DM<3>
DDR0_DM<2>
DDR0_DM<1>
DDR0_DM<0>
NC_DDR0_CSN<1>
DDR0_CSN<0>
NC_DDR0_CKE<1>
DDR0_CKE<0>
DDR0_CK_N
DDR0_CK_P
DDR0_CA<9>
DDR0_CA<8>
DDR0_CA<7>
DDR0_CA<6>
DDR0_CA<5>
DDR0_CA<4>
DDR0_CA<3>
DDR0_CA<2>
DDR0_CA<1>
DDR0_CA<0>
NC_DDR3_CSN<1>
DDR3_CSN<0>
NC_DDR3_CKE<1>
DDR3_CKE<0>
DDR3_CK_N
DDR3_CK_P
H4G_DDR3_ZQ
=PP1V2_S2R_H4
DDR3_DQS_N<3>
DDR3_DQS_P<3>
DDR3_DQS_N<2>
DDR3_DQS_P<2>
DDR3_DQS_N<1>
DDR3_DQS_P<1>
DDR3_DQS_N<0>
DDR3_DQS_P<0>
DDR3_DM<3>
DDR3_DM<2>
DDR3_DM<1>
DDR3_DM<0>
DDR3_CA<9>
DDR3_CA<8>
DDR3_CA<7>
DDR3_CA<6>
DDR3_CA<5>
DDR3_CA<4>
DDR3_CA<3>
DDR3_CA<2>
DDR3_CA<1>
DDR3_CA<0>
DDR3_DQ<31>
DDR3_DQ<30>
DDR3_DQ<29>
DDR3_DQ<28>
DDR3_DQ<27>
DDR3_DQ<26>
DDR3_DQ<25>
DDR3_DQ<24>
DDR3_DQ<23>
DDR3_DQ<22>
DDR3_DQ<21>
DDR3_DQ<20>
DDR3_DQ<19>
DDR3_DQ<18>
DDR3_DQ<17>
DDR3_DQ<16>
DDR3_DQ<15>
DDR3_DQ<14>
DDR3_DQ<13>
DDR3_DQ<12>
DDR3_DQ<11>
DDR3_DQ<10>
DDR3_DQ<9>
DDR3_DQ<8>
DDR3_DQ<7>
DDR3_DQ<6>
DDR3_DQ<5>
DDR3_DQ<4>
DDR3_DQ<3>
DDR3_DQ<2>
DDR3_DQ<1>
DDR3_DQ<0>
NC_DDR2_CSN<1>
DDR2_CSN<0>
NC_DDR2_CKE<1>
DDR2_CKE<0>
DDR2_CK_N
DDR2_CK_P
H4G_DDR2_ZQ
=PP1V2_S2R_H4
DDR2_DQS_N<3>
DDR2_DQS_P<3>
DDR2_DQS_N<2>
DDR2_DQS_P<2>
DDR2_DQS_N<1>
DDR2_DQS_P<1>
DDR2_DQS_N<0>
DDR2_DQS_P<0>
DDR2_DM<3>
DDR2_DM<2>
DDR2_DM<1>
DDR2_DM<0>
DDR2_CA<9>
DDR2_CA<8>
DDR2_CA<7>
DDR2_CA<6>
DDR2_CA<5>
DDR2_CA<4>
DDR2_CA<3>
DDR2_CA<2>
DDR2_CA<1>
DDR2_CA<0>
DDR2_DQ<31>
DDR2_DQ<30>
DDR2_DQ<29>
DDR2_DQ<28>
DDR2_DQ<27>
DDR2_DQ<26>
DDR2_DQ<25>
DDR2_DQ<24>
DDR2_DQ<23>
DDR2_DQ<22>
DDR2_DQ<21>
DDR2_DQ<20>
DDR2_DQ<19>
DDR2_DQ<18>
DDR2_DQ<17>
DDR2_DQ<16>
DDR2_DQ<15>
DDR2_DQ<14>
DDR2_DQ<13>
DDR2_DQ<12>
DDR2_DQ<11>
DDR2_DQ<10>
DDR2_DQ<9>
DDR2_DQ<8>
DDR2_DQ<7>
DDR2_DQ<6>
DDR2_DQ<5>
DDR2_DQ<4>
DDR2_DQ<3>
DDR2_DQ<2>
DDR2_DQ<1>
DDR2_DQ<0>
C1056
1
2
R1055
1
2
R1056
1
2
C1054
1
2
R1053
1
2
R1054
1
2
C1084
1
2
R1083
1
2
R1084
1
2
C1096
1
2
R1095
1
2
R1096
1
2
C1020
1
2
C1021
1
2
C1022
1
2
C1023
1
2
R1020
1
2
R1021
1
2
R1022
1
2
R10234
1
2
C1057
1
2
C1058
1
2
C1095
1
2
C1085
1
2
U0600
G5
G6
H5
H6
J5
M5
M6
N6
P5
P6
P4
N4
J1
K1
K6
J6
E12
E9
C14
D6
B14
B13
B8
C8
B7
B6
C6
D7
B17
C17
B16
E17
D13
D16
E16
C15
D15
E6
B5
C5
E5
C4
D4
C12
B3
C3
D12
B11
C11
B10
C9
D9
A12
A7
A15
A4
A13
A6
A16
A3
G11
D10
M4
E15
F15
F14
E14
F13
E8
F8
F7
E7
F6
F11
F12
A10
A9
F10
E13
L5
N5
G4
R5
H2
H3
P3
R3
U3
T2
U2
R4
C2
D2
E2
E4
J3
E3
F3
F4
G2
R6
T4
U4
V1
V2
V3
J4
V4
V5
K2
L2
K4
K5
N2
P2
G1
M1
D1
R1
F1
N1
C1
T1
N7
L3
E11
U0600
AL6
AK6
AL7
AK7
AL8
AL11
AK11
AK12
AL12
AK13
AM13
AM12
AR10
AR9
AK9
AK8
AD4
AG4
AA6
AK4
AB2
AB3
AH3
AF4
AJ3
AJ2
AK3
AF5
Y2
W2
Y3
W4
AC2
Y4
AA3
AA5
AA4
AL2
AL3
AL4
AM2
AN2
AN3
AC4
AL5
AK5
AE2
AD3
AF2
AE3
AG3
AH2
AD1
AJ1
AA1
AM1
AC1
AK1
Y1
AN1
AE7
AE4
AL9
AB5
AB6
AC5
AC6
AD5
AG5
AG6
AH6
AH5
AJ6
AH4
AJ4
AF1
AG1
AE6
AD6
AM11
AL13
AM6
AK14
AP7
AM7
AL10
AP13
AP14
AM14
AL14
AN14
AP4
AP3
AN4
AM4
AP8
AP5
AN5
AN6
AM5
AN15
AM15
AP16
AM16
AR18
AP17
AN8
AN17
AM17
AN9
AP10
AP11
AN11
AN12
AM10
AR7
AR12
AR4
AR15
AR6
AR13
AR3
AR16
AJ12
AM9
AE5
051-8773
10.0.0
10 OF 157
8 OF 48
8
45
8
45
8
45
8
45
8
45
8
45
8
45
8
45
8 9
35
8 9
35
8 9
35
8 9
35
8
35
46
46
8
35
46
46
46
46
8
35
46
46
8
35
(9 OF 12)
VDD
VDD
VDDIO18_GPIO
VDDIO18_UART1_TXD0
VDD_CPU
VDDIOD
VDDIOD7
VDDIOD6
VDDIOD5
VDDIOD4
VDDIOD3
VDDIOD2
VDDIOD1
VDDIOD0
VDDIO18_XO0
VDDIO18_FUSE0_FSRC
VDDIO18_UART2_TXD
VDDIO30_USB11
VDDIO30_GPIO_3V0
VDDIO30_DP_HPD
VDDIO30_CFSB
(10 OF 12)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
FMI0-1 88MA
FMI2-3 88MA
1000MA
160MA
44MA
FMI2-3_CEN 2MA
ISP FLASH, SPI3 3MA
UART4 ?MA
GPIO30-39 4MA
2300MA
3800MA
SPI1 1MA
I2C2 1MA
C1100, C1102, C1103, C1117,
C1121, C1122, C1124, C1153,
C1154, C1155, C1156, C1158,
C1191, C1615, C1621, C1715,
C1721
10%
1UF
402
CERM
6.3V
10%
1UF
402
CERM
6.3V 6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
402
10%
1UF
CERM
6.3V
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
603
10UF
X5R
6.3V
20%
0610
20%
4V
X5R-CERM
4.3UF
603
10UF
X5R
6.3V
20%
0610
20%
4V
X5R-CERM
4.3UF
01005
10%
6.3V
X5R
0.01UF
01005
10%
6.3V
X5R
0.01UF
01005
10%
6.3V
X5R
0.01UF
01005
10%
6.3V
X5R
0.01UF
01005
0.01UF
X5R
6.3V
10%
0201
0.22UF
X5R
6.3V
20%
0201
20%
6.3V
X5R
0.22UF
0201
20%
6.3V
X5R
0.22UF
0201
20%
6.3V
X5R
0.22UF
0201
0.22UF
X5R
6.3V
20%
0201
0.22UF
X5R
6.3V
20%
01005
10%
0.01UF
6.3V
X5R
4.3UF
0610
4V
X5R-CERM
20%
10UF
603
6.3V
X5R
20%
X5R-CERM
0610
4.3UF
4V
20%
0201
20%
6.3V
X5R
0.22UF
0402-1
CERM-X5R
10UF
6.3V
20%
0201
0.22UF
X5R
6.3V
20%
6.3V
X5R
0201
0.22UF
20%
56PF
5%
NP0-C0G
01005
6.3V
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
0
5%
NAND_IO_1V8
MF
1/20W
201
NAND_IO_3V3
MF
1/20W
0
5%
201
H4G
FCBGA
OMIT
FCBGA
H4G
OMIT
01005
5%
6.3V
NP0-C0G
56PF
01005
56PF
NP0-C0G
6.3V
5%
01005
NP0-C0G
5%
56PF
6.3V
01005
NP0-C0G
5%
56PF
6.3V
01005
NP0-C0G
5%
56PF
6.3V
01005
NP0-C0G
5%
56PF
6.3V
56PF
5%
NP0-C0G
01005
6.3V
6.3V
X5R
0201
0.22UF
20%
0610
20%
4V
X5R-CERM
4.3UF
0610
20%
4V
X5R-CERM
4.3UF
0201
0.22UF
X5R
6.3V
20%
6.3V
X5R
0201
0.22UF
20%
0201
0.22UF
X5R
6.3V
20%
4V
X5R-CERM
0610
4.3UF
20%
6.3V
X5R
0201
0.22UF
20%
0610
20%
4V
X5R-CERM
4.3UF
603
10UF
6.3V
X5R
20%
0610
4.3UF
X5R-CERM
4V
20%
0201
0.22UF
X5R
6.3V
20%
0201
20%
6.3V
X5R
0.22UF
0201
20%
6.3V
X5R
0.22UF
01005
10%
6.3V
X5R
0.01UF
6.3V
X5R
0201
0.22UF
20%
0201
0.22UF
X5R
6.3V
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
0610
4.3UF
X5R-CERM
4V
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
X5R-CERM
4V
0610
4.3UF
20%
0610
4V
4.3UF
X5R-CERM
20%
4.3UF
X5R-CERM
4V
0610
20%
6.3V
56PF
5%
NP0-C0G
0100501005
NP0-C0G
5%
56PF
6.3V
6.3V
X5R
0201
0.22UF
20%
138S0657138S0702
QTY 17 RADAR:8837828
C1100,C1102
SYNC_MASTER=MIKE
SYNC_DATE=N/A
AP: POWER
=PPVDD_SOC_H4
=PPVDD_CPU_H4
=PPVDD_SOC_H4
=PP1V2_VDDIOD_H4
=PP3V0_VDDIOD_H4
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.8V
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
PPIO_NAND_H4
=PP1V8_VDDIOD_H4
=PP1V8_VDDIO18_H4
=PP3V0_IO_H4
=PP1V8_NAND_H4
=PP3V3_NAND_H4
C1197
1
2
C1196
1
2
C1192
1
2
C1195
1
2
C1124
1
2
C1132
1
2
C1131
1
2
C1122
1
2
C1121
1
2
C1130
1
2
C1129
1
2
C1191
1
2
C1194
1
2
C1103
1
2
C1102
1
2
C1111
1
2
C1110
1
2
C1109
1
2
C1104
1
2
C1108
1
2
C1159
1
2
C1160
1
2
C1161
1
2
C1162
1
2
C1163
1
2
C1164
1
2
C1165
1
2
C1166
1
2
C1154
1
2
C1155
1
2
C1156
1
2
C1152
1
2
C1151
1
2
C1184
1
2
C1170
1
2
C1171
1
2
C1174
1
2
C1173
1
2
C1172
1
2
C1183
1
2
C1181
1
2
C1182
1
2
C1101
1
2
C1100
1
2
C1123
1
2
C1117
1
2
C1105
1
2
C1107
1
2
C1106
1
2
C1126
1
2
C1125
1
2
C1135
1
2
C1134
1
2
C1133
1
2
C1138
1
2
C1137
1
2
C1136
1
2
C1150
1
2
C1153
1
2
C1157
1
2
C1158
1
2
C1175
1
2
C1190
1
2
C1193
1
2
C1177
1
2
C1176
1
2
C1199
1
2
C1198
1
2
R1100
12
R1101
12
U0600
AA9
AA11
AC11
U25
U27
V10
V12
V14
V16
W9
W11
W13
W15
AD10
W17
Y10
Y12
Y14
Y16
AE11
AF10
AF11
AF12
AG10
AG11
AG12
AG13
AA13
J13
J15
J17
J19
J21
J23
J25
J27
K12
K14
AA15
K16
K18
K20
K22
K24
K26
L9
L11
L13
L15
AA17
L17
L19
L21
L23
L25
L27
M10
M12
M14
M16
AB10
M18
M20
M22
M24
M26
N9
N11
N13
N15
N17
AB12
N19
N21
N23
N25
N27
P10
P12
P14
P16
P18
AB14
P20
P22
P24
P26
R9
R11
R13
R15
R17
R19
AB16
R21
R23
R25
R27
T10
T12
T14
T16
T18
T20
AC9
T22
T24
T26
U11
U13
U15
U17
U19
U21
U23
U0600
AA19
AA21
AC19
AC21
AC23
AC25
AC26
AC27
AD18
AD20
AD22
AD24
AA23
AD26
AE19
AE21
AE23
AE25
AE27
V18
V20
V22
V24
AA25
V26
W19
W21
W23
W25
W27
Y18
Y20
Y22
Y24
AA27
Y26
AB18
AB20
AB22
AB24
AB26
N29
AJ17
AJ22
AJ25
AJ26
T8
V28
V8
AF15
AJ28
M29
N28
Y8
AH20
AK20
AL19
AK30
AH29
AE29
AF29
AB29
AC29
AA7
AB7
AJ10
AJ11
G7
G8
G9
G10
G12
G13
G14
G15
AC7
G16
H7
J7
K7
L7
M7
P7
R7
AD7
AF7
AG7
AH7
AJ7
AJ8
AJ9
C1140
1
2
C1141
1
2
C1142
1
2
C1144
1
2
C1143
1
2
C1145
1
2
C1146
1
2
051-8773
10.0.0
11 OF 157
9 OF 48
9
35
35
9
35
8
35
35
6
45
5
35
35
7
35
35
35
IN
OUT
OUT
OUT
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
0101
0100
J2A DEV
J2A AP
1111 RESERVED
1101 FMI0/1 4/4 CS
010
CURRENT SETTING ->
001
011
EVT
PROTO 2
100
0100 FMI0 2CS
0010 SPI0 W/TEST
0011 SPI1 W/TEST
0000 SPI0
0101 FMI0 4CS
0111 RESERVED
1000 FMI1 2 CS
BOOT_CONFIG[3:0]
0110 FMI0 4CS W/TEST
1010 FMI1 4CS W/TEST
1001 FMI1 4 CS
1100 FMI0/1 2/2 CS
FOR REFERENCE
0001 SPI1
PROTO 1 CHINA
PROTO 1 LOCAL
3. READ
BOARD REVISION
PROTO 0
000
BRD_REV[2-0]
1110 FMI0/1 4/4 CS W/TEST
2. ENABLE PU AND DISABLE PD
1. SET GPIO AS INPUT
S/W READ FLOW
0001
J2 DEV
J2 AP
J1 AP
0000
BOARD_ID[2]
BOARD_ID[1]
BOARD_ID[0]
BOARD_ID[3-0]
J1 DEV
BOARD_ID_3
BOARD ID
DEVELOPMENT_JTAG
2-WIRE DAP
SCAN DUMP
JTAG_DAP
PRODUCTION
3. READ
3. READ
JTAG_DAP
DEVELOPMENT_JTAG
S/W READ FLOW
JTAG
I2C PULL-UPS
0010
0011
1. SET GPIO AS INPUT
1110
1101
1100
FMI0/1 4/4 CS
BOOT_CONFIG[3-0]
BOOT_CONFIG[3] (GPIO29)
BOOT_CONFIG[0] (GPIO18)
BOARD_ID[3]
2. DISABLE PU AND ENABLE PD
FMI0/1 4/4 CS WITH TEST
FMI0/1 2/2 CS
BOOT_CONFIG[1] (GPIO25)
BOOT_CONFIG[2] (GPIO28)
S/W READ FLOW
BOOT CONFIG ID
2. DISABLE PU AND ENABLE PD
DEVELOPMENT_JTAG_TAP
1. SET GPIO AS INPUT
MF
5%
01005
1/32W
10K
J2
4
42
4
42
4
10 42 45
11 27 43
11 27 43
11 27 43
4
4
10 42 45
201
5%
1/20W
10K
MF
5%
1/20W
10K
201
MF
1/32W
MF
5%
01005
10K
NOSTUFF
5%
01005
1/32W
MF
DEV
10K
J2A
1/32W
10K
MF
5%
01005
SHORT-01005
NOSTUFF
SHORT-01005
NOSTUFF
NOSTUFF
SHORT-01005
100K
MF
1/32W
01005
5%
01005
5%
MF
1/32W
10K
1.00K
5%
1/32W
MF
01005
1.00K
5%
1/32W
MF
01005
1.00K
1/32W
MF
01005
5%5%
01005
MF
1/32W
1.00K
5%
1/32W
MF
01005
1.00K
5%
1/32W
MF
1.00K
01005
NOSTUFF
201
5%
MF
1/20W
10K
JTAG_DAP
100
DEVELOPMENT_JTAG_TAP
1/32W
0.00
0%
MF
01005
1/32W
0.00
0%
MF
DEVELOPMENT_JTAG_TAP
01005
100
JTAG_DAP
1/32W
0.00
0%
MF
DEVELOPMENT_JTAG_TAP
01005
1/20W
10K
MF
201
5%
201
MF
1/20W
5%
10K
NOSTUFF
MF
10K
201
5%
1/20W
SYNC_DATE=N/A
AP: MISC & ALIASES
SYNC_MASTER=ALEX
=PP1V8_H4
PP3V0_SENSOR_FLT
I2C0_SCL_1V8
I2C1_SDA_1V8
I2C2_SDA_3V0_ALS
I2C1_SCL_1V8
AP_TESTMODE
BOARD_ID_1
BOOT_CONFIG_1
BOOT_CONFIG_2
=PP1V8_H4
=PP1V8_H4
BOOT_CONFIG_0
BOOT_CONFIG_3
JTAG_AP_TRST_L
AP_FAST_SCAN_CLK
VIDEO_EMI_C_Y
VIDEO_EMI_Y_PR
VIDEO_EMI_CVBS_PB
JTAG_AP_TDO
JTAG_AP_TDI
JTAG_AP_TRST_L
AP_TST_STPCLK
JTAG_AP_SEL
AP_HOLD_RESET
USB_AP_VBUS1
BOARD_ID_2
I2C2_SCL_3V0_ALS
I2C0_SDA_1V8
BOARD_ID_0
GPIO42_BRD_REV2
GPIO41_BRD_REV1
GPIO40_BRD_REV0
R1205
1
2
R1202
1
2
R1210
12
R1212
12
R1213
12
R1211
12
R1214
12
R1207
1
2
R1208
1
2
R1209
1
2
R1201
1
2
R1200
1
2
R1203
1
2
R1206
1
2
R1204
1
2
XW1201
12
XW1200
12
XW1202
12
R1260
12
R1261
12
R0706
1
2
R0705
1
2
R0704
1
2
R0703
1
2
R0702
1
2
R0701
1
2
051-8773
10.0.0
12 OF 157
10 OF 48
4 7
10 35
24 26 45
5
19 22 37 42
5
25 42
24 25 42
5
25 42
4
5
5
5
4 7
10 35
4 7
10 35
5
5
4
4
4
4
5
24 25 42
5
19 22 37 42
5
5
5
5
RX_VHIGH/USB_2D+
TX_VHIGH/USB_2D-
CH.3_OUT
CH.2_OUT
CH.1_OUT
VID_EN
USB_1D-
USB_1D+
SEL
DGNDAGND
CH.1_IN
CH.2_IN
CH.3_IN
USB_D-
USB_D+
RX_VLOW
TX_VLOW
VA_1
VDH
VA_0
VDL
OUT
OUT
OUT
OUT
IN
OUT
IN
BI
BI
BI
BI
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CVBSIN
BB USB <-> H4P FS USB
DOCK_BB_EN = 0:
DOCK_BB_EN = 1:
BB USB <-> DOCK SERIAL
NOTE:
H4P UART0 <-> DOCK SERIAL
NOTE: PLACE R0960-62 NEAR U0900
CIN
YIN
~15MA
THS7380IZSYR
UCSP
CRITICAL
10 27 43
10 27 43
75
1/20W
MF
1%
201
JTAG_DAP
201
MF
1%
75
JTAG_DAP
1/20W
201
1%
MF
75
JTAG_DAP
1/20W
10 27 43
6.3V
0.1UF
10%
X5R
201
MF
100K
5%
1/32W
01005
27 42
27 42 15 42
15 42
30 42
30 42
4
42
4
42
7
43
7
43
7
43
01005
6.3V
5%
NP0-C0G
56PF
6.3V
0.1UF
10%
X5R
201
100K
5%
MF
01005
1/32W
5
37
1/32W
01005
5%
1.00M
MF
RADAR:9009078
U1300
343S0539 343S0520
AP: VIDEO BUFFER,BB USB MUXES
SYNC_DATE=12/10/2010
SYNC_MASTER=CHOPIN
=PP3V0_VIDEO_BUF
BUF_C_Y
USB11_ACC_RX_P
=PP3V2_S2R_USBMUX
BUF_Y_PR
PORT_DOCK_VIDEO_AMP_EN
DAC_AP_OUT1
DAC_AP_OUT3
DAC_AP_OUT2
VIDEO_EMI_CVBS_PB
VIDEO_EMI_Y_PR
VIDEO_EMI_C_Y
USB11_MUX_D0_N
DOCK_BB_EN
BUF_CVBS_PB
USB11_MUX_D0_P
USB11_ACC_TX_N
USB_BB_D_N
USB_BB_D_P
UART0_MUX_RXD
UART0_MUX_TXD
U1300
B2
B3
A3 A2
A4 A1
B4 B1
D3
E3
E1
E4
C2
D1
D4
F1
F2
F4
F3
C1
C4E2D2
C3
R1360
12
R1361
12
R1362
12
C1370
1
2
R1372
1
2
C1301
1
2
C1300
1
2
R1320
1
2
R1315
1
2
051-8773
10.0.0
13 OF 157
11 OF 48
35
43
35
43
43
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IO0-1
IO7-1
IO6-1
IO3-1
IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0
IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1
WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQ
VSS
VCCQ
VDDI
TMSC
TCKC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IO0-1
IO7-1
IO6-1
IO3-1
IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0
IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1
WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQ
VSS
VCCQ
VDDI
TMSC
TCKC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
NC
NC
NC
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
LEAVE VREF AS TP FOR MLB
DO NOT PLACE IN NAND SINGLE PCS SHIELD CAN AREA
TEST POINTS
LEAVE VREF AS TP FOR MLB
10UF
CERM-X5R
0402-1
6.3V
20%
CERM
402-LF
2.2UF
6.3V
20%
0.1UF
10%
201
6.3V
X5R
6
12 44
6
44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
44
6
12 44
6
12 44
6
12 44
6
12 44
MF
1/20W
1%
243
201
0.1UF
10%
201
6.3V
X5R
CERM-X5R
0402-1
10UF
6.3V
20%
0402-1
CERM-X5R
10UF
6.3V
20%
0402-1
CERM-X5R
6.3V
20%
10UF
LGA
OMIT
XXNM-XGBX8-MLC-PPN1.5-ODP
6.3V
X5R
0201-MUR
1.0UF
20%
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
MF
1/20W
5%
1K
NOSTUFF
201
1K
5%
1/20W
MF
NOSTUFF
201
0402-1
CERM-X5R
10UF
6.3V
20%
402-LF
CERM
2.2UF
6.3V
20%
0.1UF
10%
201
6.3V
X5R
0.1UF
10%
201
6.3V
X5R
CERM-X5R
0402-1
10UF
6.3V
20%
CERM-X5R
0402-1
10UF
6.3V
20%
0402-1
CERM-X5R
10UF
6.3V
20%
6
44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
OMIT
XXNM-XGBX8-MLC-PPN1.5-ODP
LGA
MF
1/20W
1%
243
201
6.3V
X5R
1.0UF
20%
0201-MUR
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
MF
1/20W
5%
1K
NOSTUFF
201
1K
MF
5%
1/20W
NOSTUFF
201
0.22UF
6.3V
X5R
0201
20%
0.22UF
6.3V
X5R
0201
20%
0.22UF
6.3V
X5R
0201
20%
0.22UF
6.3V
X5R
20%
0201
0.22UF
6.3V
X5R
0201
20%
0.22UF
6.3V
X5R
0201
20%
0.22UF
6.3V
X5R
0201
20%
0.22UF
6.3V
X5R
0201
20%
5%
1/32W
MF
01005
100K
01005
MF
1/32W
5%
100K
NAND_IO_3V3
MF
1/20W
0
5%
201
MF
0
5%
NAND_IO_1V8
201
1/20W
6.3V
X5R
0201-MUR
20%
1.0UF
6.3V
X5R
0201-MUR
1.0UF
20%
SYNC_DATE=N/A
NAND
SYNC_MASTER=MIKE
FMI0_AD<0>
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
VOLTAGE=1.8V
PPVCCQ_NAND
=PP3V3_NAND
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
MAX_NECK_LENGTH=3MM
PPVDDI_NAND_U1400
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.2MM
FMI1_AD<0>
FMI0_ALE
FMI0_WE_L
=PP3V3_NAND
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MM
PPVDDI_NAND_U1410
PPVCCQ_NAND
VOLTAGE=1.8V
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
FMI1_RE_N
FMI0_RE_N
FMI0_AD<1>
=PP1V8_NAND
FMI0_AD<7>
FMI1_CLE
FMI0_RE_N
FMI0_AD<2>
FMI0_AD<1>
FMI1_AD<2>
FMI1_AD<1>
FMI1_AD<0>
FMI0_AD<7>
FMI0_AD<6>
FMI0_AD<5>
FMI0_AD<4>
FMI0_AD<0>
FMI0_ALE
FMI0_CLE
FMI0_WE_L
FMI0_CE1_L
FMI0_CLE
FMI0_ALE
FMI0_WE_L
FMI0_RE_N
FMI1_CLE
FMI1_ALE
FMI1_WE_L
FMI1_RE_N
FMI1_DQS_P
TP_VREF_SLOT1
FMI_ZQ_U1410
FMI_TCKC_U1400
FMI1_DQS_P
FMI1_ALE
FMI0_DQS_P
FMI0_CE0_L
FMI1_CE0_L
FMI0_AD<0>
FMI0_AD<3>
FMI0_AD<2>
FMI0_AD<4>
FMI1_AD<5>
FMI1_AD<4>
FMI1_AD<3>
FMI1_AD<6>
FMI1_AD<7>
FMI1_AD<1>
FMI1_AD<0>
FMI0_AD<5>
FMI0_CLE
FMI1_AD<2>
FMI1_RE_N
FMI1_ALE
FMI1_WE_L
FMI1_CLE
FMI_TMSC_U1400
FMI0_AD<6>
FMI1_AD<5>
FMI_ZQ_U1400
TP_VREF_SLOT0
FMI1_WE_L
FMI_TMSC_U1410
FMI_TCKC_U1410
FMI1_AD<7>
FMI1_AD<6>
FMI1_CE1_L
FMI0_DQS_P
NAND_SLOT1_RDYBSY_L
FMI1_AD<4>
FMI1_AD<3>
FMI0_AD<3>
NAND_SLOT0_RDYBSY_L
=PP3V3_NAND
TP1400
1
TP1401
1
TP1402
1
TP1403
1
TP1404
1
TP1405
1
TP1406
1
TP1407
1
TP1408
1
TP1409
1
C1432
1
2
C1431
1
2
C1430
1
2
R1474
1
2
C1424
1
2
C1422
1
2
C1421
1
2
C1420
1
2
U1410
C1
D2
A5
C5
A3
C3
H4
F4
M4
K4
G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7
E5
E7
B4
C7
D4
D6
OA0
OB0
B6F2M6N1N7
OC8
OD8
OE0
OF8G0OA8
OB8
G5
B2F6L3A7M2
OC0
OD0
OE8
OF0
G8
E3
E1
A1
C1470
1
2
R1473
1
2
R1472
1
2
C1412
1
2
C1411
1
2
C1410
1
2
C1404
1
2
C1402
1
2
C1401
1
2
C1400
1
2
U1400
C1
D2
A5
C5
A3
C3
H4
F4
M4
K4
G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7
E5
E7
B4
C7
D4
D6
OA0
OB0
B6F2M6N1N7
OC8
OD8
OE0
OF8G0OA8
OB8
G5
B2F6L3A7M2
OC0
OD0
OE8
OF0
G8
E3
E1
A1
R1454
1
2
C1450
1
2
R1453
1
2
R1452
1
2
C1413
1
2
C1414
1
2
C1434
1
2
C1433
1
2
C1406
1
2
C1405
1
2
C1426
1
2
C1425
1
2
R1455
1
2
R1475
1
2
R1401
12
R1400
12
C1451
1
2
C1471
1
2
051-8773
10.0.0
14 OF 157
12 OF 48
12 45
12 35
45
6
12 44
12 35
12 45
6
12 44
35
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
12 35
CK_1
DQ13_2
DQ14_2
DQ2_2
DQ1_2
DQ0_2
CKB_2
CKE_2
DQ21_1
DQ12_1
DQ11_1
DQ10_1
DQ0_1
DQ1_1
DQ2_1
DQ3_1
DQ4_1
DQ5_1
CSB_1
CKE_1
CKB_1
CA9_1
CA8_1
CA7_1
CA6_1
CA5_1
CA4_1
CA3_1
CA2_1
CA1_1
CA0_1
DQSB2_1
DQS2_1
DQ20_1
DQ19_1
DQ22_1
DQ23_1
DQ18_1
DQ16_1
DQ17_1
DQ15_1
DQ14_1
DQ13_1
DQ9_1
DQ7_1
DQ8_1
DQ6_1
DQ24_1
DQ31_1
DQ30_1
DQ31_2
DQ29_2
DQ30_2
DQ28_2
DQ26_2
DQ27_2
DQ25_2
DQ24_2
DQ23_2
DQ21_2
DQ22_2
DQ20_2
DQ19_2
DQ18_2
DQ17_2
DQ16_2
DQ15_2
DQ12_2
DQ11_2
DQ10_2
DQ8_2
DQ9_2
DQ6_2
DQ7_2
DQ5_2
DQ4_2
DQ3_2
DQSB3_2
DQS3_2
CA7_2
CA8_2
CA9_2
CK_2
DQS1_2
VREFCA_1 VREFCA_2
VREFDQ_1 VREFDQ_2
ZQ_1 ZQ_2
DQSB3_1
DQSB2_2
DQSB1_2DQSB1_1
DQSB0_2DQSB0_1
DQS3_1
DQS2_2
DQS1_1
DQS0_2DQS0_1
DQ29_1
DQ28_1
DQ27_1
DQ26_1
DQ25_1
CA6_2
CA5_2
CA4_2
CA3_2
CA2_2
CA1_2
CA0_2
DM0_1
DM1_1
DM2_1
DM3_1
CSB_2
DM0_2
DM1_2
DM2_2
DM3_2
DDR_1
DDR_2
SYM 1 OF 2
VDD1_3
VDD1_1
VSS55
VSS51
VSS6
VSS49
VSS4
VSS3
VDDQ33
VDDCA1
VDDCA2
VSS46
VDD1_0
VDD1_8
VDD1_5
VDD1_6
VDD1_7
VSS52
VSS0
VSS2
VSS7
VSS9
VSS10
VSS13
VSS18
VSS20
VSS32
VSS33
VSS34
VSS42
VSS43
VSS44
VSS29
VSS28
VSS27
VSS26
VSS25
VSS23
VSS22
VSS47
VSS53
VSS48
VSS50
VSS1
VSS12
VDD1_11
VDD2_3
VDD2_2
VDD1_2
VDD2_6
VDD2_7
VDD2_13
VDD2_14
VDD2_16
VDDQ27
VDDQ32
VDDQ31
VDDQ
VDDQ6
VDDQ23
VDDQ30
VDDQ22
VDDQ16
VDDQ34
VDDQ17
VDDQ21
VDDQ19
VDDQ24
VDDQ20
VDDQ28
VDDCA3
VDDCA4
VDDCA5
VDDCA6
VDDCA7
VDDCA8
VDD2_1
VDDQ26
VDDQ25
VSS24
VDD2_9
VDD2_8
VDDQ1
VDD1_9
VDD1_10
VDDCA9
VDDCA10
VDDQ29
VDDQ3
VDD1_4
VDD2_5
VDD2_4
VDD2_15
VSS41
VSS40
VSS39
VSS54
VSS36
VSS35
VDD2_10
VDD2_11
VDD2_12
VSS45
VDD2VDDQ
VDDCA
VDD1
VSS
SYM 2 OF 2
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
XXXMB
BGA
H4G-DRAM
OMIT
XXXMB
H4G-DRAM
BGA
OMIT
4.3UF
4V
X5R-CERM
0610
20%
603
10UF
6.3V
X5R
20%
56PF
NP0-C0G
01005
5%
6.3V
6.3V
X5R
0201
0.22UF
20%
56PF
NP0-C0G
01005
5%
6.3V
0.01UF
10%
01005
6.3V
X5R
6.3V
X5R
0201
0.22UF
20%
10V
10%
0.01UF
X5R
201
01005
0.01UF
10%
6.3V
X5R
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
1UF
10%
CERM
402
6.3V
10%
CERM
1UF
402
6.3V
CERM
10%
1UF
402
6.3V
402
10%
CERM
1UF
6.3V
X5R-CERM
4V
0610
4.3UF
20%
10UF
603
6.3V
X5R
20%
603
10UF
6.3V
X5R
20%
NP0-C0G
01005
56PF
5%
6.3V6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
6.3V
X5R
0201
0.22UF
20%
10%
01005
0.01UF
6.3V
X5R
5%
56PF
01005
NP0-C0G
6.3V
0.01UF
01005
10%
6.3V
X5R
6.3V
X5R
0201
0.22UF
20%
10%
402
CERM
1UF
6.3V
6.3V
X5R
0201
0.22UF
20%
10%
402
CERM
1UF
6.3V
6.3V
X5R
0201
0.22UF
20%
603
10UF
6.3V
X5R
20%
MF
1/20W
1%
240
201
MF
1/20W
1%
240
201
2.21K
1%
1/32W
MF
01005
NOSTUFF
10%
01005
0.01UF
6.3V
X5R
01005
MF
2.21K
1%
1/32W
01005
MF
1%
1/32W
2.21K
NOSTUFF
10%
01005
0.01UF
6.3V
X5R
01005
2.21K
1%
MF
1/32W
01005
MF
1%
1.00K
1/32W
NOSTUFF
10%
01005
0.01UF
6.3V
X5R
01005
1%
1/32W
1.00K
MF
01005
1/32W
MF
1%
1.00K
NOSTUFF
0.01UF
10%
01005
6.3V
X5R
0.01UF
10%
01005
6.3V
X5R
01005
1.00K
MF
1%
1/32W
NOSTUFF
0.01UF
01005
10%
6.3V
X5R
0.01UF
01005
10%
NOSTUFF
6.3V
X5R
0.01UF
01005
10%
NOSTUFF
6.3V
X5R
0.01UF
01005
10%
NOSTUFF
6.3V
X5R
6.3V
X5R
0201
0.22UF
20%
SYNC_MASTER=MIKE
DDR 0 AND 1
SYNC_DATE=06/21/2010
PPVREF_DDR0_CA
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
PPVREF_DDR0_CA
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
PPVREF_DDR0_DQ
NET_SPACING_TYPE=PWR
PPVREF_DDR0_DQ
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
PPVREF_DDR1_CA
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
PPVREF_DDR1_CA
PPVREF_DDR1_DQ
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.6V
PPVREF_DDR1_DQ
DDR1_DM<3>
DDR1_DM<1>
DDR0_DQ<8>
=PP1V2_VDDQ_DDR
DDR0_DQ<30>
DDR0_DQ<27>
DDR1_DQ<5>
DDR0_DQ<1>
DDR0_DQ<2>
DDR0_DQ<3>
DDR0_DQ<4>
DDR0_DQ<5>
DDR0_DQ<6>
DDR0_DQ<10>
DDR0_DQ<13>
DDR0_DQ<24>
DDR0_DQ<25>
DDR0_DQ<26>
DDR0_DQ<28>
DDR0_DQ<12>
DDR0_DQ<11>
DDR0_DQ<0>
DDR0_DM<2>
DDR0_DM<3>
DDR0_DM<0>
DDR0_DQ<7>
DDR0_DQS_N<2>
=PP1V2_S2R_DDR
DDR1_DQ<30>
DDR1_DQ<26>
DDR0_DQ<18>
DDR1_DQ<25>
DDR0_DQ<14>
DDR0_DQ<9>
DDR0_DQ<15>
DDR1_DQ<7>
DDR1_DQ<6>
DDR1_DQ<4>
DDR1_DQ<3>
DDR1_DQ<2>
DDR1_DQ<1>
DDR1_DQ<0>
DDR1_DQ<8>
DDR1_DQ<9>
DDR1_DQ<10>
DDR1_DQ<11>
DDR1_DQ<12>
DDR1_DQ<14>
DDR1_DQ<15>
DDR1_DQ<13>
DDR0_DQS_P<3>
=PP1V2_S2R_DDR
=PP1V8_S2R_DDR
DDR1_DQS_P<0>
DDR1_DQS_N<1>
=PP1V2_VDDQ_DDR
=PP1V2_VDDQ_DDR
=PP1V2_S2R_DDR
=PP1V2_S2R_DDR
DDR0_CSN<0>
DDR1_DM<2>
DDR1_DM<0>
DDR0_CA<0>
DDR0_CA<1>
DDR0_CA<2>
DDR0_CA<3>
DDR0_CA<4>
DDR0_CA<5>
DDR0_CA<6>
DDR1_DQ<17>
DDR1_DQ<18>
DDR1_DQ<19>
DDR1_DQ<20>
DDR1_DQ<21>
DDR1_DQS_P<1>
DDR1_DQS_P<2>
DDR1_DQS_N<0>
DDR0_DQS_N<1>
DDR0_DQS_N<3>
DDR1_DQS_N<2>
DDR0_ZQDDR1_ZQ
DDR0_CK_P
DDR0_CA<9>
DDR0_CA<8>
DDR0_CA<7>
DDR0_DQS_P<2>
DDR0_DQ<29>
DDR0_DQ<31>
DDR0_DQ<23>
DDR1_DQ<22>
DDR1_DQ<23>
DDR1_DQ<16>
DDR1_DQ<24>
DDR1_DQ<31>
DDR1_DQ<27>
DDR1_DQ<28>
DDR1_DQS_P<3>
DDR1_DQS_N<3>
DDR1_CA<0>
DDR1_CA<1>
DDR1_CA<4>
DDR1_CA<5>
DDR1_CA<6>
DDR1_CA<7>
DDR1_CA<8>
DDR1_CA<9>
DDR1_CK_N
DDR1_CKE<0>
DDR1_CSN<0>
DDR1_DQ<29>
DDR0_CKE<0>
DDR0_CK_N
DDR1_CK_P
DDR0_DM<1>
DDR1_CA<3>
DDR1_CA<2>
DDR0_DQ<16>
DDR0_DQ<22>
DDR0_DQ<19>
DDR0_DQ<20>
DDR0_DQ<17>
DDR0_DQS_P<1>
DDR0_DQS_N<0>
DDR0_DQS_P<0>
DDR0_DQ<21>
C1622
1
2
C1621
1
2
C1620
1
2
C1623
1
2
C1613
1
2
C1619
1
2
C1605
1
2
C1612
1
2
C1618
1
2
C1604
1
2
C1611
1
2
C1610
1
2
C1617
1
2
C1603
1
2
C1616
1
2
C1602
1
2
C1615
1
2
C1601
1
2
C1614
1
2
C1609
1
2
C1608
1
2
C1607
1
2
C1606
1
2
C1631
1
2
C1635
1
2
C1630
1
2
C1634
1
2
C1629
1
2
C1633
1
2
C1628
1
2
C1632
1
2
C1627
1
2
R1620
1
2
R1621
1
2
R1605
1
2
C1650
1
2
R1606
1
2
R1651
1
2
C1652
1
2
R1652
1
2
R1653
1
2
C1654
1
2
R1654
1
2
R1655
1
2
C1656
1
2
R1656
1
2
C1660
1
2
C1662
1
2
C1663
1
2
C1661
1
2
C1626
1
2
C1625
1
2
C1624
1
2
U1600
T15 G16
U15 G17
U14 H17
V14 H18
T13 J16
T9 N16
U9 N17
U8 P17
V8 P18
T7 R16
U12 K17
U11 L17
V13 J18
U13 J17
C12 K3
B10 M2
B16 G4
D7 T2
C15 G3
B8 P5
C8 P4
D8 P3
E8 P2
B7 R4
C7 R3
B18 B2
C18 C2
D18 D3
E18 D2
D15 G2
B17 E4
D17 E3
E17 E2
E16 F2
B6 T5
B5 U5
C5 U4
D5 U2
B4 V5
C4 V4
B14 H5
B3 V3
C3 V2
C14 H4
D14 H3
E14 H2
B13 J3
C13 J2
C9 N4
D9 N3
D13 J4
D10 M4
C16 F4
D6 T3
D12 K4
C10 M3
D16 F3
C6 T4
U10 M17
D11 L4
U7 R17
U1600
A2
B1
W17
U19
B11
F17
L2
M16
T10
U18
V17
V6
E11
W5
W16
W19
W18
V19
A3
T19
E19
L5
M18
U17
T18
V10
V16
V18
F18
T8
H16
K16
L16
P16
T11
T12
T14
V7
E1
U1
J5
K2
N2
R5
A8
A10
A14
A13
C17
C19
H1
E10
E15
B12
U3
W3
M1
P1
A17
D4
A16
A1
D19
E12
E13
F16
A4
G18
J1
K18
K5
L18
L3
M5
N18
N5
A6
R18
R2
T1
T17
U16
U6
B15
V11
V12
V15
T6
V9
W1
W4
A18
B19
C1
E7
G5
T16
V1
W2
A19
B9
C11
D1
051-8773
10.0.0
16 OF 157
13 OF 48
13 44 45
13 44 45
13 44 45
13 44 45
13 44 45
13 44 45
13 44 45
13 44 45
8
44
8
44
8
44
13 14 35
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
44
8
40 44
8
44
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