Apple A1181, K36 Schematics

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK
APPD

DATE

ENG
APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

8/9/2007

MK

MK

REFERENCED FROM M70

MK

MM-MARY(YUAN) MA

LD-LINDA DUNN

LT-LAWRENCE TAN

MK-MARC KLINGELHOFER

RC-RAY CHANG

DK-DINESH KUMAR

RX-RAYMOND XU

ES

Schematic / PCB #’s

LT

LD

RX

LT

ES

ES

MK

MK

MK

MK

RX

ES

RX

ES

LD

ES

ES

RX

RX

DK

RX

RX

ES

RX

ES

ES

MK

MK

MK

RX

RX

RX

ES

ES

LD

LD

LD

LT

LT

RX

DK

LD

LT

LT
LT

LT

RX
RX

DK
DK

RX

LD

ES

RX

MK

ES

RX

RX

RX

RX

LD

RX
MK

MKRX

RX

ES

RX

RX

LD

K36 MLB SCHEMATIC

ES

K36 EE DRIS:

LT

DVT BUILD

22

SB Power & Ground

Page

07/17/2006

45

50

GPU

SMC SUPPORT

10/30/2006

44

49

T9_MLB

SMC

09/05/2006

43

48

USB

IR CONTROLLER & BT INTERFACE

06/29/2006

42

47

USB

CONNECTOR MISC

06/30/2006

41

46

USB

USB EXTERNAL CONNECTORS

07/17/2006

40

45

GPU

SATA CONNECTOR

07/17/2006

39

44

GPU

PATA CONNECTOR

07/17/2006

38

43

GPU

FIREWIRE PORT

08/30/2005

37

40

ENET

FIREWIRE CONTROLLER

09/14/2006

36

39

USB

ETHERNET CONNECTOR

10/07/2006

35

38

USB

Yukon Power Control

10/07/2006

34

37

USB

Ethernet (Yukon)

08/19/2005

33

34

ENET

06/20/2005

33

MEMORY

Memory Active Termination

06/20/2005

31

32

MEMORY

DDR2 SO-DIMM Connector B

06/20/2005

30

31

MEMORY

DDR2 SO-DIMM Connector A

06/06/2006

29

30

DSIMON-WF

Clock Termination

06/06/2006

28

29

DSIMON

Clock (CK505)

07/26/2005

27

28

NB

SB Misc

06/01/2006

26

27

WFERRY

SB Decoupling

10/30/2006

25

26

T9_MLB

10/30/2006

24

25

T9_MLB

SB Pwr Mgt, GPIO, Clink

10/30/2006

23

24

T9_MLB

SB PCI, PCIe, DMI, USB

10/30/2006

23

T9_MLB

SB Enet, Disk, FSB, LPC

06/15/2006

21

22

WFERRY

NB Graphics Decoupling

06/15/2006

20

21

WFERRY

NB Standard Decoupling

10/30/2006

19

20

T9_MLB

NB Grounds

10/30/2006

18

19

T9_MLB

NB Power 2

10/30/2006

17

18

T9_MLB

NB Power 1

10/30/2006

16

17

T9_MLB

NB DDR2 Interfaces

10/30/2006

15

16

T9_MLB

NB Misc Interfaces

10/30/2006

14

15

T9_MLB

NB PEG / Video Interfaces

10/30/2006

13

14

T9_MLB

NB CPU Interface

5/23/05

12

13

MASTER

CPU ITP700FLEX DEBUG

04/26/2006

11

12

MSARWAR

CPU Decoupling & VID

11/12/2006

10

11

T9_MLB_NOMECPU Power & Ground

11/12/2006

9

10

T9_MLB_NOME

CPU FSB

07/17/2006

8

9

GPU

SIGNAL ALIAS /RESET

06/15/2006

7

8

WFERRY

Power Aliases

07/25/2005

6

7

TP

FUNC TEST 1 OF 2

N/A

5

5

N/A

Revision History

07/18/2005

4

4

SMC

06/30/2005

3

3

POWER

Power Block Diagram

05/11/2006

2

2

WFERRY-WF

System Block Diagram

76

06/12/2006

WFERRY

106

FireWire & SMC Constraints

75

06/12/2006

WFERRY

105

Clock Constraints

74

06/12/2006

WFERRY

104

SB Constraints (2 of 2)

73

06/12/2006

WFERRY

103

SB Constraints (1 of 2)

72

06/08/2006

WFERRY

102

Memory Constraints

71

06/12/2006

WFERRY

101

NB Constraints

70

06/08/2006

WFERRY

100

CPU/FSB Constraints

69

05/21/05

EUGENE

94

MINI-DVI CONNECTOR

68

06/06/2005

GRAPHIC

92

EXTERNAL TMDS

67

06/23/2006

GPU

90

INVERTER,LVDS,TMDS

66

08/19/2005

SMC

79

65

06/12/2006

DSIMON-WF

78

S3 FET & S3/S5 Control

64

12/06/2005

ENET

77

3.42V/1.25V Switcher

63

07/13/2005

POWER

76

5V/3.3V Supplies

62

07/13/2005

POWER

75

1.8V/0.9V Supplies

61

07/13/2005

POWER

73

1.5V / 1.05V Supplies

60

06/29/2006

GPU

72

Render VCore Supplies

59

07/13/2005

POWER

71

IMVP6 CPU VCore Regulator

58

05/31/2006

DSIMON-WF

70

S0 FETS & Power Sequencing

57

07/13/2005

POWER

69

DC-In & Battery Connectors

56

03/12/2007

M70AUDIO

68

AUDIO: JACK TRANSLATORS

55

03/12/2007

M70AUDIO

67

AUDIO: JACK

54

03/12/2007

M70AUDIO

66

AUDI0: SPEAKER AMP

53

03/12/2007

M70AUDIO

62

AUDIO: CODEC

52

04/26/2006

WFERRY

61

SPI ROMs

51

08/23/2005

SMC

59

SMS

50

11/10/2005

ENET

56

Fan

49

06/21/2006

GPU

55

TEMPERATURE SENSE

48

07/17/2006

GPU

53

CPU Current & Voltage Sense

47

06/01/2006

WFERRY

52

SMBUS CONNECTIONS

SCHEM,MLB,K36

?

? ??

?

761

01

051-7455

46

06/01/2006

WFERRY

51

LPC+ Debug Connector

09/05/2006

1

1

USB

Table of Contents

Page

Contents

Sync

(.csa)

Date

SCHEM,MLB,K36

051-7455 CRITICAL

SCH

1

PCBF,MLB,K36

820-2279 CRITICAL

PCB

1

Contents

Sync

(.csa)

Date

CONFIGURATION OPTIONS

32

PBUS Supply/Battery Charger

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Core ~1.2V

2.? GHz

U1000

PG 49

PG 49

HEAT-PIPE/FIN

U5920 SUDDEN MOTION DETECT PG 51

J5100

PG 44

POWER SENSE PG 48

FAN CONN PG 50

PG 46

Bluetooth

J4810

PG 41PG 43PG 42PG 43

J4850

PG 56

PG 55

PG 54

Pg 53

Pg 37

PG 38

Pg 34

Pg 36

PG 39

PG 40

J4501

PG 57-67

PG 57

PCI-E

1.05 - 1.25V

Core

NB-GMCH

CPU

800/1066? MHz

Pg 14

TMDS

U9200

SDVO

J9401

DVI-I

GPIO

PG 68

GPIOs

CONTROLLER

U4800

Pg 22

Pg 15

J9001

MUX

Out

RGB

LVDS

Pg 14

DMI

Pg 17,18,19

U1400

64-Bit

J4600

USB

Connectors

J4601

J4700

Geyser

Trackpad/Keyboard

3G

CONNECTOR

IR

PG 44

Pg 22

J3201

J3101

Pg 13

U5500

U5520

J5601

8

Core 1.05V

SB-ICH8

CLnk 0

Pg 24

97

CAMERA

SATA-0

U2300

Pg 23

Codec

Audio

Conns

Audio

Amps

Speaker

U6600/10/20

TRANSLATORS

JACK

J6702/03 INTERNAL SPEAKER

J6701 INTERNAL MIC
J6750/00 LINE IN/OUT

J4300

FW32306

J3900

J4401

PG 54

J3201

J3101

ITP CONN

PG 12

J1302

FSB

Main Memory

x4 DMI

2.5 GHz

TV

Boot ROM

DC/Batt

Supply

Conn

533/667/800? MHz

Pg30,31

Pg 24

LPCSMB

Pg 24

Pg 22

SATA

SATA-2SATA-1

Pg 23

PCI-E

UATA

Pg 22

Ln6Ln5Ln4Ln3Ln2Ln1

Conn

FireWire

U4000

32-Bit

33 MHz

E-NET

Conn

E-NET

NINEVEH

U3700

AirPort

Mini PCI-E

Pg 33

J3400

U6200

CPU

Temp Sense

Power

J6900/50

LPC Conn

Prt

Ser

Fan

SPI

U6100/50

UC500

U2900

Clk Gen

DIMM’s

Pg 23

USB

AZALIA

Pg 23

PCI

Pg 24

CLnk 1

Pg 22

E-NET

Pg 25

Core

4321 5 6

Pg 23

SPIDMI

Conn

UATA

Conn

SATA

Pg 15/16

DIMM

1.8V - 64 Bits

DDR2 - Dual Channel

Pg 15

Pg 15

CLnk 0

Pg 32

Term

Parallel

Misc

Clocks

U2900

CK 505

Pg 29

TERMS

Pg 28

Pg 9

Pg 10

A

B,0 BSA BSB

ADC

SMC

U4900

PG 69

Int Disp

PG 67

Conn

01

76

SYNC_DATE=05/11/2006

System Block Diagram

2

SYNC_MASTER=WFERRY-WF

051-7455

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

K36 POWER SYSTEM ARCHITECTURE

Q7859

07

5VS5_RUNSS

3.3V

Q3810

Q7001

TPS62510

1.25V S0

ENA

PP4V5_AUDIO_ANALOG

VOUT

(PAGE 21)

U2265

TPS731125

MCH DPLL

R7502

18

VOUT2

PP1V5_S0_REG

PP1V8_S3_REG

Q7006

19

15

PP1V8_S3_REG_R

PP3V3ENET_SS

15

P1V25_S0_NB_DPLL

15

Q7007

(10.75A MAX CURRENT)

0.9V

1V25S0_RUNSS

RUNSS_GATE_D

Q7006

START

(S0)

GFX_VR_EN

Q7004

CHGR_EN

Q7860

17-1

PM_ENET_EN_L

PPBUS_G3H

SMC_BATT_ISENSE

01

U7970

A

VOUT

MAX8719

VIN

U7950

D7950

U7975

ENRGYSTR LDO

SMC_ENRGYSTR_LDO_EN

6A FUSE

SHGN*

(PAGE 66)

VOUT

GPU_VCORE

U7200

ISL6263

(PAGE 60)

02

ENA

VIN

21

(7.7A MAX CURRENT)

PPVCORE_S0_NB_GFX_IMVP

(PAGE 62)

TPS51116

1.8V

02

15

P1V8S0_EN

SMC_PM_G2_EN

LOGIC

PPVBAT_G3H_CHGR_REG

IMVP_VR_ON

ENA2

TPS51120

(PAGE 63)

PP1V2_ENET_REG

RSMRST_PWRGD

PGOOD1,2

(PAGE 59)

U7100

VR_ON

02

PGOOD

CLKEN#

VOUT

CPUVCORE

ISL9504

VIN

CHGR_EN

(S5)

ENABLES

VIN

ISL6257HRZ

U7900

(PAGE 66)

VOUT

SMC_DCIN_ISENSE

A

BATTERY

3S2P

BATT_POS_F

Q7860

11

PM_SLP_S4_L

PM_SLP_S3_L

PM_S4_STATE_L

ICH

DELAY

(S3)

12

P3V3S3_EN_L

RC

RC
DELAY

(S3)

P5VS3_EN_L

12

Q3802

Q3801

PM_ENET_EN_L

IN

AC

ADAPTER

DCIN

ENA1

(S5)

3V3S5_RUNSS

PP1V05_S0_REG

VR_PWRGD_CK505_L

PGOOD_1V05S0

PGOOD2

VOUT2

PP3V42_G3H_REG

VOUT2

VOUT1

02

PPBUS_G3H

PPDCIN_G3H

D6901

SMC_ADAPTER_EN

PM_SLP_S3_L

1V8S3_RUNSS

S5

1V5S0_RUNSS
(S0)

WOL_EN

04-1

START

SOFT

P25

06

(S5)

17

17

A

12

S3

U7870

14

18

17

18

18

16

15

17

SOFT
START

U7500

PP0V9_S0_REG

U5300

PPVCORE_CPU_S0

(36A MAX CURRENT)

P5VS0_EN

(7.5A MAX CURRENT)

09

CURRENT)

PP3V3_S5_REG

Q7865

(4A MAX CURRENT)

PP1V5_S0_REG

(8A MAX CURRENT)

PGOOD_1V5S0

SMC_CPU_VSENSE

Q7000

Q7866

(5A MAX

PP5V_S5_REG

24

29

28

27

26

30

23

22

20

19

VOUT1

14

(PAGE 45)

VLDOIN

13

P1V8_S0_FET

16

P5VS3_EN_L

PP5V_S3

4.5V AUDIO
TPS79501

U6201

TPS51124

U7300

VOUT

(PAGE 35)

PP3V3_S5

CLK_PWRGD

PM_SB_PWROK

17

17

15

13

15

15

15

15

14

GATE B

GATE D

P3V3S0_EN

P1V8S0_EN

RUNSS_GATE_D

ISL6130IRZA

5V

13

12

10

CPUPWRGD(GPIO49)

PWROK

09

05

08

PP5V_S5

VR_PWRGOOD_DELAY

08

07

04

03

02

02

7A FUSE

FSB_CPURST_L

RSMRST_OUT(P15)

IMVP_VR_ON(P16)

PLT_RST*

PWR_BUTTON(P90)

P17(BTN_OUT)

SLP_S3_L

SLP_S5_L

BATTERY ONLY:

SMC_ONOFF_L

ALL_SYS_PWRGD

U2801

PP1V8_S0_FET

PM_SLP_S3_L

PP3V3_S0_FET

PGOOD_1V8S3
PP5V_S0_FET

(PAGE 58)

ENA*

U7000

P5VS0_EN

VOUT

SMC_CPU_ISENSE

U4900

RST*

RSMRST_IN(P13)

(PAGE 9)

PWRGOOD

U2300

(PAGE 22)

RSMRST*

PWRBTN*

PLTRST*

(PAGE 28)

U2900

SLG8LP537V

CLOCK

PP1V05_S0_REG_R

R7302

3.425V G3HOT

PGOOD1

VOUT1

1V5S0_RUNSS

(S0)

(S0)

1V05S0_RUNSS

(S5)

SMC

U4900

Q7007

1V05S0_RUNSS
(S0)

SOFT

VIN

ADAPTER IN :

VREG3

1.2V YUKON

ENA

ENA

VIN

IMVP_VR_ON

HCPURST*

99ms DLY

Q7859

MAX8516

U7790

U7600

(PAGE 44)

SMC_RESET_L

SLP_S5_L(P95)

PM_RSMRST_L

PM_PWRBTN_L

P60

VIN

1.05V

VIN

SLP_S4_L

SLP_S4_L(P94)
SLP_S3_L(P93)

(PAGE 13)

U1400

CRESTLINE

CPU

VIN

RESET*

PLT_RST_L

ENA1

ENA2

CPU_PWRGD

SMC

ENA

U3830

V

SMC_RESET_L

U5000

RN5VD30A-F

SMC PWRGD

ENABLE

(PAGE 64)

(PAGE 45)

LT3470

PBUSB_VSENSE

(PAGE 61)

Q5350

1.5V

ICH8M

VRMPWRGD

CK_PWRGD

PWRGD

VIN

PWROK

U1000

VR_PWRGOOD_DELAY

25

V

18

U2803

VR_PWRGD_CK505

PP5V_S0_FET

PM3V3ENET_SS

P3V3_ENET_FET

GATE C

RST*

19

RESET*

SENSE

PP1V25_S0_REG

PP1V9_ENET_REG

17

18

RSMRST_PWRGD

PWRGD(P12)

TPS3808-1.25V

U7200

VIN

VIN
ENA

PP3V3_ENET_FET

16

GATE A

P3V3S0_EN

12

(PAGE 58)

MR*

VOUT

U3820

TPS79501DRB

1.9V S3

(PAGE 64)

U7720

VOUT

(PAGE 53)

P3V3S3_EN_L

1V25S0_RUNSS

(PAGE 35)

PGOOD_SEQUENCER

UVLO_A
UVLO_B
UVLO_C
UVLO_D

PBUS CONVERTER/
BATTERY CHARGER

23

01

06-1

10-1

17-1

PP1V25_S0_FET

PP3V3_S3

PP3V3_S0_FET

16

PGOOD_1V05S0

PGOOD_1V5S0

3

01

SYNC_DATE=06/30/2005

SYNC_MASTER=POWER

Power Block Diagram

76

051-7455

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

SIGNAL

Signal aliases required by this page:

NBCFG_PEG_REVERSE

0.031

0.076

Page Notes

(NONE)

NBCFG_DMI_X2

>

>
>

>

>

>

>

BOMOPTION

0.014

0.014

TOTAL

0.014

L8-L9

>> > >

BOM OPTION

630-7935

TRACE WIDTH

(MM)

>
>

>> >>

>>

>

>

>

>

>

>

> >

>

>> >>

>

>>
>

CONCEPT

>

L4 SIGNAL

INVERTER_UNBUF

>

ISL6130

NBCFG_SDVO_AND_PCIE

ITP

0.1

YUKON_ULTRA

>>

> >

> > > >

LAYER

COMMON

LPCPLUS

0.018

L7-L8

BETTER

L1-L2

YUKON_EC

ISL6126

NBCFG_DMI_REVERSE

L1 SIGNAL(TOP)

CONFORMAL_COAT

GOOD

BEST

---

0.07

L11-L12

L12 SIGNAL(BOTTOM)

L6-L7

L7 POWER

L5-L6

L4-L5

L5 GND

L6 POWER

L2 GROUND

L2-L3

L3 SIGNAL

THICKNESS

0.014

0.076

0.014

0.014

1.276

0.156

0.047

0.07

0.076

(MM)

0.047

0.1

0.1

---

0.1

0.1

---

---

(NONE)

(NONE)

L3-L4

0.156

0.014

0.076

0.07

MLB STACKUP

---

0.079

ODD_PWR_RESUME

ODD_PWR_CORE

STANDOFF

FANCY

NORMAL

M70 GOOD

ARB_ONLY

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

K36

K36_PGM

K36 GOOD

K36 BETTER K36 BEST

630-9104 630-9105 630-9106

EVT

EVT EVT

L10 SIGNAL

0.031

0.07

0.079

NBCFG_DYN_ODT_DISABLE

NO_REBOOT_MODE

INVERTER_BUF

ALTERNATE

Power aliases required by this page:

BOM options provided by this page:

GROUND

POWER
POWER

GROUND
SIGNAL(High Speed)
SIGNAL(High Speed)

GROUND

GROUND

SIGNAL

BOTTOM

11

10

9

8

7

6

5

3

2

Top

L9-L10

L9 SIGNAL

BOARD STACK-UP AND CONSTRUCTION

LOCKED BOOTROM PN 341S2197

L11 GROUND

L10-L11

0.076

SIGNAL(High Speed)

SIGNAL(High Speed)

4

BOM TABLE FOR HF POSCAPS

---

0.014

L8 GROUND

CONFORMAL_COAT

0.018

PAGE_BORDER=TRUE

SYNC_MASTER=SMC

01

4 76

SYNC_DATE=07/18/2005

051-7455

K36
K36

CRITICAL

EEE:Z57

1

CRITICAL BEST

826-4393

EEE:Z56

CRITICAL1BETTER

826-4393

EEE:Z55

826-4393

1

CRITICAL GOOD

CRITICAL

K36

GOOD

BEST

U1000

2

CRITICAL

1

1

CRITICAL

CRITICAL

BETTER

CRITICAL

U1000

1

1

U1000

U2300

U1400

516-0162

338S0434

343S0448

LBL,P/N LABEL,PCB,28MMX6MM

LBL,P/N LABEL,PCB,28MMX6MM

LBL,P/N LABEL,PCB,28MMX6MM

1

IC,16MBIT 8PIN SPI SERIAL FLASH,SOIC8

341S2196

K36_PGM

CRITICAL

IC,CYPRESS,CY7C63833,ENCORE_II,USB_CONTR

341S2093

K36_PGM

U4800

1

341S2198

IC,SMC,HS8/2116

1

CRITICAL

U4900

341S2060

IC,EEPROM,SERIAL IIC,8KBIT,SO8

1

K36_PGM

CRITICAL

CONFIGURATION OPTIONS

CRITICAL

4

C4610,C4611,C6830,C6831

K36

128S0147 HF VERSION OF 128S0057

CRITICAL

K36

HF VERSION OF 128S0085

C6605

K36

CRITICAL

HF VERSION OF 128S0111

C7220,C7352,C7542

CRITICAL

K36

C2130,C2716,C7543

K36

CRITICAL

3

128S0164

6

HF VERSION OF 128S0115

C6204,C6205,C7651,C7652,C7691,C7692

CRITICAL

K362

HF VERSION OF 128S0113

C2173,C2700

CRITICAL

K36

128S0157

1

HF VERSION OF 128S0122

C2220

IN-LINE SODIMM CONNECTOR

IC,ICH8,BGA

IC,CRESTLINE,GM965,667

IC,MDC,SR,E1,2.0G,800FSB,4M,BGA

IC,MDC,SR,G0,2.2G,800FSB,4M,BGA

IC,MDC,SR,G0,2.2G,800FSB,4M,BGA

1

337S3463

337S3500

337S3500

J3101,J3201

U6100
U3780

CRITICAL

K36_PGM

CRITICAL

K361

128S0162 HF VERSION OF 128S0123

C2140

K36

CRITICAL

128S0135 HF VERSION OF 128S0129

2

C6601,C6603

HF VERSION OF 128S0073

1
3

128S0150

128S0160

128S0148

128S0169

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- ALL 128S0122 BECOME 128S0157.

- ALL 128S0115 BECOME 128S0150.

- ADD ISOLATION BUFFER FOR ODD_RESET_L SIGNAL, ADD 100K PULL-DOWN TO ODD_PWR_EN_L, ADD ’DRAG’ CIRCUIT TO

- LOWER RDS(ON) MOSFET (FDC606P - APN: 376S0552) FOR ODD AND LCD POWER - RADAR: TBD

- HIGH-PRECISION 0.1% RESISTORS TO INCREASE OUTPUT VOLTAGE REGULATION (5V, 3.3V, PBUS_LDO) ACCURACY - RADAR:4972500

- FIX LINDA CARD POWER ALIAS (NEED TO CONNECT TO PP3V42_G3HOT INSTEAD OF PP3V3_S5) - RADAR: 4927858

- CHANGE BOM STUFFING TO SPEED UP PORT POWER SHUT-OFF RESPONSE TIME DURING ACTIVE LATE-VG EVENT (RADAR: 4985252)

- CHANGE BOM STUFFING TO ENABLE ON-BOARD MICROPHONE CONNECTOR (M42/M42A SOLUTION) INSTEAD OF ROUTING

- CHANGE BEST CPU FROM 337S3465(2.4GHZ) TO 337S3464(2.2GHZ).

- ADD BOM OPTION TABLE FOR ALL SANYO POSCAP TO USE HF PARTS.

CSA PAGE 4:

- ADD OMIT TO ALL ABOVE PARTS SO THE HF PARTS IN BOM TABLE TAKE OVER.

- ALL 128S0129 BECOME 128S0135.

- ALL 128S0123 BECOME 128S0162.

- ALL 128S0113 BECOME 128S0160.

- ALL 128S0111 BECOME 128S0169.

- ALL 128S0085 BECOME 128S0148.

- ALL 128S0073 BECOME 128S0164.

- ALL 128S0057 BECOME 128S0147.

PER CE, ALL SANYO POSCAPS HAVE NEW HF PART NUMBERS.

8/9/2007

M70 EVT TO DVT CHANGES

M70 EVT TO DVT CHANGES

- TEST POINT MOVEMENTS REQUESTED BY ICT AND MAC-1 GROUPS - RADAR: 4924481

- MODIFY FIREWIRE CONNECTOR SYMBOL TO SUPPORT MINI-DVI CONNECTOR WITH TAB

- CHANGE 10UF, 16V CPU VCORE CAPS TO 10UF, 6.3V CAPS - RADAR: 4952553

- CHANGE LOAD CAP STUFFING OPTION FOR RTC AND ETHERNET CRYSTALS TO MEET 5XESR (-R) REQUIREMENT

PROPERLY DISCHARGE ODD POWER WHEN IT’S TURNED OFF - RADAR: 4923903

M70 PROTO TO EVT CHANGES

- ADD 270K PULL-DOWN RESISTOR ON HTPLG - RADAR: 4888755

- MOVE SMC RESET BUTTON PAD TO TOP SIDE OF MLB - RADAR: 4920913

CSA PAGE 8:

- 4954357 BREAK OUT =PP3V3_S3_AIRPORT_AUX(J3400,PIN 24) FROM PP3V3_S3_AP_AUX AGAIN.

- 4954357 MOVE C3409 AND C3410 FROM PP3V3_S3_AP_AUX RAIL TO =PP3V3_S3_AIRPORT_AUX RAIL.

- NORMAL CHANGES FROM 514-0409 TO 514-0459, FANCY CHANGES FROM 514-0411 TO 514-0479.

- CHANGE J6750 FROM 514-0408 TO 514-0458 (DIFFERENT JEDEC, SAME LANDPATTERN).

- UPDATE BOM OPTION TABLE FOR J6750.

- NORMAL CHANGES FROM 514-0408 TO 514-0458, FANCY CHANGES FROM 514-0410 TO 514-0478.

- CHANGE J6700 FROM 514-0409 TO 514-0459 (DIFFERENT JEDEC, SAME LANDPATTERN).

- CHANGE R9201 AND R9202 FROM 5.23K TO 2.94K.

- NORMAL CHANGES FROM 514-0375 TO 514-0480, FANCY CHANGES FROM 514-0376 TO 514-0481.

- CHANGE L7900 FROM 152S0302 TO 152S0670 FOR CORRECT AVL.

- SMC PART NUMBER CHANGES FROM 341S2088 TO 341S2198.

CSA PAGE 29:

- ADD ALIAS =PP3V3_S3_SMBUS_SMC_MGMT TO PP3V3_S3.

- UPDATE EEE CODES, Z55 FOR GOOD, Z56 FOR BETTER, Z57 FOR BEST.

CSA PAGE 32:

- STUFF C3110 AND C3111.

CSA PAGE 31:

CSA PAGE 9:

- FIX MOJO-CARD SMC TX, RX REVERSAL - RADAR: 4910888

CSA PAGE 90:

- CHANGE SB FROM 338S0427 TO 338S0434.

- CHANGE J3900 FROM 514S0143 TO 514-0443.

- REMOVE NO_TEST=TRUE FOR 1V8S3_COMP, 1V8S3_FSET, 3V3S5_COMP, 3V3S5_FSET, 1V05S0_COMP, 1V05S0_FSET, IMVP6_RBIAS, IMVP6_COMP, 5VS5_RUNSS, 1V5S0_RUNSS.

- REMOVE ALIASES FOR GND_CHASSIS_AUDIO_SPKRCONN,GND_CHASSIS_AUDIO_SHIELD1,GND_CHASSIS_AUDIO_SHIELD2,GND_CHASSIS_AUDIO_SHIELD3,MIC_SHIELD_LVDS_R,MIC_SHLD_CONN.

- ADD FUNC_TEST=TRUE FOR THRM_FINSTACK_P/N.

7/6/2006

- CHANGE U5500 FROM M70 EMC1033 CIRCUIT TO M71 EMC1043 CIRCUIT.

- CHANGE J4810 FROM 518S0369 TO 518S0521.

- CHANGE C2700 FROM 128S0051 TO 128S0113 PER CE.

7/5/2006

- CHANGE R2514 TO 100K.
CSA PAGE 29:

- RENAME CPU_VID_R<6:0> TO CPU_VID<6:0>.

CSA PAGE 71:

- ADDED R6856 NO STUFF.

- CONNECTED MIC_SHLD_CONN TO GND_CHASSIS_AUDIO_MIC THROUGH R6854.

CSA PAGE 68:

- ADDED R6740 NO STUFF.

- REMOVED DZ6772.

- ADDED L6771 AND L6773 TO MIC INPUT EMI FILTER.

- CHANGED ALL TRANSIENT SUPPRESSORS TO 6.8V/100PF DEVICES (WERE ORIGINALLY 8V/100PF DEVICES).

CSA PAGE 67:

- ADDED SMALL 15PF COMPENSATION CAP. TO U6201 FEEDBACK NETWORK (C6224).

- ADDED A NO STUFF PULL-UP TO CODEC_DVDD AT GPIO1.

- RE-CONNECTED /SHDN INPUT OF U6801 SO THAT IT’S CONTROLLED BY U6200 PORTA VREF. - DISCONNECTED GPIO1 AND TERMINATED IT WITH A 10K PULL DOWN.

CSA PAGE 62:

- RE-DRAW CPU VOLTAGE SENSE RC FILTERING.

CSA PAGE 53:

- REMOVE TEXT NOTE WILL CHANGE TO 606P.

CSA PAGE 44:

- CHANGE R2902 FROM 1OHM TO 0OHM.

- CHANGE R2900, R2901 FROM 2.2OHM TO 0OHM.

- NOSTUFF C2907, C2910, C2916, C2911, C2914.

- CHANGE L2902 AND L2903 FROM 155S0302 TO 0OHM R2906 AND R2907.

- ADD R2597 AND R2596 FOR 10K PU ON GPIO6 AND GPIO17(EXTGPU_RST_L).

CSA PAGE 25:

- RENAME LVDS_VREFH/L TO TP_LVDS_VREFH/L.

CSA PAGE 15:

- DELETE TEXT NOTE AND WITH RESET BUTTON.

CSA PAGE 13:

- REMOVE R1290 TO R1296 ON CPU_VID<0:6>.

CSA PAGE 12:

- ADD SPN ALIASES FOR CK505_PCI2/4_CLK.

- ADD SPN ALIASES FOR TP_CK505_SRC7_N/P.

- REMOVE ALIAS FOR =FWPWR_PWRON.

CSA PAGE 9:

- ADD FUNC_TEST=TRUE FOR PP1V05_S0_R.

- REMOVE NO_TEST=TRUE FOR CK505_PCI4_CLK_SPN, CK505_SRC1_N/P_SPN, CK505_SRC3_N/P_SPN, CK505_SRC7_N/P_SPN, CK505_SRC_CLKREQ1/3_L?SPN.

CSA PAGE 8:

- CHANGE J9000 FROM 518S0369 TO 518S0521.

CSA PAGE 90:

- CHANGE J6703 FROM 518S0369 TO 518S0521.

- CHANGE J6702 FROM 518S0487 TO 518S0519.

CSA PAGE 67:

- CHANGE J5601 FROM 518S0369 TO 518S0521.

CSA PAGE 56:

- J5550 CHANGES FROM 2PIN TO 4PIN.

CSA PAGE 55:

CSA PAGE 48:

6/29/2007

M70 DVT TO K36 CHANGES

- REMOVE R4660 AND R4601 (U4675 BYPASS RESISTORS).

CSA PAGE 46:

- CHANGE J2800 FROM 518S0487 TO 518S0519.

CSA PAGE 28:

CSA PAGE 27:

- CHANGE C2173 FROM 128S0051 TO 128S0113 PER CE.

CSA PAGE 21:

- REPLACE ALL M70 WITH K36 (TEXT, BOM OPTIONS, 630 NUMBERS).

CSA PAGE 4:

- 5040728 CHANGE L9404 FROM 155S0303 TO 155S0348.

CSA PAGE 94:

- REPLACE BATTERY INTERFACE CIRCUIT WITH THE ONE ON M42B ESTAR.

- CHANGE J6900 FROM 518S0287 TO 518S0526.

CSA PAGE 69:

- CHANGE J4700 FROM 516S0251 TO 516S0588.

CSA PAGE 47:

- ADD NOSTUFF R4660 AND R4661.

- REMOVE MIN_NECK_WIDTH=0.3MM FROM PP5V_S3_USB2_EXTA/B.

- CHANGE U4600 FROM 353S1245 TO 353S1728.

CSA PAGE 46:

- EDIT BOM OPTION TABLE.

CSA PAGE 39:

- CHANGE STRAPPING FROM 0010 ON GFX_VID<1:4> TO 0001 ON GFX_VID<0:3>.

- CHANGE GFX_VID<1:4> TO GFX_VID<0:3>.

- SIZING DOWN R2205 FROM 0603 TO 0402 FOR PLACEMENT.

- 5282756 ADD C2207 (0.1UF, 0402).

CSA PAGE 22:

- ADD R1600 (0OHM, 0402) TO CONNECT GFX_VID<4> TO GND.

- CONNECT GFX_VID<0:3> TO GFX_VID0:3 ON NB.

- DISCONNECT GFX_VID<0> TO GND.

CSA PAGE 16:

- CHANGE NB FROM 338S0426(500M) TO 343S0448(667M).

- CHANGE BEST CPU FROM 337S3457(2.2G) TO 337S3465(2.4G).

- CHANGE BETTER CPU FROM 337S3456(2.0G) TO 337S3464(2.2G).

- CHANGE GOOD CPU FROM 337S3471(1.8G) TO 337S3463(2.0G).

CSA PAGE 4:

CSA PAGE 49:

- 5040728 STUFF C9421 FOR EMI.

3/5/2007

- 5048817 SYNC 1P25V REGULATOR CIRCUIT FROM M82, CHANGE R AND C TO 0402, CHANGE =PP3V3_S5_P1V25S0 TO =PP3V3_S5_1V25S0,
C7723 FROM 2.2NF TO 10000PF, C7724 FROM 22PF TO 100PF, C7728 FROM 2.2NF TO 10000PF,
AND REVERT REFERENCE DESIGNATORS. (CHANGE FROM TPS62510 TO LTC3412A)

3/12/2007

- 4924443 CHANGE R2514 FROM 100K PULL-UP TO 47K PULL-UP.

CSA PAGE 45:

- 4924443 CHANGE R2514 FROM 100K PULL-DOWN TO 10K PULL-UP TO 3.3V_S5.

- 4986074 CHANGE L2205 TO R2205(100OHM,5%,1/10W,0603).

CSA PAGE 69:

- ADD TEXT NOTE TO UPDATE J4700 FROM 516S0251 TO 516S0588 WHEN SYMBOL IS READY.

- 4986074 CHANGE R9469 FOR CRT_TVO_IREF FROM 1.3K TO 1.21K.

- ADD TEXT NOTE TO UPDATE J6900 FROM 518S0287 TO 518S0526 WHEN SYMBOL IS READY.

- DELETE LVDS_VREFH AND LVDS_VREFL TO GROUND TO FIX LVDS GLITCH.

- ADD TEXT NOTE TO CHANGE L9404 FROM 155S0303 TO 155S0348 WHEN SYMBOL IS READY.

CSA PAGE 77:

- SYNC FROM AUDIO TEAM.

3/14/2007
CSA PAGE 47:

CSA PAGE 94:

CSA PAGE 79:

- UPDATE SYMBOL FOR J4501.

CSA PAGE 22:

- NO STUFF 3G CONNECTOR CIRCUITRY

CSA PAGE 62,66,67,68:
CSA PAGE 67:

CSA PAGE 25:

3/8/2007

CSA PAGE 25:

CSA PAGE 62,66,67,68:

- SYNC FROM AUDIO TEAM.

CSA PAGE 94:

MICROPHONE THROUGH LVDS CABLE

CSA PAGE 34:

- 5029811 CHANGE Q7940 FROM 376S0326 TO 376S0558.

- 4999533 SWAP PIN 2 AND PIN 3 OF MIC CONNECTOR, BACK TO M42 PIN OUT.

Revision History

- WAKE-ON-WIRELESS SUPPORT - RADAR: 4954357

CSA PAGE 4:

CSA PAGE 8:

- ADD CRITICAL TO U2900.
CSA PAGE 44:

- ADD CRITICAL TO U4401.
CSA PAGE 46:

CSA PAGE 49:

CSA PAGE 52:

- STUFFED R6740.
CSA PAGE 68:

- NO STUFFED R6854
CSA PAGE 72:

CSA PAGE 50:

- SMC MANAGEMENT SMBUS CONNECTION:

7/10/2007

- BOOTROM PART NUMBER CHANGES FROM 341S2085 TO 341S2196.

- SMB_ME_CLK AND SMB_ME_DATA ON SOUTHBRIDGE DISCONNECTED FROM SMB_MGMT_CLK AND SMB_MGMT_DATA FROM SMC.B

- THE 10K PULL-UP RESISTORS (R5230 AND R5231), AND STILL REMAIN CONNECTED TO PP3V3_S5_SMBUS_SB_ME AND STAY ON THE SB SIDE.

- ADD TWO NEW 10K PULL-UP RESISTOR (R5232 & R5233) TO =PP3V3_S3_SMBUS_SMC_MGMT.B
CSA PAGE 59:

- ICH8-M ME SMBUS:

- CHANGE R5077 FROM PULL-UP TO A PULL-DOWN RESISTOR AND NAME IT SMC_SMS_INT.

- REMOVE ALIAS FOR =SMC_SMS_INT TO SMC_PG1 - SIGNAL SHOULD JUST BE CALLED SMC_SMS_INT.

- ADD R4670 & R4671. (USB BYPASS ROUTING).

- CHANGE U4675 FROM APN 353S1505 TO APN 353S1742. (SMALL PACKAGE)

CSA PAGE 59:

CSA PAGE 46:

CSA PAGE 67:

CSA PAGE 39:
CSA PAGE 50:

CSA PAGE 62:

CSA PAGE 67:

7/11/2007

- CHANGE R7208 FROM 8.66K TO 15.8K.

- MADE DZ6702, DZ6703, DZ6704, DZ6705, DZ6752, DZ6753, DZ6754, DZ6755, DZ6770, DZ6771B CRITICAL.

- REMOVED NO STUFF RESISTORS R6730, R6731, AND R6732. ALSO REMOVED L6774.

- MADE NO_TEST ATTRIBUTE VISIBLE FOR NET NC_VRP CONNECTED TO PIN 37 OF U6200.

- CHANGED C6210 FROM A CASE-R 10UF TANT. CAP. TO A SMA-LF 3.3UF TANT. CAP.

-ADD 2ND SMS (U5930).

- THE PULL-UP RESISTORS SHOULD BE CONNECTED BETWEEN SMB_MGMT_CLK AND SMB_MGMT_DATA TO =I2C_SMS_SCL AND =I2C_SMS_SDA OF THE NEW ACCELEROMETER.

- STUFF U5930 (DIGITAL ACCELEROMETER) CIRCUIT.

- STUFF C3210 AND C3211.

- REMOVE R5077 (BECOMES R5931).

- ADD R5931 (WAS R5077 BEFORE), 10K PD ON SMC_SMS_INIT.

- ADD R5930, 10K PU ON SMC_SMS_INT.

- UPDATE PN FOR FANCY RJ45 CONNECTOR, 514-0475.

- CHANGE Z0901 AND Z0906 FROM 998-1178 TO 998-1186 (NON-PLATED).

- 4954357 ADD =PP3V3_S3_AIRPORT_AUX BACK TO PP3V3_S3 ALIAS.

- UPDATE BOM OPTION TABLE FOR J6700.

7/17/2007
CSA PAGE 59:

CSA PAGE 43:

7/12/2007

- UPDATE SYMBOL FOR U5930, VENDOR PART NUMBER CHANGES FROM SMB380 TO BMA150.

CSA PAGE 38:

CSA PAGE 4:

7/13/2007

- UPDATE BOM OPTION TABLE FOR J9401.

CSA PAGE 94:

CSA PAGE 79:

- CHANGE C3831 AND C3832 FROM 138S0582 TO 138S0554 (DON’T NEED LOW-PROFILE PARTS).

7/24/2007
CSA PAGE 4:

- CHANGE BETTER AND BEST CPU TO G0 STEPPING PARTS (FROM 337S3464 TO 337S3500).
CSA PAGE 22:

- STUFF R2242 AND NOSTUFF R2247.
CSA PAGE 92:

- CHANGE R9211 AND R9212 FROM 16.5K TO 9.09K.

CSA PAGE 62:

- CHANGE J4300 FROM 514-0289 TO 514-0456 (SAME JEDEC).

- UPDATE BOM OPTION TABLE FOR J4600 AND J4601.

- ADD PAGE_TITLE AUDIO: CODEC.

- NORMAL CHANGES FROM 514-0288 TO 514-0457, FANCY CHANGES FROM 514-0315 TO 514-0477.

- CHANGE J4600 AND J4601 FROM 514-0288 TO 514-0457 (DIFFERENT JEDEC, SAME LANDPATTERN).

- NORMAL CHANGES FROM 514-0359 TO 514-0456, FANCY CHANGES FROM 514-0316 TO 514-0476.

- UPDATE BOM OPTION TABLE FOR J4300.

051-7455

Revision History

5 76

01

SYNC_MASTER=N/A

SYNC_DATE=N/A

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FUNC_TEST

INVERTER CONNECTOR FUNC_TEST

Battery charger FUNC_TEST

DC-JACK FUNC_TEST

MIC FUNC_TEST

USB FUNC_TEST

Battery FUNC_TEST

SMC FUNC_TEST

FIREWIRE FUNC_TEST

SMBus FUNC_TEST

Other Func Test Points

Fan Connectors

SLEEP LED FUNC_TEST

Battery Digital Connector

NO_TEST

FUNC_TEST

NO_TEST

NO_TEST

Audio FUNC_TEST

Functional Test Points

FUNC_TEST

FUNC_TEST

LPC+ Debug Connector

SPEAKER FUNC_TEST

THERMAL FUNC_TEST

Power Supply FUNC_TEST

Power Supply NO_TESTs

NO_TEST

CLOCK NO_TESTS

NO_TEST

FIREWARE NO_TESTS

LVDS NO_TESTS

I1

I10

I11

I111
I112
I113

I114

I115

I116
I117
I118
I119

I12

I120

I122

I125

I15

I151

I152

I153
I154

I155

I156

I157
I158
I159

I16

I160
I161

I162
I163
I164

I166
I167
I168

I169

I17

I171
I172
I173

I174

I175
I176

I177

I178

I18

I180

I181

I182

I183

I186
I187
I188
I189

I19

I190
I191

I194
I195

I199

I20

I200
I201
I202
I203
I204
I205
I206
I207
I208

I209

I21

I210
I211
I212
I213
I214
I215

I219

I22

I220

I221

I222

I223

I224
I225

I226

I227

I228

I229

I23

I230

I231

I232
I233
I234
I235

I236

I237

I238

I239

I24

I240

I241

I242

I243

I244

I25

I29

I3

I31

I32

I33
I36
I38

I4

I44

I45

I46

I47

I48

I57

I58

I59

I60

I61
I63

I71
I72
I73
I74
I75
I76
I77
I78
I79
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89

I9

I90

I91

I92

I93
I94

I95
I96

051-7455

76

01

6

FUNC TEST 1 OF 2

IMVP6_RBIAS

TRUE

CK505_CPU1_N

CK505_DOT96_27M_N

TRUE
TRUE

CK505_DOT96_27M_P

TRUE

CK505_CPU2_ITP_SRC10_N

TRUE

CK505_CPU1_P
CK505_CPU2_ITP_SRC10_P

TRUE

TRUE

CK505_CPU0_P

TRUE

CK505_CPU0_N

TRUE

SMC_TMS
DEBUG_RESET_L

TRUE

SMC_TRST_L

TRUE

TRUE

LPC_AD<1>

TRUE

=PP5V_S0_LPCPLUS

TRUE

LPC_AD<0>

TRUE

ACZ_BITCLK

TRUE

ACZ_SDATAOUT

TRUE

MIC_HI

MIC_LO

TRUE

MIC_SHIELD

TRUE

MIC_HI_CONN

TRUE

TRUE

INV_BKLIGHT_PWM_L

TRUE

PP5V_INV_F

PPVBAT_G3H_CHGR_OUT

TRUE

TRUE

ACIN_ENABLE_GATE

PPBUS_ALL_INV_CONN

TRUE

TRUE

USB2_3G_F_N

TRUE

USB2_BT_F_N

TRUE

USB2_BT_F_P

TRUE

TP_USB_EXTC_N

TRUE

TP_USB_EXTC_P

TP_USB_EXCARD_N

TRUE

TP_USB_EXCARD_P

TRUE

ACZ_RST_L

TRUE

TRUE

USB2_3G_F_P

TRUE

INV_GND

TRUE

SYS_ONEWIRE

LPC_AD<3>

TRUE

SMC_TCK

TRUE

TRUE

LVDS_B_DATA_P1_SPN

TRUE

FW_C_TPA_P_SPN

TRUE

FW_B_TPBIAS_SPN

TRUE

PP3V3_S5

TRUE

PP1V8_S3

TRUE

SMC_LID

SPKRCONN_R_P_OUT

TRUE

SPKRCONN_L_N_OUT

TRUE

SPKRCONN_L_P_OUT

TRUE

TRUE

PPFW_SWITCH

TRUE

SYS_LED_ANODE

SMBUS_SMC_B_S0_SDA

TRUE

SMBUS_SMC_B_S0_SCL

TRUE

LINDACARD_GPIO

TRUE

SMC_TDI

TRUE

TRUE

SMC_MD1

TRUE

SMC_TX_L

TRUE

FWH_INIT_L
PCI_CLK33M_LPCPLUS

TRUE

LPC_AD<2>

TRUE

INT_SERIRQ

TRUE

PM_SUS_STAT_L

TRUE

SMC_RESET_L

TRUE

TRUE

SMC_TDO

TRUE

BOOT_LPC_SPI_L

=PP5V_S0_FAN_RT

TRUE

FAN_RT_PWM

TRUE

FAN_RT_TACH

TRUE
TRUE

SMC_FAN_1_CTL

TRUE

SMC_ADAPTER_EN

TRUE

SMC_BC_ACOK

GND_BT_F

TRUE

TRUE

PP0V9_S0

TRUE

BATT_POS

SMBUS_BATT_SCL_F

TRUE

SMBUS_BATT_SDA_F

TRUE

TRUE

BATT_NEG

SMC_FAN_3_TACH

TRUE

LVDS_B_DATA_P2_SPN

TRUE

TRUE

LVDS_B_DATA_N0_SPN

TRUE

FW_C_TPB_P_SPN

TRUE

=PP3V3_S0_FAN_RT

TRUE

FW_C_TPB_N_SPN

TRUE

LVDS_B_CLK_N_SPN

LVDS_B_DATA_N1_SPN

TRUE

TRUE

FW_C_TPA_N_SPN

TRUE

FW_B_TPB_P_SPN

TRUE

FW_C_TPBIAS_SPN

TRUE

LVDS_B_CLK_P_SPN

TRUE

FW_B_TPB_N_SPN

TRUE

FW_B_TPA_N_SPN

=PP5V_S0_AUDIO

TRUE

GND_AUDIO_AMP

TRUE
TRUE

GND_AUDIO_CODEC

=PP5V_S0_AUDIO_AMP

TRUE

TRUE

SMC_BS_ALRT_L

TRUE

LVDS_B_DATA_N2_SPN

SMC_BATT_CHG_EN

TRUE

TRUE

SMC_BATT_TRICKLE_EN_L

TRUE

ACZ_SYNC

TRUE

ACZ_SDATAIN<0>

TRUE

SMC_BATT_ISET

SMC_NMI

TRUE

SMC_RX_L

TRUE

TRUE

=PP1V05_S0_REG

PP18V5_G3H

TRUE

TRUE

=PP3V42_G3H_LPCPLUS

TRUE

SMC_FAN_1_TACH

PM_CLKRUN_L

TRUE

TRUE

LPC_FRAME_L

TRUE

CK505_SRC8_N

TRUE

CK505_LVDS_P

TRUE

CK505_SRC2_P

TRUE

CK505_SRC2_N

TRUE

CK505_SRC4_N

TRUE

CK505_SRC4_P

TRUE

CK505_SRC5_N
CK505_SRC5_P

TRUE

TRUE

CK505_SRC8_P

TRUE

CK505_SRC6_N
CK505_SRC6_P

TRUE

TRUE

THRM_DIMM_DX_F_N

SPKRCONN_SUB_P_OUT

TRUE

SPKRCONN_SUB_N_OUT

TRUE

MIC_SHLD_CONN

TRUE

MIC_LO_CONN

TRUE

THRM_HEATPIPE_P

TRUE

THRM_HEATPIPE_N

TRUE

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PP3V3_S3_BT_F

TRUE

TRUE

THRM_FINSTACK_P

TRUE

THRM_DIMM_DX_F_P

PP5V_S3

TRUE

PP3V3_S3

TRUE

SMC_MANUAL_RST_L

TRUE
TRUE

SMC_CPU_VSENSE

SPKRCONN_R_N_OUT

TRUE

TRUE

PP3V42_G3H

TRUE

PP1V2_ENET_S0

PP5V_S0

TRUE

PP3V3_S0

TRUE

TRUE

ALL_SYS_PWRGD

TRUE

PP1V5_S0

TRUE

PP1V8_S0

TRUE

PP1V05_S0

PPVCORE_S0_CPU

TRUE
TRUE

PP1V05_S0_R

TRUE

THRM_FINSTACK_N

IMVP6_COMP
5VS5_RUNSS

1V5S0_RUNSS

CK505_LVDS_N

TRUE

TRUE

CK505_PCIF1_CLK

TRUE

FW_B_TPA_P_SPN

57C4

46B6

45B3

66A6

46B4

57A8

45D5

44D5

57C7

54D8

45D5

46B6

75D3

75D3

75D3

75D3

75D3

75D3

75D3

75D3

46B6

46C6

46C6

57C8

46C4

46B4

45C5

46B4

46B4

44C5

75C3

46C4

46B4

46B4

46B4

46B6

38C6

57C3

56C4

54C8

57A2

66A4

66A3

44C5

44C5

46B6

75C3

75D3

75C3

75C3

75C3

75C3

75C3

75C3

75C3

75C3

75C3

56A6

58A3

75C3

75D3

59B7

29D6

29B6

29B6

29D6

29D6

29D6

29D6

29D6

45C5

46B6

46B6

44C8

46C6

44C8

53C7

53C7

56A6

56A6

55D3

66C2

66A6

53B7

45D5

44C8

45C5

44B5

55C2

55C2

55C2

45A3

76C3

76C3

24D5

45C5

46B6

44B8

46C4

44C8

44C8

44C5

45D7

45C5

46B6

50C4

50B4

35C7

45B6

44A8

50C4

53A7

54B8

45C5

45B6

45B6

53C7

53C7

66A8

46B4

44B8

61B8

46C6

50C4

37A5

44C8

29B6

29C6

29C6

29C6

29C6

29C6

29C6

29C6

29B6

29B6

29C6

55C2

55C2

55D3

55D3

48B1

55C2

45D1

44D8

45D2

59B7

65C5

61B5

29C6

29B6

59A4

28C4

28A4

28A4

28C4

28C4

28C4

28C4

28C4

44B5

27D1

44C1

22D4

7A7

22D4

8A5

8A5

55B3

55B3

55B1

67D2

67D3

66B5

57C3

67D3

43A4

43C2

43C2

8B2

8B2

8B2

8B2

8A5

43A4

67D2

44B8

22D4

44B5

8D5

8D1

8D1

7D1

7B4

42C3

54D1

54C1

54C1

38D3

40C5

47C5

47C5

24A7

44B5

44D1

41A8

46C5

29B3

22D4

24C8

24D5

44C3

44B5

23B5

7A7

50B3

50C3

44A8

33C7

44C5

43C2

7D7

57B5

57A5

57A5

57A5

44A4

8D5

8D5

8D1

7C4

8D1

8D5

8D5

8D1

8D1

8D1

8D5

8D1

8D1

7A7

8A4

8B4

7A7

44C5

8D5

44C8

44C8

8A5

8A5

44B5

44C1

41A8

7D8

7B1

7B1

44A8

24C8

22D4

28A4

28B4

28B4

28B4

28B4

28B4

28B4

28B4

28A4

28B4

28B4

49B6

54B1

54B1

55A1

55B1

49D6

49D6

7C1

7B1

43D2

49C6

49B6

7A4

7A4

45D8

44C5

54C1

7C1

7B5

7A7

7D4

27A5

7C7

7B7

7D7

7D7

7D7

49C6

59A4

63B5

58B1

28B4

28B6

8D1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"G3H" RAILS

"S5" RAILS

"S0,S0M" RAILS

(REGULATOR OUTPUT CPU 0.90V PWR)

(DDR2 TERMINATION 0.9V PWR)

(REGULATOR OUTPUT CPU VCORE PWR)

(CPU VCOR PWRE)

"S3" RAILS

051-7455

76

SYNC_DATE=06/15/2006

Power Aliases

SYNC_MASTER=WFERRY

01

7

MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=3.3V

PP3V3_S3

=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_ENET_P3V3ENETFET

=PPVCORE_S0_NB_GFX

=PP5V_S0_3G
=PP5V_S0_LPCPLUS
=PP5V_S0_ISENSECAL
=PP5V_S0_FAN_RT
=PP5V_S0_AUDIO
=PP5V_S0_AUDIO_AMP

=PP5V_S0_CPU_IMVP

=PP5V_S0_SB

VOLTAGE=5V

PP5V_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

=PP5V_S0_NB_GFX_IMVP

=PP5V_S0_LCD
=PP5V_S0_TMDS
=PP5V_S0_NB_TVDAC

=PP5V_S0_SATA

VOLTAGE=1.25V

PPVCORE_S0_NB_GFX

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

=PP1V8_S0_NB_DPLL

MAKE_BASE=TRUE

PP1V8_S0

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

=PP1V5_S0_NB_FOLLOW

=PP1V5_S0_AIRPORT

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_CPU

VOLTAGE=1.5V

PP1V5_S0

MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

=PP1V25_S0_FET

=PP1V25_S0_NB_VCCA

=PP1V25_S0_NB_VCC

=PP1V25_S0_NB_PLL

=PP1V25_S0_NB_VCCAXF

=PP1V25_S0_NB_VCCDMI

=PP1V25_S0_NB_PLL

MAKE_BASE=TRUE

PP1V25_S0

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 mm

=PP1V05_S0M_NB_VCCAXM

=PP1V25R1V05_S0_NB_VTT

=PP1V25R1V05_S0_FSB_NB

=PPVCORE_S0_NB

=PP1V05_S0_NB_PCIE

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0_R

=PPVCORE_S0_SB

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.05V

MAKE_BASE=TRUE

PP1V05_S0

=PP0V9_S3M_MEM_TERM

=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_VCCPCORE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP3V3_S5

=PP3V3_S5_FET

=PP3V3_S5_SB

=PP3V3_S5_SB_GPIO

=PP3V3_S5_SB_USB

=PP3V3_S5_SB_PM

=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_S5_FWLATEVG

=PP3V3_S5_SMBUS_SB_ME
=PP3V3_S5_ROM
=PP3V3_S5_LCD

=PP3V3_S5_1V25S0
=PP3V3_S5_AIRPORT_AUX

VOLTAGE=5V

PP5V_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

=PP5V_S5_SB

=PP5V_S5_USB

=PP5V_S5_PWRCTL
=PP5V_S5_FET

VOLTAGE=3.42V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V42_G3H

=PP3V42_G3H_SMC

=PP3V42_G3H_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_ACIN
=PP3V42_G3H_LIDSWITCH
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SB_RTC
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_LPCPLUS

VOLTAGE=18.5V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.6 MM

PP18V5_G3H

=PP18V5_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

=PPVIN_G3H_P3V42G3H

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5V

MAKE_BASE=TRUE

=PPDCIN_G3H

=PPBUSA_G3H

=PP5V_S5_PATA

=PP5V_S5_1V8S30V9S0

=PP3V3_S0_AIRPORT

=PP3V3_S0_SB

=PP3V3_S5_REG

=PP3V3_S0_THRM_SNR

=PP18V5_G3H_INRUSH

=PP3V3_S5_SB_CLINK1

=PP3V3_S0_NB

=PP3V3_S0MWOL_SB_CLINK0

=PPSPD_S0_MEM

MIN_NECK_WIDTH=0.2 mm

PP1V2_ENET_S0

MAKE_BASE=TRUE

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 mm

=PP1V2_ENET_PHY

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S0_PBATTISENS

=PPBUS_S5_FWPWRSW

=PP5V_S5_1V51V05S0

=PP3V3_S0_NB_FOLLOW
=PP3V3_S0_SB_GPIO

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_PM
=PP3V3_S0_RSTBUF

=PP3V3_S0_SMC_LS

=PP3V3_S0_LPCPLUS
=PP3V3_S0_SMBUS_SB

=PP3V3_S0_LCD

=PPVIN_S5_IMVP

=PPVIN_S5_1V5S0
=PPVIN_S5_1V05S0

=PPVIN_S5_5VS5
=PPVIN_S5_3V3S5

=PPVIN_S5_1V8S30V9S0

=PPBUS_S5_INV

=PP3V3_S0_PATA

=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_FW

=PP3V3_S0_SB_VCC3_3_DMI

PPVCORE_S0_CPU

VOLTAGE=0.9V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 MM

=PPVORE_S0_CPU_REG

=PP0V9_S0_REG

=PPVCORE_S0_CPU

=PPVIN_S5_NB_GFX_IMVP

=PPVIN_S5_CPU_IMVP

=PPVCORE_S0_NB_GFX_IMVP

=PP1V8_S0_TMDS

=PP1V8_S0_FET

=PP1V5_S0_REG

=PP5V_S3_IR

=PP5V_S3_GEYSER

=PP5V_S3_SYSLED

=PP3V42_G3H_REG

=PP5V_S5_REG

=PP5V_S3_CAMERA

=PP1V25_S0_REG

=PP5V_S0_FET

=PP1V05_S0_REG

=PP1V05_S0_REG_R

=PP3V3_S0_SB_VCCGLAN3_3

=PP3V3_S0_PDCISENS

=PP3V3_S0_CPUPOWER

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V9_ENET_S0

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=2.5V

=PPBUSB_G3H

=PP3V3_S0MWOL_SB_VCCLAN3_3

=PPVIN_S0_NB_DPLL

=PP3V3_S0MWOL_SB_VCCCL3_3

=PP3V3_S0_FET

=PP3V3_S0_NB_VCCHV

=PP3V3_S0_SB_VCC3_3_SATA

=PP5V_S3_FET

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP3V3_S0

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

=PP3V3_S0_SB_PCI

=PP3V3_S0_TMDS

=PP3V3_S0_AUDIO

=PP3V3_S0_FAN_RT
=PP3V3_S0_ENET

=PP3V3_S0_IMVP

=PP3V3_S0_NB_GFX_IMVP

=PP1V8_S0_YUKON

=PP1V8R2V5_ENET_PHY

PP3V3_ENET_FET

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP1V8_S0_NB_LVDS

=PP5V_S0_IDE_RESET

=PP3V3R1V5_S0_SB_VCCHDA

=PP3V3_S0_NB_VCCA_PEG_BG

=PP3V3_S0_CK505
=PP3V3_S0_NB_VCCSYNC

=PP3V3_S0_TMDS

=PP1V9_ENET_REG

=PP1V8_S3_MEMVREF

=PP1V8_S3_FET

=PP1V8_S3_MEM

=PP1V8_S3M_MEM_NB

=PP1V8_S3_REG

=PP1V8_S3_NB_VCC

=PP3V3_S3_PDCISENS

=PP3V3_S3_SMBUS_SMC_A_S3

VOLTAGE=1.8V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PP1V8_S3_MEM_NB

PP5V_S3

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_S3_ENETPWRCTL

=PP3V3_S3_FET

VOLTAGE=0.9V

PP0V9_S0

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_SB_CPU_IO

=PP1V05_S0_CPU

=PP1V25_S0_SB_DMI

=PP1V2_ENET_REG

=PP3V3_ENET_PHY

=PP1V8_S3_REG_R

=PP3V3_S3_AIRPORT_AUX
=PP3V3_S3_FW
=PP3V3_S3_PCI
=PP3V3_S3_BT
=PP3V3_S3_SMS

=PP1V8_ENET_P1V8ENETFET

PP1V8_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.8V

69C8

69C8

69C2

69C2

12C5

69B7

69B7

12B3

58D3

68D8

68D8

31D6

11A3

51B8

48B5

58C4

21B7

68C8

29D2

68C8

31D4

31D2

10C7

48B3

54D8

20D8

35C7

65B5

45D8

66B8

24D8

48B3

59D8

58C3

20A8

68B7

56B5

29B2

68B7

31B2

30D2

9D5

21C5

56C4

54C8

26D6

20D3

20D3

20D8

29C6

20B4

26C6

65C4

26D8

26D2

33D7

58D5

45D4

66A8

31A7

24B3

67C6

11D7

59D4

66C3

58B8

18B3

68B2

55D8

28D8

68B2

30D6

20C8

26C4

9C5

51B6

17D5

46C6

50C4

53A7

54B8

26B6

26C2

26D5

26C8

11B3

20B4

20A8

20B4

17C1

20C8

29B6

17D7

26D2

45D2

26B4

26A6

65A5

24A8

26D2

26B6

26B2

38A8

33D6

58C6

45C1

66A5

46C6

39C8

49D2

31A3

26C6

22D7

26B4

27B8

67B7

63B6

26A8

10D7

59C2

58C4

62C5

45A4

58D4

61B8

61C5

26D3

26B2

58B3

15C7

26B8

26C2

45D1

68B1

53D7

50C4

26C4

20A6

28D3

21B5

68B1

35D1

20A6

30D4

17D7

62C2

65C3

25C3

9B6

26A6

6A2

47C3

35D3

17B7

43B5

6D2

48B8

6D2

6D1

6D1

59D8

26D8

6A2

60D2

67D7

69D7

21D6

40C6

21A7

6B2

21D5

33D2

25A6

25B6

25B6

26A8

21D8

10B7

6B2

58A3

20B8

20A8

7C7

20D4

18C3

7C7

17B3

18D3

13B7

17D3

20D5

6B2

25D3

6B2

32D4

25C3

25C3

6A2

58C5

24A3

24D8

23C8

27C5

25A3

25A3

25B3

38A6

47A7

52C6

67C7

64B6

33C7

6A2

26D8

41C8

65B6

58B3

6A2

44D4

45C8

47C3

57C4

57A8

65C7

27D7

41A6

6D2

6A2

66D8

64C6

6A2

57D3

66C2

39D6

62C5

33C6

26D8

63B1

49C2

57D1

24B1

69C8

24C1

30A7

6A2

34D6

25B6

66B3

38D5

61C4

20B2

22D2

25B3

27B6

27D4

45D4

46C4

47D8

67B5

45A6

61B3

61B5

63A6

63B3

62B3

67D4

39C2

47D5

47C5

38C6

25C3

6B2

59D1

62B8

10B5

60C2

48D7

60C2

68D6

58B8

61B1

43D8

42D6

40B6

64C4

63B8

67A5

64B2

58C8

6B2

61C7

25A6

60C2

48D2

66C2

25A3

25A6

58A3

15B7

25C3

65B4

25B6

6A2

23A3

7C4

53A7

6D2

8A4

59D8

60C7

36D8

34C7

35D4

21C5

39B7

25B3

18C6

28C8

18D6

7C4

35B2

20A5

58C5

30B2

15D2

62B2

20A4

62A2

47D3

6A2

35D7

65A4

6A2

22D2

9B5

25C3

35C1

34D6

62C4

33C2

37D5

37C5

43D3

51C7

35C3

6A2

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FOR LAYOUT PLACEMENT
BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL

CPU HEATSINK STANDOFF SCREW HOLE

Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL

NB CFG ALIASES

DCIN CONNECTOR CHASSIS GND

NO-CONNECT UNUSED LVDS INTERFACE PORTS

(EMI PAD FOR INVERTER GONNECTOR)

DIP DIMM CONNECTOR CHASSIS GND

USB PORT [0] = External USB2.0 Port A

USB PORT [1] = PCI-E Mini Card

USB PORT [2] = 3G USB

USB PORT [3] = CAMERA

USB PORT [4] = IR CONTROLLER

USB PORT [5] = Trackpad(Geyser)

USB PORT [6] = BLUETOOTH

NO-CONNECT UNUSED FIREWIRE INTERFACE PORTS

ANALOG SWITCH GPIO

NB ALIASES

USB PORT [9] = Unused

USB PORT [8] = Unused

USB PORT [7] = External USB2.0 Port B

SO-DIMM ALIASES

PCI_EXP ALIASES

SATA ALIASES

NO-CONNECT UNUSED SATA INTERFACE PORTS

NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS

NO-CONNECT UNUSED SDVO INTERFACE PORTS

NO-CONNECT UNUSED ADDRESS INTERFACE PORTS

FIREWIRE ALIASES

DIP DIMM CONNECTOR CHASSIS GND

NC NC

I/O CONNECTOR CHASSIS GND

PCI_EXPRESS GRAPHICS ALIASES

AIRPORT CARD STANDOFF SCREW HOLE

Ethernet ALIASES

SATA,LVDS CONNECTOR CHASSIS GND

LVDS ALIASES

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

CLOCK ALIASES

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

SB ALIASES

BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND

CHASSIS GND

1

5R2P3-7SQBNP

OMIT

Z0906

Z0902

1

7X7R2P3-5B

OMIT

C0908

1

2

0.01UF

10%
16V
CERM
402

C0907

1

2

X5R

16V

10%
402

0.1UF

1

5R2P3-7SQBNP

OMIT

Z0901

Z0909

1

5R2P3-7SQB

OMIT

Z0911

1

OMIT

5R2P3-7B

Z0910

1

OMIT

5R2P3-7SQB

R0912

1

2

5%

0

1/16W
MF-LF
402

Z0913

1

OMIT

STDOFF-4.2OD3.95H-5.52R3.37-6B

Z0912

1

OMIT

STDOFF-4.2OD2.15H-1.2-3.2-TH

Z0908

1

OMIT

5P0R2P3-7BLB

ZS0920

1

EMI-SPRING

CLIP-SM-M42

Z0904

1

OMIT

STDOFF-4.2OD3.95H-5.52R3.37-7SQB

Z0921

1

OMIT

STDOFF-4.5OD3.95H-1.1-3.2-TH

Z0907

1

OMIT

6P5R2P6-7SQB

Z0903

1

OMIT

STDOFF-4.2OD3.95H-5.52R3.37-6B

C0930

1

2

0.1UF

X5R

10%
16V

402

C0910

1

2

16V
X5R
402

10%

0.1UF

C0911

1

2

402

CERM

16V

10%

0.01UF

C0916

1

2

402

16V

10%

0.1UF

X5R

C0917

1

2

0.01UF

10%
16V

402

CERM

C0914

1

2

16V

10%
402

0.1UF

X5R

C0915

1

2

10%
402

0.01UF

16V
CERM

C0912

1

2

X5R

0.1UF

10%
16V

402

C0913

1

2

402

10%

0.01UF

CERM

16V

C0918

1

2

402

10%
X5R

16V

0.1UF

C0919

1

2

0.01UF

10%
16V
CERM
402

R0910

1

2

MF-LF

5%
1/16W

402

0

R0921

1

2

1/16W
MF-LF
402

5%

0

Z0905

1

OMIT

STDOFF-4.5OD3.95H-1.1-3.2-TH

R0911

1

2

1/16W

0

5%
MF-LF

402

XW0802

1 2

SM

XW0801

1 2

SM

4

STANDOFF

Z0903,Z0904,Z0905,Z0921

860-0876

THERMAL STANDOFF

1

860-0723 STANDOFF

Z0912

STANDOFF WIRELESS

860-0749

1

STANDOFF

Z0913

STANDOFF W/THRU HOLES,WIRELESS

051-7455

SYNC_DATE=07/17/2006

76

01

8

SIGNAL ALIAS /RESET

SYNC_MASTER=GPU

=GND_CHASSIS_DIPDIMM_LEFT

=GND_CHASSIS_AUDIO_MIC

=GND_CHASSIS_AUDIO_JACK

=GND_BATT_CHGND

GND_CHASSIS_IO

SATA_C_R2D_C_P_SPN

MAKE_BASE=TRUE

SATA_C_D2R_N_SPN

MAKE_BASE=TRUE

FW_B_TPA_P

TP_HDA_SDIN2

CPU_THERMAL_SCREW_UP

=GND_CHASSIS_TMDS_UPPER

=GND_CHASSIS_RJ45

GND_CHASSIS_DCIN

MAKE_BASE=TRUE

VOLTAGE=0V

=GND_CHASSIS_LVDS

=GND_CHASSIS_3GPOWER

MAKE_BASE=TRUE

LVDS_B_CLK_P_SPN
LVDS_B_DATA_N0_SPN

MAKE_BASE=TRUE

=GND_CHASSIS_FW_DOWN
=GND_CHASSIS_USB

USB_EXTA_P
USB_EXTA_N

MAKE_BASE=TRUE

USB2_3G_P

=USB2_3G_P

MAKE_BASE=TRUE

EXTAUSB_OC_L

USB2_AIRPORT_N

MAKE_BASE=TRUE

USB2_CAMERA_P

MAKE_BASE=TRUE

USB2_CAMERA_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB_IR_P

MAKE_BASE=TRUE

USB_IR_N

MAKE_BASE=TRUE

USB2_GEYSER_P

MAKE_BASE=TRUE

USB2_GEYSER_N

USB_BT_P

MAKE_BASE=TRUE

USB_BT_N

MAKE_BASE=TRUE

=USB2_IR_P

MEM_CLK_P_5_SPN

MAKE_BASE=TRUE

=PP3V3_S0_ENET
=YUKON_EC_PP2V5_ENET

MAKE_BASE=TRUE

HDN_SPIN3_SPN

MAKE_BASE=TRUE

HDN_SPIN2_SPN

MAKE_BASE=TRUE

HDN_SDIN1_SPN

TP_HDA_SDIN3

NB_CFG<3>
NB_CFG<4>
NB_CFG<6>

NB_CFG<7>
NB_CFG<8>

=GND_CHASSIS_TMDS_DOWN

=GND_CHASSIS_FW_UPPER

MAKE_BASE=TRUE

TP_NB_CFG<3>

MAKE_BASE=TRUE

ACZ_SYNC

ACZ_BITCLK

MAKE_BASE=TRUE

MEM_A_A15_SPN

MAKE_BASE=TRUE

=NB_TDB_FORCE

=NB_TDE_SENSE

=NB_CLK96M_DOT_P

=GFX_VR_EN

MAKE_BASE=TRUE

PM_EXTTS_L<1>

MAKE_BASE=TRUE

TP_USB_EXTC_N

=USB2_EXTA_N

TP_MEM_CLKN5

MEM_CLK_N_5_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PEG_D2R_P10_SPN

PEG_D2R_P<9>

PEG_D2R_P<8>

PEG_D2R_P<7>

PEG_D2R_P<5>

PEG_D2R_P<4>

PEG_D2R_P<0>

PEG_D2R_N<15>

PEG_D2R_N<13>

PEG_D2R_N<6>

TP_LVDS_B_DATAP3

=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N

=NB_TDE_FORCE

=NB_CLK96M_DOT_N

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_N

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_P

MAKE_BASE=TRUE

NB_CLK96M_DOT_N

NB_CLK96M_DOT_P

MAKE_BASE=TRUE

CLINK_MPWROK

MAKE_BASE=TRUE

GFX_VR_EN

MAKE_BASE=TRUE

PM_EXTTS_L<0>

MAKE_BASE=TRUE

MEM_CLK_N_2_SPN

MAKE_BASE=TRUE

MEM_B_A15_SPN

MAKE_BASE=TRUE

SATA_B_R2D_C_N

SATA_C_D2R_P

MAKE_BASE=TRUE

TP_USB_EXCARD_P

MAKE_BASE=TRUE

TP_USB_EXCARD_N

EXTBUSB_OC_L

MAKE_BASE=TRUE

USB2_EXTB_N

MAKE_BASE=TRUE

USB2_EXTB_P

MAKE_BASE=TRUE

=USB2_BT_N

MAKE_BASE=TRUE

SATA_B_D2R_N_SPN

SATA_C_R2D_C_N_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCIE_A_D2R_N_SPN

TP_PCIE_A_D2R_N

=NB_CLINK_MPWROK

DIMM_OVERTEMPA_L

DIMM_OVERTEMPB_L

MAKE_BASE=TRUE

LVDS_A_DATA_N3_SPN

LVDS_B_DATA_N2_SPN

MAKE_BASE=TRUE

=GND_AUDIO_AMP

MEM_CLK_P_2_SPN

MAKE_BASE=TRUE

USB_EXTC_P

USB_EXTC_N

HDA_SDOUT

PEG_R2D_C_P<15>

HDA_RST_L
HDA_SDIN0

MAKE_BASE=TRUE

PEG_R2D_C_P7_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P8_SPN
PEG_R2D_C_P9_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PEG_R2D_C_P4_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N15_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N8_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N6_SPN

PEG_R2D_C_N4_SPN

MAKE_BASE=TRUE

PEG_D2R_P14_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N5_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>

PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>

MAKE_BASE=TRUE

PEG_R2D_C_N13_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P5_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P6_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N9_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N7_SPN

MAKE_BASE=TRUE

PEG_D2R_P13_SPN

PEG_D2R_P12_SPN

MAKE_BASE=TRUE

PEG_D2R_P11_SPN

MAKE_BASE=TRUE

TP_PCIE_A_R2D_C_P

TP_PCIE_B_D2R_P

TP_PCIE_FW_R2D_C_P

MAKE_BASE=TRUE

PEG_D2R_P5_SPN

MAKE_BASE=TRUE

PEG_D2R_N14_SPN

MAKE_BASE=TRUE

PCIE_D_R2D_C_P_SPN

MAKE_BASE=TRUE

PCIE_D_R2D_C_N_SPN

MAKE_BASE=TRUE

PCIE_C_D2R_P_SPN

TP_PCIE_B_D2R_N

MAKE_BASE=TRUE

PCIE_B_R2D_C_P_SPN

MAKE_BASE=TRUE

PCIE_C_D2R_N_SPN

TP_PCIE_A_R2D_C_N

SATA_C_D2R_P_SPN

MAKE_BASE=TRUE

SATA_B_R2D_C_N_SPN

MAKE_BASE=TRUE

SATA_B_R2D_C_P

SATA_B_R2D_C_P_SPN

MAKE_BASE=TRUE

SATA_B_D2R_P

MAKE_BASE=TRUE

SATA_B_D2R_P_SPN

SATA_B_D2R_N

MAKE_BASE=TRUE

PEG_D2R_N0_SPN
PEG_D2R_N2_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P<7>

MAKE_BASE=TRUE

LVDS_B_DATA_P0_SPN

FW_C_TPB_N

PEG_D2R_P4_SPN

MAKE_BASE=TRUE

PEG_D2R_P<6>

MAKE_BASE=TRUE

PEG_D2R_N15_SPN

FW_B_TPBIAS_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

FW_B_TPA_P_SPN

MAKE_BASE=TRUE

FW_B_TPB_N_SPN

FW_C_TPA_P
FW_C_TPA_N
FW_C_TPB_P

GND_CHASSIS_CPU

MAKE_BASE=TRUE

FW_C_TPB_N_SPN

FW_C_TPB_P_SPN

MAKE_BASE=TRUE

FW_C_TPA_N_SPN

MAKE_BASE=TRUE

FW_C_TPA_P_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

FW_C_TPBIAS_SPN

MAKE_BASE=TRUE

FW_B_TPA_N_SPN

FW_B_TPB_N
FW_C_TPBIAS

FW_B_TPB_P

FW_B_TPBIAS

FW_B_TPA_N

PEG_D2R_P0_SPN

MAKE_BASE=TRUE

PEG_D2R_P<15>

=GND_CHASSIS_DIPDIMM_CENTER

GND_CHASSIS_FANSCREW

=GND_DCIN_CHGND

USB_TPAD_P
USB_TPAD_N

USB_IR_P
USB_IR_N

USB_BT_P
USB_BT_N

USB_EXCARD_P

USB_EXTB_OC_L

USB_EXTA_OC_L

MAKE_BASE=TRUE

USB2_EXTA_N

MAKE_BASE=TRUE

USB2_EXTA_P

=USB2_EXTA_P

=EXTAUSB_OC_L

USB_MINI_P
USB_MINI_N

MAKE_BASE=TRUE

USB2_AIRPORT_P

=USB2_AIRPORT_P
=USB2_AIRPORT_N

USB_EXTD_N

USB_EXTD_P

USB2_3G_N

MAKE_BASE=TRUE

=USB2_3G_N

USB_CAMERA_P
USB_CAMERA_N

=USB2_CAMERA_P

MAKE_BASE=TRUE

VOLTAGE=0V

GND_CHASSIS_RIGHT

=EXTBUSB_OC_L

=USB2_EXTB_P

=USB2_BT_P

=USB2_GEYSER_P

TP_PCIE_A_D2R_P

NB_RIGHT_DOWN_SCREW

MAKE_BASE=TRUE

PEG_R2D_C_N14_SPN

CPU_THERMAL_SCREW_DOWN

GND_CHASSIS_CENTER

MAKE_BASE=TRUE

VOLTAGE=0V

PEG_D2R_N<0>

=USB2_EXTB_N USB_EXTB_N

=USB2_IR_N

USB_EXCARD_N

PEG_D2R_P8_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

VOLTAGE=0V

GND_CHASSIS_IO

=USB2_CAMERA_N

=USB2_GEYSER_N

TP_LVDS_A_DATAP3

PEG_D2R_P6_SPN

MAKE_BASE=TRUE

PEG_D2R_N8_SPN

MAKE_BASE=TRUE

LVDS_B_CLK_N

LVDS_B_CLK_N_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

LVDS_B_DATA_N3_SPN

LVDS_B_DATA_N<0>

LVDS_B_CLK_P

MAKE_BASE=TRUE

LVDS_B_DATA_P1_SPN

LVDS_B_DATA_N1_SPN

MAKE_BASE=TRUE

LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>

TP_LVDS_B_DATAN3

LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>

PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>

PEG_D2R_N<14>

PEG_D2R_P<2>
PEG_D2R_P<3>

PEG_D2R_P<10>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>

PEG_R2D_C_N<4>
PEG_R2D_C_N<5>

PEG_R2D_C_N<9>

PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>

PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>

PEG_R2D_C_P11_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P10_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PEG_R2D_C_N10_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N11_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N12_SPN

PEG_D2R_P9_SPN

MAKE_BASE=TRUE

PEG_D2R_P2_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PEG_D2R_N6_SPN

PEG_D2R_N3_SPN

MAKE_BASE=TRUE

SATA_C_D2R_N

PCIE_B_D2R_N_SPN

MAKE_BASE=TRUE

PCIE_A_R2D_C_P_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCIE_A_R2D_C_N_SPN

PCIE_A_D2R_P_SPN

MAKE_BASE=TRUE

SATA_C_R2D_C_P

SATA_C_R2D_C_N

TP_PCIE_FW_D2R_P

TP_HDA_SDIN1

HDA_SYNC

HDA_BIT_CLK

MAKE_BASE=TRUE

TP_USB_EXTC_P

PEG_R2D_C_P12_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P13_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P14_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P15_SPN

MAKE_BASE=TRUE

TP_NB_CFG<4>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_NB_CFG<6>

MAKE_BASE=TRUE

TP_NB_CFG<7>

MAKE_BASE=TRUE

TP_NB_CFG<8>

LVDS_B_DATA_P<2>

MAKE_BASE=TRUE

VOLTAGE=0V

GND_CHASSIS_SATA

VOLTAGE=0V

GND_CHASSIS_IO1

MAKE_BASE=TRUE

PEG_D2R_N7_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

ACZ_RST_L

MAKE_BASE=TRUE

ACZ_SDATAIN<0>

MAKE_BASE=TRUE

ACZ_SDATAOUT

=GND_AUDIO_CODEC

MEM_A_A<15>

TP_MEM_CLKP5

TP_LVDS_A_DATAN3

CPU_THERMAL_SCREW_RIGHT

MAKE_BASE=TRUE

FW_B_TPB_P_SPN

USB_EXTB_P

=NB_TDB_SENSE

MAKE_BASE=TRUE

LVDS_B_DATA_P3_SPN

MAKE_BASE=TRUE

LVDS_B_DATA_P2_SPN

MAKE_BASE=TRUE

LVDS_A_DATA_P3_SPN

PEG_D2R_N4_SPN

MAKE_BASE=TRUE

PEG_D2R_N5_SPN

MAKE_BASE=TRUE

PEG_D2R_N<5>

PEG_D2R_N<4>

PEG_D2R_N<3>

PEG_D2R_N<2>

VOLTAGE=0V

INVT_CHGND

MAKE_BASE=TRUE

TP_MEM_CLKN2

TP_MEM_CLKP2

=ENET_VMAIN_AVLBL

MAKE_BASE=TRUE

GND_AUDIO_AMP

MAKE_BASE=TRUE

GND_AUDIO_CODEC

MEM_B_A<15>

MAKE_BASE=TRUE

PEG_D2R_P7_SPN

MAKE_BASE=TRUE

PEG_D2R_P15_SPN

MAKE_BASE=TRUE

PCIE_D_D2R_P_SPN

MAKE_BASE=TRUE

PCIE_D_D2R_N_SPN

PCIE_C_R2D_C_P_SPN

MAKE_BASE=TRUE

TP_PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_R2D_C_N

TP_PCIE_EXCARD_R2D_C_P

PEG_D2R_N13_SPN

MAKE_BASE=TRUE

PEG_D2R_N9_SPN

MAKE_BASE=TRUE
MAKE_BASE=TRUE

PEG_D2R_N10_SPN

TP_PCIE_FW_R2D_C_N

TP_PCIE_FW_D2R_N

MAKE_BASE=TRUE

PCIE_C_R2D_C_N_SPN

MAKE_BASE=TRUE

PCIE_B_R2D_C_N_SPN

MAKE_BASE=TRUE

PCIE_B_D2R_P_SPN

MAKE_BASE=TRUE

CLINK_MPWROK=SB_CLINK_MPWROK

MAKE_BASE=TRUE

VR_PWRGD_CK505VR_PWRGD_CLKEN

MAKE_BASE=TRUE

SB_CLK100M_SATA_OE_L

SB_SATA_CLKREQ_L

MAKE_BASE=TRUE

TP_SB_GPIO17EXTGPU_RST_L

TP_CK505_SRC1_N
TP_CK505_SRC1_P
TP_CK505_SRC3_N

MAKE_BASE=TRUE

CK505_SRC1_N_SPN

CK505_SRC3_N_SPN

MAKE_BASE=TRUE

CK505_SRC1_P_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CK505_PCI4_CLK_SPN

MAKE_BASE=TRUE

CK505_SRC7_P_SPN

MAKE_BASE=TRUE

CK505_PCI2_CLK_SPN

MAKE_BASE=TRUE

CK505_SRC7_N_SPN

CK505_PCI2_CLK

TP_CK505_SRC7_P

CK505_PCI4_CLK

TP_CK505_SRC7_N

CK505_SRC3_P_SPN

MAKE_BASE=TRUE

TP_CK505_SRC3_P

MAKE_BASE=TRUE

PEG_D2R_P3_SPN

MAKE_BASE=TRUE

PEG_D2R_N12_SPN

MAKE_BASE=TRUE

PEG_D2R_N11_SPN

TP_PCIE_EXCARD_D2R_N

TP_PCIE_B_R2D_C_P

TP_PCIE_B_R2D_C_N

MAKE_BASE=TRUE

ENET_CLKREQ_L

=ENET_CLKREQ_L

=GND_CHASSIS_DIPDIMM_RIGHT

56C4 56B8 56B5

56B4 56B1 56A8 56A4 55B3

54C8 54B8

67B2

41C4

73B3

73B3

54C8

54A8

67A6

41C2

23C2

23C2

54B8

73B3

73B3

73B3

73B3

53D3

69C4

67A4

43B5

41A4

73B3

73B3

8C1

8C1

53C7

53C7

44B8

75B3

75B3

75B3

75B3

27A6

44B8

54A8

73B3

73B3

73B3

73C3

73C3

31A5

73B3

73B3

23C2

23C2

23C2

23C2

73B3

73B3

73B3

73B3

73B3

73B3

73B3

73C3

73C3

53B7

53C7

53C7

53B7

73B3

27A6

24C5

75D3

75D3

34B8

30A5

56A4

55C3

57A6

37B3

22C8

69A4

36B2

67A2

43A5

6A7

6A7

38B1

41A2

23C2

23C2

43A4

43C4

7C4

34C7

22C8

15B6

15B6

15B6

15B6

15B6

69A3

38B1

6C1

6C1

19C2

19D2

15C3

15B3

15B7

6C1

41A8

15C6

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14D3

15C6

15C3
15C3

19C2

15C3

29C3

29C3

29B3

29B3

8B3

60C6

15B7

22B6

22B6

6C1

6C1

43C3

23D5

15A3

30C4

31C4

6A7

54A5

23C2

23C2

22B8

14A3

22C8

22C8

14B3

14B3

14B3

14B3

14B3

14B3

23D5

23D5

23D5

23D5

23D5

22B6

22B6

22B6

14B3

37B3

14C3

6B7

6B7

6B7

37B3

37B3

37B3

6B7

6B7

6B7

6B7

6B7

6B7

37B3

37B3

37B3

37B3

37B3

14C3

30D5

57C8

23C2

23C2

8C2

8C2

8C2

8B2

23C2

23C8

23C8

41A8

41C8

23C2

23C2

33B3

33B3

23C2

23C2

43A4

23C2

23C2

67B4

41C8

41B5

43C3

42C7

23D5

14D3

41B5 23C2

43C4

23C2

8D7

67A4

42C7

15C6

14C5

6A7

14C5

14C5

6A7

6A7

14C5

14C5

15C6

14C5

14C5

14D3

14D3

14D3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14A3

14A3

14A3

22B6

22B6

22B6

23D5

22C8

22C8

22C8

6C1

14C5

40C8

6C1

6D1

6D1

53A7

30C4

15C6

15C6

6B7

23C2

19C2

6A7

14D3

14D3

14D3

14D3

67C2

15C6

15C6

34C2

6D1

6D1

31C4

23D5

23D5

23D5

23D5

23D5

8B1

24C3

27A8 24C5

28B4 24C5

24B5

28B4

28B4

28B4

28B6

28B4

28B6

28B4

28B4

23D5

23D5

23D5

28A4

31D4

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN

OUT

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN
IN
IN
IN
IN

IN
IN

IN
IN

OUT

IN
IN

IN

IN

IN
IN

IN

IN

OUT

BI
BI
BI
BI

LOCK*

INIT*

A20M*

A6*

A3*
A4*

A14*

A16*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD9

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*
A21*
A22*
A23*
A24*

A26*
A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

NC

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

RESERVED

ADDR GROUP0ADDR GROUP1

ICH

DINV1*

D31*

D30*

D25*

D11*
D12*
D13*
D14*

DSTBP0*
DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

DATBP1*

D0*

D32*
D1*
D2*

D5*

D16*

D20*
D21*
D22*
D23*
D24*

D26*
D27*
D28*
D29*

DSTBN1*

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL0
BSEL1
BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*
DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4
PIN. MAKE SURE CPU_TEST4 IS

R1002

1

2

1%
1/16W

54.9

MF-LF
402

R1004

1

2

68

5%
1/16W

402

MF-LF

R1005

1

2

1/16W

1%

MF-LF

1K

402

R1006

1

2

1%

MF-LF

2.0K

1/16W

402

R1019

1%

MF-LF

1/16W

54.9

402

R1018

27.4

1/16W
MF-LF

1%

402

R1017

1%

MF-LF

1/16W

54.9

402

R1016

1%

MF-LF

1/16W

27.4

402

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B3 70C3

13A3 70C3

13B3 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B3 70C3

13A3 70C3

13B3 70C3

15B6 22C4 59C7 70B3

22C4 70B3

13B3 70D3

13A5 70B3

27B3

12B1 22C4 70C3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13C5 70D3

13C5 70D3

13C5 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13B3 70C3

13B3 70C3

13B3 70C3

29B6 70B3

29A6 70B3

29C6 70B3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13C3 70C3

13C3 70C3

13A3 70C3

13A3 70C3

13A3 70C3

13A3 70C3

13A3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70D3

13C3 70D3

13C3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

12B2 70A3

12B2 70A3

12B2 70A3

12B3 70A3

12B2 70A3

12B2 70A3

9A7

12B5 70B3

12B4 27C6

45B5 45C3 59C8 70C3

49B7

15A6 22C2 45B3 70B3

22C4 46B2 70B3

12B5 13A5 70D3

13A3 70D3

13A3 70D3

13A3 70D3

13B3 70D3

9A7

12B2 12B3 70B3

9B7

12B3 70B3

9B7

12B2 70B3

9A7

12B3 70A3

49C7

29D3 75C3

29D3 75C3

22C4 70C3

22C4 70B3

22C4 70C3

22C4 70C3

22C4 70B3

22C4 70B3

22C2 70C3

R1030

0

1/16W
MF-LF

5%

NOSTUFF

402

R1007

1

2

1/16W

5%

MF-LF

1K

NOSTUFF

402

R1003

1

2

1/16W

1%

MF-LF

54.9

402

R1020

1%

MF-LF

1/16W

54.9

402

R1021

54.9

1/16W
MF-LF

1%

402

R1022

54.9

1/16W
MF-LF

1%

402

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

R1023

649

1/16W
MF-LF

1%

402

R1012

1

2

1/16W

5%

1K

NOSTUFF

MF-LF

402

C1000

1

2

X5R

NOSTUFF

0.1uF

10%
16V

402

U1000

N3
P5

P2

L2
P4

P1
R1

Y2
U5

R3

W6

A6

U4

Y5

U1
R4

T5

T3
W2

W5
Y4

J4

U2

V4
W3

AA4

AB2
AA3

L5
L4

K5

M3
N2

J1

H1

M1

V1

A22

A21

E2

AD4

AD3
AD1

AC4

G5

F1

C20

E1

H5
F21

A5

G6

E4

D20

C4

B3

C6

B4

H4

B1

AC2
AC1

D21

K3
H2

K2

J3
L1

C1

F3
F4

G3

M4

N5
T2

V3
B2

C3

D2

D22

D3

F6

A3

D5

AC5

AA6
AB3

A24

B25

C7

AB5

G2

AB6

OMIT

MEROM

FCBGA

U1000

B22

B23
C21

R26

U26
AA1

Y1

E22
F24

J24

J23
H22

F26

K22
H23

N22

K25
P26

R23

E26

L23
M24

L22

M23
P25

P23

P22
T24

R24
L25

G22

T25

N25

Y22
AB24

V24

V26
V23

T22

U25
U23

F23

Y25

W22
Y23

W24
W25

AA23

AA24
AB25

AE24

AD24

G25

AA21

AB22

AB21
AC26

AD20

AE22
AF23

AC25

AE21
AD21

E25

AC22
AD23

AF22

AC23

E23

K24

G24

M26

H25

N24

U22

AC20

E5

B5
D24

J26

L26

Y26

AE25

H26

AA26

AF24

AD26

AE6

D6

D7

C23
D25

C24

AF26

AF1

A26

OMIT

MEROM

FCBGA

R1024

1%

MF-LF

1/16W

54.9

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

402

SYNC_DATE=11/12/2006

SYNC_MASTER=T9_MLB_NOME

76

051-7455

01

9

CPU FSB

TP_CPU_TEST5

FSB_DINV_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<25>

FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>

FSB_DSTB_L_P<0>
FSB_DINV_L<0>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<19>

FSB_D_L<18>

FSB_DSTB_L_P<1>

FSB_D_L<0>

FSB_D_L<32>
FSB_D_L<1>
FSB_D_L<2>

FSB_D_L<5>

FSB_D_L<16>

FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>

FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>

FSB_DSTB_L_N<1>

CPU_GTLREF
CPU_TEST1

CPU_TEST2
TP_CPU_TEST3
CPU_TEST4

TP_CPU_TEST6

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>

FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>

CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>

CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L

FSB_D_L<17>

FSB_D_L<4>

FSB_D_L<3>

FSB_DSTB_L_N<0>

FSB_D_L<15>

FSB_D_L<10>

FSB_LOCK_L

CPU_INIT_L

CPU_A20M_L

FSB_A_L<6>

FSB_A_L<3>
FSB_A_L<4>

FSB_A_L<14>

FSB_A_L<16>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD9

TP_CPU_RSVD8

TP_CPU_RSVD7

TP_CPU_RSVD6

TP_CPU_RSVD5

TP_CPU_RSVD4

TP_CPU_RSVD3

TP_CPU_RSVD2

TP_CPU_RSVD1

TP_CPU_RSVD0

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_STPCLK_L

CPU_FERR_L

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>

FSB_A_L<26>
FSB_A_L<27>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

FSB_A_L<25>

CPU_IGNNE_L

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

XDP_TCK

XDP_TDO

XDP_TMS

XDP_TDI

XDP_TRST_L

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

CPU_THERMD_N

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<2>

12C5

12C5

12C5

12C5

12B3

12B3

12B3

12B3

11A3

11A3

11A3

11A3

10C7

10C7

10C7

10C7

70B3

9D5

9D5

9D5

9C5

12B3

70B3

70B3

70B3

70A3

9C5

9B6

9C5

9B6

12B2

12B5

12B2

12B3

12B3

9B5

9B5

9B6

9B5

70B3 70B3

70B3

70B3

70B3

70C3

9C6

9C6

9C6

9C6

9C6

7C7

7C7

7C7

7C7

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

VCC

VSSSENSE

VCCSENSE

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VCCA

VCCP

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

11.5 A (Deeper Sleep)

25.0 A (Deep Sleep HFM)

27.4 A (Sleep HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

30.4 A (LFM)

25.5 A (SuperLFM)

9.4 A (Enhanced Deeper Sleep)

2500 mA (after VCC stable)

4500 mA (before VCC stable)

16.0 A (Deep Sleep SuperLFM)

16.8 A (Sleep SuperLFM)

41.0 A (HFM)

44.0 A (Design Target)

Standard Voltage:

(CPU CORE POWER)

130 mA

(CPU IO POWER 1.05V)

(CPU INTERNAL PLL POWER 1.5V)

Low Voltage:

Ultra Low Voltage:

17.0 A (Design Target)23.0 A (Design Target)

21.0 A (HFM)

18.7 A (LFM)
TBD A (SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Sleep HFM)
TBD A (Sleep SuperLFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep SuperLFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep) TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep HFM)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (HFM)
TBD A (LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep LFM)

TBD A (Deep Sleep LFM)

CPU_VID<2>
CPU_VID<3>

CPU_VID<5>

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<0>
CPU_VID<1>

=PPVCORE_S0_CPU

CPU_VID<6>

CPU_VID<4>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

SYNC_DATE=11/12/2006

SYNC_MASTER=T9_MLB_NOME

CPU Power & Ground

051-7455

01

10 76

MF-LF
402

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

1/16W

1%

100

2

1

R1100

FCBGA

MEROM

OMIT

V25

V22

V5

V2

U24

U21

U6

U3

T26

T23

B8

T4

T1

R25

R22

R5

R2

P24

P21

P6

P3

B6

N26

N23

N4

N1

M25

M22

M5

M2

L24

L21

AF2

L6

L3

K26

K23

K4

K1

J25

J22

J5

J2

A23

H24

H21

H6

H3

G26

G23

G1

G4

F25

F22

A19

F2

F19

F16

F13

F11

F8

F5

E24

E21

E19

A16

E16

E14

E11

E8

E6

E3

D26

D23

D19

D16

A14

D13

D11

D8

D4

D1

C25

C22

C2

C19

C16

A11

C14

C11

C8

AF25

A25

AF21

C5

AF19

AF16

AF13

AF11

AF8

AF6

A2

AE26

AE23

AE19

B24

AE16

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

B21

AD13

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

B19

AC11

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

B16

AB8

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

B13

AA5

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

B11

A8

A4

U1000

FCBGA

MEROM

AE7

AE2

AF3

AE3

AF4

AE5

AF5

AD6

AF7

N6

N21

M21

K21

J21

M6

K6

J6

W21

V21

T6

T21

R6

R21

V6

G21

C26

B26

AF20

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

B7

AE17

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

A20

AD12

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

A18

AC7

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

A17

AB9

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

A15

F20

F18

F17

F15

F14

F12

F10

F9

F7

E20

A13

E18

E17

E15

E13

E12

E10

E9

E7

D18

D17

A12

D15

D14

D12

D10

D9

C18

C17

C15

C13

C12

A10

C10

C9

B20

B18

B17

B15

B14

B12

B10

B9

A9

A7

U1000

70A3 59A5 59A4

70A3 59A5 59A4

70A3 59C7

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

MF-LF
402

100

1%
1/16W

2

1

R1101

70A3 59C7

70A3 59C7

70A3 59C7

70A3 59C7

70A3 59C7

70A3 59C7

OMIT

12C5 12B3 11A3

48B5

48B5

9D5

48B3

48B3

9C5

11D7

11D7

9B6

10D7

10B5

11B3

9B5

7D7

7D7

7C7

7C7

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

CPU VCORE HF AND BULK DECOUPLING

C1250, C1251, C1252 AND C1253 NEED TO USE 6mOHM CAPS.

PLACE ON BOTTOMSIDE

PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)

PLACE ON BOTTOMSIDE

LAYOUT NOTE:

LAYOUT NOTE:

LAYOUT NOTE:

LAYOUT NOTE:
PLACE C1235 CLOSE TO CPU

PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)

4x 330uF. 20x 10uF 0805

1X 330UF, 6X 0.1UF

VCCP (CPU I/O) DECOUPLING

VCCA (CPU AVdd) DECOUPLING

PLACE C1281 NEAR PIN B26 OF U1000

LAYOUT NOTE:

1x 10uF, 1x 0.01uF

C1235

1

2 3

CRITICAL

330uF

10%

2.5V
TANT

D2T

C1237

1

2

20%
10V
CERM

0.1UF

402

C1238

1

2

0.1UF

CERM

10V

20%

402

C1239

1

2

20%
10V
CERM

0.1UF

402

C1240

1

2

0.1UF

CERM

10V

20%

402

C1241

1

2

0.1UF

CERM

10V

20%

402

C1210

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1216

1

2

805-2

6.3V
X5R

CRITICAL

10%

10UF

C1201

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1202

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1203

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1204

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1205

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1206

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1207

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1208

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1209

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1214

1

2

805-2

6.3V
X5R

CRITICAL

10%

10UF

C1213

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1212

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1211

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1219

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1200

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1236

1

2

402

0.1UF

CERM

10V

20%

C1215

1

2

805-2

6.3V
X5R

10UF

10%

CRITICAL

C1217

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1218

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1281

1

2

0.01UF

16V
CERM
402

10%

C1280

1

2

10uF

20%

6.3V
X5R
603

C1250

1

23

D2T

2.0V

330UF

10%

CRITICAL

TANT

C1251

1

23

D2T

2.0V

330UF

TANT

10%

CRITICAL

C1252

1

23

2.0V

330UF

CRITICAL

TANT

10%

D2T

C1253

1

23

D2T

2.0V

330UF

TANT

10%

CRITICAL

CPU Decoupling & VID

76

01

SYNC_DATE=04/26/2006

SYNC_MASTER=MSARWAR

11

051-7455

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

12C5 12B3 10C7

48B5

9D5

48B3

9C5

10D7

9B6

10B5

9B5

10B7

7D7

7C7

7C7

OUT

IN
IN

OUT

OUT

OUT

OUT

IO

IN

OUT

IN

IO

IO

IO

IO

IO

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(FROM CK505 HOST 133/167MHZ)

516S0394

INDICATE THAT ITP IS USING TAP I/F, NC IN 965GM CHIPSET SYSTEM.

TO ICH8M SYS_RST*, AND WITH SYSTEM RESET LOGIC

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S

ITP TCK SIGNAL LAYOUT NOTE:

CONNECTOR’S FBO PIN.

TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

(DBA#)
(DEBUG PORT ACTIVE)

(DBR#)

(DEBUG PORT RESET)

(FBO)

CPU ITP700FLEX DEBUG SUPPORT

(TCK)

C1300

1

2

0.1UF

X5R

10%

ITP

16V
402

R1302

1 2

ITP

22.6

1%
1/16W
MF-LF

402

R1301

1

2

NOSTUFF

54.9

MF-LF
402

1/16W

1%

R1300

1 2

ITP

MF-LF

402

1/16W

1%

22.6

J1302

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

ITP

M-ST-SM

CRITICAL

QT500306-L021-9F

01

12 76

SYNC_DATE=5/23/05

CPU ITP700FLEX DEBUG

SYNC_MASTER=MASTER

051-7455

=PP1V05_S0_CPU

XDP_TDO

XDP_TRST_L

XDP_BPM_L<2>

CPU_PWRGD

XDP_BPM_L<1>

FSB_CPURST_L

XDP_BPM_L<4>

=PP1V05_S0_CPU

ITPRESET_L

ITP_TDO

XDP_TMS
LVDS_CTRL_DATA
LVDS_CTRL_CLK

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_BPM_L<3>

CPU_XDP_CLK_P

CPU_XDP_CLK_N

XDP_TCK

XDP_TDI

12B3

12C5

11A3

11A3

10C7

10C7

9D5

9D5

9C5

9C5

70B3

70B3

9B6

70B3

70A3

70C3

70D3

9B6

70B3

12B3

12B2

70B3

9B5

9C6

9C6

70A3

22C4

70A3

13A5 70A3

9B5

9C6

67A7

67A7

9C6

70A3

70A3

27C6

70A3

9C6

9C6

7C7

9A7

9A7

9C6

9B2

9C6

9D6 9C6

7C7

9B7

14D5

14D5

9A7

9C5

9C6

9C6

9C6

29D3

29D3

9A7

9B7

BI

BI
BI

OUT

OUT

BI

BI

BI

BI
BI

BI

BI
BI
BI
BI

BI
BI

BI

BI
BI

BI
BI
BI
BI

BI
BI

OUT

BI

OUT

OUT

OUT

BI
BI
BI
BI
BI

BI
BI

H_D0*

H_D3*

H_D2*

H_D33*
H_D34*
H_D35*

H_D1*

H_D4*

H_D10*

H_A4*
H_A5*
H_A6*
H_A7*
H_A8*

H_A9*
H_A10*
H_A11*
H_A12*
H_A13*
H_A14*
H_A15*
H_A16*
H_A17*
H_A18*
H_A19*
H_A20*
H_A21*
H_A22*
H_A23*
H_A24*
H_A25*
H_A26*
H_A27*
H_A28*
H_A29*
H_A30*
H_A31*
H_A32*
H_A33*
H_A34*
H_A35*

H_ADS*

H_ADSTB0*
H_ADSTB1*

H_A3*

H_D7*
H_D8*
H_D9*

H_D11*
H_D12*
H_D13*
H_D14*
H_D15*
H_D16*
H_D17*
H_D18*
H_D19*
H_D20*
H_D21*
H_D22*
H_D23*

H_D25*
H_D26*
H_D27*
H_D28*
H_D29*
H_D30*

H_D32*

H_D36*
H_D37* H_BNR*
H_D38*

H_BPRI*
H_D39*
H_D40*

H_DEFER*

H_D41*

H_DBSY*
H_D42*
H_D43*
H_D44*

H_DPWR*
H_D45*

H_DRDY*
H_D46* H_HIT*
H_D47*

H_HITM*
H_D48*

H_LOCK*

H_TRDY*

H_D51*
H_D52*
H_D53*

H_DINV0*

H_D54*

H_DINV1*

H_D55*

H_DINV2*

H_D56*

H_DINV3*

H_D57*
H_D58*

H_DSTBN0*

H_D59*

H_DSTBN1*

H_D60*

H_DSTBN2*

H_D61*

H_DSTBN3*

H_D62*
H_D63*

H_DSTBP0*
H_DSTBP1*

H_DSTBP2*
H_SWING
H_RCOMP

H_REQ0*
H_SCOMP H_REQ1*
H_SCOMP*

H_REQ2*

H_REQ3*
H_CPURST*

H_REQ4*
H_CPUSLP*

H_RS0*
H_RS1*

H_AVREF

H_RS2*

H_DVREF

H_D5*
H_D6*

H_D31*

H_BREQ*

H_D24*

H_D49*
H_D50*

H_DSTBP3*

HPLL_CLK

HPLL_CLK*

HOST

(1 OF 10)

BI
BI
BI
BI

BI

IN

IN

IN

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI

BI

BI

BI
BI
BI
BI
BI

BI

BI
BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

9D8

70C3

9D8

70C3

9C8

70C3

9D6

70D3

9D6

70D3

9D6

70D3

9D6

70D3

9D6

70D3

9B2

70D3

9D6

70D3

9D8

70C3

C1425

1

2

402

16V

10%

0.1uF

X5R

R1426

1

2

402

1/16W

1%

MF-LF

2.0K

R1425

1

2

402

1/16W

1%

MF-LF

1K

9C4

70D3

9B4

70C3

9C2

70C3

9B2

70C3

9C4

70D3

9B4

70C3

9D8

70C3

9C2

70C3

9B2

70C3

9C4

70D3

9B4

70C3

9C2

70C3

9B2

70C3

9C6

70D3

9C6

70D3

9D6

70D3

9D8

70C3

9D6

70D3

9D6

70D3

9D6

70D3

9D8

70C3

9D8

70C3

9D8

70C3

9D8

70C3

9C8

70C3

9D8

70C3

R1420

1

2

402

1/16W

1%

MF-LF

54.9

R1415

1

2

402

1/16W

1%

MF-LF

24.9

R1410

1

2

402

1/16W

1%

MF-LF

221

R1411

1

2

402

1/16W

1%

MF-LF

100

C1410

1

2

402

16V

10%

0.1uF

X5R

9D8

70C3

U1400

G17

C14

K16
B13

L16

J17
B14

K19

P15
R17

B16
H20

L19

D17
M17

N16

J19
B18

E19

B17

J13

B15

E17
C18

A19

B19
N19

B11
C11

M11

C15
F16

L13

G12
H17

G20

B9

C8
E8

F12

B6
E5

E2

G2

M10

N12

N9
H5

P13

K9
M2

W10

Y8

V4

G7

M3
J1

N5

N3
W6

W9

N2
Y7

Y9
P4

M6

W3

N1

AD12

AE3

AD9
AC9

AC7

AC14
AD11

AC11

H7

AB2

AD7

AB1

Y3

AC6

AE2
AC5

AG3

AJ9
AH8

H3

AJ14

AE9

AE11

AH12

AJ5

AH5

AJ6
AE7

AJ7

AJ2

G4

AE5

AJ3
AH2

AH13

F3

N8

H2

C10

D6

K5

L2
AD13

AE13

H8

K7

M7

K3
AD2

AH11

L7

K2
AC2

AJ10

A9

E4

C6

G10

C2

M14

E13

A11
H13

B12

E12

D7
D8

W1

W2

B3

B7

AM5
AM7

FCBGA

CRESTLINE

OMIT

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

R1421

1

2

402

1/16W

1%

MF-LF

54.9

9D6

70D3

29D3 75C3

29D3 75C3

9D6

12B5 70D3

9A2

70B3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C4

70D3

9D8

70C3

9D8

70C3

9D8

70C3

9D8

70C3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70C3

9B4

70C3

9C4

70C3

9C4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9D8

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9D8

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9D8

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9B2

70C3

9C2

70C3

9C2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9D8

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9D6

70D3

SYNC_MASTER=T9_MLB

13 76

01

051-7455

NB CPU Interface

SYNC_DATE=10/30/2006

=PP1V25R1V05_S0_FSB_NB

FSB_D_L<47>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>

FSB_D_L<1>

FSB_D_L<10>

FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>

FSB_D_L<11>

FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>

FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>

FSB_D_L<32>

FSB_D_L<36>
FSB_D_L<37>

FSB_D_L<39>
FSB_D_L<40>

FSB_D_L<42>

FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>

FSB_D_L<48>

FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>

FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

NB_FSB_SCOMP
NB_FSB_SCOMP_L

FSB_CPURST_L
FSB_CPUSLP_L

FSB_D_L<6>

FSB_D_L<31>

FSB_D_L<24>

FSB_D_L<49>
FSB_D_L<50>

FSB_D_L<12>

FSB_D_L<43>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<0>

FSB_D_L<38>

FSB_D_L<41>

FSB_D_L<59>

NB_FSB_SWING
NB_FSB_RCOMP

NB_FSB_VREF

FSB_A_L<3>

FSB_A_L<6>

FSB_A_L<4>
FSB_A_L<5>

FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>

FSB_A_L<32>

FSB_A_L<30>
FSB_A_L<31>

FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>

FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>

FSB_BPRI_L

FSB_BNR_L

FSB_BREQ0_L
FSB_DEFER_L
FSB_DBSY_L

FSB_DPWR_L

FSB_CLK_NB_P
FSB_CLK_NB_N

FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L

FSB_TRDY_L

FSB_LOCK_L

FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>

FSB_DSTB_L_N<0>
FSB_DSTB_L_N<1>
FSB_DSTB_L_N<2>
FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0>
FSB_DSTB_L_P<1>
FSB_DSTB_L_P<2>
FSB_DSTB_L_P<3>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_RS_L<2>

29C6 29B6

7C7

IN

IN

OUT

IN

OUT
OUT
OUT

IN
IN

OUT
OUT
OUT

OUT

IN

OUT

OUT

BI

L_BKLT_CTRL

L_VDD_EN

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX14

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX15

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_COMPI
PEG_COMPO

CRT_DDC_DATA

L_CTRL_DATA

LVDSB_DATA1
LVDSB_DATA2

LVDSB_DATA0

LVDSB_DATA2*

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA2

LVDSA_DATA0
LVDSA_DATA1

LVDSB_CLK*

LVDS_VREFL

LVDS_IBG

TVC_RTN

TVA_RTN
TVB_RTN

TVC_DAC

TVB_DAC

TVA_DAC

CRT_RED*

CRT_RED

CRT_GREEN*

CRT_GREEN

CRT_BLUE*

CRT_BLUE

CRT_VSYNC

CRT_TVO_IREF

CRT_HSYNC

CRT_DDC_CLK

L_BKLT_EN

L_DDC_CLK

TV_DCONSEL0
TV_DCONSEL1

LVDSA_DATA2*

L_DDC_DATA

LVDSA_DATA1*

LVDSA_DATA0*

LVDSB_CLK

LVDSA_CLK

LVDSA_CLK*

LVDS_VREFH

L_CTRL_CLK

LVDS_VBG

VGA

TV

LVDS

(3 OF 10)

PCI-EXPRESS GRAPHICS

BI

BI

OUT

OUT

IN

IN
IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

IN

BI
BI

OUT
OUT
OUT
OUT

OUT
OUT

IN

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

IN

OUT
OUT
OUT

OUT

OUT

OUT

BI
BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

rails must be filtered except for VCCA_CRT.

Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).

decoupling. Otherwise, tie VCCD_LVDS to GND also.

Can leave all signals NC if LVDS is not implemented.

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can

share filtering with VCCA_CRT_DAC.

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.

Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

CRT & TV-Out Disable

All CRT/TVDAC rails must be powered. All

omit filtering components. Unused DAC outputs

VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,
VCCD_CRT, VCCD_QDAC and VCC_SYNC.

NOTE: Must keep VDDC_TVDAC powered
and filtered at all times!

Internal Graphics Disable

Follow instructions for LVDS and CRT & TV-Out Disable above.

TV_DCONSELx to GND.

Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and

Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.

Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).
Tie VCC_AXG and VCC_AXG_NCTF to GND.
Leave GFX_VID<3..0> and GFX_VR_EN as NC.

Tie TVx_DAC and TVx_RTN to GND. Must power all

TV-Out Disable / CRT Enable

CRT Disable / TV-Out Enable

VSYNC and CRT_TVO_IREF to GND.
Can tie the following rails to GND:

TV-Out Signal Usage:

Composite: DACA only

Component: DACA, DACB & DACC

should connect to GND through 75-ohm resistors.

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can

Tie VCC_TX_LVDS and VCCA_LVDS to GND.

LVDS Disable

If SDVO is used, VCCD_LVDS must remain powered with proper

SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP

SDVOB_BLUE
SDVOB_CLKP

SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVOC_RED#
SDVOC_GREEN#
SDVOC_BLUE#
SDVOC_CLKN

SDVOB_RED
SDVOB_GREEN

SDVO_FLDSTALL

SDVO_INT

SDVO_TVCLKIN

SDVO_INT#

SDVO_TVCLKIN#

SDVO Alternate Function

SDVO_FLDSTALL#

8C6

8C6

R1510

1

2

402

MF-LF

1/16W

1%

24.9

67B8

8C6

69B8

69A8

69A8

69D7

69D8

69D7

69A8

8C6

69B8

69A8

67A8 71C3

U1400

H32

G32

K33

G35

K29
J29

F33

F29

E29

C32

E33

J40
H39

E39

E40
C37

D35
K40

L41
L43

N41

N40

C45

D46

G50

G51

E50

E51

F48

F49

E42

D44

E44

G44

A47

B47

A45

B45

N43
M43

J50

J51

L50

L51

AC45

AD44

AC41

AD40

AH47

AG46

AG49

AH49

AH45

AG45

AG42

AG41

M47

N47

U44

T45

T49

T50

T41

U40

W45

Y44

W41

Y40

AB50

AB51

Y48

W49

M45

N45

T38

U39

AD47

AC46

AC50

AC49

AD43

AC42

AG39

AH39

AE50

AE49

AH43

AH44

T46

U47

N50

N51

R51

R50

U43

T42

W42

Y43

Y47

W46

Y39

W38

AC38

AD39

M35
P33

E27

F27

G27

J27

K27

L27

OMIT

CRESTLINE

FCBGA

12B1 67A7

12B1 67A7

69C8

69C8

8C6

8C6

8C6

8C6

8C6

8C6

8D6

68B6 71D3

8C6

8C6

8C6

8C6

8C6

8C6

8C6

8C6

8C6

68B6 71D3

8C6

8B6

8B6

8B6

68C6 71D3

68C6 71D3

8B6

8A6

8B6

8B6

8C6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8C6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8C6

68B6 71D3

68B6 71D3

68B6 71D3

68B6 71D3

68C6 71D3

68C6 71D3

67C6

67D8

8C6

67B6

67B6

67B3 71D3

67B3 71D3

8D6

8D6

67B2 71D3

67B2 71D3

8C6

67B2 71D3

8D6

8D6

8D6

67B2 71D3

67B2 71D3

67B2 71D3

8D6

8D6

8D6

8C6

69D8

69D8

69D8

69D7

69D7

69D7

69B8

69B8

SYNC_DATE=10/30/2006

14 76

01

051-7455

NB PEG / Video Interfaces

SYNC_MASTER=T9_MLB

=TV_B_RTN

=TV_B_DAC

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_CTRL_DATA

LVDS_CTRL_CLK

TP_LVDS_VBG

PEG_D2R_P<9>

PEG_D2R_P<11>

PEG_D2R_P<10>

PP1V05_S0_NB_VCCPEG

PEG_D2R_N<1>

PEG_D2R_N<6>

TP_LVDS_VREFH

LVDS_A_CLK_N
LVDS_A_CLK_P

LVDS_B_CLK_P

LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>

TV_DCONSEL<1>

TV_DCONSEL<0>

LVDS_BKLT_EN

CRT_DDC_CLK

=CRT_HSYNC_R
=CRT_TVO_IREF
=CRT_VSYNC_R

=CRT_BLUE
=CRT_BLUE_L
=CRT_GREEN
=CRT_GREEN_L
=CRT_RED
=CRT_RED_L

=TV_A_DAC

=TV_C_DAC

=TV_A_RTN

=TV_C_RTN

LVDS_IBG

TP_LVDS_VREFL

LVDS_B_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

CRT_DDC_DATA

PEG_COMP

PEG_D2R_N<0>

PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>

PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>

PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>

PEG_D2R_P<12>
PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>

PEG_D2R_P<14>

PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>

PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>

LVDS_BKLT_CTL

LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_VDD_EN

20D3 18B3

IN

IN

CLKREQ*

NC1

NC8

CL_CLK

CL_PWROK

CL_RST*

RSVD6

THERMTRIP*

PM_BM_BUSY*

RSVD4

RSVD3

RSVD7

SM_CKE1

SM_CK0*

SM_CKE0

SM_ODT0

SM_ODT2

SM_RCOMP

SM_RCOMP*

SM_VREF0
SM_VREF1

SM_RCOMP_VOL

SM_CS1*

SM_CS0*

RSVD14

RSVD11

RSVD10

RSVD9

RSVD5

RSVD8

RSVD2

DPLL_REF_CLK*

DPLL_REF_SSCLK

PEG_CLK

DMI_RXN1

DMI_RXN0

DMI_RXN3

DMI_RXN2

DMI_RXP0
DMI_RXP1
DMI_RXP2

DMI_TXN0

DMI_RXP3

DMI_TXN2

DMI_TXN1

DMI_TXP0

DMI_TXN3

DMI_TXP1
DMI_TXP2
DMI_TXP3

PEG_CLK*

RSVD12

CL_DATA

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

ICH_SYNC*

TEST1
TEST2

GFX_VID0
GFX_VID1
GFX_VID2

GFX_VR_EN

GFX_VID3

RSVD20
RSVD21

RSVD24
RSVD25

RSVD27

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39

RSVD41
RSVD42

RSVD40

RSVD43
RSVD44
RSVD45

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13

CFG16

CFG15

CFG14

CFG17
CFG18
CFG19
CFG20

PM_DPRSTP*
PM_EXT_TS0*

PWROK

PM_EXT_TS1*

RSTIN*

DPRSLPVR

NC2

NC4

NC3

NC5

NC7

NC6

NC10

NC9

NC12

NC11

NC13
NC14
NC15
NC16

DPLL_REF_CLK

SM_RCOMP_VOH

SM_ODT3

SM_ODT1

RSVD13

SM_CS2*
SM_CS3*

SM_CK3
SM_CK4

SM_CK4*

SM_CKE3

RSVD1

SM_CKE4

DPLL_REF_SSCLK*

SM_CK3*

SM_CK1*

SM_CK1

SM_CK0

SA_MA14

RSVD22
RSVD23

RSVD26

SB_MA14

SM_CK2
SM_CK2*
SM_CK5
SM_CK5*

(2 OF 10)

RSVD

DDR MUXING

CLK

CFG

DMI

PM

GRAPHICS VID

ME

MISC

NC

OUT
OUT
OUT
OUT
OUT

BI
BI

IN

OUT

BI

BI
OUT
OUT

IN

IN

OUT

OUT
OUT

IN
IN
IN
OUT

OUT
OUT
OUT

BI

OUT

BI

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT

IN

IN
IN

IN

IN

IN

IN

IN
IN
IN
IN

IN
IN

IN

IN

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

IPU

NB CFG<13:12> require ICT access

IPU

IPU

RESERVED

RESERVED

Low = DMIx2

NB_CFG<8>

IPU

IPU

IPU

IPU

IPU

IPU

IPU
IPU
IPU
IPU
IPD

IPD

IPD

IPU

RESERVED

NB_CFG<6>

NB_CFG<7>

RESERVED

RESERVED

RESERVED

High = Normal

Low = Reversed

NB_CFG<10>

NB_CFG<9>

PCIe Graphics
Lane Reversal

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

See Below

See Below

Low = Disabled

High = Enabled

10 = All-Z Mode Enabled

01 = XOR Mode Enabled

Low = Normal

High = Both active

NB_CFG<13:12>

Low = Only SDVO

High = Reversed

11 = Normal Operation

or PCIe x16

00 = RESERVED

NB_CFG<19>

NB_CFG<20>

Concurrent
SDVO/PCIe x1

Reversal

DMI Lane

NB_CFG<13>

NB_CFG<12>

NB_CFG<11>

NB_CFG<16>

NB_CFG<14>

NB_CFG<17>

ODT

FSB Dynamic

NB_CFG<15>

NB_CFG<18>

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
If ME/AMT is not used, short CL_PWROK to PWROK.

PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

NOTE: GMCH CL_PWROK input must be PWRGD signal for

DMI x2 Select

NB_CFG<5>

NB_CFG<4>

IPU

NB CFG<8:0> used for debug access

High = DMIx4

NB_CFG<3>

Clk used for PEG and DMI

27D1

20A4

C1616

1

2

402

CERM

20%

0.1uF

10V

C1615

1

2

402

CERM

20%

0.1uF

10V

U1400

P27
N27

R24

L23
J23

E23

E20
K23

M20

M24
L32

N33

N24

L35

C21
C23

F23

N23
G23

J20

C20

AM49

AK50
AT43

AN49
AM50

G39

AN47
AJ38

AN42

AN46

AM47
AJ39

AN41

AN45

AJ46
AJ41

AM40
AM44

AJ47

AJ42

AM39
AM43

B42

C42
H48

H47

G36

E35
A39

C38

B39
E36

G40

BJ51

E1
A5

C51

B50
A50

A49
BK2

BK51
BK50

BL50
BL49

BL3

BL2
BK1

BJ1

K44

K45

G41
L39

L36
J36

AW49

AV20

P36

AR37

AM36

AL36
AM37

D20

P37

H10

B51
BJ20

BK22

BF19
BH20

BK18
BJ18

R35

BH39

AW20
BK20

C48

D47

B44

N35

C44

A35

B37

B36

B34

C34

AR12

AR13

AM12
AN13

J12

BJ29
BE24

H35
K36

AV29

AW30

BB23

BA23

BF23

BG23

BA25

AW25

AV23

AW23

BC23

BD24

BE29

AY32

BD39
BG37

BG20

BK16

BG16
BE13

BH18

BJ15
BJ14

BE16

BL15

BK14

BK31
BL31

AR49

AW4

A37
R32

N20

CRESTLINE

FCBGA

OMIT

21B6 60C6

21B6 60C6

21B6 60C6

21B6 60C6

8B2

24C3 74A3

24C3 74A3

8B2

24C3 74A3

68A6

68A6

28B4

24B5

R1691

1

2

402

20K

MF-LF

1/16W

5%

R1690

1

2

402

0

MF-LF

1/16W

5%

24C3 59D8 70B3

8B2

44B8

R1631

1

2

402

10K

MF-LF

5%
1/16W

C1625

1

2

0.01UF

10%
16V

CERM

402

C1624

1

2

603

2.2UF

6.3V
CERM1

20%

R1624

1

2

1K

MF-LF

1%
1/16W

402

R1622

1

2

402

1%
1/16W
MF-LF

3.01K

C1622

1

2

603

6.3V
CERM1

2.2UF

20%

C1623

1

2

0.01UF

10%
16V

CERM

402

R1620

1

2

1K

402

1/16W

1%

MF-LF

R1641

1

2

402

392

MF-LF

1/16W

1%

R1640

1

2

402

MF-LF

1/16W

1K

1%

C1640

1

2

402

20%
10V

CERM

0.1uF

R1655

1

2

402

5%

3.9K

MF-LF

1/16W

NBCFG_DMI_X2

R1659

1

2

402

5%
1/16W
MF-LF

3.9K

NBCFG_PEG_REVERSE

R1666

1

2

402

NBCFG_DYN_ODT_DISABLE

3.9K

1/16W

5%

MF-LF

R1669

1

2

402

3.9K

MF-LF

1/16W

5%

NBCFG_DMI_REVERSE

R1670

1

2

402

5%
1/16W
MF-LF

3.9K

NBCFG_SDVO_AND_PCIE

60C6

30C4 32C6 72D3

31C4 32A5 72B3

29C8 70B3

29B8 70B3

29B8 70B3

8A6

8A6

8A6

8A6

15D7

24D5

8A6

R1600

1 2

0

5%
1/16W
MF-LF

402

9C6

22C2 45B3 70B3

8B2

44B8

9B2

22C4 59C7 70B3

27B5 59C7

30D4 72D3

31A4 72B3

31D4 72B3

30A4 72D3

30D4 72D3

31A4 72B3

31D4 72B3

30A4 72D3

30C6 32D6 72D3

30C4 32D6 72D3

31C6 32D6 72B3

30B4 32D6 72D3

31C4 32D5 72B3

30B6 32D6 72D3

31B4 32D6 72B3

31B6 32D6 72B3

30B4 32D6 72D3

30B6 32D6 72D3

31B4 32D6 72B3

31B6 32D6 72B3

R1610

1

2

MF-LF

1/16W

1%

20

402

R1611

1

2

1/16W

1%

MF-LF

20

402

20A5

29C3 75B3

29C3 75B3

8B2

8B2

8B2

8B2

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

R1630

1

2

402

MF-LF

1/16W

5%

10K

051-7455

01

7615

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

NB Misc Interfaces

GFX_VID<4>

DMI_N2S_P<0>

DMI_N2S_P<2>

CLINK_NB_CLK
CLINK_NB_DATA
=NB_CLINK_MPWROK
CLINK_NB_RESET_L

SDVO_CTRLCLK

TP_NB_RSVD<42>

TP_NB_RSVD<41>

TP_NB_RSVD<43>

NB_BSEL<1>

NB_CFG<3>

NB_CFG<9>

TP_NB_CFG<12>

TP_NB_CFG<15>
NB_CFG<16>

DMI_N2S_N<3>

DMI_N2S_P<1>

DMI_N2S_P<3>

GFX_VID<1>

=GFX_VR_EN

GFX_VID<3>

TP_LVDS_A_DATAP3

TP_NB_RSVD<34>

MEM_B_A<14>

TP_NB_RSVD<27>

TP_NB_RSVD<26>

TP_NB_RSVD<25>

NB_BSEL<0>

NB_CFG<5>

MEM_CKE<4>

TP_NB_RSVD<1>

MEM_CLK_P<0>

MEM_CLK_N<4>

MEM_CLK_N<3>

MEM_CLK_P<4>

MEM_CLK_P<3>

TP_NB_RSVD<13>

TP_NB_NC<16>

TP_NB_NC<15>

TP_NB_NC<14>

TP_NB_NC<13>

TP_NB_NC<11>
TP_NB_NC<12>

TP_NB_NC<9>
TP_NB_NC<10>

TP_NB_NC<6>
TP_NB_NC<7>

TP_NB_NC<5>

TP_NB_NC<3>

TP_NB_NC<2>

PM_EXTTS_L<0>

NB_CFG<20>

NB_CFG<19>

TP_NB_CFG<18>

TP_NB_CFG<14>

TP_NB_CFG<10>

TP_NB_RSVD<23>

TP_NB_RSVD<22>

TP_NB_RSVD<21>

TP_NB_RSVD<20>

NB_TEST2

NB_TEST1

TP_NB_RSVD<2>

TP_NB_RSVD<8>
TP_NB_RSVD<9>
TP_NB_RSVD<10>
TP_NB_RSVD<11>

MEM_CS_L<0>
MEM_CS_L<1>

MEM_CKE<0>

MEM_CLK_N<1>

MEM_CLK_P<1>

MEM_CLK_N<0>

TP_NB_RSVD<7>

TP_NB_RSVD<3>
TP_NB_RSVD<4>

TP_NB_NC<8>

TP_NB_NC<1>

NB_CLK100M_PCIE_P

DMI_S2N_P<0>

DMI_N2S_N<0>

SDVO_CTRLDATA
NB_CLKREQ_L
NB_SB_SYNC_L

TP_MEM_CLKN2
TP_MEM_CLKP5
TP_MEM_CLKN5

PM_BMBUSY_L
CPU_DPRSTP_L

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

MEM_CS_L<2>

MEM_ODT<2>
MEM_ODT<3>

MEM_CS_L<3>

MEM_ODT<0>
MEM_ODT<1>

TP_NB_RSVD<6>

TP_NB_RSVD<12>

TP_NB_NC<4>

DMI_S2N_P<3>

=PP0V9_S3M_MEM_NBVREFB

TP_NB_RSVD<5>

TP_NB_RSVD<24>

TP_MEM_CLKP2

TP_LVDS_A_DATAN3

TP_LVDS_B_DATAP3

MEM_A_A<14>

TP_NB_RSVD<35>
TP_NB_RSVD<36>

TP_LVDS_B_DATAN3

TP_NB_RSVD<45>

TP_NB_RSVD<14>

PM_DPRSLPVR

NB_RESET_L

PM_EXTTS_L<1>

NB_CFG<16>

=PP3V3_S0_NB_VCCHV

NB_CFG<19>

NB_CFG<20>

=PP3V3_S0_NB_VCCHV

TP_NB_CFG<11>

TP_NB_CFG<13>

=PP3V3_S0_NB_VCCHV

TP_NB_CFG<17>

PP1V25_S0M_NB_VCCAXD

NB_CLINK_VREF

NB_BSEL<2>

NB_CFG<6>
NB_CFG<7>
NB_CFG<8>

NB_CFG<5>

MEM_RCOMP_L

TP_NB_RSVD<44>

NB_CFG<4>

MEM_CKE<1>
MEM_CKE<3>

=PP0V9_S3M_MEM_NBVREFA

MEM_RCOMP_VOL

MEM_RCOMP

=PP1V8_S3M_MEM_NB

MEM_RCOMP_VOH

NB_CFG<9>

GFX_VID<0>

=NB_CLK96M_DOT_P
=NB_CLK96M_DOT_N
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N

NB_CLK100M_PCIE_N

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<1>
DMI_S2N_P<2>

DMI_N2S_N<1>
DMI_N2S_N<2>

GFX_VID<2>

21B7

21B7

20A8

20A8

21B7

31D2

18B3

18B3

20A8

30D2

15C7

15C7

18B3

20C8

15B7

15B7

15C7

20A6

17D7

15D7

15D7

8D6

15B6

15C7

15C7

8B4

8B4

8B4

8B4

8D6

8D6

8D6

15B6

7D4

15B6

15B6

7D4

7D4

18C3

74A3

7A4

15B6

BI

BI
BI
BI
BI
BI

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

BI
BI
BI

BI

BI
BI
BI
BI

BI BI

BI
BI
BI
BI
BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI
BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

BI

OUT

OUT

OUT

BI

BI

BI
BI
BI

BI

BI

BI

BI
BI
BI

BI
BI

BI

BI
BI

OUT

BI

BI

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

SA_DQ0
SA_DQ1
SA_DQ2

SA_DQ4

SA_DQ6

SA_DQ14

SA_CAS*

SA_BS2

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ34
SA_DQ35

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ30

SA_DQ28
SA_DQ29

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ20

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ13

SA_DQ11
SA_DQ12

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ3

SA_BS1

SA_BS0

SA_DQ45

SA_DM0
SA_DM1

SA_DM3

SA_DM2

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS1*

SA_DQS0*

SA_DQS2*

SA_DQS4*

SA_DQS3*

SA_DQS5*
SA_DQS6*
SA_DQS7*

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7

SA_MA9

SA_MA8

SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_RAS*

SA_RCVEN*

SA_WE*

DDR SYSTEM MEMORY A

(4 OF 10)

SB_DQ2

SB_DQ1

SB_DQ5

SB_DM0

SB_DQ0

SB_DQ4

SB_DQ6
SB_DQ7

SB_CAS*

SB_BS2

SB_BS0
SB_BS1

SB_DQ63

SB_DQ62

SB_DQ59

SB_DQ58

SB_DQ56

SB_DQ55

SB_DQ54

SB_DQ53

SB_DQ52

SB_DQ51

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ45
SB_DQ46

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ34
SB_DQ35

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ28
SB_DQ29

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQ24

SB_DQ23

SB_DQ22

SB_DQ21

SB_DQ20

SB_DQ19

SB_DQ18

SB_DQ17

SB_DQ16

SB_DQ15

SB_DQ14

SB_DQ13

SB_DQ11
SB_DQ12

SB_DQ10

SB_DQ9

SB_DQ8

SB_DQ3

SB_DQ57

SB_DQ61

SB_DQ60

SB_WE*

SB_RCVEN*

SB_RAS*

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA8
SB_MA9

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA2

SB_MA1

SB_MA0

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS3*
SB_DQS4*

SB_DQS2*

SB_DQS0*
SB_DQS1*

SB_DQS7

SB_DQS6

SB_DQS5

SB_DQS4

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS0

SB_DM6
SB_DM7

SB_DM4
SB_DM5

SB_DM2
SB_DM3

SB_DM1

(5 OF 10)

DDR SYSTEM MEMORY B

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT
OUT
OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

30A6 72D3

30C6 72C3

30B6 72C3

30B4 72C3

30A4 72C3

30A6 72C3

30A4 72C3

30A6 72C3

30B6 72C3

30B4 72C3

30C4 72C3

30A6 72D3

30C6 72C3

30D4 72C3

31A6 72B3

31A4 72B3

31A6 72B3

31A4 72B3

31A6 72B3

31A6 72B3

31A4 72B3

31A4 72B3

30A6 72D3 31A6 72B3

31A6 72B3

31A4 72B3

31A6 72B3

31A4 72B3

31A4 72B3

31B6 72B3

31A6 72B3

31A4 72B3

31A4 72B3

30A4 72D3

31B6 72B3

31A6 72B3

31B4 72B3

31B4 72B3

31A4 72B3

31A6 72B3

31B6 72B3

31B6 72B3

31B4 72B3

31B4 72B3

30A4 72D3

31B6 72B3

31C6 72B3

31C6 72B3

31B6 72B3

31B4 72B3

31B4 72B3

31C4 72B3

31C6 72B3

31C4 72B3

31C6 72B3

30A6 72D3

31C4 72B3

31C4 72B3

31C4 72B3

31C6 72B3

31C4 72B3

31C6 72B3

31C4 72B3

31C6 72B3

31C6 72B3

31C4 72B3

30A6 72D3

31D4 72B3

31D4 72B3

31D4 72B3

31D6 72B3

31D4 72B3

31D6 72B3

31D6 72B3

31D6 72B3

31D6 72B3

30A4 72D3

31D4 72B3

31D4 72B3

31D6 72B3

31D4 72B3

31D6 72B3

31D4 72B3

31D6 72B3

31B6 32A6 72B3

31B4 32A6 72B3

31B4 32A5 72B3

30A6 72D3

31C6 32A5 72B3

31B6 32B5 72B3

31C4 32A5 72B3

31C6 32B5 72B3

31C6 32B5 72B3

31C4 32B5 72B3

31B6 32B5 72B3

31C4 32B5 72B3

31B4 32B5 72B3

31B6 32B5 72B3

30A4 72D3

31B4 32B5 72B3

31B6 32B5 72B3

31B4 32B5 72B3

31A4 72A3

31A6 72A3

31C4 72A3

31B6 72A3

31B4 72A3

31C6 72A3

31D6 72A3

30A4 72D3

31A6 72A3

31A4 72A3

31D6 72A3

31B6 72A3

31A4 72A3

31C4 72A3

31D6 72A3

31C6 72A3

31A6 72A3

31D6 72A3

30A6 72D3

31A6 72B3

31A4 72A3

31C6 72B3

31B4 72B3

31C4 72B3

31D4 72B3

31D4 72B3

31B6 32A6 72B3

31C6 32A6 72B3

31B6 32A6 72B3

30A4 72D3

31B4 32A6 72B3

U1400

BB19

BK19

BF29

BL17

AT45

BD44
BD42

AW38

AW13
BG8

AY5
AN6

AR43

AW44

BG47
BJ45

BB47

BG50
BH49

BE45

AW43
BE44

BG42

BE40

BA45

BF44

BH45
BG40

BF40

AR40
AW40

AT39

AW36
AW41

AY41

AY46

AV38
AT38

AV13
AT13

AW11

AV11
AU15

AT11

BA13
BA11

AR41

BE10

BD10

BD8

AY9

BG10

AW9

BD7
BB9

BB5

AY7

AR45

AT5

AT7

AY6
BB7

AR5
AR8

AR9

AN3
AM8

AN10

AT42

AT9
AN9

AM9

AN11

AW47

BB45
BF48

AT46

AT47

BE48

BD47

BB43

BC41

BC37

BA37

BB16

BA16

BH6

BH7

BB2

BC1

AP3

AP2

BJ19
BD20

BC19

BE28
BG30

BJ16

BK27
BH28

BL24

BK28
BJ27

BJ25

BL28
BA28

BE18

AY20

BA19

OMIT

CRESTLINE

FCBGA

U1400

AY17

BG18

BG36

BE17

AR50

BD49
BK45

BL39

BH12
BJ7

BF3
AW2

AP49

AR51

BA49
BE50

BA51

AY49
BF50

BF49

BJ50
BJ44

BJ43

BL43

AW50

BK47

BK49
BK43

BK42

BJ41
BL41

BJ37

BJ36
BK41

BJ40

AW51

BL35
BK37

BK13
BE11

BK11

BC11
BC13

BE12

BC12
BG12

AN51

BJ10

BL9
BK5

BL5
BK9

BK10

BJ8
BJ6

BF4

BH5

AN50

BG1

BC2

BK3
BE4

BD3
BJ2

BA3

BB3
AR1

AT3

AV50

AY2
AY3

AU2

AT2

AV49

BA50
BB50

AT50

AU50

BD50

BC50

BK46

BL45

BK39

BK38

BJ12

BK12

BL7

BK7

BE2

BF2

AV2

AV3

BC18
BG28

BG17

BE37
BA39

BG13

BG25
AW17

BF25

BE25
BA29

BC28

AY28
BD37

AV16

AY18

BC17

OMIT

CRESTLINE

FCBGA

30B4 72D3

30A6 72D3

30B6 72D3

30B6 72D3

30B4 72D3

30B6 72D3

30B6 72D3

30D4 72D3

30B4 72D3

30B6 72D3

30B4 72D3

30B4 72D3

30B6 72D3

30B4 72D3

30C6 72D3

30C4 72D3

30D4 72D3

30C4 72D3

30A6 72D3

30C6 72D3

30C4 72D3

30C6 72D3

30D6 72D3

30C6 72D3

30C4 72D3

30C6 72D3

30C4 72D3

30C6 72D3

30C6 72D3

30A4 72D3

30C4 72D3

30C4 72D3

30D4 72D3

30D4 72D3

30D6 72D3

30D4 72D3

30D4 72D3

30D6 72D3

30D6 72D3

30D6 72D3

30A4 72D3

30D6 72D3

30D4 72D3

30D4 72D3

30D4 72D3

30D6 72D3

30D6 72D3

30D6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30C6 32C6 72D3

30A4 72D3

30B6 32B6 72D3

30D4 72C3

30B4 32C6 72D3

30B4 32B6 72D3

30B6 32B6 72D3

30C6 32C6 72D3

30C4 32C6 72D3

30B6 32C6 72D3

30C6 32C6 72D3

30A6 72D3

30C6 32C6 72D3

30C4 32C6 72D3

30C4 32C6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30D6 72C3

30A4 72D3

30D6 72C3

30C4 72C3

30C6 72C3

30B6 72C3

30B4 72C3

30A4 72C3

30A6 72C3

30D6 72C3

30D6 72C3

30C4 72C3

16 76

01

051-7455

NB DDR2 Interfaces

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

MEM_A_DQ<35>

TP_MEM_A_RCVEN_L TP_MEM_B_RCVEN_L

MEM_B_DQ<39>

MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>

MEM_B_DM<0>

MEM_B_CAS_L

MEM_B_DM<1>
MEM_B_DM<2>

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>

MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<1>

MEM_B_DQS_P<7>
MEM_B_DQS_N<0>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<7>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>

MEM_B_RAS_L

MEM_B_A<13>

MEM_B_WE_L

MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>

MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_CAS_L

MEM_A_BS<2>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_DM<0>
MEM_A_DM<1>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>

MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

VCC_SM20

VCC_AXG_NCTF42

VCC_SM9
VCC_SM10

VCC_SM17

VCC_SM16

VCC3

VCC_SM5

VCC_SM8

VCC_AXG_NCTF1
VCC_AXG_NCTF2
VCC_AXG_NCTF3
VCC_AXG_NCTF4
VCC_AXG_NCTF5
VCC_AXG_NCTF6

VCC_AXG_NCTF8

VCC_AXG_NCTF7

VCC_AXG_NCTF10

VCC_AXG_NCTF9

VCC_AXG_NCTF11
VCC_AXG_NCTF12
VCC_AXG_NCTF13
VCC_AXG_NCTF14
VCC_AXG_NCTF15
VCC_AXG_NCTF16

VCC_AXG_NCTF18

VCC_AXG_NCTF17

VCC_AXG_NCTF20

VCC_AXG_NCTF19

VCC_AXG_NCTF21
VCC_AXG_NCTF22

VCC_AXG_NCTF25
VCC_AXG_NCTF26

VCC_AXG_NCTF28

VCC_AXG_NCTF27

VCC_AXG_NCTF29
VCC_AXG_NCTF20
VCC_AXG_NCTF31
VCC_AXG_NCTF32
VCC_AXG_NCTF33
VCC_AXG_NCTF34
VCC_AXG_NCTF35
VCC_AXG_NCTF36

VCC_AXG_NCTF38

VCC_AXG_NCTF37

VCC_AXG_NCTF40

VCC_AXG_NCTF39

VCC_AXG_NCTF41

VCC_AXG_NCTF43
VCC_AXG_NCTF44
VCC_AXG_NCTF45
VCC_AXG_NCTF46

VCC_AXG_NCTF48

VCC_AXG_NCTF47

VCC_AXG_NCTF49
VCC_AXG_NCTF50
VCC_AXG_NCTF51

VCC_AXG_NCTF55

VCC_AXG_NCTF58

VCC_AXG_NCTF57

VCC_AXG_NCTF59

VCC_AXG_NCTF61

VCC_AXG_NCTF60

VCC_AXG_NCTF62
VCC_AXG_NCTF63
VCC_AXG_NCTF64

VCC_AXG_NCTF66

VCC_AXG_NCTF65

VCC_AXG_NCTF67
VCC_AXG_NCTF68
VCC_AXG_NCTF69

VCC_AXG_NCTF71

VCC_AXG_NCTF70

VCC_AXG_NCTF72
VCC_AXG_NCTF73
VCC_AXG_NCTF74

VCC_AXG_NCTF76

VCC_AXG_NCTF75

VCC_AXG_NCTF77
VCC_AXG_NCTF78
VCC_AXG_NCTF79

VCC_AXG_NCTF81

VCC_AXG_NCTF80

VCC_AXG_NCTF82
VCC_AXG_NCTF83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC_AXG_NCTF56

VCC_AXG_NCTF54

VCC_AXG_NCTF53

VCC_AXG_NCTF52

VCC_AXG1
VCC_AXG2
VCC_AXG3
VCC_AXG4
VCC_AXG5
VCC_AXG6
VCC_AXG7
VCC_AXG8
VCC_AXG9
VCC_AXG10
VCC_AXG11
VCC_AXG12
VCC_AXG13
VCC_AXG14
VCC_AXG15
VCC_AXG16
VCC_AXG17
VCC_AXG18
VCC_AXG19
VCC_AXG20
VCC_AXG21
VCC_AXG22
VCC_AXG23
VCC_AXG24
VCC_AXG25
VCC_AXG26
VCC_AXG27
VCC_AXG28
VCC_AXG29
VCC_AXG30
VCC_AXG31
VCC_AXG32
VCC_AXG33
VCC_AXG34

VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4

VCC_SM6
VCC_SM7

VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15

VCC_SM18
VCC_SM19

VCC_SM21
VCC_SM22
VCC_SM23

VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36

VCC_SM25

VCC_SM24

VCC1
VCC2

VCC7
VCC8
VCC9
VCC10
VCC11
VCC12

VCC13

VCC_AXG_NCTF24

VCC_AXG_NCTF23

VCC6

VCC5
VCC4

VCC GFX

VCC SM

VCC SM LF

(6 OF 10)

VCC CORE

POWER

VCC GFX NCTF

VCC_NCTF49

VCC_NCTF15

VCC_NCTF2

VCC_NCTF10

VCC_AXM7

VCC_AXM5

VCC_AXM4

VCC_AXM3

VCC_AXM2

VCC_AXM1

VSS_SCB6

VSS_SCB5

VSS_SCB4

VSS_SCB3

VSS_SCB2

VSS_SCB1

VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF12

VSS_NCTF11

VSS_NCTF13

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_NCTF22

VCC_NCTF27

VCC_NCTF50

VCC_NCTF47
VCC_NCTF48

VCC_NCTF44

VCC_NCTF43

VCC_NCTF39
VCC_NCTF40

VCC_NCTF38

VCC_NCTF37

VCC_NCTF34
VCC_NCTF35

VCC_NCTF33

VCC_NCTF32

VCC_NCTF31

VCC_NCTF29

VCC_NCTF28

VCC_NCTF26

VCC_NCTF24
VCC_NCTF25

VCC_NCTF23

VCC_NCTF21

VCC_NCTF18
VCC_NCTF19

VCC_NCTF16
VCC_NCTF17

VCC_NCTF3
VCC_NCTF4

VCC_NCTF41
VCC_NCTF42

VCC_NCTF45
VCC_NCTF46

VCC_AXM6

VCC_AXM_NCTF1
VCC_AXM_NCTF2
VCC_AXM_NCTF3
VCC_AXM_NCTF4
VCC_AXM_NCTF5
VCC_AXM_NCTF6
VCC_AXM_NCTF7
VCC_AXM_NCTF8
VCC_AXM_NCTF9
VCC_AXM_NCTF10
VCC_AXM_NCTF11
VCC_AXM_NCTF12
VCC_AXM_NCTF13
VCC_AXM_NCTF14
VCC_AXM_NCTF15
VCC_AXM_NCTF16
VCC_AXM_NCTF17
VCC_AXM_NCTF18
VCC_AXM_NCTF19

VCC_NCTF8

VCC_NCTF20

VCC_NCTF1

VCC_NCTF5
VCC_NCTF6
VCC_NCTF7

VCC_NCTF36

VCC_NCTF30

VCC_NCTF9

VCC AXM NCTF

VCC NCTF

VSS SCBVCC AXM

VSS NCTF

(7 OF 10)

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1395 mA (1 ch, 533MHz)

1700 mA (1 ch, 667MHz)

2700 mA (2 ch, 533MHz)

3300 mA (2 ch, 667MHz)

540 mA

1573 mA (Int Graphics)

1310 mA (Ext Graphics)

7700 mA (Int Graphics)

5 mA (standby)

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

Current numbers from Crestline EDS, doc #21749.

U1400

AT35

AH31
AH29

AF32

R30

AT34
AH28

AC31

AC32

AK32

AJ31
AJ28

AH32

R20

AB21
AB24

AB29

AC20
AC21

AC23

AC24
AC26

AC28

AC29

T14

AD20

AD23
AD24

AD28

AF21
AF26

AA31

AH20
AH21

AH23

W13

AH24
AH26

AD31
AJ20

AN14

W14

Y12
AA20

AA23

AA26
AA28

T17

U17
U19

U20

U21
U23

U26
V16

V17

V19
V20

T18

V21

V23
V24

Y15

Y16
Y17

Y19
Y20

Y21

Y23

T19

Y24

Y26

Y28
Y29

AA16

AA17
AB16

AB19
AC16

AC17

T21

AC19
AD15

AD16

AD17
AF16

AF19

AH15
AH16

AH17
AH19

T22

AJ16

AJ17
AJ19

AK16

AK19
AL16

AL17

AL19
AL20

AL21

T23

AL23

AM15

AM16
AM19

AM20

AM21
AM23

AP15

AP16
AP17

T25

AP19
AP20

AP21

AP23
AP24

AR20

AR21
AR23

AR24

AR26

U15

V26

V28
V29

Y31

U16

AU32

BA35

BB33

BC32
BC33

BC35

BD32
BD35

BE32
BE33

BE35

AU33

BF33
BF34

BG32

BG33
BG35

BH32

BH34
BH35

BJ32
BJ33

AU35

BJ34

BK32
BK33

BK34

BK35
BL33

AU30

AV33
AW33

AW35
AY35

BA32

BA33

AW45

BC39

BE39
BD17

BD4
AW8

AT6

OMIT

FCBGA

CRESTLINE

U1400

AT33

AT31
AK29

AK24

AK23
AJ26

AJ23

AL24

AP29

AP31

AP32
AP33

AL29

AL31
AL32

AR31

AR32
AR33

AL26

AL28

AM26
AM28

AM29

AM31
AM32

AM33

AB33

AF36
AH33

AH35

AH36
AH37

AJ33

AJ35
AK33

AK35
AK36

AB36

AK37

AD33
AJ36

AM35

AL33
AL35

AA33

AA35
AA36

AP35

AB37

AP36

AR35

AR36

Y32

Y33

Y35
Y36

Y37

T30
T34

AC33

T35
U29

U31

U32
U33

U35

U36
V32

V33

V36

AC35

V37

AC36

AD35
AD36

AF33

T27

AD19
AD37

AF17

AF35
AK17

AM17
AM24

AP26

AP28
AR15

T37

AR19

AR28

U24

U28
V31

V35

AA19
AB17

AB35

A3
B2

C1

BL1
BL51

A51

OMIT

CRESTLINE

FCBGA

C1806

1

2

402

0.1uF

10V

CERM

20%

C1807

1

2

402

0.1uF

10V

CERM

20%

C1804

1

2

402

X5R

0.22UF

6.3V

20%

C1805

1

2

402

X5R

0.22UF

6.3V

20%

C1802

1

2

402

10%

CERM

1uF

6.3V

C1803

1

2

402

10%

0.47UF

6.3V

CERM-X5R

C1801

1

2

402

10%

CERM

1uF

6.3V

17 76

01

051-7455

NB Power 1

SYNC_DATE=10/30/2006

SYNC_MASTER=T9_MLB

=PPVCORE_S0_NB

=PP1V05_S0M_NB_VCCAXM

=PPVCORE_S0_NB_GFX

=PP1V8_S3M_MEM_NB

=PPVCORE_S0_NB

=PPVCORE_S0_NB_GFX

NB_VCCSM_LF6

NB_VCCSM_LF4

NB_VCCSM_LF3

NB_VCCSM_LF2

NB_VCCSM_LF1

NB_VCCSM_LF7

NB_VCCSM_LF5

=PP1V05_S0M_NB_VCCAXM

31D2

20D8

48B3

30D2

20D8

48B3

20B4

20D8

21C5

20C8

20B4

21C5

20D8

17D7

17C1

17B7

15D2

17D3

17D5

17B3

7C7

7C7

7B7

7A4

7C7

7B7

7C7

VCCA_CRT_DAC1

VTT7
VTT8

VCC_AXD_NCTF

VCCD_CRT

VCC_RXR_DMI1
VCC_RXR_DMI2

VTT1

VCCA_SM_CK2 VCC_TX_LVDS

VCC_HV2

VCC_PEG1
VCC_PEG2
VCC_PEG3

VCC_AXF2

VCC_AXD1
VCC_AXD2

VSSA_LVDS

VCCA_SM5

VCCA_PEG_PLL

VCCA_MPLL

VCCA_HPLL VTT16

VTT17

VTT15

VCCD_LVDS2

VCCD_LVDS1

VCCD_PEG_PLL

VCCD_HPLL

VCCD_QDAC

VCCD_TVDAC

VCCA_TVC_DAC1
VCCA_TVC_DAC2

VCCA_TVB_DAC2

VCCA_TVB_DAC1

VCCA_TVA_DAC2

VCCA_TVA_DAC1

VCCA_SM_CK1

VCCA_SM2

VCCA_SM1

VCCA_SM_NCTF2

VCCA_SM_NCTF1

VCCA_SM11

VCCA_SM10

VCCA_SM9

VCCA_SM8

VCCA_SM7

VCCA_SM4

VCCA_SM3

VSSA_PEG_BG

VCCA_PEG_BG

VCCA_LVDS

VCCA_DPLLB

VCCA_DPLLA

VSSA_DAC_BG

VCCA_DAC_BG

VCC_AXF3

VCC_HV1

VCC_PEG5

VTTLF1

VTTLF3

VTTLF2

VCC_PEG4

VCC_SM_CK3

VCC_SM_CK2

VCC_SM_CK1

VCC_SM_CK4

VCC_DMI

VCC_AXF1

VTT22

VCC_AXD6

VCC_AXD5

VCC_AXD4

VCC_AXD3

VTT19

VTT2

VTT6

VTT5

VTT11

VTT10

VTT9

VTT13

VTT12

VTT14

VTT18

VTT21

VTT20

VTT3
VTT4

VCCA_CRT_DAC2

VCC_SYNC

CRT

AXD

PEG

HV

AXF

VTTLF

VTT

SM CK

DMI

TV/CRT

D

LVDS

A SMA CK

CRT A LVDS

A PEG

PLL

(8 OF 10)

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

100 mA

100 mA

100 mA

200 mA

5 mA

50 mA

100 mA

10 mA

40 mA

40 mA

40 mA

60 mA

250 mA

150 mA

5 mA

S0 or S3M is acceptable

S0 or S3M is acceptable

TBD mA @ 1067MHz FSB (1.25V)

150 mA

770 mA @ 667MHz FSB (1.05V)

1260 mA

260 mA

0.4 mA

80 mA

30 mA

60 mA

100 mA

35 mA

850 mA @ 800MHz FSB (1.05V)

495 mA

515 mA

Current numbers from Crestline EDS, doc #21749.

640 mA (667MHz DDR)
550 mA (533MHz DDR)

C1911

1

2

0.47UF

10%

CERM-X5R
402

6.3V

C1913

1

2

0.47UF

10%

6.3V
CERM-X5R
402

C1912

1

2

0.47UF

10%

6.3V
CERM-X5R
402

U1400

AT23

AU28
AU24

AT29

AT25
AT30

AR29

B23

B21
A21

AJ50

C40

B40

AD51
W50

W51

V49
V50

AH50

AH51

BK24

BK23

BJ24
BJ23

J32

A43

A33
B33

A30

B49

H49

AL2

A41

AM2

K50

U51

AW18

AT18

AT17

AV19

AU19
AU18

AU17

AT22

AT21

AT19

BC29

BB29

AR17

AR16

C25
B25

C27
B27

B28

A28

M32

AN2

J41
H42

U48

N28

L29

B32

B41

K49

U13

U1

T13
T11

T10
T9

T7

T6
T5

T3

T2

U12

R3

R2

R1

U11

U9

U8
U7

U5

U3
U2

A7
F2

AH1

OMIT

FCBGA

CRESTLINE

051-7455

01

7618

NB Power 2

SYNC_DATE=10/30/2006

SYNC_MASTER=T9_MLB

NB_VTTLF_CAP2

=PP1V8_S0_NB_VCCD_LVDS

PP1V25_S0_NB_VCCA_DPLLA

PP1V25_S0M_NB_VCCA_HPLL

PP3V3_S0_NB_VCCA_TVDACA

=PP1V5_S0_NB_VCCD_CRT
PP1V5_S0_NB_VCCD_TVDAC

PP1V5_S0_NB_VCCD_QDAC

=PP1V25_S0M_NB_VCCD_HPLL

=GND_NB_VSSA_LVDS

PP3V3_S0_NB_VCCA_DAC_BG

PP1V25_S0M_NB_VCCA_MPLL

NB_VTTLF_CAP1

NB_VTTLF_CAP3

=PP1V25_S0_NB_VCCDMI

=GND_NB_VSSA_DAC_BG

=GND_NB_VSSA_PEG_BG

PP1V8_S0_NB_VCCTXLVDS

PP1V05_S0_NB_VCCPEG

=PP3V3_S0_NB_VCCHV

PP1V05_S0_NB_VCCRXRDMI

PP1V25_S0_NB_VCCAXF

PP1V25_S0M_NB_VCCAXD

PP3V3_S0_NB_VCCA_TVDACC

PP1V25_S0_NB_VCCA_DPLLB

PP3V3_S0_NB_VCCA_TVDACB

=PP1V25R1V05_S0_NB_VTT

PP1V8_S0_NB_VCCTXLVDS

PP3V3_S0_NB_VCCA_CRTDAC

=PP3V3_S0_NB_VCCSYNC

PP1V25_S0M_NB_VCCA_SM_CK

PP1V25_S0_NB_PEGPLL

PP1V8_S3M_NB_VCCSMCK

PP1V25_S0M_NB_VCCA_SM

=PP3V3_S0_NB_VCCA_PEG_BG

21B7

20A8 15C7

20A8

21C3

20D3

15B7

20A6

20C8

21C3

21B5

20A6

21B3

21A3

20D1

21D1

21C7

21D6

21C5

20D1

21B3

21B1

20C1

7C7

21B1

20A6

18C6

14D2

7D4

20C3

20D5

15A2

21C1

21A3

21C1

7C7

18B3

21D1

7C4

20B5

20B2

20A2

20B5

7C4

VSS198VSS99

VSS197VSS98

VSS196VSS97

VSS195VSS96

VSS194VSS95

VSS193VSS94

VSS192VSS93

VSS191VSS92

VSS190VSS91

VSS189VSS90

VSS188VSS89

VSS187VSS88

VSS186VSS87

VSS185VSS86

VSS184VSS85

VSS183VSS84

VSS182VSS83

VSS181VSS82

VSS180VSS81

VSS179VSS80

VSS178VSS79

VSS177VSS78

VSS176VSS77

VSS175VSS76

VSS174VSS75

VSS173VSS74

VSS172VSS73

VSS171VSS72

VSS170VSS71

VSS169VSS70

VSS168VSS69

VSS167VSS68

VSS166VSS67

VSS165VSS66

VSS164VSS65

VSS163VSS64

VSS162VSS63

VSS161VSS62

VSS160VSS61

VSS159VSS60

VSS158VSS59

VSS157VSS58

VSS156VSS57

VSS155VSS56

VSS154VSS55

VSS153VSS54

VSS152VSS53

VSS151VSS52

VSS150VSS51

VSS149VSS50

VSS148VSS49

VSS147VSS48

VSS146VSS47

VSS145VSS46

VSS144VSS45

VSS143VSS44

VSS142VSS43

VSS141VSS42

VSS140VSS41

VSS139VSS40

VSS138VSS39

VSS137VSS38

VSS136VSS37

VSS135VSS36

VSS134VSS35

VSS133VSS34

VSS132VSS33

VSS131VSS32

VSS130VSS31

VSS129VSS30

VSS128VSS29

VSS127VSS28

VSS126VSS27

VSS125VSS26

VSS124VSS25

VSS123VSS24

VSS122VSS23

VSS121VSS22

VSS120VSS21

VSS119VSS20

VSS118VSS19

VSS117

VSS116VSS17

VSS115VSS16

VSS114VSS15

VSS113VSS14

VSS112VSS13

VSS111VSS12

VSS110VSS11

VSS109VSS10

VSS108

VSS9

VSS107VSS8

VSS106VSS7

VSS105VSS6

VSS104VSS5

VSS103VSS4

VSS102

VSS101

VSS100

VSS1

VSS18

VSS2
VSS3

VSS

(9 OF 10)

VSS202

VSS289
VSS290
VSS291
VSS292

VSS295

VSS199 VSS287
VSS200 VSS288
VSS201

VSS203
VSS204

VSS293
VSS294

VSS208 VSS296
VSS209 VSS297
VSS210 VSS298
VSS211 VSS299
VSS212 VSS300
VSS213 VSS301
VSS214
VSS215
VSS216 VSS302
VSS217
VSS218
VSS219 VSS303
VSS220
VSS221
VSS222 VSS304
VSS223
VSS224
VSS225 VSS305
VSS226
VSS227
VSS228
VSS229 VSS306
VSS230 VSS307
VSS231 VSS308
VSS232 VSS309
VSS233 VSS310
VSS234 VSS311
VSS235 VSS312
VSS236 VSS313
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243

VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286

VSS207

VSS206

VSS205

(10 OF 10)

VSS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TDE_SENSE

TDE_FORCE

TDB_FORCE

alias these nets directly to GND.

Mainly for investigation. If not used,

NOTE: TDB = _N

TDB_SENSE

Crestline Thermal Diode Pins

NOTE: TDE = _P

U1400

A13

AB26

AW24

AW29
AW32

AW5

AW7
AY10

AY24

AY37
AY42

AY43

AB28 AY45

AY47

AY50
B10

B20

B24
B29

B30

B35
B38

AB31

B43

B46
B5

B8
BA1

BA17

BA18
BA2

BA24

BB12

AC10

BB25

BB40

BB44
BB49

BB8
BC16

BC24

BC25
BC36

BC40

AC13

BC51
BD13

BD2

BD28
BD45

BD48
BD5

BE1

BE19
BE23

AC3

BE30

BE42
BE51

BE8

BF12
BF16

BF36
BG19

BG2

BG24

AC39

BG29

BG39

BG48
BG5

BG51

BH17
BH30

BH44
BH46

BH8

AC43

BJ11
BJ13

BJ38

BJ4
BJ42

BJ46

BK15
BK17

BK25
BK29

AC47

BK36

BK40
BK44

BK6

BK8
BL11

BL13

BL19
BL22

BL37

AD1

BL47

C12

C16
C19

C28

C29
C33

C36

C41

A15

AD21

AD26

AD29

AD3

AD41
AD45

AD49

AD5

AD50

AD8

A17

AE10
AE14

AE6

AF20
AF23

AF24
AF31

AG2

AG38
AG43

A24

AG47

AG50

AH3

AH40

AH41

AH7

AH9
AJ11

AJ13

AJ21

AA21

AJ24

AJ29

AJ32
AJ43

AJ45

AJ49
AK20

AK21
AK26

AK28

AA24

AK31
AK51

AL1

AM11
AM13

AM3

AM4
AM41

AM45

AN1

AA29

AN38

AN39
AN43

AN5

AN7

AP4

AP48

AP50
AR11

AR2

AB20

AR39

AR44

AR47

AR7

AT10

AT14
AT41

AT49

AU1
AU23

AB23

AU29

AU3

AU36

AU49
AU51

AV39

AV48

AW1

AW12

AW16

FCBGA

OMIT

CRESTLINE

U1400

C46

C50

C7

D13

D24

D3

D32

D39
D45

D49

E10
E16

E24
E28

E32

E47
F19

F36

F4
F40

F50

G1
G13

G16
G19

G24

G28
G29

G33

G42
G45

G48

G8
H24

H28

H4

H45

J11
J16

J2

J24
J28

J33

J35
J39

K12

K47

K8

L1

L17

L20
L24

L28

L3
L33

L49
M28

M42

M46
M49

M5

M50

M9

N11

N14
N17

N29
N32

N36

N39
N44

N49

N7
P19

P2

P23

P3

P50
R49

T39

T43
T47

U41

U45
U50

V2

V3

W11

W39
W43

W47

W5
W7

Y13

Y2
Y41

Y45

Y49
Y5

Y50
Y11

P29

T29

T31

T33

R28

AA32

AB32

AD32
AF28

AF29
AT27

AV25

H50

FCBGA

OMIT

CRESTLINE

051-7455

01

7619

NB Grounds

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

=NB_TDB_SENSE

=NB_TDB_FORCE

=NB_TDE_FORCE

=NB_TDE_SENSE

8A2

8A2

8A2

8A2

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

this is "1 of 2" 1.8V bulk decoupling caps.

spec requires "3.9uH ferrite,1A,32mohm max".

5.6nH,0.9A,45mohm max.no bigger than 0603

WF: Matanzas has 270uF

and DDR2 taps." (C2125)

Memory I/O logic and DLL voltage.

WF: 220-ohm

Memory voltage supply.

??? mA

540 mA

These supplies are still needed even using external GPU

250mA,0.5ohm

250mA,0.5ohm

MPLL Analog Supply

GMCH Core Power

100 mA

450 mA

Host PLL Analog Supply

200 mA

LAYOUT NOTE: PLACE THOSE COMPONENT CLOSE TO GMCH

200 mA

5 mA

Current numbers from Crestline EDS Addendum, doc #20127.

50 mA

150 mA

850 mA

GMCH FSB I/O Rail

200 mA

100 mA

100 mA

Memory clock logic voltage.

200 mA

250 mA

Host PLL Digital Supply

Layout Note: Route to caps, then GND

WF: Should be 1.0, 1%

100 mA

??? mA

1200 mA

Layout Note:

be close to MCH
on opposite side.

Analog PLL Voltage for PCI-E GPU

need to find "1uH,220mA,150mohm max"

I/O voltage Supply

350 mA

1450 mA

Layout Note:

??? mA

WF: "Place where LVDS

Place L and C
close to MCH

GMCH ME Core Power

GMCH Memory I/O Rail

2400 mA

WF: Should be 1.0, 1%

NOTE: This follower is redundant if VCORE is always 1.05V.

on opposite side.

be close to MCH

10uF caps should

Layout Note:

250 mA

RX and I/O Logic for DMI

10uF caps should

Analog,I/O logic,and Term Voltage for PCI-E Graphics

C2124

1

2

CERM-X5R

10%

0.47UF

6.3V
402

C2123

1

2

6.3V

CERM1

603

2.2uF

20%

C2121

1

2

4.7uF

6.3V
CERM

20%

603

C2100

1

2 3

470UF

20%

2.5V
TANT

D2T

C2112

1

2

402

X5R

6.3V

20%

0.22uF

C2111

1

2

402

6.3V

20%
X5R

C2122

1

2

20%

4.7uF

6.3V
CERM

603

C2131

1

2

805

CERM

22UF

PLACEMENT_NOTE=Place close to U1400

20%

6.3V

C2132

1

2

805

CERM

22UF

6.3V

20%

PLACEMENT_NOTE=Place close to U1400

C2135

1

2

CERM

20%

0.1UF

10V

R2183

1

2

1/16W
MF-LF

402

1%

0.51

R2190

1

2

MF-LF

1/16W

1%

402

1.1

1 2

C2190

1

2

X5R

20%

6.3V

10uF

1

2

C2174

1

2

10uF

20%

6.3V
X5R
603

C2173

1

2

20%

POLY

2.5V

220UF

CASE-B2

L2173

1 2

91NH

1210

R2195

1

2

402

1/16W
MF-LF

1%

1.1

L2195

1 2

1.0UH-0.23A

0603

C2195

1

2

6.3V

20%

10uF

X5R
603

C2196

1

2

CERM

22UF

805

20%

6.3V

C2171

1

2

402

1UF

10%

6.3V
CERM

C2170

1

2

10uF

20%

6.3V
X5R
603

C2151

1

1UF

402

CERM

10%

C2150

1

2

10uF

6.3V
X5R
603

20%

NOSTUFF

C2142

1

2

805

CERM

22UF

20%

6.3V

C2143

1

2

4.7UF

603

6.3V

10%
X5R-CERM

C2144

1

2

1UF

CERM

6.3V

10%

402

R2141

1 2

MF-LF

1/16W

0

5%

C2145

1

2

805

CERM

22UF

6.3V

20%

1 2

5%

0

C2147

1

2

402-LF

NOSTUFF

20%

2.2UF

6.3V
CERM

C2148

1

2

402

CERM

10V

20%

0.1UF

R2186

1 2

402

MF-LF

1/16W

1%

10

R2112

1

2

1%

1/16W

402

1K

1

2

1/16W
MF-LF

1%

402

1K

R2110

1

2

1%

MF-LF

1/16W

1K

402

R2111

1

2

1/16W
MF-LF

1%

402

1K

L2183

1 2

0402-LF

120-OHM-0.3A-EMI

C2113

1

2

20%

0.1UF

CERM

10V
402

C2114

1

2

CERM

10V

20%

0.1UF

402

C2115

1

2

20%
10V
CERM
402

1

2

CERM

10V

20%

0.1UF

402

C2161

1

2

402

20%
10V
CERM

2

402

CERM

10V

20%

C2197

1

2

0.1UF

402

CERM

10V

20%

C2191

1

2

CERM

10V

20%

0.1UF

402

C2192

1

2

0.1UF

10V
CERM
402

20%

C2182

1

2

402

0.1UF

CERM

10V

20%

C2180

1

2

0.1UF

402

CERM

10V

20%

C2110

1

2

805

CERM

22UF

20%

6.3V

R2109

1 2

MF-LF

402

0

1/16W

5%

D2186

12

1SS418

SOD-723

L2181

1 2

120-OHM-0.3A-EMI

0402-LF

C2104

1

2

402

20%
10V

0.1UF

CERM

C2177

1

2

10uF

20%

6.3V
X5R
603

C2103

1

2

PLACEMENT_NOTE=Place in GMCH cavity

6.3V

20%
X5R

402

0.22uF

C2102

1

2

402

PLACEMENT_NOTE=Place in GMCH cavity

X5R

20%

0.22uF

6.3V

C2184

1

2

10V
CERM
402

PLACEMENT_NOTE=Place C2184 by U1400.AM2

0.1UF

20%

C2181

1

2

CERM

22UF

6.3V

20%

805

C2183

1

2

22UF

CERM

805

20%

6.3V

C2101

1

2

805

CERM

22UF

PLACEMENT_NOTE=Place in GMCH cavity

6.3V

20%

76

01

20

SYNC_DATE=06/15/2006

SYNC_MASTER=WFERRY

NB Standard Decoupling

051-7455

PP1V25_S0M_NB_VCCA_SM

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

=PPVCORE_S0_NB

=PP1V25_S0_NB_VCC

=PP0V9_S3M_MEM_NBVREFB

=PP3V3_S0_NB_VCCHV

=PP1V8_S3_NB_VCC

=PP3V3_S0_NB_FOLLOW

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V

PP1V8_S3_NB_VCCSMCK_RC

=PP1V8_S3_MEMVREF

PP1V25_S0M_NB_VCCA_MPLL

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

=PP1V25_S0M_NB_VCCD_HPLL

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.4 MM

PP0V9_S3M_MEM_NBVREFB

=GND_NB_VSSA_PEG_BG

=PP1V25_S0_NB_VCCDMI

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.25 MM
VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_PEGPLL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM
VOLTAGE=1.05V

=PP1V25_S0_NB_PLL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.25V

PP1V25_S0_NB_VCCAXF

=PP1V25_S0_NB_VCCAXF

=PP1V05_S0_NB_PCIE

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V

MIN_LINE_WIDTH=0.25 MM

PP1V8_S3M_NB_VCCSMCK

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

=PP1V25_S0_NB_PLL

=PP1V25R1V05_S0_NB_VTT

=PPVCORE_S0_NB

PP1V25_S0M_NB_VCCA_HPLL

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0M_NB_MPLL_RC

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

PP1V25_S0M_NB_VCCA_SM_CK

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0_NB_PEGPLL_RC

VOLTAGE=1.25V

=PP1V05_S0M_NB_VCCAXM

PLACEMENT_NOTE=Place in GMCH cavity

0.22uF

0.1UF

CRITICAL

=PP1V25_S0_NB_VCCA

402

R2145

1/16W
MF-LF

402

PP1V25_S0M_NB_VCCAXD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

6.3V

2

=PP3V3_S0_NB_VCCA_PEG_BG

1

0.1UF 0.1UF

C2165

R2113

=PP0V9_S3M_MEM_NBVREFA

VOLTAGE=0.9V

MF-LF

PP0V9_S3M_MEM_NBVREFA

=PP1V8_S3_MEMVREF

603

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

0603

FERR-220-OHM-2.5A

L2190

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_NBCORE_FOLLOW_R

PP1V05_S0_NB_VCCRXRDMI

PP1V05_S0_NB_VCCPEG

CRITICAL

CRITICAL

OMIT

PLACEMENT_NOTE=Place close to U1400

402

C2160

CRITICAL

CASE-C2

POLY

2.5V

20%

330UF

C2130

=PP1V8_S3M_MEM_NB

CRITICAL

20%

POLY

330UF

2.0V

CASE-B2

2

1

C2140

OMIT

OMIT

21B7

31D2

20D8

18B3

20B4

30D2

17D7

15C7

17D7

17C1

17D7

17D3

18C3

15B7

20A6

20A5

18C3

20B4

18B3

20D3

18D3

17D3

17B3

15D2

18C6

18C6

7C7

15A2

7C7

15C2

7D4

7A4

7D4

7B4

7B4

18D6

18A6

18C6

7C7

18C6

18B3

7C7

18C3

7C7

7C7

18B3

14D2

7C7

7C7

7C7

7C7

18D6

7C7

7A4

18B6

7C4

OUT

EN

NR/FB

IN

GND

THRML

NC

EN

IN

OUT

NR

PAD

GND

OUT
OUT
OUT
OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Matanzas has 2x 330uF

NEED TO FIND A "1#GH, 500MA, 78MOHM" INDUCTOR

WF: Should be 1uH, 30%

260 mA

Layout Note: Route to cap, then GND

WARNING VOLTAGE DROP

VCCD_TVDAC also powers internal thermal sensors.

0011=1.21025V

1000=1.08150V

VID<3:0>=1001=1.05575V

65 mA

WF: Check part properties

10 mA

6 mA

5 mA

Vout = 1.204V * (Ra + Rb)/Rb

110 mA

Layout Note:

80 mA

80 mA

WF: Is this the best part to use?

These 2 caps should be
within 6.35 mm of NB edge

80 mA

125 mA

80 mA

Layout Note:
These 8 caps should be

Layout Note: Route to caps, then GND

within 6.35 mm of NB edge

40 mA

5 mA

40 mA

40 mA

80 mA

Layout Note:

Current numbers from Crestline EDS Addendum, doc #20127.

150 mA

60 mA

(1.7V - 5.5V)

NC

205 mA

Ra || Rb should be 19Kohms

7700 mA

WF: Check C2266 value, R2267 value

GMCH Graphics Core Power
These 4 caps should be
within 6.35 mm of NB edge

205 mA

NOTE: This filter is required even if using only external graphics.

C2289

2

1 3

CRITICAL

22000pF-1000mA

NFM18

16V

C2282

1

2

0.01UF

CERM

402

10%
16V

R2205

1

2

MF-LF

5%

100

1/16W
402

C2207

1

2

402

0.1UF

CERM

10V

20%

R2281

1

2

402

1/16W
MF-LF

5%

0

C2281

1

2

1UF

NO STUFF

CERM
402

6.3V

10%

C2280

1

2

402

CERM

6.3V

1UF

10%

C2292

2

1 3

CRITICAL

22000pF-1000mA

NFM18

16V

C2291

1

2

0.1UF

402

20%
10V
CERM

C2294

2

1 3

22000pF-1000mA

CRITICAL

NFM18

16V

C2293

1

2

402

20%
10V
CERM

0.1UF

C2288

1

2

402

20%
10V
CERM

0.1UF

C2296

2

1 3

CRITICAL

NFM18

22000pF-1000mA

16V

C2295

1

2

402

20%
10V
CERM

0.1UF

C2298

2

1 3

CRITICAL

22000pF-1000mA

NFM18

16V

C2297

1

2

402

20%
10V
CERM

0.1UF

C2290

1

2

10uF

603

X5R

20%

6.3V

L2290

1 2

120-OHM-0.3A-EMI

0402-LF

R2261

1 2

1/16W

5%

MF-LF

0

402

C2261

1

2

0.1UF

402

CERM

10V

20%

R2262

1 2

1/16W
MF-LF

5%

0

402

C2262

1

2

20%
10V
CERM

0.1UF

C2223

1

2

CERM

0.001uF

402

50V

20%

C2221

1

2

0.001uF

402

CERM

50V

20%

C2201

2

1 3

22000pF-1000mA

CRITICAL

16V

NFM18

C2206

2

1 3

NFM18

16V

22000pF-1000mA

CRITICAL

C2200

1

2

402

20%
10V
CERM

0.1UF

C2205

1

2

X5R

10%

1UF

10V
402

L2220

1 2

1007

C2220

1

CASE-B2-SM

220UF

20%

POLY

CRITICAL

C2217

1

2

PLACEMENT_NOTE=Place in GMCH cavity

20%

402

10V
CERM

0.1UF

C2216

1

2

402

20%
10V
CERM

0.1UF

PLACEMENT_NOTE=Place in GMCH cavity

C2215

1

2

402

CERM-X5R

6.3V

10%

0.47UF

PLACEMENT_NOTE=Place in GMCH cavity

C2213

1

2

603

X5R

6.3V

20%

10uF

PLACEMENT_NOTE=Place in GMCH cavity

C2212

1

2

6.3V
805

PLACEMENT_NOTE=Place in GMCH cavity

20%

22UF

CERM

C2210

1

2 3

CRITICAL

2.5V
D2T

TANT

470UF

20%

C2226

1

2

1UF

10%

6.3V
402

CERM

R2285

1 2

NO STUFF

1%

MF-LF

1/16W

402

10

L2288

1 2

120-OHM-0.3A-EMI

0402-LF

C2214

1

2

402

6.3V

10%
CERM

1UF

PLACEMENT_NOTE=Place in GMCH cavity

C2265

1

2

10%

1UF

CERM

6.3V
402

R2266

1

2

603

FF

0.300

5%
1/10W

C2266

1

2

603

10UF

20%
X5R

6.3V

C2230

1

2

10V
CERM
402

20%

0.1UF

C2285

1

2

20%

10UF

603

X5R

6.3V

U2265

3

2

1

4

5

CRITICAL

TPS731125

SOT23-5

C2267

1

2

10%
CERM

0.01UF

16V
402

D2285

12

1SS418

SOD-723

NO STUFF

U2280

4

3

6

5

2

1

7

CRITICAL

SON

TPS79933

15B3 60C6

15B3 60C6

15B3 60C6

15B3 60C6

R2245

1

2

1/16W
MF-LF

5%

22K

402

R2250

1

2

MF-LF
402

22K

5%
1/16W

NO STUFF

R2244

1

2

1/16W
MF-LF

5%

22K

402

NO STUFF

R2243

1

2

22K

5%
MF-LF

1/16W
402

NO STUFF

R2249

2

MF-LF

1/16W

5%

22K

402

1

2

1/16W
MF-LF
402

22K

5%

R2242

1

2

402

1/16W

22K

5%
MF-LF

1

2

402

1/16W
MF-LF

22K

NB Graphics Decoupling

01

76

SYNC_MASTER=WFERRY

SYNC_DATE=06/15/2006

21

051-7455

VOLTAGE=1.5V

PP1V5_S0_NB_VCCD_QDAC

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V5_S0_NB_QDAC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP3V3_S0_NB_TVDAC

PP1V8_S0_NB_VCCTXLVDS

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V

MIN_LINE_WIDTH=0.2 MM

=PP3V3_S0_NB_VCCHV

=GND_NB_VSSA_DAC_BG

P3V3TVDAC_EN_RC

=PP1V8_S0_NB_DPLL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V

PP3V3_S0_NB_VCCA_CRTDAC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PP3V3_S0_NB_VCCA_TVDACA

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM
VOLTAGE=3.3V

PP3V3_S0_NB_VCCA_TVDACC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM
VOLTAGE=3.3V

PP3V3_S0_NB_VCCA_DAC_BG

PP3V3_S0_NB_TVDAC_F

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

PP1V25_S0_NB_VCCA_DPLLB

MIN_LINE_WIDTH=0.3 MM

PP3V3_S0_NB_VCCA_TVDACB

MIN_LINE_WIDTH=0.3 MM
VOLTAGE=3.3V

P3V3TVDAC_NOISE

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_NB_TVDAC_FOLLOW

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

PP1V25_S0_NB_DPLL_RF

P1V25S0NBDPLL_FB

PP1V5_S0_NB_VCCD_CRT

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V

PP1V5_S0_NB_VCCD_TVDAC

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

PP1V5_S0_NB_VCCD_CRT

MAKE_BASE=TRUE

=PP1V5_S0_NB_VCCD_CRT

=GND_NB_VSSA_LVDS

=PP3V3_S0_NB_VCCSYNC

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0_NB_DPLL

VOLTAGE=1.25V

PP1V25_S0_NB_VCCA_DPLLA

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

=PPVCORE_S0_NB_GFX

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V

PP3V3_S0_NB_CRTDAC_F

GFX_VID<2>

GFX_VID<1>

GFX_VID<0>

GFX_VID<3>

R2247

1

R2248

5%

NO STUFF

=PP1V5_S0_NB_TVDAC

=PP1V8_S0_NB_VCCD_LVDS

402

MIN_NECK_WIDTH=0.2 MM

=PP1V5_S0_NB_FOLLOW

=PP5V_S0_NB_TVDAC

2

2.5V

1.0UH-0.5A-0.675A

=PP1V8_S0_NB_LVDS

OMIT

20A8 18B3

48B3

15C7

17D5

18C6

15B7

18D6

17B7

7A7

7B7

18B6

18B3

7D4

18D6

7B7

18D6

18B6

18B6

18D6

18D6

18B6

21C5

18B6

21D6

18B6

18C6

18A6

7B7

7C4

18D6

7B7

7B7

SATA0RXP

SATA0RXN

SATALED*

RTCRST*

HDA_BIT_CLK

DDREQ

RTCX1
RTCX2

DCS1*
DCS3*

IDEIRQ

DDACK*

IORDY

DIOR*
DIOW*

DD11
DD12

DD4

DD2

DD14

DD0

DD15

DD1

DD13

DD5

DD10

DD8

DD3

DD9

LDRQ0*

FWH2/LAD2
FWH3/LAD3

FWH1/LAD1

LDRQ1*/GPIO23

FWH0/LAD0

FWH4/LFRAME*

HDA_SDIN0

HDA_SYNC

SATA1TXN
SATA1TXP

HDA_SDIN1
HDA_SDIN2

RCIN*

SATA0TXP

SATA0TXN

CPUPWRGD/GPIO49

SMI*

A20M*

SATA1RXP

SATA1RXN

SATARBIAS

SATARBIAS*

IGNNE*

DPRSTP*

INTVRMEN

A20GATE

SATA2RXN
SATA2RXP

THRMTRIP*

DPSLP*

INIT*

HDA_RST*

HDA_SDOUT

HDA_DOCK_EN*/GPIO33

SATA2TXN
SATA2TXP

FERR*

NMI

HDA_SDIN3

INTR

SATA_CLKP

SATA_CLKN

DA2

DD6

STPCLK*

TP8

DA0
DA1

HDA_DOCK_RST*/GPIO34

INTRUDER*

LAN_TXD0

LAN100_SLP

LAN_RSTSYNC

LAN_RXD0
LAN_RXD1
LAN_RXD2

DD7

LAN_TXD2

LAN_TXD1

GLAN_DOCK*/GPIO13

GLAN_COMPI
GLAN_COMPO

GLAN_CLK

LAN/GLANIHDA

CPU

RTC

LPC

(1 OF 6)

SATA

IDE

OUT

IN

IN

IN

BI

BI
BI

BI

BI

OUT

OUT

IN

IN

OUT

OUT

IN

IN
OUT
OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT
OUT

IN

OUT

OUT
OUT
OUT

IN
IN
IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT
OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

IN

IN

OUT
OUT

OUT

OUT

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

INT PU

INT PU

INT PU

INT PD

HDA

24.000MHZ CLOCK W/INTERNAL WEAK PD

HDA_BIT_CLK

HDA_RST#

HDA_SDIN[0-2]

HDA_SDOUT

ACZ_SYNC

INTEGRATED PDs

INTEGRATED PD

INTEGRATED PD

INT PDINT PU

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PU

INT PU

INT PU

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

U2300

AF13
AG26

AG29

AA4

AA1
AB3

Y6

Y5

V1
U2

T4

V6
V5

U1
V2

U6

V3
T1

V4

T5
AB2

T6

T3
R2

Y2

W5

W4
W3

AF26

AE26

AD24

E5

F5
G8

F6

C4

B24

D25

C25

AH21

AJ16

AE10

AG14

AE14

AJ17
AH17

AH15

AD13

AE13

AJ15

Y3

AF27

AE24

AC20

AD22

AF25

Y1

AD21

D22

C21
B21

C22

D21

E20
C20

G9

E6

AD23

AH14

AF23

AG25

AF24

AF6

AF5

AH5
AH6

AG3

AG4

AJ4
AJ3

AF2
AF1

AE4

AE3

AB7
AC6

AF10

AG2

AG1

AG28

AA24

AE27

AA23

OMIT

BGA

ICH8M

27C8

27C8

27D5

27C5

6D2

44C8 46C6

6C2

44C8 46C4

6C2

44C8 46C4

6D2

44C8 46C6

6C2

44C8 46B6

9C8

70C3

R2304

1

2

402

MF-LF

1/16W

5%

2.2K

NO STUFF

R2302

1

2

402

1%

24.9

MF-LF

1/16W

R2301

1

2

1%

332K

MF-LF
402

1/16W

40C4 73D3

40D4 73D3

40D4 73D3

40D4 73D3

8D4

8D4

8D4

8D4

8D4

8D4

8D4

8D4

29C3 75B3

29C3 75B3

40D2

40D2

9B2

15B6 59C7 70B3

9B2

70B3

9C8

70C3

9B2

12B1 70C3

39C3 73D3

39B5 73D3

39B3 73D3

39B5 73D3

39B5 73D3

39C3 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39B5 73D3

39B5 73D3

39B3 73D3

9B8

70B3

9B8

70C3

9B8

70B3

9C8

70B3

9D6

46B2 70B3

9B8

70C3

R2306

1

2

10K

MF-LF
402

5%
1/16W

9C6

15A6 45B3 70B3

R2308

1 2

PLACEMENT_NOTE=Place R2308 within 50mm of U2300

1%

MF-LF

1/16W

24.9

402

8A6

73C3

R2300

1

2

1/16W

1%

332K

402

MF-LF

R2303

1

2

8.2K

5%
1/16W
MF-LF

402

8A6

73C3

8A6

73C3

8A6

73B3

8A6

73C3

R2310

1

2

402

MF-LF

1/16W

5%

8.2K

R2305

1

2

1%
1/16W
MF-LF

402

54.9

R2309

1

2

1%
1/16W
MF-LF
402

54.9

PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)

R2313

1 2

402

33

MF-LF1/16W

5%

R2314

1 2

5%

1/16W MF-LF33402

R2315

1 2

1/16W33MF-LF5%402

R2316

1 2

5%

1/16W MF-LF

402

33

R2311

1

2

1/16W

402

MF-LF

10K

5%

39B3 73D3

39B5 73D3

01

22 76

051-7455

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

SB Enet, Disk, FSB, LPC

PP3V3_G3_SB_RTC

SB_RTC_X1
SB_RTC_X2

HDA_DOCK_EN_L

LAN_ENERGY_DET

=PP3V3_S0_SB_GPIO

PP1V5_S0_SB_VCC1_5_B

GLAN_COMP

SB_INTVRMEN
SB_LAN100_SLP

SB_SM_INTRUDER_L

SB_RTC_RST_L

TP_LAN_R2D<2>

LPC_AD<2>

LPC_AD<0>
LPC_AD<1>

LPC_AD<3>

LPC_FRAME_L

EXTGPU_PWR_EN

PM_THRMTRIP_L

CPU_THERMTRIP_R

CPU_A20M_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD

CPU_IGNNE_L

CPU_INIT_L
CPU_INTR

CPU_NMI
CPU_SMI_L

CPU_STPCLK_L

IDE_PDD<0>

IDE_PDD<2>

IDE_PDD<1>

IDE_PDD<3>
IDE_PDD<4>
IDE_PDD<5>

IDE_PDD<7>

IDE_PDD<6>

IDE_PDD<8>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<12>

IDE_PDD<11>

IDE_PDD<13>

IDE_PDD<15>

IDE_PDD<14>

IDE_PDA<0>
IDE_PDA<1>
IDE_PDA<2>

IDE_PDCS3_L

IDE_PDCS1_L

IDE_PDIOW_L

IDE_PDIOR_L

IDE_PDDACK_L
IDE_IRQ14
IDE_PDIORDY
IDE_PDDREQ

=PP1V05_S0_SB_CPU_IO

=PP3V3_S0_SB_GPIO

CPU_FERR_L

SB_A20GATE

TP_LPC_DRQ0_L

SB_RCIN_L

TP_SB_TP8

TP_LAN_D2R<2>

SATA_A_D2R_P

TP_SB_SATALED_L

SATA_A_R2D_C_P

SATA_A_R2D_C_N

SATA_B_D2R_P

SATA_B_D2R_N

TP_HDA_DOCK_RST_L

TP_LAN_R2D<0>

TP_LAN_RSTSYNC

TP_LAN_D2R<0>

TP_LAN_R2D<1>

SATA_B_R2D_C_N
SATA_B_R2D_C_P

SATA_C_D2R_P

SATA_C_D2R_N

SATA_C_R2D_C_N
SATA_C_R2D_C_P

SB_CLK100M_SATA_P

SB_CLK100M_SATA_N

SATA_RBIAS_P

SATA_RBIAS_N

HDA_BIT_CLK_R
HDA_SYNC_R

HDA_RST_L_R

HDA_SDOUT_R

HDA_SYNC

HDA_BIT_CLK

HDA_RST_L

HDA_SDOUT

SATA_A_D2R_N

TP_HDA_SDIN1

TP_ENET_GLAN_CLK

TP_LAN_D2R<1>

HDA_SDIN0

TP_HDA_SDIN3

TP_HDA_SDIN2

24D8

26C6

24D8

27D4

24B3

26A4

26C4

24B3

26A5

22D2

25D6

25C3

22D7

25D6

7D4

23C2

74B3

7D7

7D4

73C3

73C3

73C3

73B3

8A6

8A6

8A6

SPI_CS1*

PETN1

PERP1

OC4*/GPIO43
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31
OC8*
OC9*

SPI_MOSI

OC0*
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42

PERN5

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI_CLKN
DMI_CLKP

PETP1

USBP9N
USBP9P

PERN2

USBP7N
USBP7P
USBP8N
USBP8P

PETN2

USBP6N
USBP6P

PERP3

USBP4N
USBP4P
USBP5N
USBP5P

PETN3

PETP3

USBP3N
USBP3P

PERN4
PERP4

USBP1N
USBP1P
USBP2N
USBP2P

PETN4
PETP4

USBP0N
USBP0P

PERP5

SPI_MISO

USBRBIAS

USBRBIAS*

PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0*

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI_IRCOMP

DMI_ZCOMP

PERN1

PERP2

PETP2

PERN3

PETN5

PCI_EXPRESS

DIRECT MEDIA INTERFACE

SPI

USB

(2 OF 6)

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

IN
OUT
OUT

IN

IN
OUT
OUT

BI
BI

BI

BI

AD4
AD5

AD9

PIRQF*/GPIO3

PIRQE*/GPIO2

AD13

PME*

PCIRST*

GNT2*/GPIO53

C/BE2*

PIRQG*/GPIO4

SERR*

PIRQA*

AD1

REQ1*/GPIO50

C/BE3*

AD11

C/BE1*

AD25
AD26

AD0

AD2

DEVSEL*

AD18

AD21

PAR

GNT0*

AD7

GNT1*/GPIO51

C/BE0*

STOP*

AD20

AD16

GNT3*/GPIO55

TRDY*

IRDY*

AD22

PIRQC*

REQ2*/GPIO52

AD19

PCICLK

PLOCK*

AD15

PIRQB*

PIRQH*/GPIO5

PLTRST*

AD3

AD6

AD8

FRAME*

AD14

AD12

AD10

REQ3*/GPIO54

PIRQD*

AD17

PERR*

REQ0*

AD31

AD27
AD28

AD30

AD29

AD24

AD23

(3 OF 6)

INTERRUPT I/F

PCI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

BI

BI

BI

BI

BI
BI

OUT

BI
BI
BI

BI

BI

BI

BI

OUT

IN

BI
BI

IN

IN

IN
IN
IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PCIe Mini Card

rises, or PCIe ports 5 & 6 will be disabled.

NOTE: GNT[0-3]# have internal 20K pull-ups

Provide a pull-down on this GPIO if not used.

R2415 pull-down on GNT0#

Nineveh-GLCI

Yukon-PCIE

enabled only when PCIRST# = 0 and PWROK = 1

If used, ensure GNT2# is not low when PWROK

INT PU

INT PU

FireWire INT*

SPI

I/F

LPC

NOTE:

0

GNT0#

1

INT PU

INT PU

INT PU

SB BOOT BIOS SELECT

GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

high for x2)

pull HDA_SYNC

(x2-capable,

Ethernet

(AirPort)

FireWire

ExpressCard

Spares

INT PD

INT PD

INT PD

EHCI1

INT PU

INT PU

INT PU

INT PU

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

EHCI0

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

External C

Camera

AirPort (PCIe Mini-Card)

ExpressCard

External B

Geyser Trackpad/Keyboard

External A

External D / WWAN

Bluetooth

IR

NOTE: USBP[0-9]P/N have internal 15K pull-downs.

selects SPI ROM by default.

R2408

1

2

5%

10K

402

1/16W
MF-LF

R2407

1

2

1/16W
MF-LF
402

10K

5%

R2400

1

2

10K

402

5%
1/16W
MF-LF

R2409

1

2

1/16W
402

MF-LF

5%

10K

R2401

1

2

MF-LF
402

5%

10K

1/16W

R2402

1

2

402

5%
1/16W
MF-LF

10K

R2404

1

2

402

1/16W
MF-LF

10K

5%

R2403

1

2

10K

MF-LF
402

1/16W

5%

U2300

V27

V26
U29

U28

Y27

Y26

W29
W28

AB26
AB25

AA29
AA28

AD27
AD26

AC29

AC28

T26

T25

Y24

Y23

AJ19
AG16

AG15

AE15
AF15

AG17

AD12
AJ18

AD14
AH18

P27

M27

K27

H27

F27

D27

P26

M26

K26

H26

F26

D26

N29

L29

J29

G29

E29

C29

N28

L28

J28

G28

E28

C28

C23

B23

E22

F21

D23

G3
G2

H5

H4
H2

H1

J3
J2

K5
K4

K2

K1
L3

L2

M5
M4

M2

M1
N3

N2

F3

F2

BGA

ICH8M

OMIT

15B3 71D3

15B3 71D3

15C3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15C3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

29C3 75B3

29C3 75B3

R2413

1 2

1%

402

MF-LF1/16W

24.9

8C1

73B3

8C1

73B3

8C1

73B3

8C1

73B3

8C1

8C1

8C1

73B3

8C1

73B3

8C1 8C2

73B3

8C1 8C2

73B3

8C1

73B3

8C1

73B3

8B1 8B2

73B3

8C1 8C2

73B3

8B1

73B3

8B1

73B3

8B1

73B3

8B1

73B3

8B1

73B3

8B1

73B3

R2414

1 2

22.6

MF-LF

402

1%

1/16W

33B6

33B6

33B6

33B6

34C8

34C8

34C8

34C8

52C7 73A3

52C7 73A3

52C3 73A3

52C3 73A3

U2300

D20
E19

A12

E16
A14

G16

A15

B6

C11

A9
D11

B12

D19

C12

D10

C7
F13

E11

E13
E12

D8

A6

E8

A20

D6

A3

D17

A21

A19
C19

A18
B16 C17

E15

F16
E17

D16

A17

D7

C18

F18

C10

C8
D9

B10

G6

A7

F9

B5

C5
A10

F8

G11

F12
B3

B7

AG24

G7

A4

E18

B19

A11

F10

C16

C9

OMIT

BGA

ICH8M

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B6 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

23A4 74C3

23A4 74C3

23A4 74C3

23A4 37A5 74C3

23A4 74D3

23A4 37A5 74D3

23A4 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

23A4 37A5 74D3

37B5 74D3

37A6

23A4 37A5 74D3

23A4 37A5 74D3

23A4 74D3

23A4 37A5 74D3

23A4 37A5 74D3

23A4 37A5 74D3

23A4 37A5 74D3

27D4 67C6

29A5 29B3 75B3

23A4 74C3

R2405

1

2

5%

402

MF-LF

1/16W

10K

R2406

1

2

1/16W

5%

MF-LF

100K

402

NOSTUFF

R2415

1

2

MF-LF

1K

1/16W

5%

402

R2423

1 2

8.2K

R2424

1 2

8.2K

R2425

1 2

8.2K

R2426

1 2

8.2K

R2427

1 2

8.2K

R2428

1 2

8.2K

R2430

1 2

8.2K

R2429

1 2

8.2K

R2432

1 2

8.2K

R2431

1 2

8.2K

R2433

1 2

8.2K

R2437

1 2

8.2K

R2439

1 2

8.2K

R2438

1 2

8.2K

R2436

1 2

8.2K

R2440

1 2

8.2K

23A4 74C3

R2441

1 2

8.2K

8C1

8B1

23A4 39C8

68A4 68B8

37A5 74D3

39A8 73D3

6C2

46B6

R2442

1 2

8.2K

39B8

33B6

SYNC_DATE=10/30/2006

051-7455

7623

01

SYNC_MASTER=T9_MLB

SB PCI, PCIe, DMI, USB

SB_GPIO42

=PP3V3_S5_SB_USB

EXTGPU_LVDS_EN

MAKE_BASE=TRUE

PCI_FW_GNT_L

TP_SB_GPIO55

TP_SB_GPIO51

ODD_RST_5VTOL_L

SB_GPIO30

USB_EXTA_OC_L

USB_EXTB_OC_L
EXCARD_OC_L

SB_GPIO40
USB_EXTD_OC_L

USB_EXTC_OC_L

ODD_PWR_EN_L

INT_PIRQF_L

INT_PIRQE_L

PCI_FRAME_L

PCI_TRDY_L

PCI_STOP_L

PCI_LOCK_L

PCI_PERR_L

PCI_RST_L

PCI_PAR

PCI_FW_REQ_L

TP_SB_GPIO53

PCI_C_BE_L<0>

PCI_C_BE_L<2>

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

TP_SPI_CE_R_L<1>

PCI_DEVSEL_L

PM_LATRIGGER_L

TP_PCIE_A_R2D_C_P

PCI_AD<14>

PCI_AD<4>
PCI_AD<5>

PCI_AD<9>

PCI_AD<13>

INT_PIRQA_L

PCI_AD<1>

PCI_AD<11>

PCI_AD<25>
PCI_AD<26>

PCI_AD<0>

PCI_AD<2>

PCI_AD<18>

PCI_AD<21>

PCI_AD<7>

PCI_AD<20>

PCI_AD<16>

PCI_AD<22>

INT_PIRQC_L

PCI_AD<19>

PCI_AD<15>

INT_PIRQB_L

PCI_AD<3>

PCI_AD<6>

PCI_AD<8>

PCI_AD<12>

PCI_AD<10>

INT_PIRQD_L

PCI_AD<17>

PCI_AD<31>

PCI_AD<27>
PCI_AD<28>

PCI_AD<30>

PCI_AD<29>

PCI_AD<24>

PCI_AD<23>

BOOT_LPC_SPI_L

PCI_REQ1_L

PCI_C_BE_L<3>

PCI_SERR_L

PCI_REQ1_L

PCI_TRDY_L

INT_PIRQE_L

INT_PIRQD_L

INT_PIRQB_L

INT_PIRQA_L

PCI_REQ2_L

PCI_STOP_L

PCI_IRDY_L

PCI_FRAME_L

PCI_FW_REQ_L

PCI_LOCK_L

INT_PIRQF_L

INT_PIRQC_L

ODD_PWR_EN_L

PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L

=PP3V3_S0_SB_PCI

PP1V5_S0_SB_VCC1_5_B

USB_RBIAS

DMI_IRCOMP_R

TP_PCIE_A_R2D_C_N

TP_PCIE_A_D2R_P

SPI_SI_R

PCIE_MINI_D2R_N

TP_PCIE_B_D2R_N

TP_PCIE_B_R2D_C_N

TP_PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_R2D_C_N
TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_FW_D2R_N
TP_PCIE_FW_D2R_P
TP_PCIE_FW_R2D_C_N
TP_PCIE_FW_R2D_C_P

PCIE_MINI_D2R_P

PCIE_ENET_D2R_N

SPI_SCLK_R
SPI_CE_R_L<0>

TP_PCIE_A_D2R_N

TP_PCIE_B_D2R_P

TP_PCIE_B_R2D_C_P

TP_PCIE_EXCARD_D2R_N

USB_EXTC_P

USB_EXCARD_P
USB_EXTC_N

USB_EXCARD_N

USB_EXTB_P

USB_EXTB_N

USB_BT_P

USB_TPAD_P
USB_BT_N

USB_TPAD_N

USB_IR_P

USB_IR_N

USB_CAMERA_N
USB_CAMERA_P

USB_EXTD_P

USB_EXTD_N

USB_MINI_P

USB_MINI_N

USB_EXTA_P

USB_EXTA_N

SB_CLK100M_DMI_P

SB_CLK100M_DMI_N

DMI_S2N_P<3>

DMI_S2N_N<3>

DMI_N2S_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>

DMI_S2N_N<2>

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_S2N_P<1>

DMI_S2N_N<1>

DMI_N2S_P<1>

DMI_N2S_N<1>

DMI_S2N_P<0>

DMI_S2N_N<0>

DMI_N2S_P<0>

DMI_N2S_N<0>

PCI_IRDY_L

PCIE_ENET_R2D_C_N

SPI_SO

PCI_C_BE_L<1>

PLT_RST_L

PCI_REQ2_L

PCI_CLK33M_SB
TP_PCI_PME_L

DVI_HOTPLUG_DET

26C6

74D3

74C3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

26A4

74D3

37A5

74C3

37A5

74C3

74C3

74D3

37A5

37A5

37A5

37A5

74D3

74C3

74C3

39C8

37A5

37A5

37A5

25D6

7D1

8D4

23B6

23A6

23A6

23A8

23A8

23A8

23B6

23A6

23A6

23A6

23B6

23A6

23A6

23A8

23A6

23A6

23A6

23A6

7C4

22D7

73B3

8D4

8D4

8D4

8C4

8C4

8C4

8C4

8C4

8C4

8C4

8C4

8D4

8D4

8C4

8C4

OUT
OUT

BI

IN

BI

IN
IN

SMBALERT*/GPIO11

STP_PCI*/GPIO15

BMBUSY*/GPIO0

SYS_RESET*

SUS_STAT*/LPCPD*

QRT_STATE0/GPIO27

THRM*

SMLINK0

GPIO12

SPKR

SDATAOUT1/GPIO48

QRT_STATE1/GPIO28

SLP_S5*

GPIO20

GPIO8

WAKE*

CL_CLK1

BATLOW*

PWROK

SLOAD/GPIO38

SATA2GP/GPIO36

SERIRQ

RI*

CL_DATA1

SLP_S4*

EC_ME_ALERT/GPIO14

TACH0/GPIO17

CLK14

SCLOCK/GPIO22

SATA3GP/GPIO37

SATACLKREQ*/GPIO35

STP_CPU*/GPIO25

WOL_EN/GPIO9

LINKALERT*

SLP_S3*

RSMRST*

TACH3/GPIO7

CLKRUN*/GPIO32

GPIO18

LAN_RST*

CL_VREF1

S4_STATE*/GPIO26

TACH1/GPIO1
TACH2/GPIO6

SATA1GP/GPIO19

SDATAOUT0/GPIO39

SATA0GP/GPIO21

MCH_SYNC*

DPRSLPVR/GPIO16

VRMPWRGD

TP3

TP7

CL_RST*

ME_EC_ALERT/GPIO10

SLP_M*

MEM_LED/GPIO24

PWRBTN*

SUSCLK

CL_VREF0

CK_PWRGD

CLPWROK

CL_DATA0

CL_CLK0

CLK48

SMBCLK
SMBDATA

SMLINK1

MISC

SYS GPIO

SMB

CLOCKS

POWER MGT

CONTROLLER LINK

GPIO

SATA

GPIO

(4 OF 6)

IN
IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

BI
BI

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

BI
BI

BI
BI

OUT

BI

BI

BI

BI

IN

IN

OUT
OUT

OUT

IN

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LAYOUT NOTE:
PLACE R2511-16 WHERE PHYSICALLY ACCESSIBLE

See note below

have been up for at least 1ms.

PM_LAN_ENABLE must remain deasseted
until VccCL3_3, VccLAN3_3 and VccLAN1_05

INT PU

NOTE: ICH CLPWROK input must be PWRGD signal for
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
If ME/AMT is not used, short CLPWROK to PWROK.

INT PU

INT PU

INT PU

INT PD

INT PD

INT PU

for XOR chain testing.

Test access required

INT PU

NOTE: DPRSLPVR HAS INT 20K PD ENABLED

INT PU

AT BOOT/RESET FOR STRAPPING FUNCTION

28C4 29C2

28C4 29C2

6C2

37A5 44C5 46B6

33C5 34B8

6C2

44C8 46B4

44B8

44C5

R2514

1

2

MF-LF

1/16W

5%

100K

402

R2515

1

2

1/16W

10K

5%

MF-LF
402

R2516

1

2

1/16W

5%

ARB_ONLY

MF-LF

0

402

R2511

1

2

MF-LF

10K

1/16W

5%

402

R2512

1

2

0

5%
1/16W
MF-LF
402

NOSTUFF

R2502

1

2

1/16W

5%

10K

MF-LF

402

R2504

1

2

402

10K

5%

MF-LF

1/16W

R2500

1

2

1K

5%
1/16W
MF-LF
402

R2507

1

2

402

8.2K

5%
1/16W
MF-LF

R2506

1

2

10K

402

5%
1/16W
MF-LF

R2505

1

2

402

1/16W

8.2K

5%

MF-LF

U2300

AE21

AG12

E1

F23
AE18

F22
AF19

AJ23

D24
AH23

AG9

G5

AH11

E3

AJ14

AF22

AC19

AH12
AE11

AE16

AH20

AG21

AJ13 AJ24

AJ27

C2

AE23

AH25
AD16

AF17

AG27

AH27

AJ12

AJ10

AF11
AG11

AG13

AG10

AJ11

AD10

AF12

AF9

AJ25

AG23
AF21

AD18

AG22

AJ26

AD19

AC17

AE19

AD9

AG18

AE20

F4 D3

AD15

AG8

AJ8

AJ9
AH9

AC13

AJ21

AJ22

AJ20

AE17

AG19

OMIT

BGA

ICH8M

29A5 29D6 75B3

29A5 29D6 75B3

45A8

33C7 35C7 44C5 45A6 58B7 62B8

R2510

1

2

402

1/16W

5%

1K

NO_REBOOT_MODE

MF-LF

44C5 45C3

15A6 59D8 70B3

27A6

24A5 44B8

44C8

44C8

47D8 73A3

47D8 73A3

6C2

44C5 46B4

27C5 44B8

15B6

8B4

24A5 37A5

15A3

33B7 44C5 65A6 65C4

28A4

8B4

15A3 74A3

74A3

15A3 74A3

74A3

R2526

1

2

402

3.24K

1%
1/16W
MF-LF

R2527

1

2

402

453

1%
1/16W
MF-LF

C2500

1

2

402

16V

10%

0.1uF

X5R

R2529

1

2

402

1/16W

1%

MF-LF

453

R2528

1

2

402

3.24K

1%
1/16W
MF-LF

C2501

1

2

402

16V

10%

X5R

0.1uF

15A3 74A3

24A7

R2523

1

2

NOSTUFF

100K

5%

1/16W

402

MF-LF

47A8 73A3

47A8 73A3

74A3

24A5

R2536

1 2

1/16W

10K

MF-LF

1%

402

R2544

1 2

5%

MF-LF

1/16W

8.2K

402

R2545

1 2

MF-LF

10K

1/16W

1%

402

R2531

1 2

10K

1/16W
MF-LF

1%

402

R2530

1 2

10K

1/16W
MF-LF

1%

402

R2525

1

2

10K

MF-LF

1/16W

5%

402

6C2

24A7 46B4

24A5

8B4

24B5

8B4

R2534

2

1

MF-LF

1/16W

5%

10K

402

R2552

1

2

402

MF-LF

1/16W

10K

5%

R2550

1

2

10K

MF-LF

5%

1/16W

402

R2553

1

2

402

MF-LF

1/16W

5%

8.2K

R2551

1

2

1/16W

8.2K

5%

MF-LF
402

44D8

R2598

1 2

1%

MF-LF

1/16W

10K

402

R2546

1 2

1%

MF-LF

1/16W

10K

402

R2532

2

1

10K

MF-LF

402

5%

1/16W

R2533

2

1

402

1/16W

5%

MF-LF

10K

R2535

2

1

1/16W
MF-LF

10K

402

5%

69A6

R2547

2

1

1/16W

5%

MF-LF

10K

402

R2524

1

2

100K

402

5%
1/16W
MF-LF

R2597

1 2

10K

1/16W
MF-LF

1%

402

R2596

1 2

10K

1/16W
MF-LF

1%

402

01

24 76

051-7455

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

SB Pwr Mgt, GPIO, Clink

FWH_MFG_MODE

ARB_DETECT_L

LINDACARD_GPIO

=PP3V3_S5_SB_GPIO

PM_BATLOW_L

ARB_DETECT_L

SB_CLINK_VREF1

PM_CLKRUN_L

PM_STPCPU_L

PCIE_WAKE_L

VR_PWRGD_CLKEN

SMC_WAKE_SCI_L

SB_SDATAOUT<0>

TP_SB_TP3

SB_GPIO36
SB_CRT_TVOUT_MUX_L

RSVD_EXTGPU_LVDS_EN

PM_STPPCI_L

=PP3V3_S5_SB

PM_LAN_ENABLE

PM_RSMRST_L

=SB_CLINK_MPWROK

CLINK_NB_CLK

PM_RI_L

CLINK_NB_RESET_L

=PP3V3_S5_SB_CLINK1

SB_CLK48M_USBCTLR

SUS_CLK_SB

CLINK_WLAN_RESET_L

PM_PWRBTN_L

SMC_RUNTIME_SCI_L

SMB_ME_CLK

SMB_CLK

PCI_PME_FW_L

LAN_PHYPC
EXTGPU_RST_L
SB_GPIO18
TP_SB_GPIO20

SB_SDATAOUT<1>

PM_DPRSLPVR

CLK_PWRGD

TP_SB_GPIO6

PM_RI_L

SB_GPIO10_CL1

LAN_PHYPC

SB_GPIO14_CL2

=PP3V3_S0MWOL_SB_CLINK0

SATA_B_PWR_EN_L
FWH_MFG_MODE

TP_SB_TP7

SMB_ME_DATA

PM_SYSRST_L

TP_PM_SLP_S4_L
PM_SLP_S5_L

PM_S4_STATE_L

PM_BATLOW_L

CLINK_NB_DATA

PM_BMBUSY_L

LINDACARD_GPIO

SB_SATA_CLKREQ_L

PM_SUS_STAT_L

PM_THRM_L

SB_SCLOCK

SB_CLK14P3M_TIMER

PM_SLP_S3_L

WOL_EN

SB_GPIO14_CL2

SB_GPIO10_CL1

SB_CLINK_VREF0

CLINK_WLAN_DATA

SATA_B_DET_L

NB_SB_SYNC_L

SB_SPKR

CLINK_WLAN_CLK

TP_PM_SLP_M_L

INT_SERIRQ

SB_SLOAD

PM_SB_PWROK

SMB_DATA

=PP3V3_S0_SB_GPIO

PCI_PME_FW_L

SATA_B_PWR_EN_L

TP_SB_GPIO6

=PP3V3_S0_SB_GPIO

EXTGPU_RST_L

=PP3V3_S5_SB

35C7

24B3

24D8

35C7

46B4

26D8

22D7

22D7

26D8

24D5

44B8

24A8

22D2

37A5

22D2

24C5

24A3

24C5

24B3

6C2

7D1

24C3

74A3

7D1

7C1

24B5

24D5

24B3

24C5

24B3

7C4

24A5

24A7

35B7

24A5

24A5

74A3

7D4

24C5

24C5

24C5

7D4

8B4

7D1

VSS

VSS_NCTF

VSS

(5 OF 6)

VCC1_5_B

V5REF_SUS

VCCDMIPLL

VCC_DMI

VCC3_3

VCC1_05

V5REF

VCCCL1_5

VCCGLANPLL

VCC3_3

VCC1_5_A

VCC3_3

VCCHDA

VCCSUS1_5

VCCSUS3_3

V_CPU_IO

VCC3_3

VCCSUSHDA

VCC1_5_A

VCC3_3

VCCSATAPLL

VCCGLAN3_3

VCCSUS3_3

VCCLAN3_3

VCCCL1_05

VCCSUS1_05

VCCSUS1_5

VCCSUS3_3

VCCA3GP

VCCGLAN1_5

VCCCL3_3

VCCLAN1_05

VCC1_5_A24

VCC1_5_A

VCCRTC

VCC1_5_A

VCCUSBPLL

VCC1_5_A

VCC1_5_A

VCC1_5_A

GLAN POWER

USB CORE

ATX ARX

(6 OF 6)

VCCPSUS

IDE

COREVCCP CORE

PCI

VCCPUSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

6 uA S0-G3

1 mA

1 mA S0-S5

657 mA

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

Current figures provided assume 1.5V.

depending on VIO of HD Audio interface.

VccHDA and VccSusHDA can be 1.5V or 3.3V

NOTE:

1130 mA

23 mA

50 mA

1 mA

(VCC3_3 total)

442 mA

117 mA S0,

11 mA S0,

44 mA S3-S5

1 mA S3-S5

(VCCSUS3_3 total)

32 mA

1080 mA

47 mA

(VCC1_5_A total)

63 mA M1 & WOL

19 mA S0,

10 mA

23 mA

80 mA

1 mA

51 mA M1 & WOL

19 mA S0,

C2600

1

2

1uF

6.3V
CERM

10%

402

C2601

1

2

402

CERM

10V

20%

0.1uF

U2300

A23

A5

AC26

L13
L15

L26

L27
L4

L5

M12
M13

M14

M15

AC27

M16

M17
M23

M28

M29
M3

N1

N11
N12

N13

AD17

N14
N15

N16
N17

N18

N26
N27

N4

N5
N6

AD20

P12

P13
P14

P15
P16

P17

P23
P28

P29

R11

AD28

R12

R13

R14
R15

R16
R17

R18

R28
R4

T12

AD29

T13
T14

T15

T16
T17

T2
U12

U13

U14
U15

AD3

U16

U17
U23

U26

U27
U3

U5
V13

V15

V28

AD4

V29

W2

W26
W27

Y28

Y29
Y4

AB4
AB23

AB5

AD6

AB6
AD5

U4

W24

AE1

AA2

AE12

AE2

AE22

AD1

AE25

AE5

AE6

AE9
AF14

AF16

AA7

AF18

AF3

AF4

AG5

AG6

AH10
AH13

AH16

AH19

AH2

A25

AF28

AH22
AH24

AH26

AH3

AH4

AH8

AJ5

B11

B14

AB1

B17

B2

B20

B22

B8

C24

C26

C27

C6

D12

AB24

D15

D18

D2

D4
E21

E24

E4

E9

F15
E23

AC11

F28

F29

F7

G1

E2
G10

G13

G19
G23

G25

AC14

G26

G27

H25
H28

H29

H3

H6

J1

J25
J26

AC25

J27

J4

J5

K23
K28

K29

K3

K6

K7
L1

A1

A2

B1

B29

A28

A29
AH1

AH29

AJ1
AJ2

AJ28

AJ29

ICH8M

BGA

OMIT

U2300

A16

T7

G4

AC23
AC24

A13

B13

L14

L16

L17
L18

M11
M18

P11

P18
T11

T18

C13

U18
V17

V14

V11
U11

V18
V16

V12

C14
D14

E14

F14
G14

L11

L12

AE7

AF7

AC10

AC9

AA5

AA6

G12
G17

H7

AC7

AD7

F1

AG7

L6

L7

M6
M7

W23

AH7

AJ7

AC1

AC2
AC3

AC4

AC5

AA25

AA26

E27
F24

F25

G24
H23

H24

J23
J24

K24
K25

AA27

L23

L24
L25

M24

M25
N23

N24

N25
P24

P25

AB27

R24

R25

R26
R27

T23

T24
T27

T28

T29
U24

AB28

W25
V24

U25

Y25
V25

V23

AB29

D28

D29
E25

E26

AF29

AD2

W6
W7

Y7

A8

B15
B18

B4

B9
C15

D13

AC8

D5

E10

E7
F11

AD8
AE8

AF8

AA3

U7
V7

W1

AE28
AE29

G22

A22

F20
G21

R29

B27
A27

B28

B26
A26

B25

A24

AC12

F17

G18

F19

G20

AD25

AJ6

J6
AF20

AC16

J7

C3

AC18

P1
P2

P3

P4
P5

R1
R3

R5

R6

AC21

AC22
AG20

AH28

P6

P7
C1

N7

AD11

D1

BGA

ICH8M

OMIT

SYNC_MASTER=T9_MLB

051-7455

7625

01

SYNC_DATE=10/30/2006

SB Power & Ground

=PP1V05_S0_SB_CPU_IO

=PP1V25_S0_SB_DMI

PP1V5_S0_SB_VCCDMIPLL

=PP3V3_S0_SB_VCC3_3_DMI

=PP3V3_S0_SB_VCC3_3_SATA

=PP3V3_S0_SB_VCC3_3_VCCPCORE

PP5V_S0_SB_V5REF

VCCCL1_5V

=PPVCORE_S0_SB

=PP3V3_S0_SB_VCC3_3_IDE

PP1V5_S0_SB_VCC1_5_B

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S5_SB_VCCSUS3_3

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S0MWOL_SB_VCCLAN3_3

=PP1V5_S0_SB_VCC1_5_A

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP3V3_S0MWOL_SB_VCCCL3_3

=PP1V5_S0_SB_VCCGLAN1_5

PP5V_S5_SB_V5REF_SUS

PP1V5_S0_SB_VCCGLANPLL

=PP3V3R1V5_S0_SB_VCCHDA

TP_VCCSUS1_5_INTERNAL_REG1

=PP3V3_S5_SB_3V3_VCCSUSHDA

PP1V5_S0_SB_VCCSATAPLL

=PP3V3_S0_SB_VCCGLAN3_3

TP_VCCCL1_05_INTERNAL_REG

TP_VCCSUS1_05_INTERNAL_REG1

TP_VCCSUS1_5_INTERNAL_REG2

TP_VCCSUS1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG1

PP3V3_G3_SB_RTC

=PP1V5_S0_SB_VCCUSBPLL

=PP3V3_S0_SB_VCC3_3_PCI

26C6

26C4

26C6

26A4

26D2

27D4

22D2

26A6

26A8

26B8

26A6

26D2

26B4

23C2

26D5

26C6

26B6

26D2

26D3

26C2

26C2

26B2

26C4

26B2

26A5

26B6

26B4

7D7

7C7

26A6

7D4

7D4

7D4

26D7

7D7

7D4

22D7

7B7

7B7

7D1

7D1

7C4

7B7

7B6

7C4

26A4

26C7

26B7

7C4

7D1

26D5

7D4

22D7

7B7

7D4

NC

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ICH VCC1_5_A/ATX BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

ON SECONDARY SIDE OR 3.56MM ON PRIMARY
DISTRIBUTED BETWEEN AA25..V23

M70 DOES NOT USE GIGABIT IN SB, SO NO NEED FOR PLL FILTERING

L2703 NEED CHANGE TO 1UH PART

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AC1..AC5

DISTRIBUTE IN PCI SECTION OF SB

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN AC12

(ICH CPU I/O 1.05V PWR)

PLACE NEAR PINS AC23,AC24 OF SB

ICH IDE/VCC3_3 BYPASS

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PIN AH11

3.56MM ON PRIMARY NEAR PIN AJ6

L2702 MAY HAVE CHANGE TO 1.0UH PART

PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN AD2

PLACEMENT NOTE:
PLACE CAPS < 2.54MM OF SB ON
SECONDARY SIDE OR 3.56MM ON PRIMARY

(ICH IO BUFFER 3.3V PWR)

ICH VCC3_3 BYPASS

PLACE CAP UNDER SB NEAR PINS
F19 AND G20

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

ICH VCCSUS3_3 BYPASS
(ICH SUSPEND 3.3V PWR)

PLACE < 2.54MM OF SB ON SECONDARY
OR 3.56MM ON PRIMARY NEAR PIN AD11

OR 3.56MM ON PRIMARY NEAR PIN AE29

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEHOLDER

AC18..AH28

(ICH SUSPEND 3.3V PWR)

PLACEMENT NOTE:

PLACE CAPS NEAR PINS

ICH VCC1_5A BYPASS

PLACEMENT NOTE:

ICH VCCDMIPLL BYPASS

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:

P6..R6

ICH VCCSUS3_3 BYPASS

OR 3.56MM ON PRIMARY NEAR PIN AF29

PLACEMENT NOTE:

ICH VCC1_5_A/ARX BYPASS

PLACE C2715 NEAR PIN D1 OF SB

PLACE CAP NEAR PINS

PLACEMENT NOTE:

PLACE CAP < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

(ICH LOGIC&IO 1.5V PWR)

(ICH LOGIC&IO[ARX] 1.5V PWR)

3.56MM ON PRIMARY NEAR PINS F20,G21

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH USB/VCCSUS3_3 BYPASS
(ICH SUSPEND USB 3.3V PWR)

3.56MM ON PRIMARY NEAR PINS F1..M7

ICH VCC3_3/VCCHDA BYPASS
(ICH INTEL HDA CORE 3.3V PWR)

ICH USB CORE/VCC1_5_A BYPASS
(ICH USB CORE 1.5V PWR)

AC10..AD7 OF SB

PLACE CAP NEAR PINS

PLACEMENT NOTE:

(ICH INTEL HDA CORE 3.3V/1.5V PWR)

ICH VCCHDA BYPASS

(ICH IDE I/O 3.3V PWR)

(ICH IO BUFFER 3.3V PWR)

(ICH USB PLL 1.5V PWR)

ICH VCCUSBPLL BYPASS

ICH VCC3_3 BYPASS

PLACE < 2.54MM OF SB ON SECONDARY

PLACE CAPS NEAR PIN AD25 OF SB

PLACE CAP NEAR PIN B27..A26

NEAR PINS A8 ... F11

(ICH LAN I/F BUFFER 3.3V PWR)

ICH VCC_PAUX/VCCLAN3_3 BYPASS

ICH VCCRTC BYPASS
(ICH RTC 3.3V PWR)

ICH V_CPU_IO BYPASS

PLACEMENT NOTE:

FOR 270UF

(ICH DMI PLL 1.5V PWR)

(ICH LOGIC&IO[ATX] 1.5V PWR)

PLACE CAPS NEAR PIN C2..AH28

(ICH PCI I/O 3.3V PWR)

ICH PCI/VCC3_3 BYPASS

3.56MM ON PRIMARY NEAR PINS AA3...Y7

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACE CAPS < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

PLACEMENT NOTE:

PLACEMENT NOTE:
PLACE C2709 NEAR PIN B27 OF SB

PLACEMENT NOTE:
PLACE C2700 & C2705-07 < 2.54MM OF SB

OR 3.56MM ON PRIMARY NEAR PIN A24

ICH V5REF BYPASS
(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)

ICH CORE/VCC1_05 BYPASS
(ICH CORE 1.05V PWR)PLACEMENT NOTE:

PLACE CAPS AT EDGE OF SB

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS AE7..AJ7

PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB

PLACEMENT NOTE:

ICH V5REF_SUS BYPASS
(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)

PLACEMENT NOTE:
PLACE C2704 < 2.54MM OF PIN G4 OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH VCCA3GP(VCC1_5_B BYPASS

(ICH IO,LOGIC 1.5V PWR)

L2700 MAY HAVE CHANGE TO 0.5UH PART

1

2

2.5V
POLY

20%

CASE-B2

C2710

1

2

0.1UF

X5R

10%
16V

402

C2712

1

2

X5R

0.1UF

10%
16V

402

R2700

1 2

402

1/16W
MF-LF

5%

1

C2724

1

2

603

6.3V

4.7UF

CERM

20%

L2703

1 2

1.0UH-0.5A-0.675A

1007

C2735

1

2

603

6.3V

20%
X5R

10UF

1

2

10%
16V

402

X5R

1

2

6.3V

10%

402

CERM

C2740

1

2

10%
X5R

0.1UF

16V
402

C2742

1

2

NOSTUFF

20%

603

X5R

10UF

6.3V

C2732

1

2

2.2uF

603

20%

6.3V
CERM1

C2736

1

2

4.7uF

20%

6.3V
CERM
603

C2733

1

2

6.3V
603

CERM

20%

4.7uF

C2741

1

2

10%

0.1UF

X5R

16V
402

L2702

1 2

10UH-100MA

0805

C2739

1

2

805

CERM

22UF

20%

6.3V

C2704

1

2

0.1UF

X5R

10%

402

16V

C2738

1

2

16V

0.1UF

X5R

10%

402

C2737

1

2

10%
X5R

0.1UF

16V
402

C2720

1

2

X5R
402

16V

10%

0.1UF

C2743

1

2

10%
X5R

16V
402

0.1UF

C2715

1

2

16V

0.1UF

X5R

10%

402

C2709

1

2

10%
X5R

0.1UF

16V
402

C2718

1

2

16V
X5R

10%

402

0.1UF

C2702

1

2

10%
X5R

16V
402

0.1UF

C2719

1

2

16V

0.1UF

X5R

10%

402

C2721

1

2

X5R

0.1UF

16V
402

10%

C2723

1

2

10%

0.1UF

16V
X5R
402

C2722

1

2

10%
X5R

0.1UF

16V
402

C2725

1

2

16V

0.1UF

X5R

10%

402

C2726

1

2

NOSTUFF

16V

10%

0.1UF

402

X5R

C2727

1

2

10%
X5R

0.1UF

16V
402

C2728

1

2

10%
X5R

0.1UF

16V
402

C2713

1

2

0.1UF

10%
16V
X5R
402

3

2

HN2S02JE

SOT-363

D2702

1

5

2

R2701

1 2

5%

10

402

MF-LF

1/16W

2

1

2

CERM

20%

6.3V
805

C2706

1

2

CERM

20%

22UF

805

6.3V

C2707

1

2

2.2UF

603

6.3V
CERM1

20%

C2701

1

2

402

10%
16V
CERM

0.01UF

C2708

1

2

20%

603

X5R

10UF

6.3V

C2717

10%

1UF

6.3V
CERM
402

C2714

1

2

1UF

6.3V
402

CERM

10%

C2716

1

2

2.5V
CASE-C2

POLY

20%

330UF

CRITICAL

R2702

1

2

100

MF-LF

5%

402

C2729

1

2

X5R

10%

0.1UF

16V
402

C2730

1

2

10%
X5R

0.1UF

16V
402

C2734

1

2

X5R

0.1UF

10%
16V

402

C2731

1

2

0.1UF

10%
16V
X5R
402

051-7455

76

SYNC_MASTER=WFERRY

SB Decoupling

01

26

SYNC_DATE=06/01/2006

=PP1V5_S0_SB_VCC1_5_A_ATX

PP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCCGLANPLL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5V

=PP3V3_S0_SB_VCC3_3_SATA

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5V

PP1V5_S0_SB_VCC1_5_B

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

VOLTAGE=1.5V

=PP1V05_S0_SB_CPU_IO

=PP1V5_S0_SB_VCCGLAN1_5

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

VOLTAGE=5V

=PP3V3_S0_SB

=PP1V5_S0_SB

=PP5V_S5_SB

=PP5V_S0_SB

=PP3V3_S0_SB_VCC3_3_VCCPCORE

PP3V3_G3_SB_RTC

=PP1V25_S0_SB_DMI

=PP1V5_S0_SB

=PP3V3_S0_SB_VCC3_3_DMI

=PP3V3_S5_SB_VCCSUS3_3

=PP3V3_S5_SB_VCCSUS3_3_USB

=PP3V3_S5_SB_3V3_VCCSUSHDA

=PP3V3_S0MWOL_SB_VCCCL3_3

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP3V3R1V5_S0_SB_VCCHDA

=PP1V5_S0_SB_VCCUSBPLL

PP1V5_S0_SB_VCCDMIPLL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5V

=PP1V5_S0_SB_VCC1_5_A

MAKE_BASE=TRUE

PP1V5_S0_SB_VCC1_5_B

=PP3V3_S0_SB_VCC3_3_VCCPCORE

=PP3V3_S5_SB_VCCSUS3_3

MIN_NECK_WIDTH=0.25MM

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5MM

PP1V5_S0_SB_VCCSATAPLL

=PPVCORE_S0_SB

=PP3V3_S0MWOL_SB_VCCLAN3_3

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_VCC3_3_IDE

=PP3V3_S5_SB

=PP1V5_S0_SB_VCC1_5_A_ARX

D2702

1/16W

OMIT

C2711

1UF

PP5V_S0_SB_V5REF

4

C2703

0.1UF

HN2S02JE

SOT-363

PP5V_S5_SB_V5REF_SUS

MIN_LINE_WIDTH=0.3MM

0805-1

FERR-330-OHM-1.5A

L2700

NOSTUFF

C2705

22UF

220UF

C2700

1

=PP1V5_S0_SB

OMIT

CRITICAL

26A4

26C6

35C7

26D6

25D6

25C3

26D6

26A6

27D4

26C8

26B6

25D6

26C6

26D2

24A8

25B6

26A8

25C3

23C2

22D2

39C8

26C8

25C3

25D6

25C3

26A8

25C3

25A3

25A3

25B3

25A6

25B6

25B3

25A6

25B6

23C2

25C3

25A3

25D3

25A3

25B3

25C3

24A3

25B6

7B7

7B7

25A6

7D4

25D6

22D7

7D7

25A6

25D6

7D4

7B7

7C1

7A7

7D4

22D7

7C7

7B7

7D4

7D1

7D1

7D1

7C4

7B6

7C4

7B7

25C3

7B7

22D7

7D4

7D1

7D7

7C4

7D4

7D4

7D1

7B7

GND

Y

A

B

VCC

OUT

OUT

NC

NC

Y

B

A

IN

OUT

IN

IN

Y

B

A

IN

OUT

IN

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0519

RTC Battery Connector

It may take a few days before this is done through

2-input NAND gate-APN:311S0304

Pulled a new APN for U2803(0.6mm max

CPU VCORE PSI

MIN_LINE_WIDTH=0.3MM

it provides a set of pads

Initial resistor values are based on CRB,

This part is never stuffed,

Silk: "SYS RST"

NC

Buffered

Linda Card represents 3 loads

Unbuffered

but may change after characterization.

NC

on the board to short or

VOLTAGE=3V

VOLTAGE=3V
MIN_LINE_WIDTH=0.3MM

Platform Reset Connections

This will allow us to sequence this part under wireless card

to solder a reset button.

In CLOSE=12.5pF

Change Y2800 to 197S019 -7.0mmx1.5mmx1.4mm

197S0219

SB RTC Crystal Circuit

C2809

1 2

402

10PF

CERM

50V

5%

C2807

1

2

402

0.1UF

20%
10V

CERM

C2811

1

2

10V

20%

CERM

0.1UF

402

J2800

3

4

1
2

M-RT-SM

78171-0002

CRITICAL

R2801

1 2

402

5%

MF-LF

1/16W

0

R2802

1 2

0

402

1/16W

5%

MF-LF

U2803

2

1

3

5

4

SON

TC7SH00FEF

CRITICAL

R2803

1

2

100K

5%

402

MF-LF

1/16W

R2886

1 2

100

5%
1/16W
MF-LF

402

C2810

1

2

402

1UF

6.3V

10%
CERM

C2805

1

2

1UF

6.3V
CERM
402

10%

R2800

1 2

20K

1/16W

402

5%

MF-LF

D2800

1 5

2

SOT-363

HN2S02JE

R2806

1

2

MF-LF
402

5%

1M

1/16W

D2800

3 4

2

SOT-363

HN2S02JE

R2887

1 2

1/16W
MF-LF

0

5%

402

R2885

1 2

1/16W
MF-LF

402

0

5%

R2883

1 2

5%

402

MF-LF

1/16W

100

R2881

1 2

1/16W

5%

0

MF-LF

402

U2880

2

1

3

5

4

TC7SZ08AFEF

SOT665

CRITICAL

R2880

1

2

100K

1/16W

5%
402

MF-LF

C2880

1

2

CERM

402

20%
10V

0.1UF

R2897

1

2

MF-LF

402

1/16W

10K

5%

I59

R2898

1

2

OMIT

1/16W
MF-LF

5%

402

100K

R2811

1

2

MF-LF
402

1/16W

5%

1.8K

U2801

2

1

3

5

4

TC7SZ08AFEF

SOT665

CRITICAL

R2812

1

2

MF-LF

1/16W

10K

5%

402

R2807

1

2

1K

5%
1/16W
MF-LF
402

R2896

12

5%

MF-LF

402

1K

1/16W

C2808

1 2

402

10PF

CERM

50V

5%

Y2800

1

4

7X1.5X1.4-SM

CRITICAL

32.768K

R2810

1 2

MF-LF

402

5%

1/16W

0

R2809

1

2

1/16W

402

5%

10M

MF-LF

051-7455

76

01

SYNC_MASTER=NB

SB Misc

SYNC_DATE=07/26/2005

27

MAKE_BASE=TRUE

VR_PWRGD_CK505_L

=PP3V3_S0_SB_PM =PP3V3_S0_SB_PM

CK410_PD_VTT_PWRGD_L

PLT_RST_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

IMVP6_PSI_L

VR_PWRGOOD_DELAY

PP3V3_G3C_SB_RTC_D

MAKE_BASE=TRUE

SB_RTC_X1

ENET_RESET_L

XDP_DBRESET_L_R

SMC_LRESET_L

TMDS_RST_L

SB_SM_INTRUDER_L

XDP_DBRESET_L

=PP3V3_S0_RSTBUF

=PP3V3_S5_SB_PM

PP3V3_G3_SB_RTC

=PP3V42_G3H_SB_RTC

PPVBATT_G3C_RTC

PPVBATT_G3C_RTC_R

SB_RTC_RST_L

PM_SYSRST_L

MAKE_BASE=TRUE

VR_PWRGD_CK505

DEBUG_RESET_L

AIRPORT_RST_L

NB_RESET_L

CPU_PSI_L

MAKE_BASE=TRUE

ALL_SYS_PWRGD

PM_SB_PWROK

CLINK_MPWROK

SB_RTC_X2

SB_RTC_X1_R

26A5

58A3

27B6 27B8

67C6

59C7

12B4

25D6

44B8

46B6

44D8

8B3

59C7

7D4 7D4

23A6

59C7

15B6

22D8

34B8

44C8

68B5

22D8

9C6

7D4

7D1

22D7

7B1

22D8

24D5

8B3

6C2

33C3

15B6

9A2

6B2

24C3

8B1

22D8

IN
IN

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT
OUT

IN

BI

IN

BI

IN

IN

IN

OUT

OUT

IN

OUT

OUT

OUT
OUT

OUT
OUT

IN

VSS_PCI

CLKREQ_7*

CLKREQ_8*

GPU_STOP*

REF_0/FS_C/TEST_SEL

48M/FS_A

DOT_96/27M

DOT_96*/27M_SS

SRC_8*

SRC_8

PCI_5/FCT_SEL

PCIF_0/ITP_EN

VDD_PCI

VDD_48

THRM_PAD

SRC_4*

CLKREQ_3*

SRC_3

SRC_0/LCD_CLK

SRC_0*/LCD_CLK*

CPU_1_MCH*

CPU_1_MCH

CPU_ITP*/SRC_10*

CPU_ITP/SRC_10

VSS_SRC

VSS_REF

VSS_CPU

VSS_48

SDA

PCIF_1

PCI_4

PCI_3

PCI_2

PCI_1

VSS_A

XTAL_OUT

CLKREQ_6*

CLKREQ_5*

CLKREQ_4*

CLKREQ_1*

SCL

CPU_0

SRC_1

SRC_2*

SRC_2

SRC_4

SRC_5*

SRC_5

SRC_7*

SRC_7

SRC_6*

SRC_6

VDD_REF

CPU_0*

SRC_3*

CPU_STOP*

PCI_STOP*

XTAL_IN

VDD_A

FS_B/TEST_MODE

VDD_CPU

SRC_1*

CKPWRGD/PD*

VDD_SRC

IN

OUT
OUT

OUT

OUT
OUT

OUT

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SELIGO RECOMMEND TO REMOVE L2903,R2900,C2907,C2910

STUFF C2907,C2910,C2916,C2911,C2914

(PCI SLOT)

(ICH8M PCI 33MHZ)

(PULL UP PIN 68 TO ENABLE ITP HOST CLK)

(PORT80 LPC 33MHZ)

(ICH SM BUS)

(FW PCI 33MHZ)
(TPM LPC 33MHZ)
(SMC LPC 33MHZ)

STUFF R2905 FOR CK410M MODE

(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)

(FROM ICH8M)
(ICH8M USB 48MHZ)

(ICH8M,SIO,LPC REF. 14.318MHZ)

(DB400 SRC )

(SLOT D - 4 LANE PCI-E FOR EXPRESSCARD)

(ICH SATA 100 MHZ)

(FROM ICH8M GPIO35)

(GMCH G_CLKIN 100 MHZ )

(FROM GMCH CLK_REQ*)

U2900 HAS INTERNAL PU ON PGMODE

(WIRELESS PCI-E 100 MHZ )

SPREAD

DOT96C

PIN 7

(ICH8M DMI 100 MHZ )

(INT PU)

(NO INT PU)

(NO INT PD)

(INT PU)

(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)

(EACH POWER PIN PLACED ONE 0.1UF)

(SLOT E )

475 OHM FOR CK410M
COMPATIBILITY

(FROM ICH8M GPIO15 STPPCI* )
(FROM ICH8M GPIO25 STPCPU* )

(CPU HOST 133/167MHZ)
(GMCH HOST 133/167MHZ)
(ITP HOST 133/167MHZ)

0 = VTT_PWRGD#/PD
1 = CKPWRGD/PD#

0
1

(SLOT F - GPU PCI-E 100 MHZ )

(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)

SRCT0

PIN 11
100MC_SST

* FOR EXT. GRAPHIC SYSTEM

* FOR INT. GRAPHIC SYSTEM

FCTSEL1

SPREAD

27M NON

27M

SRCC0

100MT_SST

(INT PU)

(INT PU)

(INT PU)

PIN 10

(INT PU)

(INT PD)

PIN 6
DOT96T

ORIGINAL DESIGN:

USE 2.2OHM FOR R2900,R2901 AND 1OHM FOR R2902

USE 155S0302 FOR L2902(R2906) AND L2903(R2907)

R2901,L2902,C2916,C2911,C2914 and R2902

NEED TO CHECK CAP VALUE

C2910

1

2

10UF

603

20%
X5R

6.3V

NOSTUFF

C2915

1

2

402

16V

0.1UF

X5R

10%

24C8 29C2

24C8 29C2

6C7

29D6 75D3

6C7

29D6 75D3

6C7

29D6 75D3

6C7

29D6 75D3

6C7

29D6 75D3

6C7

29D6 75D3

6C7

29C6 75C3

6C7

29C6 75D3

8C4

8C4

6C7

29C6 75C3

6C7

29C6 75C3

6C7

29C6 75C3

6C7

29B6 75C3

6C7

29C6 75C3

6C7

29C6 75C3

C2990

1

2

402

50V
CERM

18PF

5%

C2989

1

2

402

50V
CERM

18PF

5%

29B6 75D3

8C4

75D3

29A6 75D3

8C4

75D3

47D6

47D6

C2907

1

2

X5R
603

6.3V

20%

10UF

NOSTUFF

29B8

29B2 75D3

C2911

1

2

6.3V

10%

402

CERM

1UF

NOSTUFF

C2901

1

2

6.3V
603

20%
X5R

10UF

C2902

1

2

402

X5R

16V

0.1UF

10%

L2901

1 2

0402-LF

FERR-120-OHM-1.5A

C2900

1

2

CERM

1UF

402

10%

6.3V

R2901

1 2

1/16W
MF-LF

5%

0

402

R2902

1 2

5%

MF-LF

1/16W

0

402

C2914

1

2

6.3V

20%

603

X5R

10UF

NOSTUFF

R2900

1 2

1/16W
MF-LF

5%

0

402

29C2

29C2

33C5

R2903

1

2

402

1/16W
MF-LF

5%

10K

6C7

29B6 75D3

29B6 75D3

8B3

8C4

8C4

8C4

8C4

6C7

29C6 75C3

6C7

29C6 75C3

15A3

Y2901

1 2

14.31818

5X3.2-SM

CRITICAL

R2905

1

2

475

1/16W

NOSTUFF

1%
MF-LF

402

C2916

1

2

X5R
603

6.3V

20%

10UF

NOSTUFF

C2903

1

2

X5R

10%

0.1UF

16V
402

C2904

1

2

0.1UF

X5R
402

16V

10%

C2905

1

2

10%

0.1UF

X5R

16V
402

C2906

1

2

402

16V

0.1UF

10%
X5R

C2908

1

2

0.1UF

10%
X5R

16V
402

C2912

1

2

0.1UF

10%
X5R

16V
402

C2913

1

2

402

16V

0.1UF

X5R

10%

C2909

1

2

10%
X5R

0.1UF

16V
402

U2900

4

2

9

59

20

60

25

40

34

45

44

42

41

37

36

55

6

7

8

53

57
58
63
64
65

56

68

1

54

47
48

10

11

13

14

15

16

18

19

21

22

23

24

26

27

29

30

33

32

69

33843616749121728

35

5

39

46
62

66
52
31

51
50

SLG2AP101

QFN

CRITICAL

8C4

34B8

6B7

29B6 75C3

6B7

29B6 75C3

6C7

29B6 75D3

29D8 75D3

29D8 75D3

6C7

29B6 75D3

24C3

R2906

1 2

5%

MF-LF

1/16W

0

402

R2907

1 2

5%

MF-LF

1/16W

0

402

28 76

SYNC_DATE=06/06/2006

SYNC_MASTER=DSIMON

Clock (CK505)

01

051-7455

=PP3V3_S0_CK505

MIN_LINE_WIDTH=0.5mm
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2mm

PP3V3_S0_CK505_VDDA_R

MIN_LINE_WIDTH=0.5mm

PP3V3_S0_CK505_VDD_PCI

MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V

=PP3V3_S0_CK505

CK505_PCIF0_CLK

=PP3V3_S0_CK505

CK505_XTAL_IN
CK505_XTAL_OUT

CK505_PGMODE

CK505_PCI5_FCTSEL1

=SMBUS_CK505_SDA

CK505_PCIF1_CLK

=SMBUS_CK505_SCL

SB_CLK100M_SATA_OE_L

CK505_LVDS_P

CK505_LVDS_N

CK505_REF1

CK505_CLK14P3M_TIMER

MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm

PP3V3_S0_CK505_VDD48

CK505_SRC4_N

CK505_CPU1_N
CK505_CPU1_P

CK505_CPU2_ITP_SRC10_N
CK505_CPU2_ITP_SRC10_P

CK505_PCI4_CLK

CK505_PCI3_CLK

CK505_PCI2_CLK

CK505_PCI1_CLK

CK505_SRC_CLKREQ1_L

CK505_CPU0_P

TP_CK505_SRC1_P

CK505_SRC2_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

PP3V3_S0_CK505_VDD_REF

PM_STPPCI_L

PP3V3_S0_CK505_VDDA

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm

CK505_FSB_TEST_MODE

TP_CK505_SRC1_N

CK505_CPU0_N

PM_STPCPU_L

CK505_SRC2_P

TP_CK505_SRC3_P

CK505_SRC_CLKREQ3_L

CK505_SRC4_P

NB_CLKREQ_L

TP_CK505_SRC7_N

CK505_SRC_CLKREQ6_L

CK505_SRC6_P

CK505_SRC6_N

CK505_SRC5_N

CLK_PWRGD

CK505_DOT96_27M_N

CK505_SRC8_N

CK505_DOT96_27M_P

CK505_USB48_FSA

CK505_SRC8_P

=ENET_CLKREQ_L

VOLTAGE=3.3V

PP3V3_S0_CK505_VDD_CPU_SRC

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm

CK505_PGMODE

TP_CK505_SRC7_P

CK505_SRC5_P

TP_CK505_SRC3_N

29D2

29D2

29D2

29B2

29B2

29B2

28D3

28D8

28D8

28C8

28C8

28D3

7C4

7C4

7C4

28A4

28B5

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

BI

OUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(FROM CPU FS_A)

(Int GFX DOT 96MHZ)

(TO FIREWIRE PCI 33MHZ)

(TO ICH8M PCI 33MHZ)

(PORT80 LPC 33MHZ)

(TO SMC PCI 33MHZ)

(Int Gfx LVDS 100MHz)

(ITP HOST 133/167MHZ)

(GMCH HOST 133/167MHZ)

(ICH8M DMI 100MHZ)

Place close to CLK Gen
For reducing noise coupling to wireless frequencies

(FOR YUKON 100MHZ)

(CPU HOST 133/167MHZ)

(TO MCH FS_B)

(ICH8M 14.318MHZ)

(TO MCH FS_C)

0

1

0

FS_A

0

FS_B

0

0

1

1

1

0

0

1

1

01

(TO ICH8M USB 48MHZ)

(TO MCH FS_A)

1

1

0

1

0 0 1

(FROM CPU FS_C)

CPU

266M
133M
166M

200M
400M

100M
333M

CLKREQ Controls

CLK Termination

Resrvd

0

1

FS_C

*

(FROM CPU FS_B)

NOSTUFF R3082, R3086, R3090
FOR MANUAL CPU FREQUENCY

CPU speed is currently set to 200MHz

(ICH8M SATA 100MHZ)

(GMCH PEG/DMI 100MHZ)

(WIRELESS PCI-E MINI 100MHZ)

6C7

28C4 75D3

6C7

28C4 75D3

6C7

28C4 75D3

6C7

28C4 75D3

6C7

28A4 75D3

6C7

28A4 75D3

15C3 75B3

15C3 75B3

6C7

28B4 75C3

6C7

28B4 75C3

23D2 75B3

6C7

28B4 75C3

6C7

28B4 75C3

28B6 75D3

28B6 75D3

6C7

28B6 75D3

29A5
37A5 75B3

29A5
44C8 75B3

23A6
29A5 75B3

33C5 75A3

33C5 75B3

6C7

28B4 75C3

6C7

28B4 75C3

6C2
46C4 75C3

28B8 75D3

23C2 75B3

R3067

1

2

402

MF-LF

NOSTUFF

10K

5%
1/16W

R3083

1

2

402

5%

MF-LF

1/16W

1K

R3084

1

2

402

1/16W
MF-LF

5%

1K

28C6

28B6 75D3

22B6 75B3

22B6 75B3

6C7

28B4 75C3

6C7

28B4 75C3

R3080

1

2

NOSTUFF

1K

402

1/16W
MF-LF

5%

R3082

1 2

402

1/16W

5%

0

MF-LF

9B4

70B3

9A4

70B3

R3086

1 2

402

1/16W
MF-LF

0

5%

R3087

1

2

1K

5%

402

MF-LF

1/16W

NOSTUFF

13B3 75C3

13B3 75C3

9B6

75C3

24D3 29A5 75B3

R3032

1 2

1/16W
MF-LF

33

5%

402

28A4 75D3

R3033

1 2

402

1/16W
MF-LF

5%

2.2K

9B6

75C3

R3081

1 2

402

MF-LF

1K

5%

1/16W

15C6 70B3

R3085

1 2

402

1/16W
MF-LF

5%

1K

15C6 70B3

9A4

70B3

R3090

1 2

5%

402

MF-LF

0

1/16W

R3088

1

2

402

5%

NOSTUFF

MF-LF

1/16W

1K

R3091

1

2

MF-LF

402

1/16W

1K

5%

12B3

R3089

1 2

1/16W
MF-LF

1K

5%

402

15B6 70B3

24D3 29A5 75B3

R3034

1 2

MF-LF

1/16W

33

402

5%

28A4 75D3

12B3

8B1

75B3

8A1

75B3

6C7

28B4 75D3

6C7

28B4 75C3

8B1

75B3

8B1

75B3

R3000

1 2

402

0

5%
1/16W
MF-LF

R3035

1 2

402

1/16W
MF-LF

10K

5%

R3001

1 2

402

0

MF-LF

1/16W

5%

R3002

1 2

402

0

5%
1/16W
MF-LF

R3003

1 2

402

0

1/16W

5%

MF-LF

R3004

1 2

402

0

5%
1/16W
MF-LF

R3005

1 2

402

0

MF-LF

1/16W

5%

R3006

1 2

402

0

5%
MF-LF

1/16W

R3007

1 2

402

0

MF-LF

1/16W

5%

R3010

1 2

402

0

5%

MF-LF

1/16W

R3011

1 2

402

0

1/16W
MF-LF

5%

R3014

1 2

402

0

MF-LF

1/16W

5%

R3015

1 2

402

0

MF-LF

1/16W

5%

R3016

1 2

402

0

5%
1/16W
MF-LF

R3017

1 2

402

0

MF-LF

5%

1/16W

R3018

1 2

402

0

5%
1/16W
MF-LF

R3019

1 2

402

0

5%

MF-LF

1/16W

R3024

1 2

402

0

MF-LF

1/16W

5%

R3025

1 2

402

0

1/16W
MF-LF

5%

R3026

1 2

1/16W

5%

33

402

MF-LF

R3027

1 2

1/16W

33

402

5%

MF-LF

R3028

1 2

MF-LF

1/16W

5%

33

402

R3030

1 2

33

1/16W

5%
MF-LF

402

R3046

1 2

402

1/16W

MF-LF

5%

10K

R3047

1 2

10K

5%

MF-LF

1/16W

402

R3050

1 2

10K

5%

MF-LF

1/16W

NOSTUFF

402

R3051

1 2

402

1/16W

5%

10K

NOSTUFF

MF-LF

R3066

1

2

5%
MF-LF

1/16W
402

10K

C3000

1

2

3.3PF

NOSTUFF

CERM

50V

0.25%
402

C3001

1

2

402

NOSTUFF

3.3PF

0.25%
50V
CERM

C3002

1

2

NOSTUFF

402

50V

0.25%

3.3PF

CERM

C3003

1

2

NOSTUFF

0.25%

3.3PF

402

CERM

50V

34C8

34C8

R3023

1 2

402

0

1/16W

5%

MF-LF

R3022

1 2

402

0

5%
1/16W
MF-LF

6B7

28A4 75C3

6B7

28A4 75C3

C3004

1

2

50V

0.25%

3.3PF

NOSTUFF

402

CERM

6C7

28C4 75D3

6C7

28C4 75D3

051-7455

29

SYNC_DATE=06/06/2006

Clock Termination

01

76

SYNC_MASTER=DSIMON-WF

SB_CLK48M_USBCTLR

CK505_CPU0_N

NB_CLK96M_DOT_P

CK505_DOT96_27M_N

SB_CLK100M_SATA_P

NB_CLK100M_DPLLSS_N

NB_CLK100M_DPLLSS_P

SB_CLK100M_DMI_P

NB_CLK100M_PCIE_P

PCIE_CLK100M_MINI_P

PCIE_CLK100M_ENET_P

CK505_SRC6_N

CK505_SRC8_P

CK505_SRC6_P

CK505_SRC5_P

CK505_SRC2_P

CK505_SRC5_N

CK505_LVDS_N

CK505_SRC2_N

CK505_SRC4_P

CK505_SRC4_N

CK505_SRC8_N

CK505_LVDS_P

FSB_CLK_CPU_P

CPU_XDP_CLK_P

FSB_CLK_NB_PCK505_CPU1_P

CK505_CPU0_P

CK505_CPU1_N

CK505_CPU2_ITP_SRC10_P

CK505_CPU2_ITP_SRC10_N

FSB_CLK_CPU_N

PCI_CLK33M_LPCPLUS

NB_CLK96M_DOT_N

CK505_PCIF0_CLK

CK505_PCIF1_CLK

CK505_DOT96_27M_P

PCI_CLK33M_SB

PCI_CLK33M_FW

FSB_CLK_NB_N

PCI_CLK33M_SMC

CK505_FSB_TEST_MODE

SB_CLK100M_DMI_N

CK505_CLK14P3M_TIMER

CK505_USB48_FSA

CPU_BSEL<0>

CPU_BSEL<2>

NB_BSEL<1>

CK505_FSA

NB_BSEL<0>

=PP1V25R1V05_S0_FSB_NB

CK505_FSC

SB_CLK14P3M_TIMER

NB_BSEL<2>

CPU_XDP_CLK_N

=PP3V3_S0_CK505

=PP3V3_S0_CK505

CK505_FSC

CK505_FSA

=PP1V25R1V05_S0_FSB_NB

=PP1V25R1V05_S0_FSB_NB

CK505_PCI5_FCTSEL1

PCIE_CLK100M_MINI_N

PCIE_CLK100M_ENET_N

SB_CLK100M_SATA_N

CK505_SRC_CLKREQ1_L

PM_STPCPU_L

PM_STPPCI_L

CK505_SRC_CLKREQ3_L

NB_CLK100M_PCIE_N

CK505_PCI1_CLK

CK505_PCI3_CLK

CPU_BSEL<1>

PCI_CLK33M_FW

PCI_CLK33M_SMC

SB_CLK14P3M_TIMER

SB_CLK48M_USBCTLR

PCI_CLK33M_SB

29D2

29B2

29C6

28D8

28D8

29C6

29B6

28D3

28D3

29B6

29C6

75B3

75B3

75B3

75B3

75B3

75B3

13B7

75B3

28C8

28C8

75B3

75B3

13B7

13B7

28C4

28C4

37A5

44C8

29D6

29D6

29B3

29C8

7C7

29A8

7C4

7C4

29D6

29D6

7C7

7C7

28B4

24C8

24C8

28B4

29B3

29A3

24D3

24D3

23A6

VSS10

VSS2

DQ5

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

RAS*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

VDD1

NC/CKE1

VSS30

DQ31

DQ30

VSS28

DQS3

DQS3*

VSS26

DQ29

DQ28

VSS24

DQ23

DQ22

VSS22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

VSS7

DQ7

VSS5

DM0

DQ4

VSS0

DM1

DQ12

DQ6

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

NC/ODT1

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

VSS29

DQ27

DQ26

VSS27

NC1

DM3

VSS25

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

DQS0*

VSS4

VSS1

VREF

DQ0
DQ1

DQ34

DQ40

DQ42
DQ43

DQS6

DQ51

DQ57

KEY

VSS9

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ADDR=0xA0(WR)/0xA1(RD)

NC

DDR2 Bypass Caps

NC

NC

DIP DIMM CONN

One 0.1uF per connector

DDR2 VRef

Yellow uses 10K divider and TLV2463

(See Capell Valley pg 47)

Page Notes

NC

516-0135

NC

NC

when they get cheaper.

- =PP1V8_S3_MEM

- =I2C_MEM_SDA

- =I2C_MEM_SCL

- =PPSPD_S0_MEM (2.5V - 3.3V)

(NONE)

BOM options provided by this page:

Power aliases required by this page:

(For return current)

Signal aliases required by this page:

to drive MCH and DIMM connectors.

The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

C3109

1

2

20%

6.3V

4.7uF

603

CERM

10V

C3110

1

2

0.1UF

CERM

20%

402

C3100

1

2

0.1UF

20%
10V
CERM
402

C3121

1

2

0.1UF

CERM

10V

20%
402

C3120

1

2

402

4V
X5R

20%

2.2UF

C3122

1

2

4V
402

20%

2.2UF

X5R

C3130

1

2

2.2UF

20%

6.3V

CERM
402-LF

C3132

1

2

2.2UF

20%
CERM

6.3V

402-LF

C3131

1

2

2.2UF

20%
CERM

6.3V

402-LF

J3101

102101

105

9089

10099

9897

94

92

93

91

107

106

85

113

30
32

164
166

79

10

26

52

67

130

147

170

185

5
7

35
37

20
22

36
38

43
45

55
57

17

44
46

56
58

61
63

73
75

62
64

19

74
76

123
125

135
137

124
126

134
136

4

141
143

151
153

140
142

152
154

157
159

6

173
175

158
160

174
176

179
181

189
191

14

180
182

192
194

16

23
25

13

11

31

29

51

49

70

68

131

129

148

146

169

167

188

186

201

202

116

86

84

80

119

115

50

69

83

120

163

114

108
110

198
200

197

195

81 82

117 118

87 88

95 96

103 104

111 112

199

1 2
3

27 28

33 34

39 40
41 42

47 48

8

53 54

59 60

65 66

71 72

77 78

121 122

127 128

132

133

138

139

144

9

145

149 150

155 156

161 162

165

168

171

12

172

177 178

183 184

187

190

193

196

15

18

21

24

109

DDR2-SODIMM-STD

CRITICAL

F-RT-TH3

OMIT

20%

C3111

1

2

10V

CERM

0.1UF

402

C3112

1

2

0.1UF

10V

20%

402

CERM

C3113

1

2

20%

10V

CERM

0.1UF

402

C3114

1

2

0.1UF

CERM

10V

20%

402

C3115

1

2

20%

10V

CERM

0.1UF

402

C3116

1

2

2.2UF

20%

6.3V

CERM
402-LF

C3117

1

2

2.2UF

20%

6.3V

CERM
402-LF

R3103

1 2

10K

5%
1/16W
MF-LF

402

R3102

1 2

402

MF-LF

1/16W

5%

10K

R3100

1

2

1/16W

1%

1K

MF-LF
402

R3101

1

2

1%

1K

1/16W
MF-LF
402

SYNC_MASTER=MEMORY

DDR2 SO-DIMM Connector A

01

30

SYNC_DATE=06/20/2005

76

051-7455

MEM_ODT<1>

MEM_A_BS<0>

MEM_A_A<10>

MEM_A_DQ<47>
MEM_A_DQ<45>

MEM_A_DQ<60>

MEM_A_SA1

MEM_CS_L<0>

MEM_A_A<6>

MEM_A_DQ<61>

MEM_CS_L<1>

MEM_A_CAS_L

MEM_A_A<5>

MEM_A_BS<2>

MEM_A_DQ<14>

MEM_A_DQ<12>

MEM_A_DQS_P<0>

MEM_VREF_A

MEM_A_SA0

MEM_A_SA1

MEM_A_SA0

MEM_A_DQ<62>

MEM_A_DM<7>

MEM_A_DQS_P<5>

MEM_A_DQ<48>
MEM_A_DQ<53>

MEM_A_DQS_N<6>
MEM_A_DQS_P<6>

MEM_A_DQ<50>

MEM_A_DQ<57>

=PP1V8_S3_MEM

MEM_A_A<14>

MEM_A_DQS_N<2>

MEM_A_DQ<21>

MEM_A_DQ<18>

MEM_A_DQ<31>

=PPSPD_S0_MEM

MEM_A_DM<6>

MEM_A_DQ<49>

MEM_A_DQ<52>

MEM_A_DQ<63>

MEM_A_DQ<59>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DQ<56>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<36>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_WE_L

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

=GND_CHASSIS_DIPDIMM_CENTER

MEM_A_DQ<6>

MEM_A_DQ<11>

MEM_A_DQ<29>

MEM_A_DQ<2>

MEM_A_DQ<8>

MEM_A_DQS_N<1>

MEM_A_DQ<9>

MEM_A_DQS_P<2>

MEM_A_DQ<26>

MEM_A_DQ<13>

MEM_A_DQS_P<1>

MEM_A_DQ<10>

=PP1V8_S3M_MEM_NB

MEM_CKE<0>

MEM_A_A<13>

MEM_A_RAS_L

MEM_A_DQ<30>

MEM_VREF_A

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

VOLTAGE=0.9V

MEM_A_DQ<17>

MEM_A_DQ<54>

MEM_CLK_N<1>

MEM_A_DQS_N<5>

MEM_A_DQ<40>

MEM_A_DQ<44>

MEM_A_DQ<35>

MEM_A_DQ<32>

MEM_A_DM<4>

MEM_A_DQ<34>

MEM_A_DQ<37>

MEM_A_DQ<58>

MEM_A_DQ<28>

MEM_A_DM<1>

MEM_A_DQ<46>

=I2C_SODIMMA_SDA

MEM_A_DQ<55>

MEM_A_DQ<51>

MEM_A_DM<5>

MEM_A_DQ<33>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DM<2>

MEM_A_DQ<19>

MEM_A_DQ<27>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

=GND_CHASSIS_DIPDIMM_LEFT

MEM_A_A<4>

DIMM_OVERTEMPA_L

MEM_CLK_P<1>

MEM_A_A<15>

MEM_ODT<0>

MEM_A_DQ<24>

=I2C_SODIMMA_SCL

MEM_A_DQ<23>

MEM_A_DM<3>

MEM_A_DQ<15>

MEM_A_DM<0>

MEM_A_DQ<25>

MEM_A_A<7>

MEM_A_A<11>

MEM_CKE<1>

MEM_A_DQ<20>

MEM_A_DQ<22>

MEM_A_DQ<16>

MEM_A_DQS_N<0>

MEM_CLK_N<0>

MEM_CLK_P<0>

MEM_A_DQ<3>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_BS<1>

MEM_A_A<0>

MEM_A_A<2>

MEM_A_DQ<7>

=PP1V8_S3_MEM

MEM_A_DQ<5>

MEM_A_DQ<4>

=PP1V8_S3_MEM

31D6 31D6

31D6

31D4

31D2

31D4

31D4

31B2

20C8

31B2

31B2

72D3

72D3

72D3

72D3

72D3

72D3

72D3

72D3

72D3

30D4

72D3

31A7

72D3

72D3

72D3

72D3

72D3

72D3

17D7

72D3

72D3

72D3

72D3

72D3

72D3

72D3

72D3

72D3

72D3

72D3

30D6

30D6

32D6

32C6

32C6

72D3

72D3

72D3

32D6

32C6

72D3

32D6

32B6

32C6

32C6

72D3

72D3

72C3

72D3

72C3

72C3

72D3

72D3

72C3

72C3

72D3

72D3

30B2

32C6

72C3

72D3

72D3

72D3

31A3

72C3

72D3

72D3

72D3

72D3

72C3

72C3

72D3

72D3

72D3

72D3

72D3

72D3

72D3

32B6

32C6

32C6

32C6

32C6

32C6

72D3

72D3

72D3

72D3

72D3

72C3

72D3

72C3

72D3

72D3

72C3

72D3

15D2

32D6

32C6

32B6

72D3

72D3

72D3

72D3

72C3

72D3

72D3

72D3

72D3

72C3

72D3

72D3

72D3

72D3

72C3

72D3

72D3

72D3

72C3

72D3

72C3

72C3

72C3

72D3

72D3

72C3

72C3

32C6

72D3

32D6

72D3

72D3

72C3

72D3

72C3

72D3

32C6

32C6

32D6

72D3

72D3

72D3

72C3

72D3

72D3

72D3

72D3

72D3

32C6

32C6

32C6

72D3

30B2

72D3

72D3

30D4

15C3

16D5

16B5

16B8

16B8

16A8

30A4

15D3

16B5

16A8

15D3

16D5

16B5

16D5

16C8

16C8

16C5

30D1

30A4

30A4

30A4

16A8

16C5

16C5

16B8

16B8

16C5

16C5

16B8

16B8

7B4

15C6

16C5

16C8

16C8

16C8

7C4

16C5

16B8

16B8

16A8

16B8

16C5

16C5

16B8

16B8

16B8

16B8

16B8

16B8

16B8

16B5

16C5

16B5

16B5

16B5

16B5

16D8

16C8

16C8

16D8

16C8

16C5

16C8

16C5

16C8

16C8

16C5

16C8

7A4

15D3

16B5

16B5

16C8

30D7

16C8

16B8

15D3

16C5

16B8

16B8

16B8

16C8

16C5

16B8

16B8

16B8

16C8

16D5

16B8

47D6

16B8

16B8

16C5

16C8

16C5

16C5

16C5

16C8

16C8

16C5

16C5

8D8

16B5

8B1

15D3

8B4

15C3

16C8

47D6

16C8

16C5

16C8

16D5

16C8

16B5

16B5

15D3

16C8

16C8

16C8

16C5

15D3

15D3

16D8

16D8

16D8

16D5

16C5

16B5

16D8

7B4

16D8

16D8

7B4

VSS10

VSS2

DQ5

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

RAS*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

VDD1

NC/CKE1

VSS30

DQ31

DQ30

VSS28

DQS3

DQS3*

VSS26

DQ29

DQ28

VSS24

DQ23

DQ22

VSS22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

VSS7

DQ7

VSS5

DM0

DQ4

VSS0

DM1

DQ12

DQ6

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

NC/ODT1

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

VSS29

DQ27

DQ26

VSS27

NC1

DM3

VSS25

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

DQS0*

VSS4

VSS1

VREF

DQ0
DQ1

DQ34

DQ40

DQ42
DQ43

DQS6

DQ51

DQ57

KEY

VSS9

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT OF

SIZE

D

The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,

Resistor prevents pwr-gnd short

NC

when they get cheaper.

516-0135

NC

NC

NC

BOM options provided by this page:

- =I2C_MEM_SDA

Signal aliases required by this page:

- =PP1V8_S3_MEM

(See Capell Valley pg 47)

to drive MCH and DIMM connectors.

DDR2 Bypass Caps

- =I2C_MEM_SCL

by another page.

The reference voltage must be provided

NOTE: This page does not supply VREF.

(NONE)

Power aliases required by this page:

- =PPSPD_S0_MEM (2.5V - 3.3V)

Page Notes

Yellow uses 10K divider and TLV2463

DDR2 VREF (FOR CONNECTOR B)

One 0.1uF per connector

NC
NC

(For return current)

ADDR=0xA4(WR)/0xA5(RD)

DIP DIMM CONN

20%

6.3V

CERM

C3209

1

2

4.7uF

603

C3200

1

2

402

CERM

10V

20%

0.1UF

R3201

1

2

402

MF-LF

1/16W

1%

1K

R3202

1

2

402

MF-LF

1/16W

1K

1%

C3210

1

2

402

20%

10V

CERM

0.1UF

C3220

1

2

2.2UF

20%
4V
X5R
402

C3231

1

2

402-LF

6.3V

CERM

2.2UF

20%

C3230

1

2

402-LF

2.2UF

CERM

6.3V

20%

C3232

1

2

402-LF

6.3V

20%

2.2UF

CERM

C3221

1

2

402

CERM

10V

20%

0.1UF

C3222

1

2

X5R
402

2.2UF

20%
4V

R3200

1

2

402

MF-LF

1/16W

5%

10K

J3201

102101

105

9089

10099

9897

94

92

93

91

107

106

85

113

30
32

164
166

79

10

26

52

67

130

147

170

185

5
7

35
37

20
22

36
38

43
45

55
57

17

44
46

56
58

61
63

73
75

62
64

19

74
76

123
125

135
137

124
126

134
136

4

141
143

151
153

140
142

152
154

157
159

6

173
175

158
160

174
176

179
181

189
191

14

180
182

192
194

16

23
25

13

11

31

29

51

49

70

68

131

129

148

146

169

167

188

186

201

202

116

86

84

80

119

115

50

69

83

120

163

114

108
110

198
200

197

195

81 82

117 118

87 88

95 96

103 104

111 112

199

1 2
3

27 28

33 34

39 40
41 42

47 48

8

53 54

59 60

65 66

71 72

77 78

121 122

127 128

132

133

138

139

144

9

145

149 150

155 156

161 162

165

168

171

12

172

177 178

183 184

187

190

193

196

15

18

21

24

109

OMIT

DDR2-SODIMM-STD

F-RT-TH3

CRITICAL

C3211

1

2

0.1UF

CERM

20%

402

10V

C3212

1

2

10V

20%

0.1UF

402

CERM

C3213

1

2

0.1UF

CERM

10V

20%

402

C3214

1

2

0.1UF

20%
CERM

402

10V

C3215

1

2

0.1UF

20%
CERM

10V

402

C3216

1

2

402-LF

CERM

6.3V

2.2UF

20%

C3217

1

2

402-LF

6.3V

CERM

2.2UF

20%

R3203

1 2

402

10K

5%
1/16W
MF-LF

051-7455

SYNC_DATE=06/20/2005

SYNC_MASTER=MEMORY

01

31 76

DDR2 SO-DIMM Connector B

=PP1V8_S3_MEM

MEM_B_CAS_L

=PP1V8_S3_MEM

MEM_B_WE_L

MEM_B_BS<0>

MEM_B_DQ<18>

MEM_B_DQ<22>

MEM_B_DQ<8>

MEM_B_DQS_N<1>

MEM_B_DQ<12>

=PPSPD_S0_MEM

MEM_B_DQS_N<5>

MEM_B_DQ<53>

MEM_B_DQS_P<5>

MEM_B_DQ<54>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQS_N<7>

MEM_B_DQ<62>

MEM_B_DQ<60>

MEM_B_DQ<51>

MEM_B_DQS_P<7>

MEM_B_SA0

MEM_B_DQ<29>

MEM_B_DM<5>

MEM_B_DQ<40>

MEM_B_DQ<34>

MEM_B_DM<4>

MEM_B_DQ<33>

MEM_B_RAS_L

MEM_B_DQS_P<2>

MEM_B_DQ<47>

MEM_B_DQ<39>

MEM_B_DQ<32>

MEM_B_A<8>

MEM_B_A<12>

MEM_CKE<3>

MEM_B_DQ<31>

MEM_B_DM<3>

MEM_B_DQ<35>

MEM_B_DQ<45>

MEM_B_DQ<4>

MEM_B_DQ<1>

MEM_VREF_B

MEM_B_DQ<9>

DIMM_OVERTEMPB_L

MEM_B_A<4>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_A<14>

MEM_B_DQ<52>

MEM_B_DM<2>

MEM_B_DQ<28>

MEM_B_DQS_N<3>

MEM_B_DQ<26>

=PPSPD_S0_MEM

MEM_B_DQ<27>

=PP1V8_S3M_MEM_NB

MEM_VREF_B

VOLTAGE=0.9V
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

MEM_B_A<2>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

MEM_B_DQ<63>

MEM_B_DQ<61>

MEM_B_DM<7>

MEM_B_DQ<56>

MEM_B_DQ<50>

MEM_B_DQS_N<6>

MEM_B_DQ<48>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQ<38>

MEM_ODT<3>

MEM_CS_L<3>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<9>

MEM_B_BS<2>

MEM_B_DQ<30>

MEM_B_DQ<44>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQ<57>

=GND_CHASSIS_DIPDIMM_CENTER

MEM_B_DQ<17>

MEM_B_DQS_P<1>

MEM_B_DQ<20>

MEM_B_DM<0>

MEM_B_DQ<15>

MEM_B_DM<1>

MEM_CLK_P<3>
MEM_CLK_N<3>

MEM_B_DQ<14>

MEM_B_DQ<21>

MEM_B_DQ<19>

MEM_B_DQ<25>

MEM_B_DQS_P<3>

MEM_B_DQ<24>

MEM_B_DQS_N<2>

MEM_B_BS<1>

MEM_CS_L<2>

MEM_B_DQ<10>

MEM_B_DQ<13>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_A<15>

MEM_B_DQ<23>

MEM_B_DQ<16>

MEM_CKE<4>

MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>

MEM_ODT<2>
MEM_B_A<13>

MEM_B_DQ<36>
MEM_B_DQ<37>

MEM_B_DQ<49>

MEM_B_DM<6>

=GND_CHASSIS_DIPDIMM_RIGHT

MEM_B_DQ<11>

MEM_B_DQ<2>

MEM_B_DQ<6>

MEM_B_DQ<0>

=PP1V8_S3_MEM

MEM_B_DQ<5>

MEM_B_A<5>
MEM_B_A<3>

MEM_B_A<0>

MEM_B_DQ<41>
MEM_B_DQ<46>

MEM_CLK_P<4>
MEM_CLK_N<4>

J3201_SA1

MEM_B_SA0

MEM_B_DQ<7>
MEM_B_DQ<3>

31D6

31D4 31D6

31D4

31B2

30D2

31B2

30D6

30D6

20C8

30D6

30D4

72B3

30D4

72B3

72B3

31A7

72B3

72B3

72B3

72B3

72B3

72B3

31A3

17D7

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

30D4

72B3

72B3

72B3

30B2

32A6

30B2

32A6

32A6

72B3

72B3

72B3

72A3

72B3

30A7

72A3

72B3

72A3

72B3

72B3

72B3

72A3

72B3

72B3

72B3

72A3

72B3

72B3

72B3

72B3

72B3

72B3

32A6

72A3

72B3

72B3

72B3

32B5

32A5

32D6

72B3

72B3

72B3

72B3

72B3

72B3

72B3

32B5

72B3

72B3

32A5

72B3

72B3

72B3

72A3

72B3

30A7

72B3

15D2

32B5

72B3

72B3

72A3

72B3

72B3

72A3

72B3

72A3

72A3

72B3

32D6

32D6

32B5

32B5

32B5

32A6

72B3

72B3

72A3

72B3

72B3

72B3

72A3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72B3

72A3

72B3

72A3

32A6

32D6

72B3

72B3

72A3

72A3

72B3

72B3

32D5

32A5

32B5

32B5

32D6

32A5

72B3

72B3

72B3

72A3

72B3

72B3

72B3

72B3

30B2

72B3

32B5

32B5

32B5

72B3

72B3

72B3

72B3

72B3

72B3

7B4

16D1

7B4

16B1

16D1

16C4

16C4

16C4

16C1

16C4

7C4

16C1

16B4

16C1

16B4

16B4

16B4

16C1

16A4

16A4

16B4

16C1

31A4

16C4

16C1

16B4

16B4

16C1

16C4

16B1

16C1

16B4

16B4

16C4

16B1

16B1

15D3

16C4

16C1

16B4

16B4

16D4

16D4

31D1

16C4

8B1

16B1

16B4

16B4

15C6

16B4

16C1

16C4

16C1

16C4

7C4

16C4

7A4

31D7

16B1

47C6

47C6

16A4

16A4

16C1

16B4

16B4

16C1

16B4

16C1

16C1

16B4

15C3

15C3

16B1

16C1

16B1

16D1

16C4

16B4

16C1

16B4

16B4

16C4

16C1

16C4

16D1

16C4

16D1

15D3

15D3

16C4

16C4

16C4

16C4

16C1

16C4

16C1

16D1

15D3

16C4

16C4

16C1

16C1

8B4

16C4

16C4

15D3

16B1

16B1

16B1

15C3

16B1

16B4

16B4

16B4

16C1

16C4

16D4

16D4

16D4

7B4

16D4

16B1

16B1

16C1

16B4

16B4

15D3

15D3

31A3

16D4

16D4

IN

IN

IN

IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN

IN

IN

IN

IN

IN

IN
IN
IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BOMOPTION shown at the top of each group applies to every part below it

TO PP0V9_S0_MEM_TERM

LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED

One cap for each side of every RPAK, one cap for every two discrete resistors

R3301

1 2

56

1/16WMF-LF

402

5%

R3309

1 2

1/16W56402

MF-LF

5%

R3311

1 2

56

402

MF-LF

5%

1/16W

R3325

1 2

402

5%

1/16W56MF-LF

R3335

1 2

5%

402

56

1/16WMF-LF

0

2

1

16D1 31B6 72B3

16B1 31B4 72B3

16D1 31B4 31B6 31C6 72B3

16B1 31B6 72B3

RP3300

3 6

56

SM-LF

1/16W

5%

RP3300

4 5

56

SM-LF

5%

1/16W

RP3300

1 8

SM-LF

56

5%

1/16W

RP3300

2 7

5%

SM-LF

56

1/16W

RP3301

2 7

56

SM-LF

1/16W

5%

RP3301

1 8

1/16W

SM-LF

56

5%

RP3301

4 5

5%

56

SM-LF

1/16W

RP3301

3 6

56

SM-LF

5%

1/16W

RP3302

4 5

SM-LF

56

1/16W

5%

RP3302

1 8

SM-LF

1/16W

56

5%

RP3302

3 6

5%

1/16W

56

SM-LF

RP3302

2 7

5%

1/16W

56

SM-LF

RP3303

1 8

5%

SM-LF

56

1/16W

RP3303

2 7

56

5%

SM-LF

1/16W

RP3303

3 6

5%

56

1/16W

SM-LF

RP3303

4 5

SM-LF

5%561/16W

RP3304

1 8

SM-LF

5%561/16W

RP3304

3 6

56

1/16W

5%

SM-LF

RP3304

4 5

56

5%

SM-LF

1/16W

RP3305

1 8

SM-LF

5%

1/16W

56

RP3305

2 7

5%

SM-LF

56

1/16W

RP3305

3 6

56

5%

1/16W

SM-LF

RP3305

4 5

56

5%

SM-LF

1/16W

RP3306

2 7

56

1/16W

5%

SM-LF

RP3306

3 6

5%

56

SM-LF

1/16W

RP3307

4 5

SM-LF

5%561/16W

RP3307

3 6

56

SM-LF

5%

1/16W

RP3307

2 7

SM-LF

56

5%

1/16W

RP3307

1 8

56

SM-LF

5%

1/16W

RP3308

4 5

56

SM-LF

5%

1/16W

RP3308

3 6

SM-LF

56

5%

1/16W

RP3308

2 7

SM-LF

56

5%

1/16W

RP3308

1 8

56

SM-LF

5%

1/16W

RP3309

1 8

56

1/16W

5%

SM-LF

RP3309

2 7

56

5%

SM-LF

1/16W

RP3309

3 6

56

SM-LF

5%

1/16W

RP3309

4 5

SM-LF

56

5%

1/16W

RP3310

3 6

SM-LF

56

1/16W

5%

RP3310

2 7

SM-LF

5%

1/16W

56

RP3310

1 8

56

5%

SM-LF

1/16W

RP3310

4 5

56

5%

SM-LF

1/16W

RP3311

1 8

SM-LF

5%561/16W

RP3311

2 7

SM-LF

56

1/16W

5%

RP3311

4 5

5%

56

1/16W

SM-LF

RP3306

4 5

56

SM-LF

5%

1/16W

RP3311

3 6

SM-LF

56

1/16W

5%

16C1 31B4 72B3

16B1 31B6 72B3

16B1 31B4 72B3

16B1 31B6 72B3

16B1 31B4 72B3

16B1 31B6 72B3

16B1 31C4 72B3

16B1 31C4 72B3

16B1 31C6 72B3

16B1 31C6 72B3

16C1 31B6 72B3

16B1 31C4 72B3

16B1 31C6 72B3

16B1 31B4 72B3

C3300

1

2

402

20%
10V
CERM

0.1UF

C3301

1

2

0.1UF

CERM

10V

20%

402

C3302

1

2

402

20%
10V
CERM

0.1UF

C3303

1

2

0.1UF

CERM

10V

20%

402

C3304

1

2

402

20%
10V
CERM

0.1UF

C3305

1

2

0.1UF

CERM

10V

20%

402

C3306

1

2

402

20%
10V
CERM

0.1UF

C3307

1

2

402

0.1UF

CERM

10V

20%

C3308

1

2

10V
402

CERM

0.1UF

20%

C3309

1

2

0.1UF

CERM

10V

20%

402

C3310

1

2

402

20%
10V
CERM

0.1UF

C3311

1

2

0.1UF

CERM

10V

20%

402

C3312

1

2

20%

0.1UF

10V
CERM
402

C3313

1

2

0.1UF

CERM

10V

20%

402

C3314

1

2

402

20%
10V

0.1UF

CERM

C3315

1

2

0.1UF

CERM

10V

20%

402

C3316

1

2

0.1UF

402

20%
10V
CERM

C3317

1

2

0.1UF

CERM

10V

20%

402

C3318

1

2

402

20%
10V
CERM

0.1UF

C3319

1

2

0.1UF

CERM

10V

20%

402

C3320

1

2

402

20%
10V
CERM

0.1UF

C3321

1

2

0.1UF

CERM

10V

20%

402

C3322

1

2

402

20%
10V
CERM

0.1UF

C3323

1

2

0.1UF

CERM

10V

20%

402

C3324

1

2

402

20%
10V
CERM

0.1UF

C3325

1

2

402

20%
10V
CERM

0.1UF

15D3 30C4 72D3

15D3 31C6 72B3

15D3 31C4 72B3

14

RP3304

2 7

1/16W

5%

56

SM-LF

RP3306

1 8

56

1/16W

5%

SM-LF

R3327

1 2

56

MF-LF

5%

1/16W

402

0

1

1

0

2

0

1

2

3

4

5

6

7

10

11

9

8

13

12

15C3 15D3 30B4 30B6 31B4 31B6 72B3 72D3

15D3 30C6 72D3

15C6 16B5 16C5 30B4 30B6 30C4 30C6 72D3

16D5 30B4 30B6 30C6 72D3

16B5 30B4 72D3

16D5 30B6 72D3

16B5 30B6 72D3

2

3

0

1

2

3

15C3 30B4 30B6 31B4 31B6 72B3 72D3

01

76

Memory Active Termination

32

051-7455

MEM_B_BS<2..0>

MEM_CS_L<3..0>

MEM_A_A<14..0>

MEM_ODT<3..0>

MEM_A_BS<2..0>

MEM_B_A<2>
MEM_B_A<10>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<1>

=PP0V9_S3M_MEM_TERM

MEM_CKE<4>

MEM_CKE<3>

MEM_CKE<1>

MEM_CKE<0>

MEM_B_A<0>
MEM_B_A<3>

MEM_A_CAS_L

MEM_B_CAS_L
MEM_B_WE_L

MEM_B_RAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_B_A<11>
MEM_B_A<12>

MEM_B_A<14>

MEM_B_A<13>

7D7

OUT

D

SG

D

SG

D

SG

D

SG

IN

IN

OUT

OUT

IO

IO

IN
IN

OUT

IO

IO

IN

KEY

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

* Enclosure: 516S0406

ICH8 GPIO42

PLACE CAPS < 250 MILS FROM (U2100) SB

Plexi: 516S0363

CONNECT TO M35 MODULE

SB HAS INTERNAL 15K PULL-DOWNS

AIRPORT CONN

C3406

1

2

0.1UF

402

20%
CERM

10V

C3408

1

2

CERM

0.1UF

10V

20%

402

C3407

1

2

402

10V

0.1UF

20%
CERM

R3403

12

NOSTUFF

5%

805

1/8W

0

MF-LF

Q3402

6

2

1

SOT563

SSM6N15FE

Q3402

3

5

4

SOT563

SSM6N15FE

R3404

1 2

1/16W

MF-LF

402

100K

5%

R3405

12

10K

5%
1/16W
MF-LF

402

C3411

1

2

0.033UF

16V
X5R
402

10%

Q3401

1

2

5

6

3

4

CRITICAL

SM-LF

FDC638P

Q3403

6

2

1

SOT563

SSM6N15FE

Q3403

3

5

4

SOT563

SSM6N15FE

C3412

1

2

CERM

NOSTUFF

0.01UF

10%

16V
402

R3406

1 2

100K

402

MF-LF

1/16W

5%

C3410

1

2

10V
CERM
402

20%

0.1UF

C3409

1

2

10UF

20%
X5R

6.3V
603

C3400

1 2

10V

402

0.1UF

20%

CERM

C3404

1

2

0.1UF

CERM

10V

20%

402

CK505_SRC_CLKREQ6_L

R3401

1 2

0

MF-LF

4025%1/16W

R3402

1 2

0

402

MF-LF

1/16W

5%

J3400

53

54

1

10
11 12
13 14

15

16
17 18
19

2

20
21 22
23 24
25 26
27 28
29

3

30
31 32
33 34
35 36
37 38
39

4

40
41 42
43 44
45 46
47 48
49

5

50
51 52

6
7 8
9

AS0B22-S45N-7F

CRITICAL

F-ST-SM

C3401

1 2

0.1UF

10V

CERM

402

20%

C3405

1

2

0.1UF

20%
10V

402

CERM

01

33 76

051-7455

PP3V3_S3_AP_AUX

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.2MM

=PP1V5_S0_AIRPORT

PM_WLAN_EN_L_SS

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.2MM

=PP3V3_S3_AIRPORT_AUX

AIRPORT_RST_L

=PP3V3_S0_AIRPORT

PCIE_E_D2R_P

PCIE_WAKE_L

PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_P

SMB_AIRPORT_CONN_CLK
PCIE_E_R2D_N
PCIE_E_R2D_P

PCIE_E_D2R_N

=USB2_AIRPORT_P

SMB_AIRPORT_CONN_DATA

=USB2_AIRPORT_N

=SMB_AIRPORT_CLK
=SMB_AIRPORT_DATA

PCIE_E_R2D_C_P

PM_S4_STATE_L

PCIE_E_R2D_C_N

MAKE_BASE=TRUE

WOW_EN

MAKE_BASE=TRUE

PCIE_E_R2D_C_P

PCIE_E_D2R_P

MAKE_BASE=TRUE

=PP3V3_S5_AIRPORT_AUX

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

PCIE_MINI_R2D_C_N

=PP3V3_S5_AIRPORT_AUX

PM_SLP_S3_L

PCIE_MINI_R2D_C_P

PCIE_E_R2D_C_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCIE_E_D2R_N

SB_GPIO42

PM_WLAN_EN_L

=PP3V3_S5_AIRPORT_AUX

SMC_ADAPTER_EN

WOW_EN

PM_WLAN_EN_L1

PM_WLAN_EN_L2

62B8

57C4

58B7

45B3

65C4

45A6

44D5

65A6

33D7

33D6

44C5

33D7

38C6

74C3

34B8

75A3

75B3

74B3

74C3

44C5

74C3

74C3

74C3

33D6

33C7

35C7

74C3

74B3

33C7

35C7

28B4

7B7

7A4

27D1

7D4

33B5

24C8

29B3

29C3

33B5

8C2

8C2

47C3

47C3

33B5

24D3

33B5

33C7

33B6

33B5

7C1

23C5

23D5

23C5

7C1

24D3

23C5

33B6

33C5

23C8

7C1

6C1

33B5

BI
BI

BI
BI

BI
BI

BI
BI

OUT

OUT

IN

IN

IN

OUT

OUT

IN
IN

THRML_PAD

VDDO_TTL1

VMAIN_AVLBL

SWITCH_VAUX

VAUX_AVLBL

LED_DUPLEX*

RSVD_43

RSVD_29

RSVD_25

RSVD_24

NC_64

CTRL12

NC_57

NC_52

NC_51

NC_32

RSET

SWITCH_VCC

AVDDH

AVDD0

AVDD3

VDDO_TTL3

LOM_DISABLE*

VDD0

VDD1

VDD3

VDD4

TX_P

CTRL18

TESTMODE

VDD2

VDD5

VDD7

CLKREQ*

WAKE*

PERST*

MDIP0

MDIP1
MDIN1

MDIP2
MDIN2

MDIP3

XTALI

MDIN3

XTALO

REFCLKP
REFCLKN

RX_N

RX_P

SPI_DO

SPI_CLK

SPI_CS

VPD_DATA

VPD_CLK

TX_N

MDIN0

AVDD1

LED_LINK1000*

VDD6

VDDO_TTL2

VDDO_TTL0

LED_ACT*

LED_LINK10/100*

AVDD2

SPI_DI

ANALOG

PCI EXPRESS

SPI

LED

TWSI

MEDIA

MAIN CLK

TEST/RSVD

IN

OUT
OUT

E2

WC*

NC0

NC1

VCC

VSS

SCL

SDA

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

- =PP1V8R2V5_ENET_PHY

100 Mbps: 203 mA
1000 Mbps: 426 mA 1000 Mbps: 290 mA

10 Mbps: 70 mA
100 Mbps: 70 mA
1000 Mbps: 80 mA

Yukon Ultra (1.8V)
No link: 0 mA

10 Mbps: 30 mA

Yukon EC: Alias to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF & 1x 0.001uF caps
Yukon Ultra: Alias to GND

Yukon EC: Pin 42 should be NC (or TP) net.

100 Mbps: 4 mA

10 Mbps: 4 mA

YUKON_ULTRA - Selects Yukon Ultra RSET.

YUKON_EC - Selects Yukon EC RSET value.

BOM options provided by this page:

- =ENET_CLKREQ_L (NC/TP for Yukon EC)

Signal aliases required by this page:

No link: 4 mA

16pF

too small, make R3765 smaller

If characterization shows eye height is

- Use YUKON_EC and YUKON_ULTRA BOMOPTIONs to select stuffed part

NOTE: See bottom of page for

Yukon Ultra schematic support.

instructions for dual Yukon EC /

on this page. Proper part numbers

- =ENET_VMAIN_AVLBL

must be called out elsewhere.

NOTE: Yukon IC and EEPROM are OMITted

(EC:2.5V)

No link: 82 mA

1000 Mbps: 218 mA

100 Mbps: 126 mA

10 Mbps: 108 mA

Must be high in S0 state (can use PP3V3_S0 as input)

- =YUKON_EC_PP2V5_ENET

100 Mbps: 150 mA

Yukon EC

VPD ROM

NC

EC:AVDD 2.5V

NC
NC
NC

NC

NC

NC

EC:CTRL25

(IPU)
(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPD)

NC

NC

NC

NC

NC

NC

NC

NC

(2.5V / GND)

(EC / Ultra)

- =PP1V2_ENET_PHY

Yukon Ultra

1000 Mbps: 150 mA

Yukon EC (2.5V)

No link: 60 mA

10 Mbps: 130 mA10 Mbps: 179 mA

- Connect =ENET_CLKREQ_L to clock generator via 0-ohm resistor (BOMOPTION: YUKON_ULTRA)

100 Mbps: 40 mA

1000 Mbps: 4 mA

Page Notes

NC

Yukon Ultra
No link: 130 mANo link: 171 mA

Yukon EC

(2.5V / 1.8V)

- =PP3V3_ENET_PHY

Power aliases required by this page:

EC:NO CONNECT

NC

- Use 0-ohm resistors or variable supply to provide 1.8V or 2.5V to =PP1V8R2V5_ENET_PHY

- Alias =YUKON_EC_PP2V5_ENET to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF and 1x 0.001uF caps

To support Yukon EC and Ultra on the same board:

NC

C3751

1

2

CERM

50V

5%

15PF

402

R3740

1

2

49.9

1%

SIGNAL_MODEL=EMPTY

1/16W
MF-LF
402

R3741

1

2

SIGNAL_MODEL=EMPTY

1/16W
MF-LF

1%

49.9

402

36B7 74B3

36B7 74B3

36C7 74B3

36C7 74B3

36B7 74B3

36C7 74B3

36C7 74B3

36C7 74B3

23C5

23C5

C3740

1

2

10%

402

CERM

50V

0.001UF

C3742

1

2

10%

402

CERM

50V

0.001UF

C3744

1

2

10%

402

CERM

50V

0.001UF

C3746

1

2

10%

402

CERM

50V

0.001UF

R3742

1

2

SIGNAL_MODEL=EMPTY

1/16W
MF-LF

49.9

1%

402

R3743

1

2

SIGNAL_MODEL=EMPTY

1/16W
MF-LF

1%

49.9

402

R3747

1

2

49.9

SIGNAL_MODEL=EMPTY

402

MF-LF

1/16W

1%

R3746

1

2

49.9

1%

SIGNAL_MODEL=EMPTY

1/16W
MF-LF
402

R3745

1

2

49.9

1%

SIGNAL_MODEL=EMPTY

1/16W
MF-LF

402

R3744

1

2

49.9

1%

SIGNAL_MODEL=EMPTY

1/16W
MF-LF
402

C3735

1 2

10% X5R

0.1UF

16V 402

C3736

1 2

10% X5R

0.1UF

16V 402

C3730

1 2

10% X5R

0.1UF

16V 402

PLACEMENT_NOTE=Place C3730 close to southbridge.

C3731

1 2

PLACEMENT_NOTE=Place C3731 close to southbridge.

X5R10%

0.1UF

16V 402

23C5

23C5

27C1

24C8 33C5

8C4

28A4

29B3

29B3

U3700

192223

28

8

42

3

4

59

63

62

60

10

18

21

27

31

17

20

26

30

3251525764

5

56

55

16

24
25
29
43

53

54

37
36

35

34

9

11

46

65

50

49

12

271333394448

58

14045

61

47

38
41

6

15
14

88E8058

CRITICAL

QFN

8A3

R3765

1

2

YUKON_ULTRA

4.99K

1%
1/16W
MF-LF
402

C3720

1

2

603

4.7UF

20%

6.3V
CERM

C3710

1

2

20%

6.3V

4.7UF

603

CERM

C3701

1

2

X5R

10%

0.1UF

16V
402

C3700

1

2

CERM

6.3V

20%

4.7UF

603

C3706

1

2

10%

402

CERM

50V

0.001UF

U3780

3

1

2

6

5

8

4

7

CRITICAL

OMIT

M24C08

SO8

C3780

1

2

0.1UF

10%
X5R

16V
402

R3780

1

2

5%

4.7K

1/16W
MF-LF

402

R3781

1

2

5%

4.7K

1/16W
MF-LF
402

R3760

1

2

5%

4.7K

1/16W
MF-LF

402

L3720

1 2

FERR-120-OHM-1.5A

0402-LF

C3702

1

2

16V

0.1UF

X5R

10%

402

C3703

1

2

X5R

10%

0.1UF

16V
402

C3704

1

2

16V

0.1UF

10%
X5R

402

C3705

1

2

16V

0.1UF

10%
X5R

402

C3707

1

2

402

10%
CERM

50V

0.001UF

C3708

1

2

402

10%
CERM

50V

0.001UF

C3711

1

2

16V

0.1UF

10%
X5R

402

C3712

1

2

X5R

10%

0.1UF

16V
402

C3713

1

2

X5R

10%

0.1UF

16V
402

C3714

1

2

402

10%
CERM

50V

0.001UF

C3715

1

2

10%

402

CERM

50V

0.001UF

C3721

1

2

X5R

10%

0.1UF

16V
402

C3722

1

2

16V

0.1UF

10%
X5R

402

C3723

1

2

16V

0.1UF

10%
X5R

402

C3724

1

2

10%

402

CERM

50V

0.001UF

Y3750

24

13

CRITICAL

25.0000M

SM-3.2X2.5MM

C3750

1

2

CERM

50V

5%

15PF

402

Ethernet (Yukon)

76

01

SYNC_MASTER=USB SYNC_DATE=10/07/2006

34

051-7455

114S0285

1

YUKON_EC

R3760

RES,4.87K,1%,1/16W,0402,LF

ENET_MDI_N<2>

ENET_MDI_P<1>

ENET_RESET_L

PCIE_WAKE_L

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

PCIE_ENET_R2D_N

PCIE_ENET_R2D_P

PCIE_ENET_D2R_C_N

PCIE_ENET_D2R_C_P

=YUKON_EC_PP2V5_ENET

PP1V8R2V5_ENET_PHY_AVDD

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=1.8V

MIN_NECK_WIDTH=0.22 mm

=PP3V3_ENET_PHY

=PP1V2_ENET_PHY

=ENET_CLKREQ_L

=PP1V8R2V5_ENET_PHY

PCIE_ENET_D2R_P

YUKON_VPD_DATA

TP_YUKON_CTRL18
TP_YUKON_CTRL12

YUKON_RSET

ENET_LOM_DIS_L

ENET_MDI0 ENET_MDI1 ENET_MDI2

YUKON_VPD_CLK

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

=ENET_VMAIN_AVLBL

ENET_MDI_N<0>

ENET_MDI_P<0>

ENET_MDI3

ENET_CLK25M_XTALO

ENET_MDI_P<3>
ENET_MDI_N<3>

ENET_MDI_P<2>

ENET_MDI_N<1>

ENET_CLK25M_XTALI

8A4

7B5

7B5

7B3

GND

OUT1

IN1

IN0

EN FB

PAD

OUT0

NC0

NC2

NC1

THRML

D

SG

D

SG

THRM_PAD

NC

IN1

EN

IN2

OUT1
OUT2

NR/FB

GND

D

SG

D

SG

G

DS

IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 1.2246V * (1 + R3821 / R3822)

1.2V ENET LDO

S0 on AC

0.085ohm

1.8A

Powered by S3

"ENET" = "S0" || AC

1.9V ENET LDO

NC

High (3.3V)

Low (0V)

S5 on anything

High (3.3V)

Low (0V)

AC

Power

S0 on Battery
S3 on Battery

S3 on AC

High (3.3V)

High (3.3V)

Low (0V)

Yukon Power

N/A

Low (0V)

Power

Low (0V)
Low (0V)
N/A

PM_ENET_EN_L

N/AN/A

Name
Logic

S0

High (3.3V)

Power

Power

PM_SLP_S3_L

High (3.3V)

Low (0V)

High (3.3V)

High (3.3V)

PM_ENET_EN

No Power

ENET Enable Generation

Low (0V)

SMC_ADAPTER_EN

3.3V ENET FET

4.7UF

20%

6.3V

C3832

CERM
603

2

1

R3830

1

2

402

1%

5.11K

1/16W
MF-LF

2

3.65K

1%
1/16W
MF-LF
402

1

R3831

1

7

6

2
3

4
5

10

8
9

11

SOP

MAX8516

U3830

CRITICAL

6.3V

4.7UF

20%

C3831

CERM
603

2

1

C3830

1

2

CERM

6.3V

22UF

805

20%

Q3801

3

5

4

SSM6N15FE

SOT563

Q3801

6

2

1

SOT563

SSM6N15FE

U3820

8

6

1
2

7

5

3
4

9

LREG_TPS79501DRB

SON

CRITICAL

R3821

1

2

402

MF-LF

1/16W

1%

16.9K

R3822

1

2

1%
1/16W
MF-LF
402

30.1K

C3823

1

2

6.3V

10UF

20%
X5R

603

C3820

1

2

402

CERM

6.3V

10%

1UF

C3822

1

2

CERM

5%

402

50V

27PF

R3823

1

2

5%
402

15K

MF-LF

1/16W

R3824

1

2

1/16W
402

MF-LF

33K

5%

R3832

1

2

MF-LF

1/16W

100K

5%
402

Q3802

6

2

1

SSM6N15FE

SOT563

R3802

1

2

100K

MF-LF
402

1/16W

5%

Q3802

3

5

4

SSM6N15FE

SOT563

R3810

1 2

402

10K

1/16W

5%

MF-LF

C3810

12

NOSTUFF

10%
16V

0.01UF

CERM

402

Q3810

3

1

2

NTR4101P

SOT-23

CRITICAL

C3811

1

2

16V

0.033UF

10%
X5R

402

R3801

1

2

402

1/16W

5%

100K

MF-LF

24D3 33C7 44C5 45A6 58B7 62B8

6C1

33C7 38C6 44D5 45B3 57C4

35

SYNC_DATE=10/07/2006SYNC_MASTER=USB

051-7455

01

76

Yukon Power Control

PP1V2_S3_FB

=PP1V8_ENET_P1V8ENETFET

SMC_ADAPTER_EN

P3V3ENET_SS

=PP3V3_S3_ENETPWRCTL

PP3V3_ENET_FET

PP1V2_ENET_EN

PM_ENET_EN_L

PP3V3_ENET_FET

=PP1V9_ENET_REG

=PP1V2_ENET_REG

PP1V2_ENET_EN

PP1V9_S3_FB

=PP3V3_ENET_P3V3ENETFET

PP1V9_ENET_EN

=PP1V9_ENET_REG

=PP3V3_S5_SB

PM_SLP_S3_L

PM_ENET_EN_L

PM_ENET_WOL_EN_L

WOL_EN

26D8 24A8

35D4

35D4

35D1

35B2

24A3

7B4

7A4

7B6

35B3

35C6

7B6

7B4

7B6

35B2

7A4 7B4

7D1

35A3

24B3

SYM_VER-1

IO

IO

IO

IO

IO

IO

IO

IO

OUT

RX

TX

RX

TX

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

514-0443

PLACE ONE PAIR OF CAPS AT EACH PIN 3 AND 6 OF TRANSFORMERS

ETHERNET CONNECTOR

PLACE C3911 AND C3912
ON EACH SIDE OF J3900

R3911

1 2

1/16W

402

MF-LF

5%

0

R3910

1 2

0

5%

1/16W MF-LF

402

R3909

1 2

MF-LF

0

5%

1/16W

402

R3908

1 2

402

0

1/16W5%MF-LF

R3907

1 2

0

MF-LF1/16W

402

5%

R3906

1 2

0

402

5%

1/16W MF-LF

R3905

1 2

0

5%

1/16W MF-LF

402

R3904

1 2

0

5%

1/16W MF-LF

402

OMIT

CRITICAL

F-RT-TH

RJ45-M71

8

7

6

5

4

3

2

1

9

10

J3900

C3902

1

2

X5R

16V
402

10%

0.1UF

C3900

1

2

X5R

10%

0.1UF

16V
402

C3901

1

2

10%
16V
X5R

0.1UF

402

C3903

1

2

0.1UF

10%
X5R

16V
402

R3900

1 2

MF-LF

75

1%

1/16W

402

R3901

1 2

1/16W

75

1%

MF-LF

402

R3902

1 2

1/16W MF-LF

75

1%

402

R3903

1 2

1/16W

402

75

1%

MF-LF

C3904

1

2

CERM

50V

0.001UF

402

10%

C3905

1

2

0.001UF

50V
CERM
402

10%

C3906

1

2

CERM

50V

0.001UF

402

10%

C3907

1

2

CERM

50V

0.001UF

402

10%

C3910

1

2

CRITICAL

1000PF

CERM

2KV

10%

1206

C3911

1

2

CERM

50V

0.001UF

402

10%

C3912

1

2

CERM

50V

0.001UF

402

10%

L3950

1 2

FERR-120-OHM-1.5A

0402-LF

T3902

1

10

11

12

2

3

4

5

6 7

8

9

TLA-6T213LF

CRITICAL

SM

T3901

1

10

11

12

2

3

4

5

6 7

8

9

TLA-6T213LF

SM

CRITICAL

CONN,8P RJ-45 JACK,TH,BLACK,LF

CRITICAL

514-0475

J3900 FANCY

1

CONN,8P RJ-45 JACK,TH,MG3,LF

CRITICAL

514-0443

NORMAL

1

J3900

76

051-7455

01

36

SYNC_MASTER=USB

SYNC_DATE=09/14/2006

ETHERNET CONNECTOR

=GND_CHASSIS_RJ45

=PP1V8_S0_YUKON

ENET_MDI_P<0>

ENET_MDI_N<0>

ENET_MDI_N<2>

ENET_MDI_P<3>

ENET_MDI_N<3>

ENET_MDI_R_P<0>

ENET_MDI_R_N<0>

ENET_CENTER_TAP<2>

ENET_CENTER_TAP<3>

ENET_MDI_P<1>

ENET_MDI_N<1>

ENET_CENTER_TAP<1>

ENET_MDI_R_P<3>

ENET_MDI_R_P<1>

ENET_MDI_R_N<3>

ENET_MDI_P<2>

ENET_MDI_R_N<2>

ENET_MDI_R_P<2>

ENET_MDI_R_N<1>

PP1V8_S0_YUKON_AVDD

ENET_CENTER_TAP<0>

MIN_NECK_WIDTH=0.25MM

ENET_BOB_SMITH_CAP

MIN_LINE_WIDTH=0.6MM

ENET_MDI_TRAN_P<3>

ENET_MDI_TRAN_N<3>

ENET_MDI_TRAN_N<1>

ENET_MDI_TRAN_P<2>

ENET_MDI_TRAN_N<2>

ENET_MDI_TRAN_N<0>

ENET_MDI_TRAN_P<1>

ENET_MDI_TRAN_P<0>

74B3

74B3

74B3

74B3

74B3

74B3

74B3

74B3

8C8

7B3

34B8

34B8

34B8

34B8

34B8

34B8

34B8

34B8

IO

IO
IO

IO
IO

IO

IO
IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

IO

IO
IO

IO

OUT

IN

IN

OUT

OUT

IO
IO

IO

IO

IO

IO

IO

IO

IO
IO

IO

MPCI_ACTN_323

TPB0_P

TPBIAS0

PCI_AD12

RESET*

TPBIAS2

PCI_RST*
PCI_INTA*
PCI_PME*

PCI_AD21

PCI_AD31

XO

XI

R1

R0

TPA0_N

TPA0_P

TPB0_N

TPBIAS1

TPA1_P

TPB1_P

TPA1_N

TPA2_P
TPA2_N
TPB2_P
TPB2_N

MODE_A

MODE_420

TEST0
TEST1
PTEST

SE
SM

VSS21

VSS22

VSS20

VSS18

VSS19

VSS16

VSS15

VSS17

VSS13

VSS14

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VSS0

VSSA0

VSSA1

VSSA3

VSSA4

VSSA2

VDDA4

VDDA5

VDDA3

VDDA2

VDDA1

VDDA0

VDD0

VDD2

VDD1

VDD3

VDD4

VDD7

VDD9

PCI_VIOS

PCI_AD0

PCI_AD2

PCI_AD4
PCI_AD5

PCI_AD3

PCI_AD6

PCI_AD9
PCI_AD10

PCI_AD8

PCI_AD11

PCI_AD14
PCI_AD15

PCI_AD13

PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20

PCI_AD23

PCI_AD22

PCI_AD25

PCI_AD28

PCI_AD26

PCI_AD29
PCI_AD30

PCI_CBE2*

PCI_CBE1*

PCI_CBE0*

PCI_CBE3*

PCI_PAR
PCI_FRAME*
PCI_IRDY*
PCI_TRDY*
PCI_DEVSEL*
PCI_STOP*
PCI_IDSEL

PCI_REQ*
PCI_GNT*
PCI_PERR*
PCI_SERR*

PCI_CLK
CLKRUN*

VDD5

PCI_AD27

PCI_AD24

VDD6

PCI_AD1

TPB1_N

PC0

PC2

CONTENDER

CARDBUSN

PCI_AD7

PC1

IO

IO

IO

IO

IO

IO

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PAGE NOTES

PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE

FW_PC0 - FIREWIRE POWER CLASS IDENTIFIER

PCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_L

CONNECT TO VDD FOR 3.3V OPERATION

PLACE R4032 VERY CLOSE TO SB

THIS IS FROM ICH-8

7/26/2005 - CONNECTED PIN E10 TO GND

5/19/2005 - FIRST REVISION OF PAGE
6/21/2005 - CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)

FW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRS

6/20/2005 - BGA VERSION OF FW323-06 ADDED
6/21/2005 - CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)
6/22/2005 - ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L
6/22/2005 - REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE

INT_PIRQD_L - INTERRUPT TO SB
PCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1)

PCI_RST_L - PCI RESET FROM SB

PCI_REQ3_L - PCI REQUEST TO SB
PM_CLKRUN_L - CLOCK-RUN PCI PROTOCOL

INPUT/OUTPUT

FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS

6/22/2005 - REMOVED C4421 - REDUNDANT

OUTPUT

PAGE HISTORY

NEED TO CHECK CRYSTAL LOAD CAPACITANCE

MODE FOR EXTERNAL LINK

FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS

6/22/2005 - BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE

197S0030 3.2MMX2.5MM

PLACE ONE CAP PER TWO PINS STARTING WITH C4016 ON VDDA0

PLACE ONE CAP PER TWO PINS STARTING WITH C4024 ON VDD0

0.001A DURING SLEEP

MOBILE TURNS OFF CONTROLLER POWER DURING SLEEP

=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP)

=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)

INPUT

6/22/2005 - CHANGED CLK,PME,DIFF PAIR NAMES TO BE RE-USE COMPLIANT

DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)
SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)

SPEC RECOMMENDS 2.49K

MANUFACTURING TEST PINS

6/21/2005 - CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)

PCI_AD<0..31>,PCI_C_BE_L<0..3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,

PCI_GNT3_L - PCI GRANT FROM SB

LOW = PCI OPERATION

LOW = NOT BUS MANAGER

C4016

1

2

10UF

X5R
603

20%

6.3V

R4052

1

2

1%
MF-LF

1/16W

2.1K

402

C4018

1

2

402

20%
10V
CERM

0.1UF

C4029

1

2

402

16V
X5R

10%

0.1UF

C4025

1

2

402

16V

10%
X5R

0.1UF

C4017

1

2

402

16V

10%
X5R

0.1UF

C4020

1

2

402

16V

10%
X5R

0.1UF

R4000

1 2

MF-LF

1/16W

402

390

5%

C4024

1

2

10UF

X5R
603

20%

6.3V

L4000

1 2

600-OHM-300MA

0402

U4000

B1

D1

G12

M5
B6

E10

E12
F13
F12

F10
G10

L11
M12
M11
N12
M10
N11

M4
N5
N4
M3

H10

M2
N3
K4
M1
K2
J4
K1
J2
J1
H2

H12

H4
H1

J13
J12
K13
K10
L12
M13

K12

M9
L3
L1

G2

N8

N6

E1

L2

D2

M6

N10

M8

F2

E2

F1

N9

M7

N7

G13

A4

B7

A6

B4

A3
B3

C2
C1

B9

A9

B11

A11

C12

C11

A10

B10

A12

B12

D12

D13

B8

D8

C13

G4N1N2K5K6K7L13

H13

A2

D10

A13

B13A7A8

D6

A1

B2

G1G6G7G8H6H7H8J5J9

J10

C3

K8

K9

N13

D4E4E5F4F6F7F8

E13

E9D9D7

D5

A5

B5

FW32306

BGA

CRITICAL

R4020

1

2

402

1/16W
MF-LF

5%

510K

R4032

1 2

100

1%

MF-LF

1/16W

402

C4022

1

2

0.1UF

CERM

10V

20%
402

C4026

1

2

402

20%
10V
CERM

0.1UF

C4028

1

2

0.1UF

CERM

10V

20%
402

C4030

1

2

402

20%
10V
CERM

0.1UF

C4032

1

2

0.1UF

CERM

10V

20%
402

R4037

1

2

402

47

5%
MF-LF

1/16W

R4035

1

2

402

47

5%
MF-LF

1/16W

R4034

1

2

402

47

5%
MF-LF

1/16W

R4033

1

2

402

47

5%
MF-LF

1/16W

R4036

1

2

402

47

5%
MF-LF

1/16W

R4031

1

2

402

1/16W
MF-LF

5%

22

Y4003

2 4

1 3

SM-3.2X2.5MM

24.576MHZ

CRITICAL

C4011

1

2

402

50V

CERM

15PF

5%

C4012

1

2

402

50V
CERM

15PF

5%

FIREWIRE CONTROLLER

SYNC_DATE=08/30/2005

01

76

SYNC_MASTER=ENET

37

051-7455

PCI_AD<14>

PCI_AD<12>

PCI_AD<7>

PCI_AD<4>

=PP3V3_S3_PCI

FW_XO_R

FW_B_TPB_N

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

PP3V3_S3_FW_AVDD

FW_C_TPB_N

FW_C_TPB_P

FW_C_TPA_N

FW_C_TPA_P

FW_B_TPA_N
FW_B_TPB_P

FW_B_TPA_P

FW_A_TPB_N

FW_A_TPA_P
FW_A_TPA_N

FW_R0

FW_C_TPBIAS

PCI_AD<19>

PCI_PME_FW_L

INT_PIRQD_L

PCI_CLK33M_FW

PCI_SERR_L

PCI_FW_REQ_L

FW_PCI_RST_L

PCI_RST_L

PCI_AD<31>
PCI_C_BE_L<0>

PCI_C_BE_L<1>
PCI_C_BE_L<2>
PCI_C_BE_L<3>

PCI_PAR
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L

PCI_STOP_L

PCI_DEVSEL_L

PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>

PCI_AD<26>

PCI_AD<25>
PCI_AD<27>

PCI_AD<28>
PCI_AD<29>
PCI_AD<30>

PCI_AD<2>
PCI_AD<3>

PCI_AD<5>

PCI_AD<11>

PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>

FW_A_TPBIAS

FW_A_TPB_P

PCI_AD<0>
PCI_AD<1>

PCI_AD<6>
PCI_AD<8>

PCI_AD<9>
PCI_AD<10>

FW_PCI_IDSEL

PCI_FW_GNT_L
PCI_PERR_L

PM_CLKRUN_L

FW_B_TPBIAS

FW_R1

FW_XO

FW_XI

FW_PWRON_RST_L

FW_PC0

FW_PTEST

PCI_AD<13>

FW_SE

FW_TEST0

FW_SM

FW_TEST1

=PP3V3_S3_FW

46B6

74C3

75B3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

44C5

74D3

74D3

74D3

74D3

74D3

24C5

23A8

29B3

23A6

23B6

74D3

74D3

74D3

74D3

74D3

74D3

23A6

23A6

23A6

23A6

23A6

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

23A6

24C8

74D3

23A8

23B8

23B8

23B8

7A4

8D2

8D2

8D2

8D2

8D2

8D2

8D2

8D2

38B6

38B6

38B6

8D2

23A8

24A5

23A4

29A5

23A4

23A4

23A6

23A8

23B6

23B6

23B6

23B6

23A6

23A4

23A4

23A4

23A4

23A4

23A8

23A8

23A8

23A8

23A8

23A8

23A8

23A8

23A8

23A8

23A8

23B8

23B8

23B8

23B8

23A8

23A8

23A8

23A8

38C6

38B6

23B8

23B8

23B8

23B8

23B8

23B8

23B5

23A4

6C2

8D2

38C8

23B8

7A4

D

SG

D

SG

NC

V-

V+

-

+

NC

IO

IO
IO

IO

IO

OUT

TPO#

TPI

TPO

TPI#

VGND

VP

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Cable Power

Page Notes

"Snapback" & "Late VG" Protection

(TPB-)

(TPB+)

(TPA-)

(TPA+)

1394A
PORT 0

CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A 0.5V DROP

LATE-VG DETECTION CIRCUIT

FireWire Design Guide (FWDG 0.6, 5/14/03)

1394b implementation based on Apple

7/26/05 - UPDATED SIGNAL NAMES FOR FW PORT POWER ENABLE

7/26/05 - SWITCHED TO 514-0124 FOR PRE-PROTO CONNECTOR

6/22/05 - CHANGED DIFF PAIR NAMES TO MATCH REUSE

PAGE HISTORY

OUTPUT:

FW_TPA0_P/N,FW_TPB0_P/N,FW_TPBIAS0 - FIREWIRE DIFF PAIRS

=FWPWR_PWRON - ADDITIONAL POWER CONTROL

INPUT/OUTPUT:

7/26/05 - CHANGED FL4590 TO 1.1A VERSION

7/26/05 - REMOVED R4520 - IT HASN’T BEEN STUFFED FOR MANY PRODUCTS

7/26/05 - CHANGED CONNECTOR PORT NAMING TO PORT0

7/26/05 - UPDATED LATE-VG POWER RAIL CIRCUIT FROM M1

6/22/05 - REMOVED CONSTRAINTS BECAUSE USING ALLEGRO CONST MANAGER
6/22/05 - CONNECTED FW_PC0 FOR SINGLE PORT

7/26/05 - REMOVED ETHERNET LOW-POWER MODE CIRCUIT

1 FOR DUAL PORT

0 FOR SINGLE PORT

5/19/05 - INITIAL REVISION

(PPFW_PORT0_VP)
(GND_FW_PORT0_VGND)

[LATE VG NOTES]

PLACEHOLDER FOR SMALL PACKAGE DIODE

PORT POWER CLASS

machine AC Adapter is plugged

NC

Enables port power whenever

INPUT:

FW_PC0 - POWER CLASS IDENTIFIER (SINGLE PORT - TIE LOW)

or system at run state with battery only

=GND_CHASSIS_FW_PORT0 - CHASSIS GROUND

=PP3V3_S5_FW - DIGITAL POWER

=PPBUS_FW - PORT POWER

514-0456

C4301

1

2

220PF

402

5%
CERM

25V

C4323

1

2

0.01UF

CERM

402

16V

10%

C4355

1

2

CERM-X5R

6.3V

10%

0.33UF

402

R4356

1

2

MF-LF

2.0M

402

1/16W

5%

C4354

1

2

0.1UF

10%
X5R

16V
402

R4352

1

2

1%
1/16W

10K

MF-LF
402

R4351

1

2

1/16W

5%

10K

MF-LF
402

R4354

1 2

200K

1%
1/16W
MF-LF

402

R4353

1

2

80.6K

1/16W

1%
MF-LF

402

C4353

1

2

100PF

CERM

50V

5%
402

D4350

1 3

CRITICAL

MMBZ5227B

SOT23

C4352

1

2

402

0.001UF

50V
CERM

NO STUFF

10%

R4350

1 2

402

1/16W
MF-LF

5%

330

C4300

1

2

CERM-X5R
402

6.3V

10%

0.33UF

Q4392

6

2

1

SOT563

SSM6N15FE

Q4392

3

5

4

SOT563

SSM6N15FE

FL4320

1

2

3

4

5

6

7

8

CRITICAL

SM

TCM2010-100-4P

D4351

1 2

SOD-723

1SS418

U4350

4

6

3

1

5

2

CRITICAL

SC70

TLV7211

CRITICAL

D4391

1

3

5

4

2

HN2D01JEF

SOT665

C4325

1

2

402

16V

CERM

0.01UF

10%

L4310

1 2

FERR-250-OHM

SM

C4310

1

2

10%
CERM

50V

0.001UF

402

D4320

1

2

6

CRITICAL

SOT-363

BAV99DW-X-F

D4321

4

5

3

CRITICAL

BAV99DW-X-F

SOT-363

D4320

4

5

3

CRITICAL

SOT-363

BAV99DW-X-F

D4321

1

2

6

CRITICAL

SOT-363

BAV99DW-X-F

FL4390

1 2

CRITICAL

MINISMDC

1.1A-24V

R4391

1

2

402

3.3K

5%
1/16W
MF-LF

C4390

1

2

402

X7R

25V

10%

0.01UF

R4390

1

2

402

4.7K

5%

MF-LF

1/16W

R4301

1

2

MF-LF
402

56.2

1/16W

1%

R4395

1

2

402

470K

5%
MF-LF

1/16W

R4394

1 2

10K

5%

MF-LF

1/16W

402

R4300

1

2

56.2

1/16W
MF-LF
402

1%

F-RT-TH3

4

6

5

3

2

1

7 8

1394A

CRITICAL

OMIT

J4300

C4320

1

2

0.01UF

CERM

16V
402

10%

Q4390

1

2

5

6

3

4

CRITICAL

SM-LF

FDC638P

C4324

1

2

603-1

50V
X7R

10%

0.01UF

R4304

1

2

4.99K

402

1/16W

1%
MF-LF

D4390

1 2

CRITICAL

SM

CRS08

R4302

1

2

402

56.2

1%
1/16W
MF-LF

R4303

1

2

56.2

1%
1/16W
MF-LF
402

C4322

1

2

0.01UF

402

10%

CERM

16V

C4321

1

2

16V
402

10%

0.01UF

CERM

514-0456

NORMAL

CRITICAL

J4300

CONN,6P 1394A RCPT,MIDPLANE,MG3,LF

1

514-0476

FANCY

CRITICAL

J4300

CONN,6P 1394A RCPT,MIDPLANE,BLACK,LF

1

051-7455

SYNC_DATE=07/17/2006

FIREWIRE PORT

SYNC_MASTER=GPU

7638

01

VOLTAGE=19V

PPFW_SWITCH

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

PPFW_PORT0_VP_F

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

VOLTAGE=16.5V

MIN_LINE_WIDTH=0.5MM

VOLTAGE=16.5V

PPFW_PORT0_VP

MIN_NECK_WIDTH=0.25MM

FW_PORT0_TPA_P_FL
FW_PORT0_TPA_N_FL

=PPBUS_S5_FWPWRSW

FWPWR_EN_L

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.15MM

FWLATEVG_3V_REF

PP2V4_FWLATEVG

PP2V4_FWLATEVG_RC

FW_A_TPB_N

FW_PORTPWR_EN

FW_A_TPA_P
FW_A_TPA_N
FW_A_TPB_P

FW_PORT0_TPB

FW_PORT0_TPA_N

FWPWR_EN_AND

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.35MM

VOLTAGE=3.3V

PP2V4_FWLATEVG

=PP3V3_S5_FWLATEVG

FW_PC0

FW_PORTPWR_EN

=GND_CHASSIS_FW_UPPER

=GND_CHASSIS_FW_DOWN

FW_PORT0_TPB_N_FL

LATEVG_EVENT_L

FW_PORT0_TPB_P_FL

FW_PORT0_TPB_N

SMC_ADAPTER_EN

FWPWR_ACIN

FWPWR_EN

=PP3V3_S0_FW

FW_PORT0_TPB_P

FW_PORT0_TPA_P

FW_A_TPBIAS

=PP3V3_S5_FWLATEVG

FWPWR_EN_L_DIV

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.15MM

PPBUS_S5_FWPWRSW_F

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=18.5V

57C4

45B3 44D5 35C7

38A6

37A3

33C7

38A8

6B2

7B1

38A7

37B3

38C5

37B3

37B3

37B3

38C5

7D1

38A4

8A6

8C8

6C1

7D4

37B3

7D1

OUT

OUT

OUT

D

SG

D

SG

Y

B

A

SGD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ICH8 GPIO54

ODD_PWR_EN_L is OD and core well

ODD detect need less than 100ms include OS latency

This signal has integrated series resistor and pull down in ICH8M

NC

PER ATA7 SPEC

NC

NC

NC

NC

NC

Indicates disk presence, to SMC

NC

NCNC

Per ATA Spec

CORE RAIL 5V

ICH8 GPIO5

on SB page.

both pull up resistors

BLEED CIRCUIT TO DISCHARGE ODD POWER RAIL WHEN ODD IS DISABLED.

516S0339

PER ATA SPEC

R4451

1

2

4.7K

1/16W

5%
MF-LF

402

C4404

1

2

5%

CERM

50V
402

10PF

NOSTUFF

R4459

1

2

402

1/16W

5%

6.2K

MF-LF

R4458

1

2

0

5%
MF-LF

1/16W
402

R4424

1

2

10K

NOSTUFF

402

MF-LF

5%

1/16W

R4453

1

2

33K

5%
MF-LF

1/16W
402

C4476

1 2

402

X5R

16V

10%

0.1UF

NOSTUFF

R4465

1

2

MF-LF

5%

6.2K

1/16W
402

R4476

1

2

MF-LF

1/16W
402

5%

10K

J4401

51

52

1

10

1112
1314
1516
1718
19

2

20

2122
2324
2526
2728
29

3

30

3132
3334
3536
3738
39

4

40

4142
4344
4546
4748
49

5

50

6

78
9

CRITICAL

M-ST-SM

5-1775184-0

C4475

1

2

10%
CERM-X5R

402

0.47UF

6.3V

R4425

1 2

5%
1/16W
MF-LF

10K

402

Q4475

6

2

1

SSM6N15FE

SOT563

Q4475

3

5

4

SOT563

SSM6N15FE

R4420

1

2

1/16W

5%
MF-LF

402

100K

R4477

1 2

1/16W

5%

330

402

MF-LF

R4401

1 2

1/16W
MF-LF

402

5%

0

ODD_PWR_CORE

R4402

1 2

ODD_PWR_RESUME

0

1/16W

402

MF-LF

5%

R4460

1

2

402

MF-LF

5%
1/16W

100K

U4401

3

2

1

4

5

SC70

MC74VHC1G09

CRITICAL

Q4410

1

2

5

6

3

4

CRITICAL

FDC606P

SOT-6

Q4420

2

6

1

MMDT3904XF

SOT-363-LF

R4461

1 2

402

24.9K

1%
1/16W
MF-LF

R4462

1

2

1/16W

5%
MF-LF

4.7

402

C4477

1

2

10%
X5R

16V

0.1UF

402

051-7455

PATA CONNECTOR

7639

01

ODD_PWR_EN_L_B

=PP3V3_S0_SB

IDE_PDD<14>
IDE_PDD<15>

SMC_ODD_DETECT

IDE_PDCS3_L

IDE_PDDACK_L

IDE_PDD<12>

=PP3V3_S0_PATA

IDE_PDA<2>

IDE_CSEL_PD

IDE_PDD<8>

IDE_PDCS1_L

IDE_PDA<0>

IDE_PDA<1>

IDE_PDIOW_L

IDE_PDD<0> IDE_PDDREQ

IDE_PDIOR_L

IDE_PDD<13>

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.35MM

VOLTAGE=5V

PP5V_S0_IDE_PATA

IDE_PDD<3>

IDE_PDD<1>

IDE_PDIORDY

SB_GPIO40

ODD_PWR_EN_SLOW_START

ODD_PWR_EN_L

=PP5V_S0_IDE_RESET

ODD_RST_5VTOL_L

ODD_RST_BUF_L

ODD_PWR_EN_L_R

=PP5V_S0_IDE_PATA

ODD_POWER_DISCHARGE

ODD_PWR_EN_SLOW_START_L

IDE_PDD<2>

IDE_PDD<4>

IDE_PDD<5>

IDE_PDD<6>

IDE_PDD<7>

IDE_PDD<11>

IDE_PDD<10>

IDE_PDD<9>

IDE_IRQ14

ODD_PWR_EN_SLOW_START_L_R

=PP5V_S5_PATA

ODD_PWR_EN_SLOW_START_R

ODD_RST_BUF_L

=PP5V_S0_IDE_PATA

ODD_PWR_EN_L_R

26D8

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3 73D3

73D3

73D3

23A6

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

73D3

7D4

22B4

22B4

22B4

22B4

22B4

7D4

22B4

22B4

22B4

22B4

22B4

22B4

22C4

22A4

22B4

22B4 22B4

22C4

22A4

23C8

23A4

7A7

23B6

39C5

39C7

39C4

22B4

22B4

22B4

22B4

22B4

22B4

22B4

22B4

22B4

7C1

39A7

39A5

39A6

OUT

IN

OUT

OUT

IN

OUT

SYM_VER-1

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SATA CONNECTOR

518S0390

NC

PLACE L4502 NEAR SB

PLACE R4522 AND C4522 NEAR J4501

SATA DIFF PAIR GND VIAS

(TO IR RECEIVER)

NC
NC
NC

PLACE L4501 NEAR J4501

PLACE R4550 AND C4550 NEAR J4501

SYSTEM (SLEEP) LED FILTER

VALUE=3900PF IN REFERENCE SCHEM

PLACE NEAR ICH8 PIN

CAPS TO BE SAME DISTANCE

FROM SB WITHIN EACH PAIR

GV4508

1

HOLE-VIA-P5RP25

GV4506

1

HOLE-VIA-P5RP25

GV4501

1

HOLE-VIA-P5RP25

GV4503

1

HOLE-VIA-P5RP25

GV4505

1

HOLE-VIA-P5RP25

GV4507

1

HOLE-VIA-P5RP25

GV4502

1

HOLE-VIA-P5RP25

GV4504

1

HOLE-VIA-P5RP25

0

R4501

1

2

402

MF-LF

1/16W

1%

24.9

0

L4501

1

2 3

4

CRITICAL

1210-4SM1

90-OHM-100MA

C4522

1

2

16V
CERM
402

0.01UF

10%

R4550

1 2

402

100

5%

MF-LF

1/16W

C4550

1

2

4.7UF

20%

6.3V
CERM
603

L4502

1

2 3

4

CRITICAL

1210-4SM1

90-OHM-100MA

C4500

1 2

402

0.0047UF

R4522

1 2

402

1/16W
MF-LF

5%

10

C4502

1 2

402

0.0047UF

C4501

1 2

0.0047UF

402

C4503

1 2

402

0.0047UF

C4521

1

2

NOSTUFF

603

X5R

6.3V

20%

10UF

C4520

1

2

NOSTUFF

0.1UF

X5R
402

16V

10%

J4501

20

21

1

10
11
12
13
14
15
16
17
18
19

2
3
4
5
6
7
8
9

20247-019E

CRITICAL

F-ST-SM

40 76

01

SATA CONNECTOR

051-7455

GND_CHASSIS_SATA

PP5V_S3_SYSLED_F

SYS_LED_ANODE_L

IR_RX_OUT

SATA_A_D2R_C_P

SATA_A_R2D_N

SATA_A_D2R_C_N

SATA_A_R2D_P

=PP5V_S0_SATA

SATA_A_D2R_F_P

SATA_A_R2D_F_P

SATA_A_D2R_P

SATA_A_D2R_N

SYS_LED_ANODE

SATA_RBIAS_PN

MAKE_BASE=TRUE

SATA_RBIAS_P

SATA_RBIAS_N

SATA_A_R2D_F_N

=PP5V_S3_SYSLED

SATA_A_R2D_C_P

SATA_A_R2D_C_N

SATA_A_D2R_F_N

73D3

73D3

45A3

22A6

22B6

45A4

73D3

73D3

8C7

43C8

73D3

73D3

73D3

73D3

7A7

22B6

22B6

6B2

7A4

22B6

22B6

SYM_VER-1

SYM_VER-1

GND

D+

D-

VBUS

GND

D+

D-

VBUS

EN1*

OC1*

IN

OUT1

GND

TPAD

OUT2

OC2*

EN2*

OE* SEL

GND

D+A

D-B

D+

VCC

D-A

D+B

D-

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

USB 2.0 CONNECTORS

SEL=1 CHOOSE USB

ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS

PLACE L4600 NEAR J4600

SEL=0 CHOOSE SMC

ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS

L4601 Monitor SMT for tombstone

LAYOUT NOTE:C4606,C4607 ARE EMC BY-PASS CAPS FOR J4601

LAYOUT NOTE:C4602,C4603 ARE EMC BY-PASS CAPS FOR J4600

PLACE L4601 NEAR J4601

L4600 Monitor SMT for tombstone

PLACE C4675 NEAR U4675

514-0457

514-0457

41

L4601

90-OHM-100MA

TCM1005

CRITICAL

2 3

2

1

C4603

0.01UF

10%
CERM

16V
402

10%

2

1

C4602

0.01UF

CERM

16V
402

4

3

CRITICAL

L4600

90-OHM-100MA

TCM1005

1

2

3
4

2

6

1

5

F-RT-TH

USB-M71-MG3

CRITICAL

J4600

OMIT

3
4

2

6

1

5

F-RT-TH

USB-M71-MG3

OMIT

CRITICAL

J4601

2

1

6.3V

100UF

20%
POLY

B2

C4611

2

1

100UF

CRITICAL

6.3V

20%
B2

2

1

X5R

20%

603

10uF

C4613

6.3V

20%

1

402

CERM

10V

0.1UF

C4612

2

21

L4602

0402-LF

FERR-120-OHM-1.5A

21

L4604

0402-LF

FERR-120-OHM-1.5A

21

L4603

0402-LF

FERR-120-OHM-1.5A

21

L4605

FERR-120-OHM-1.5A

0402-LF

R4650

21

EXTAUSB_OC_F_L

1/16W
MF-LF

5%

1K

402

21

R4651

1K

5%
1/16W
MF-LF

402

EXTBUSB_OC_F_L

2

1

C4650

402

CERM-X5R

6.3V

10%

0.47UF

2

1

C4651

10%
402

6.3V
CERM-X5R

0.47UF

3

D4600

2

1

CRITICAL

RCLAMP0502B

SC-75

2

1

3

CRITICAL

SC-75

D4601

RCLAMP0502B

C4675

21

0.1UF

CERM

20%
10V

402

402

2

1

R4677

MF-LF

10K

1/16W

5%

2

1

C4606

0.01UF

10%
CERM

16V
402

2

1

C4607

402

16V
CERM

10%

0.01UF

9

6

7

5

8

2

1

4

3

TPS2060

MSOP

U4600

CRITICAL

PI3USB10LP

U4675

TQFN

CRITICAL

5

7

3

1

2

4

8

10

9

6

0

R4670

1/16W

NOSTUFF

21

5%

MF-LF

402

NOSTUFF

2

0

R4671

5%
1/16W
MF-LF

402

1

CONN,4P USB RCPT,MIDPLANE,MG3,LF

J4600,J4601

NORMAL

CRITICAL

2

514-0457

FANCY

CRITICAL

J4600,J4601

CONN,4P USB RCPT,MIDPLANE,BLACK,LF

2

514-0477

41

SYNC_MASTER=USB

USB EXTERNAL CONNECTORS

SYNC_DATE=06/30/2006

01

76

051-7455

=PP5V_S5_USB

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

PP5V_S3_USB2_EXTA

PP5V_S3_USB2_EXTB

VOLTAGE=5V

PM_SLP_S4_LS5V

SMC_RX_L
SMC_TX_L

=USB2_EXTA_P

USB2_MUXED_EXTA_N

USB2_MUXED_EXTA_P

USB2_EXTB_F_N

=USB2_EXTB_N

USB2_MUXED_EXTA_P

=USB2_EXTA_N

=GND_CHASSIS_USB

PP5V_S3_USB2_EXTB_F

PP5V_S3_USB2_EXTB_F

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=5V

USB2_EXTB_F_P

=PP3V42_G3H_SMCUSBMUX

=EXTBUSB_OC_L

=EXTAUSB_OC_L

=GND_CHASSIS_USB

=GND_CHASSIS_USB

PP5V_S3_USB2_EXTA_F

PP5V_S3_USB2_EXTA_F

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=5V

=GND_CHASSIS_USB

=USB2_EXTB_P

USB2_GND_EXTA_F

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.6MM
VOLTAGE=0V

USB2_GND_EXTB_F

MIN_NECK_WIDTH=0.3MM
VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

USB2_EXTA_F_N
USB2_EXTA_F_P

USB2_MUXED_EXTA_N

USB_DEBUGPRT_EN_L

MIN_LINE_WIDTH=0.6MM

POLY

CRITICAL

C4610

OMIT

OMIT

46B4

46B6

45D5

45D5

41C2

41C4

41C4

41C4

44C5

44C5

41A4

41C2

41A4

41C2

44B8

44B8

41A2

41A2

41A2

41A4

7C1

65B6

6C2

6C2

8C2

41C5

41C5

8B2

8C2

8C8

41C3

41B2

7B1

8B2

8C2

8C8

8C8

41D3

41D2

8C8

8B2

41A5

44B8

41A5

OUT

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

GEYSER AND DIMM0 REMOTE TEMP SENSORS

PLACE L4701 NEAR J4700

PLACE C4700 NEAR J4700

516S0588

R4710

1 2

402

MF-LF

1/16W

1K

5%

C4710

1

2

402

CERM

10V

0.1UF

20%

C4700

1

2

402

0.1UF

10V

20%
CERM

D4700

3

1

2

CRITICAL

RCLAMP0502B

SC-75

L4700

1 2

600-OHM-300MA

0402

L4702

1 2

600-OHM-300MA

0402

J4700

1

10

2

3

4

5

6

7

8

9

F-ST-SM

CRITICAL

53307-1039

L4703

1 2

600-OHM-300MA

0402

C4703

1

2

402

16V
CERM

0.01uF

10%

L4701

1

2 3

4

CRITICAL

90-OHM-100MA

TCM1005

CONNECTOR MISC

76

01

SYNC_DATE=06/29/2006

SYNC_MASTER=USB

42

051-7455

VOLTAGE=5V
MIN_NECK_WIDTH=0.3MM

PP5V_S3_GEYSER_F

MIN_LINE_WIDTH=0.6MM

GEYSER_GND_F

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
VOLTAGE=0V

=USB2_GEYSER_P

=USB2_GEYSER_N

CONN_GEYSER_ONOFF_L

=PP5V_S3_GEYSER

SMC_LID_LC

SMC_LID

MAKE_BASE=TRUE

SMC_ONOFF_L

CONN_GEYSER_USB_P

CONN_GEYSER_USB_N

CONN_GEYSER_ONOFF_FLTR_L

57A8

45D5

45C5

45C8

44B5

44C5

8C2

8C2

7A4

6B2

SYM_VER-1

SYM_VER-1

P0_3/INT1
P0_4/INT2
P0_5/TIO0
P0_6/TIO1
P0_7

P0_2/INT0

P0_1

THRM_PAD

NC

P1_7

P1_6/MISO

P1_5/SMOSI

P1_4/SCLK

P3_1

P3_0

P1_3/SSEL

P1_2/VREG

VDD

P1_1/D-

P1_0/D+

VSS

NC

P2_1

P2_0

P0_0

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0521

SB HAS INTERNAL 15K PULL-DOWNS

TO M13D SLOT

IR CYPRESS ENCORE II USB CONTROLLER

PLACE C4800 AND C4801

NEAR U4800 PIN 16

PLACE L4810 NEAR J4800

PLACE L4800 NEAR J4800

3G CONNECTOR

BLUETOOTH

PLACE L4811 NEAR J4800

PLACE C4810 C4811 NEAR L4810

C4803 CLOSE TO U4800 PIN 2

C4811

1

2

0.1UF

20%
10V
CERM
402

L4812

1

2 3

4

90-OHM-100MA

CRITICAL

TCM1005

C4810

1

2

603

10UF

X5R

20%

6.3V

L4810

1 2

120-OHM-0.3A-EMI

0402-LF

L4811

1 2

120-OHM-0.3A-EMI

0402-LF

C4803

1

2

0.001UF

50V
CERM

10%
402

R4800

1 2

402

1/16W

100

MF-LF

5%

J4850

1

10

11

12

13

14

2
3
4
5
6
7
8
9

LVC-D10SFYG

F-RT-SM

CRITICAL

NOSTUFF

L4855

1

23

4

90-OHM-100MA

CRITICAL

TCM1005

NOSTUFF

U4800

10
11
12
17
19

27
28
29
30
31

7
6
5
4
3
2
1

32

14
15
18
20
23
24
25
26

9
8

21
22

33

16

13

OMIT

CRITICAL

CY7C63833

QFN

C4800

1

2

1UF

10V

10%
X5R

402

C4801

1

2

402

0.1UF

20%
10V
CERM

L4854

1 2

FERR-120-OHM-1.5A

NOSTUFF

0402

L4853

1 2

FERR-220-OHM-2A

0603

NOSTUFF

L4852

1 2

FERR-220-OHM-2A

0603

NOSTUFF

C4850

1

2

10%

0.01UF

50V
402

X7R

NOSTUFF

C4851

1

2

402

0.01UF

X7R

10%
50V

NOSTUFF

J4810

5

6

1
2
3
4

M-RT-SM

78171-0004

CRITICAL

C4802

1

2

10%
CERM

50V

0.001UF

402

C4852

1

2

NOSTUFF

402

X7R

10%
50V

0.01UF

R4801

1 2

5%

MF-LF

1/16W

402

0

R4802

1 2

0

402

1/16W
MF-LF

5%

C4804

1

2

402

X5R

10%
10V

1UF

R4803

1 2

5%

MF-LF

1/16W

402

0

IR CONTROLLER & BT INTERFACE

01

43 76

051-7455

=PP5V_S3_IR

PP5V_S3_IR_R

TP_IR_P00

TP_IR_P01

TP_IR_P03
TP_IR_P04

USB2_IR_N_R

=USB2_IR_P

USB2_IR_P_R

=USB2_IR_N

ENCORE_VREG_C

IR_RX_OUT_RC

TP_IR_P02

USB2_BT_F_N
USB2_BT_F_P

MIN_LINE_WIDTH=0.2MM
VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

GND_BT_F

=USB2_BT_N

=USB2_BT_P

=GND_CHASSIS_3GPOWER

=PP3V3_S3_BT

IR_RX_OUT

MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2MM

PP3V3_S3_BT_F

USB2_3G_F_N

USB2_3G_F_P

PP5V0_S0_3G_F

GND_CHASSIS_3G_CONN

=GND_CHASSIS_3GPOWER

GND_3G_F

=USB2_3G_N

=USB2_3G_P

=PP5V_S0_3G

43B5

43A5

7A4

8C2

8C2

6C1

6C1

6A2

8B2

8C2

8D8

7A4

40C6

6A2

6C1

6C1

8D8

8C2

8C2

7A7

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN
IN
IN
IN
IN
IN
IN
IN

IN

IN

OUT

IN

OUT

OUT

P16

P51

P50

P42/SDA1

P97/IRQ15*/SDA0

P95/IRQ14*

P94/IRQ13*

P93/IRQ12*

P92/IRQ0*

P91/IRQ1*

P86/IRQ5*/SCK1/SCL1

P83/LPCPD*

P82/CLKRUN*

P80/PME*

P35/LRESET*

P34/LFRAME*

P10

P12
P13
P14
P15

P17

P31/LAD1

P30/LAD0

P32/LAD2
P33/LAD3

P36/LCLK
P37/SERIRQ

P44/TMO1

P77/AN7

P76/AN6

P81/GA20

P96/EXCL

P11

P47/PWX1/PWM1

P45
P46/PWX0/PWM0

P40/TMIO

P43/TMI1/EXSCK1

P27

P26

P25

P24

P23

P22

P21

P20

P41/TMO0

P52/SCL0

P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*

P65/KIN5*
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*

P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5

P84/IRQ3*/TXD1
P85/IRQ4*/RXD1

P90/IRQ2*

(1 OF 4)

PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD

PA5/KIN13*/PS2BD

PA4/KIN12*/PS2BC

PB2
PB3
PB4

PE0

PG6/EXIRQ14*/EXSDAB

PG5/EXIRQ13*/EXSCLA

PH1/EXIRQ7*

PH0/EXIRQ6*

PG7/EXIRQ15*/EXSCLB

PG4/EXIRQ12*/EXSDAA

PH3/EXEXCL

PH2/FWE

PB5

PF4/PWM4

PF2/IRQ10*/TMOY

PG2/EXIRQ10*/SDA2

PG0/EXIRQ8*/TMIX

PF7/PWM7

PC3/TIOCD0/TCLKB/WUE11*

PH5

PB7

PB6

PH4

PF5/PWM5
PF6/PWM6

PG1/EXIRQ9*/TMIY

PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD

PD0/AN8
PD1/AN9
PD2/AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15

PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3

PB0/LSMI*
PB1/LSCI

PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*

PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*

PG3/EXIRQ11*/SCL2

PF3/IRQ11*/TMOX

PA1/KIN9*/PA2DD

PA0/KIN8*/PA2DC

PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS

(2 OF 4)

VCL

AVREF

VCC

VCC

VCC

AVCC

XTAL
EXTAL

AVCC

VCC

MD1
MD2

NMI

RES*

ETRST*

AVREF

AVSS

VSS

(3 OF 4)

NC22

NC21

NC20

NC19

NC18

NC17

NC16

NC15

NC14

NC13

NC12

NC9

NC6

NC11

NC10

NC8

NC7

NC5

NC4

NC3

NC2

NC1

NC0

(4 OF 4)

OUT
OUT

BI

IN

IN

OUT

BI

BI

OUT

OUT

IN

IN

OUT

OUT

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN

IN
IN

IN

IN

IN
IN

IN

IN

IN

IN

OUT

IN

IN

OUT
OUT
OUT
OUT

BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

OUT
OUT

BI

BI

OUT

IN

OUT

OUT

OUT

IN

BI
BI
BI
BI

IN
IN
IN

OUT

BI

IN
IN
IN
IN

BI

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC
NC
NC
NC
NC

NC
NC
NC

NC

NC

NC

NC

NC

NC
NC

NC

NC

NC

NC
NC

(OC)

(OC)

(OC)

(OC)

(OC)

(DEBUG_SW_1)
(DEBUG_SW_2)

(OC)

(OC)

(OC)
(OC)

(OC)

(OC)

(OC)

(OC)

(DEBUG_SW_3)

pins designed as outputs can be left floating,

(OC)

NC

NC

NC

If SMS interrupt is not used, pull up to SMC rail.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

(OC)

those designated as inputs require pull-ups.

NOTE: Unused pins have "SMC_Pxx" names. Unused

(OC)

C4902

1

2

805

CERM

22UF

20%

6.3V

6C2

24D5 46B4

6C2

45D7 46B4

42C8 45C8 45D5

C4907

1

2

CERM-X5R

0.47UF

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

10%

402

6.3V

C4903

1

2

CERM

10V

0.1UF

402

20%

C4920

1

2

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

CERM

10V

0.1UF

402

20%

R4999

1 2

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

MF-LF

5%

1/16W

4.7

402

C4904

1

2

CERM

10V

0.1UF

402

20%

XW4900

1

2

SM

24C3

59C7

C4905

1

2

CERM

10V

0.1UF

402

20%

24C2

45D5 63B4 63B5

6B2

27A5 58A3

44A4

C4906

1

2

CERM

10V

0.1UF

402

20%

48C1 59C7

6B2

48B1

44A4

44A4

66C2

48D6

66B1

45B3

6D1

45C5 57A2

6C1

45B6 57C3 57C7 66A6

6C2

41A8 44C5 45D5 46B6

6C2

41A8 44C5 45D5 46B4

6C1

33C7 35C7 38C6 45B3 57C4

65C6

U4900

B12

C13
A15

B14

B15
C14

D12

C15

D13

D14

D15
E12

E14

E15
E13

F14

D9

C9
A9

B9
D8

C8

A8
D7

A5

B5

D5
C3

B1
C2

D3

C1

G1
G4

F2

L13

L14
L15

K12

K13
K14

J12

J13

N12

R13

P13
R14

P14

R15
N13

P15

C7

A7
B7

D6
C6

A6

B6

K4
J2

J1

J3
J4

H2
H1

G2

BGA

SMC_H8S2116

OMIT

U4900

R3

P3

R2
N3

R1

N2
M4

N1

B10

A10
D10

A11
B11

C11

A12
D11

G14

G15

G13
G12

H14
H15

H13

H12

M11
P11

R11

N11
P10

R10

N10
M10

M3

M2

M1
L4

L2

M7

P6
R6

N6

M6
R5

P5
N5

P9

R9

N9
P8

R8

M8
P7

R7

E1
F3

K2

C4
D4

B3

OMIT

BGA

SMC_H8S2116

U4900

N14

N15

M14

M15

P12

R12

L1

B2

E2
K1

F4

E3

P2P1J15A1F1

D1P4R4

F12

F13

B13

A13

A4B4D2

A2

SMC_H8S2116

OMIT

BGA

U4900

G3

H3

K15

J14

F15

A14
C12

C10

C5
A3

B8

E4

K3

H4

M9
N8

L3

N4
M5

N7

M12
M13

L12

BGA

SMC_H8S2116

OMIT

6C1

45B6 66A3

6C1

45B6 66A4

47B3

R4909

1

2

1/16W

5%

MF-LF

10K

402

6C2

46B4

6C2

46B6

R4901

1

2

1/16W

5%

10K

402

MF-LF

R4902

1

2

10K

MF-LF

5%
1/16W

402

R4903

1

2

1/16W

5%

MF-LF

0

NO STUFF

402

R4998

1

2

1/16W

5%

MF-LF

10K

402

41A5

6C1

45D5 57C8

8B2

15B7

24A5 24C3

48A8

39B2

45C3

44B4

24C8

45D5

44B4

6D2

50B4

44B4

44B4

6A7

44A4

44B4

6D2

50C4

44B4

51C2

51C2

61C5

51C2

44A4

44A4

62C2

6C2

45C5 46B4

45B3

6C2

45C5 46B4

6C2

45C5 46B6

6C2

45C5 46B6

6B2

42C3 45C5 57A8

6C1

66A8

44A4

66B8

44A4

47C3

47C3

47D3

47D3

47C6

47C6

45B6

45B5

44B4

51C7

45C6

6C2

41A8 44B8 45D5 46B4

6C2

41A8 44B8 45D5 46B6

45C5

51A8

45D5

44A4

45A6

6C2

24C8 46B4

8B2

15B7

24D5 27C5

6C2

46B6

24C8

6C2

24C8 37A5 46B6

24C2

45C5

6D2

22D4 46C6

6D2

22D4 46C6

6C2

22D4 46C4

6C2

22D4 46C4

6C2

22D4 46B6

27C1

29A3 29A5 75B3

44B4

47D6

24D3 33C7 35C7 45A6 58B7 62B8

24D3 33B7 65A6 65C4

24D3 45C3

45A7

47D6

47B3

45D1

SYNC_DATE=10/30/2006

SYNC_MASTER=T9_MLB

SMC

44 76

01

051-7455

PP3V3_S5_AVREF_SMC
=PP3V42_G3H_SMC

GND_SMC_AVSS

SMC_RESET_L

SMC_P67

NC_SMC_P20

MAKE_BASE=TRUE

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_P14

NC_SMC_P22

MAKE_BASE=TRUE

NC_SMC_P23

MAKE_BASE=TRUE

NC_SMC_P21

MAKE_BASE=TRUE

SMC_P14

SMC_WAKE_SCI_L

SMC_BATT_ISENSE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_P23
SMC_P26

SMC_P22

SMC_P21

SMC_SUS_CLK

SMC_BS_ALRT_L

NC_SMC_P43

MAKE_BASE=TRUE

NC_SMC_P64

MAKE_BASE=TRUE

SMC_GPU_VSENSE

SMC_P81

SMC_P64

SMC_P43

SMC_PF1

ALS_GAIN
SMC_EXCARD_PWR_EN

NC_SMC_FAN_0_CTL

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_2_TACH

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NC_SMC_PF0

MAKE_BASE=TRUE

NC_ALS_RIGHT

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

NC_ALS_LEFT

MAKE_BASE=TRUE

SMC_EXTAL

SMC_XTAL

SMC_TRST_L

SMC_KBC_MDE

SMC_NMI

SMC_MD1

MIN_NECK_WIDTH=0.20 MM

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM

SMC_VCL

SMC_RX_L

SMC_NB_1V25_ISENSE

SMC_CPU_VSENSE

SMC_P64

SMC_PROCHOT_3_3_L

PM_LAN_ENABLE

SMC_P22

PM_SYSRST_L

SMC_FAN_1_TACH

SMC_FAN_0_TACH

SMC_FAN_3_CTL

SMC_FAN_2_CTL

SMC_GFX_OVERTEMP_L

SMC_EXCARD_OC_L

ISENSE_CAL_EN

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

SMC_EXCARD_CP
SMC_EXCARD_PWR_EN

SMC_PB0

SYS_ONEWIRE
PM_BATLOW_L

SMB_0_S0_DATA

PM_S4_STATE_L

SMC_CPU_ISENSE

SMC_PM_G2_EN

SMC_PA1

PM_EXTTS_L<0>

SMC_P23

SMC_P26

RSMRST_PWRGD

SMC_RSTGATE_L
ALL_SYS_PWRGD

SMC_BATT_TRICKLE_EN_L

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>

SMC_LRESET_L
PCI_CLK33M_SMC
INT_SERIRQ

SMC_P44

USB_DEBUGPRT_EN_L

PM_EXTTS_L<1>

SMC_FAN_0_CTL

SMC_FAN_3_TACH

SMS_X_AXIS

SMC_NB_CORE_ISENSE
SMC_NB_1V8_ISENSE
ALS_LEFT
ALS_RIGHT

PM_RSMRST_L

SMC_P21

IMVP_VR_ON

SMC_FAN_1_CTL

SMC_ANALOG_ID

SMS_Z_AXIS

SMS_Y_AXIS

SMC_FAN_2_TACH

PM_SLP_S3_L

SMC_TCK

PM_CLKRUN_L
PM_SUS_STAT_L

SMC_ONOFF_L

PM_SLP_S5_L

SMC_TX_L

SMC_P81

SMB_MGMT_CLK

SMC_SYS_LED

SMC_P45

SMC_GFX_THROTTLE_L

PM_LAN_PWRGD

SMC_P14

SMC_GPU_ISENSE

SMC_ADAPTER_EN
SMC_P62
SMC_P63

SMC_P46

SMC_P20

SMC_PF1

SMC_TMS

NC_SMC_FAN_0_TACH

MAKE_BASE=TRUE

SMC_FAN_0_TACH

NC_SMC_PF1

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_BATT_VSET

ALS_LEFT

SMC_P20

SMC_TDI

LPC_FRAME_L

SMB_MGMT_DATA

SMC_BC_ACOK

SMC_TDO

SMC_PF0

SMC_LID
SMC_PF3
SMC_BATT_ISET

SMC_PA0

SMB_0_S0_CLK

SMC_RX_L

SMC_TX_L

SMC_P46

SMS_ONOFF_L

SMC_P63

SMC_P62

SMC_P44

MAKE_BASE=TRUE

NC_SMC_P44

MAKE_BASE=TRUE

NC_SMC_P27

MAKE_BASE=TRUE

NC_SMC_P63

SMC_FAN_0_CTL

NC_SMC_P46

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_P26

MAKE_BASE=TRUE

NC_SMC_P62

MAKE_BASE=TRUE

NC_SMC_P81

NC_SMC_SYS_KBDLED

MAKE_BASE=TRUE

NC_SMC_EXCARD_PWR_EN

MAKE_BASE=TRUE

NC_ALS_GAIN

MAKE_BASE=TRUE

SMC_SYS_KBDLED

SMC_P27

MAKE_BASE=TRUE

NC_SMC_RSTGATE_L

MAKE_BASE=TRUE

NC_SMC_SYS_VSET

SMC_PH4

ALS_GAIN

SMC_PF0

SMC_FAN_3_CTL

SMC_GFX_THROTTLE_L

SMC_GPU1_VSENSE

SMC_SYS_VSET

SMC_BATT_VSET

SMC_FAN_3_TACH

SMC_FAN_2_CTL

SMC_FAN_2_TACH

ALS_RIGHT

SMC_RSTGATE_L

SMC_CASE_OPEN

SMC_SYS_KBDLED

SMC_P43

SMC_P27

SMC_BATT_CHG_EN

PM_PWRBTN_L

SMC_BATT_VSET
SMC_SYS_ISET
SMC_SYS_VSET

SMC_PG0

SMB_B_S0_DATA

SMC_P45

SMC_ENRGYSTR_LDO_EN

MAKE_BASE=TRUE

SMC_ENRGYSTR_LDO_PGOOD

MAKE_BASE=TRUE

SMC_GPU1_ISENSE

SMC_GPU_ISENSE

MAKE_BASE=TRUE

SMC_GPU_VSENSE

MAKE_BASE=TRUE

SMC_PH4

SMC_FWE

SMC_THRMTRIP

SMC_PROCHOT

SMB_B_S0_CLK

SMB_A_S3_CLK

SMB_A_S3_DATA

SMB_BSA_CLK

SMB_BSA_DATA

SMC_SMS_INT

66C2 66B1 62C2 61C5 60B2

51B8

48C6

45D8

48C1

45D4

48B1

45C1

48A1

44A8

66C1

60C7

45C6

7C1

45B6

45C5

44D8

44C8

44C8

44C8

44C8

44C5

44D5

44C8

44B5

44A5

44B8

45C7

45C7

44B4

44B4

45C5

45C5

44B4

44B4

44B4

44B4

44B4

44A4

44B4

44B4

44B4

44B8

44C8

44B4

44A8

44A8

44B4

44A4

45C1

45C5

44B4

44D5

44D5

44C8

44A8

44B8

44C8

44A4

44B5

44A8

44C8

48B1

44B5

44B5

6A7

44A8

44A8

44A8

44D8

44B4

44B4

45C5

44C8

66D3

45C5

60B2

44C5

44C5

44A5

D

SG

IN

D

SG

OUT

D

SG

IN

D

SG

OUT

NC

CD

GND

OUT

VDD

OUT

GND

VIN

VOUT

OUT

TABLE_ALT_ITEM

TABLE_5_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_5_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

SYSTEM (SLEEP) LED CURRENT DRIVER

3.3V TO PBUS LEVEL SHIFTING

NC

R5011 CLOSE TO SB

0.0094A NORMAL

Silk: "SMC RST"

SMS_INT_L

0.007A FANCY

SMC_CPU_RESET_3_3_L

ENABLE VSENSE IN S0 ONLY

Silk: "PWR BTN"

SMC AVREF Supply

RC FILTERED AT SATA CONN

SMC_TPM_RESET_L

SMC 1.05V to 3.3V Level Shifting

THESE NEED TO BE PULLED TO THE PROPER RAIL:

Is this the best part to use?

SMS_INT_L

SMC 3.3V to 1.05V Level Shifting

SMC Reset Button / Brownout Detect

Debug Power Button

SMC Crystal Circuit

MF-LF

10K

5%
1/16W

402

2

1

R5076

10K

21

R5053

CERM

5%

15PF

50V
402

21

C5021

10K

21

R5085
R5086

10K

21

R5087

10K

21

R5048

2

10K

1

100K

21

R5094

R5030

10K

21

10K

21

R5080

10K

21

R5054

10K

21

R5055

10K

21

R5028

10K

21

R5024

100K

21

R5081

10K

21

R5047

10K

21

R5096

10K

21

R5097

2.0K

21

R5082

R5073

100K

21

SOT-363

MMDT3906XF

4

3

5

Q5050

402

1/16W

1%
MF-LF

3.74K

21

R5052

402

MF-LF

1%
1/16W

357

2

1

R5051

SOT-363

MMDT3906XF

1

6

2

Q5050

470K

21

R5083

CRITICAL

20.00MHZ

5X3.2-SM

21

Y5020

10K

1 2

R5091

10K

R5098

21

10K

R5099

21

SOT563

SSM6N15FE

1

2

6

Q5002

10K

21

R5084

402

MF-LF

1/16W

1%

470K

21

R5075

SOT563

SSM6N15FE

4

5

3

Q5002

R5089

1

10K

2

10K

21

R5049

R5090

21

10K

5%

MF-LF

1/16W

3.3K

402

21

R5071

3.3K

5%
MF-LF

402

1/16W

2

1

R5070

BC847BV-X-F
SOT563

1

6

2

Q5077

SOT563

BC847BV-X-F

4

3

5

Q5077

402

MF-LF

1/16W

5%

470

2

1

R5078

R5079

10K

21

402

MF-LF

1/16W

1%

OMIT

31.6

2

1

R5050

470K

21

R5088

SOT563

SSM6N15FE

4

5

3

Q5001

402

CERM

50V

10%

0.001UF

2

1

C5050

100K

21

R5006

SOT563

SSM6N15FE

1

2

6

Q5001

MF-LF
402

1/16W

1K

5%

2

1

R5000

SOT23-5

RN5VD30A-F

CRITICAL

2

1

4

3

5

U5000

CERM

20%

0.1UF

402

10V

2

1

C5000

402

0.01UF

16V

CERM

10%

2

1

C5001

5%
402

0

MF-LF

1/16W

NOSTUFF

2

1

R5001

402

50V

CERM

5%

15PF

21

C5020

402

10%
16V

0.01UF

CERM

2

1

C5067

603

X5R

6.3V

20%

10uF

2

1

C5066

10K

R5095

1 2

402

1/16W

5%

0

NOSTUFF

MF-LF

21

R5072

MF-LF

0

5%

NOSTUFF

1/10W
603

2

1

R5010

CRITICAL

SOT23-3

ISL60002-33

21

3

VR5065

CERM-X5R

10%

0.47UF

402

6.3V

2

1

C5065

0

1/16W
MF-LF

402

5%

21

R5011

?

TI REF3133

353S1381353S1278

VR5065

FANCYR5050

44.2, 1%, 1/16W, MF-LF, 402

1

114S0086

NORMAL

R5050

31.6, 1%, 1/16W, MF-LF, 402

1

114S0071

051-7455

SYNC_MASTER=GPU

45

01

SYNC_DATE=07/17/2006

SMC SUPPORT

76

SMC_NB_1V25_ISENSE

RSMRST_PWRGD

SMC_PA0

=PP5V_S3_SYSLED

SYS_LED_ILIM

PM_THRMTRIP_L

SMC_BC_ACOK

CPU_PROCHOT_L_R

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_S5_AVREF_SMC

CPU_PROCHOT_L

PP3V3_S0

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

SMC_MANUAL_RST_L

=PP3V42_G3H_SMCVREF

SMC_SUS_CLKSUS_CLK_SB

SMC_PROCHOT

SMC_ONOFF_L

SMC_RESET_L

PM_SLP_S3_L

=PPVIN_S5_IMVP

SMC_SYS_LED

SYS_LED_EN

SMC_PF3

SMC_ANALOG_ID

=PP3V42_G3H_SMC

SMC_GFX_OVERTEMP_L

SYS_LED_ISET

PBUS_SMC_VSENSE_EN_L

SMC_PROCHOT_3_3_L

PP1V05_S0

CPU_PROCHOT_BUF

CPU_PROCHOT_L

SMC_BATT_CHG_EN

SMC_THRMTRIP

SYS_LED_ANODE

SYS_LED_BIAS

SMC_PB0

SMC_PA1

SYS_ONEWIRE

SMC_TX_L

SMC_TCK

PM_LAN_PWRGD

SMC_ADAPTER_EN

SMC_CASE_OPEN

SMC_EXCARD_CP

=PP3V42_G3H_SMC

SMC_XTAL

SMC_BATT_TRICKLE_EN_L

SMC_EXTAL

SMC_FWE
SMC_LID

SMC_P67
SMC_PG0

SMC_TDI

SMC_ENRGYSTR_LDO_PGOOD

SMC_TMS

SMC_ONOFF_L

=PP3V3_S0_SMC_LS

SMC_EXCARD_OC_L

SMC_BS_ALRT_L

=PP3V42_G3H_SMC

PM_SLP_S5_L

SMC_TDO

SMC_RX_L

66C2

66B1 62C2 61C5 60B2

62B8

57C4

66A6

48C6

58B7

51B8

46B6

44D5

51B8

51B8

46B4

70B3

57C7

70C3

48C1

44C5

45D8

70C3

44C5

38C6

45D4

57A8

45D8

44C5

63B5

22C2

57C3

59C8

48B1

45D5

46B4

35C7

45D4

59C8

66A4

57C8

44B8

46B4

35C7

45C1

66A3

44B5

46B4

46B6

45C8

57A2

45C1

44B8

63B4

40B6

15A6

44C5

45B5

7D4

48A1

44C5

44C3

33C7

44D4

7D7

45C3

44C8

40C5

44B8

41A8

44B5

33C7

44D4

44C8

42C3

44B5

66C1

44B5

44C5

44C5

44D4

44C5

41A8

44C5

44D8

44B8

7A4

9C6

6C1

44D4

9C5

6A2

44C1

6B2

7C1

44C5

24D3

44A5

42C8

6C2

24D3

7A1

44C8

44B5

44A8

7C1

44A8

48D7

44C5

6B2

9C5

6C1

44A5

6B2

44B8

44B8

6C1

6C2

6C2

44C5

6C1

44B5

44B8

7C1

44C3

6C1

44C3

44A5

6B2

44C5

44B5

6C2

44A2

6C2

42C8

7D4

44B8

6D1

7C1

24D3

6C2

BI

BI

IN

IN

OUT
OUT
OUT

OUT

OUT

IN

IN

BI

BI

OUT
OUT
OUT

OUT

IN

IN

OUT

IN

OUT

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LPC+ Connector

516S0416

FWH_INIT_L Generation

6C2

22D4 44C8

6C2

24C8 44C8

6C2

29B3 75C3

6C2

24D5 44C5

6C2

24C8 37A5 44C5

6C2

23B5

6C2

44B5 45C5

6C2

44C1

6C2

44D1

6C2

27D1

6C2

22D4 44C8

6D2

22D4 44C8

6D2

22D4 44C8

6C2

44B5 45C5

6C2

44C3 45D7

6C2

44C1

6C2

24A7 24D5

R5192

1

2

402

5%
1/16W
MF-LF

LPCPLUS

330

R5191

1

2

1.3K

402

MF-LF

1/16W

5%

LPCPLUS

R5190

1 2

5%
1/16W
MF-LF

402

330

LPCPLUS

PLACEMENT_NOTE=Place R5190 to minimize CPU_INIT_L stub

9D6

22C4 70B3

6C2

41A8 44B8 44C5 45D5

6C2

41A8 44B8 44C5 45D5

6C2

44B5 45C5

6C2

44B5 45C5

Q5190

5

3

4

LPCPLUS

SOT563

BC847BV-X-F

Q5190

2

6

1

BC847BV-X-F

LPCPLUS

SOT563

J5100

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SM1

CRITICAL

LPCPLUS

F-ST-5047

6C2

22D4 44C8

76

LPC+ Debug Connector

01

SYNC_MASTER=WFERRY

SYNC_DATE=06/01/2006

46

051-7455

=PP5V_S0_LPCPLUS

LPC_AD<0>
LPC_AD<1> LPC_AD<2>

=PP3V42_G3H_LPCPLUS

BOOT_LPC_SPI_L
SMC_TMS
DEBUG_RESET_L
SMC_TRST_L
SMC_TDO

SMC_TCK

SMC_TDI

LPC_AD<3>

FWH_INIT_L

PM_CLKRUN_L

CPU_INIT_R_L

CPU_INIT_LS3V3

LINDACARD_GPIO

SMC_NMI

SMC_RESET_L

PM_SUS_STAT_L

INT_SERIRQ

PCI_CLK33M_LPCPLUS

SMC_MD1

=PP3V3_S0_LPCPLUS

CPU_INIT_L

SMC_TX_L

SMC_RX_L

LPC_FRAME_L

7A7

7B1

6D2

6D2

6C2

7C4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ICH8-M SMBus Connections

SMC MGMT Bus

SMC

AIRPORT

U4900

SMC "MANAGEMENT" SMBUS CONNECTIONS

SMC "B" SMBus Connections

SO-DIMM "A"

(Write: 0x16 Read: 0x17)

SMC "0" SMBus Connections

SMC "Battery A" SMBus Connections

J3400

CPU Temp

EMC1043-5: U5520

(MASTER?)

ICH8-M

U2300

(MASTER)

(Write: 0x98 Read: 0x99)

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "A" SMBus Connections

U4900

(MASTER)

SMC

SMC

U4900

(MASTER)

SMC

U4900

SMC

(MASTER)

U4900

J3100

(Write: 0xA0 Read: 0xA1)

Clock Chip

(Write: 0xD2 Read: 0xD3)

SLG8LP537V: U2900

ICH8-M

U2300

(MASTER)

J3200

SO-DIMM "B"

(Write: 0xA4 Read: 0xA5)

U5500

HEAT PIPE/FIN-STACK

J6950

Battery

SMS

U5930

ICH8-M ME SMBus Connections

R5200

1

2

MF-LF

4.7K

1/16W

402

5%

R5201

1

2

4.7K

402

5%
1/16W
MF-LF

R5280

1

2

402

1/16W

5%

8.2K

MF-LF

R5281

1

2

402

1/16W
MF-LF

5%

8.2K

R5261

1

2

402

5%

4.7K

1/16W
MF-LF

R5260

1

2

5%

MF-LF

402

4.7K

1/16W

R5271

1

2

402

MF-LF

1/16W

5%

100K

R5270

1

2

402

MF-LF

1/16W

100K

5%

R5251

1

2

402

5%

4.7K

1/16W
MF-LF

R5250

1

2

4.7K

5%

MF-LF

1/16W

402

R5231

1

2

10K

5%
1/16W
MF-LF
402

R5230

1

2

10K

5%

402

1/16W
MF-LF

R5233

1

2

10K

402

MF-LF

1/16W

5%

R5232

1

2

402

MF-LF

5%

1/16W

10K

SYNC_MASTER=WFERRY

SMBUS CONNECTIONS

47 76

01

051-7455

SYNC_DATE=06/01/2006

SMB_MGMT_CLK

=I2C_SMS_SDA

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

=I2C_SMS_SCL

=SMB_AIRPORT_CLK

SMB_MGMT_DATA

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

THRM_CPU_SMB_CLK

=PP3V3_S3_SMBUS_SMC_MGMT

=SMB_AIRPORT_DATA

MAKE_BASE=TRUE

SMBUS_SB_ME_SDA

SMBUS_SB_ME_SCL

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

=PP3V3_S0_SMBUS_SMC_B_S0

=SMBUS_CK505_SCL

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

=SMBUS_BATT_SDA

THRM_CPU_SMB_DATA

=PP3V3_S5_SMBUS_SB_ME

SMB_ME_CLK
SMB_ME_DATA

=PP3V3_S3_SMBUS_SMC_A_S3

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

SMB_A_S3_CLK
SMB_A_S3_DATA

=PP3V42_G3H_SMBUS_SMC_BSA

SMB_0_S0_DATA

SMB_0_S0_CLK

SMB_B_S0_CLK
SMB_B_S0_DATA

=SMBUS_CK505_SDA

=I2C_SODIMMA_SCL
=I2C_SODIMMA_SDA

SMBUS_SB_SCL

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SB_SDA

=PP3V3_S0_SMBUS_SB

SMB_CLK
SMB_DATA

=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA

SMB_BSA_DATA

SMB_BSA_CLK

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

=PP3V3_S0_SMBUS_SMC_0_S0

THRM_HEATPIPE_SMB_DATA

THRM_HEATPIPE_SMB_CLK

=SMBUS_BATT_SCL

76C3

51B6

76C3

73A3

73A3

73A3

73A3

44C5

51A6

6B2

51A6

33B3

44C8

76C3

76C3

49B4

7A4

33B3

76C3

6B2

7C4

28B6

76C3

76C3

57A2

49B4

7D1

24D5

24D5

7A4

76C3

76C3

44A5

44A5

7B1

44B5

44B8

44A5

44A5

28B6

30A6

30A6

7C4

24D5

24D5

31A6

31A6

44A5

44A5

76C3

7C4

49D4

49D4

57A2

IN

V-

V+

+

-

S D

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CPU CURRENT SENSE

PLACE C5350 NEAR SMC

PLACE RC FILTER CLOSE TO SMC

DRIVEN LOW IN S0

PROCESSOR DCIN VOLTAGE SENSE

Switches in fixed load on power supplies to calibrate current sense circuits

Current Sense Calibration Circuit

GPU VOLTAGE SENSE

C5376 CLOSE TO SMC

C5312 CLOSE TO SMC

CPU VOLTAGE SENSE

R5343

1

2

1/4W

1%
1206

1.00

MF-LF

R5351

1

2

402

MF-LF

1/16W

1%

5.49K

C5350

1

2

6.3V
CERM-X5R

0.22UF

10%
402

R5350

1

2

27.4K

1/16W
MF-LF

1%
402

C5304

1

2

NOSTUFF

0.1UF

CERM

10V

20%
402

C5355

1

2

0.1UF

NOSTUFF

CERM

10V

20%
402

R5303

1

2

1/16W
MF-LF

1M

1%
402

R5300

1 2

1%

1M

1/16W
MF-LF

402

R5307

1 2

5%

0

MF-LF

1/16W

402

R5305

1 2

30.1K

1%

MF-LF

1/16W

402

R5308

1 2

402

1/16W
MF-LF

5%

0

R5306

1 2

30.1K

1%

MF-LF

1/16W

402

C5376

1

2

0.22UF

6.3V
X5R
402

20%

R5381

1 2

4.53K

1%

MF-LF

1/16W

402

U5300

1

3

4

2

5

CRITICAL

HPA00141AIDCKR

SC70-5

C5300

1 2

50V

10%

CERM

470PF

402

R5342

1 2

1K

402

5%

MF-LF

1/16W

U5302

2

3 1

5

4

SC70-5

SN74AHCT1G125DCKRE4

CRITICAL

Q5350

3

1

2

SOT-723

SSM3J15FV

C5303

1

2

470PF

10%
50V
CERM
402

C5301

1 2

0.1UF

10V

20%
402

CERM

R5302

1 2

1%

MF-LF

1/16W

402

4.53K

C5302

1

2

20%

6.3V
X5R

0.22UF

402

Q5300

1
2
5
63

4

TSOP-LF

SI3446DV

CRITICAL

R5312

1 2

402

MF-LF

4.53K

1%

1/16W

C5312

1

2

20%

6.3V

0.22UF

X5R
402

051-7455

48

SYNC_MASTER=GPU

CPU Current & Voltage Sense

SYNC_DATE=07/17/2006

76

01

=PP3V3_S0_CPUPOWER

CPU_ISENSE_R_N

CPU_ISENSE_R_P

CPUVCORE_ISENSE_CAL

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.50 mm

ISENSE_CAL_EN_5V

=PP5V_S0_ISENSECAL

ISENSE_CAL_EN

ISENSE_CAL_EN_5V_R

=PPVCORE_S0_CPU

IMVP6_VO

IMVP6_CPU_ISENSE_N

GND_SMC_AVSS

SMC_CPU_ISENSE

IMVP6_DROOP

GND_SMC_AVSS

PBUS_S0_SMC_VSENSE

=PPVIN_S5_CPU_IMVP

PBUS_SMC_VSENSE_EN_L

IMVP6_CPU_ISENSE_P

SMC_PBUS_VSENSE

CPU_ISENSE_OUT_R

=PPVCORE_S0_NB_GFX

SMC_GPU1_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

SMC_CPU_VSENSE

=PPVCORE_S0_CPU

66C2

66C2

66C2

66C2

66B1

66B1

66B1

66B1

62C2

62C2

62C2

62C2

61C5

61C5

61C5

61C5

60B2

60B2

60B2

60B2

48B3

48C6

48C1

48C6

48C6

48B5

11D7

48B1

48B1

59D8

21C5

48C1

48C1

11D7

10D7

48A1

48A1

59D4

17D5

48B1

48A1

10D7

10B5

59B6

45B6

59C7

59B6

45B6

59C2

17B7

45B6

45B6

44C5 10B5

7C4

7A7

44B8

7D7

59A4

44C1

44C5

59A4

44C1

7B1

45A5

44C5

7B7

44A2

44C1

44C1

6B2 7D7

IO

IO

IO

IO

OUT

IN

VDD

SMDATA

SMCLK

GND

DP1
DN1

DP2
DN2

VDD

SMDATA

SMCLK

GND

DP1
DN1

DP2
DN2

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD

2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR

CPU TEMPERATURE ZONE

(TO CPU INTERNAL THERMAL DIODE)

ADDR= 1001 100B

NEXT TO U5500

10 MIL SPACING

LAYER.CPU_THERMD_N

FOR CPU_THERMD_P AND

ADD GND GUARD TRACE

LAYOUT NOTE:LAYOUT NOTE:

PLACE C5511

ADDR= 1001 100B

PLACE C5501 NEAR U5500 VDD

PLACE C5522 NEAR U5520 VDD

CPU_THERMD_N ON SAME

10 MIL TRACE

ROUTE CPU_THERMD_P AND

1. ROUTE DXP AND DXN DIFFERENTIALLY

HEAT-PIPE/FIN-STACK TEMPERATURE ZONE

3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD

2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR

1. ROUTE DXP AND DXN DIFFERENTIALLY

TEMP DIODE JUNCTIONS

CONNECTOR DRIVES TWO

518S0521

(WRITE: 0X98 READ: 0X99)

PLACE C5501 NEXT
TO U5500 VDD

2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR

1. ROUTE DXP AND DXN DIFFERENTIALLY

3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD

NEXT TO U5500

PLACE C5510

PLACE UNDER J3101

PLACE C5524 NEXT TO Q5520

2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR

1. ROUTE DXP AND DXN DIFFERENTIALLY

3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD

(Write: 0x98 Read: 0x99)

J5550

5

6

1
2
3
4

M-RT-SM

78171-0004

CRITICAL

C5524

1

2

NOSTUFF

CERM
402

50V

10%

0.0022UF

C5502

1

2

10%

1UF

6.3V
CERM
402

C5510

1

2

50V
402

CERM

10%

0.0022UF

C5501

1

2

10%
X5R

0.1UF

16V
402

R5524

1 2

33

5%
1/16W
MF-LF

402

C5523

1

2

1UF

CERM

10%

6.3V
402

C5521

1

2

10%
50V

0.0022UF

CERM
402

C5520

1

2

0.0022UF

10%
50V
CERM
402

R5522

1 2

10

1%
1/16W
MF-LF

402

U5520

2

4

1

3

5

8
7

6

MSOP

EMC1043-5

CRITICAL

R5523

1 2

10

1%
1/16W
MF-LF

402

C5522

1

2

X5R

10%

0.1UF

16V
402

Q5520

1

3

2

CRITICAL

BC846BM3T5G

SOT732-3

R5501

1 2

33

5%
1/16W
MF-LF

402

U5500

2

4

1

3

5

8
7

6

EMC1043-5

MSOP

CRITICAL

C5511

1

2

10%
50V

402

CERM

0.0022UF

051-7455

49

SYNC_DATE=06/21/2006

76

01

SYNC_MASTER=GPU

TEMPERATURE SENSE

THRM_FINSTACK_P

THRM_FINSTACK_N

=PP3V3_S0_THRM_SNR

PP3V3_S0_THRM_HEATPIPE_F

THRM_HEATPIPE_SMB_CLK
THRM_HEATPIPE_SMB_DATA

THRM_DIMM_DX_F_P

THRM_DIMM_DX_P

THRM_DIMM_DX_F_N

THRM_DIMM_DX_N

CPU_THERMD_N

CPU_THERMD_P

THRM_CPU_SMB_CLK
THRM_CPU_SMB_DATA

=PP3V3_S0_THRM_SNR

PP3V3_S0_THRM_CPU_F

THRM_HEATPIPE_N

THRM_HEATPIPE_P

49C2

49D2

6A1

6A1

7C4

47D3

47D3

6A1

6A1

9C6

9C6

47C3

47C3

7C4

6A1

6A1

D

GS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

5V DC

518S0521

NC

GND

NC

MOTOR CONTROL

TACH

R5665

1 2

402

MF-LF

5%

1/16W

47K

R5660

1

2

47K

1/16W
MF-LF

402

5%

R5661

1

2

100K

402

MF-LF

1/16W

5%

Q5660

3

1

2

SOD-VESM

SSM3K15FV

J5601

5

6

1
2
3
4

M-RT-SM

78171-0004

CRITICAL

051-7455

76

SYNC_MASTER=ENET

50

01

SYNC_DATE=11/10/2005

Fan

=PP3V3_S0_FAN_RT

FAN_RT_TACH

=PP5V_S0_FAN_RT

SMC_FAN_1_TACH

SMC_FAN_1_CTL

FAN_RT_PWM

7C4

7A7

44A8

44A8

6D2

6D2

6D2

6D2

6D2

6D2

TEST

S0

S1

PS

GND

NC2

NC1

OUTPUTX

NC13
NC14

OUTPUTZ

OUTPUTY

VMUX

SELF

THRML

PAD

VDD

NC

CSB

RESERVED

SCK

INT

GND

VDD

SDO

SDI

VDDIO

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

NC

NC

NC

7/26/2005 - CONNECTED PD PIN TO SMC’S SMS_ONOFF_L

INPUT

PAGE HISTORY

OUTPUT

SMS_ACC_*_AXIS - ACCELEROMETER OUTPUT TO SCU

=PP3V3_S3_SMS - 3.3V POWER FOR SMS (STAYS ALIVE IN SLEEP)

7/26/2005 -

7/26/2005 - REMOVED BOM TABLE AND UPDATED SYMBOL TO KXM52-2050

NC

NC

+X

+Z (up)

1

Package Top

+Y

(Placed on board bottom side)

Desired Orientation

5/19/2005 - FIRST REVISION OF PAGE

SMS_ONOFF_L - CONNECT TO SMC TO BE ABLE TO PUT SMS INTO LOW-POWER MODE

PAGE NOTES

SMC_ACC_SELFTEST-->is a test signal

NC

NC

Package Top

1

+Y

+Z

(UP)

+X

Desired Orientation

(Placed on board bottom side)

0 -->Normal operation
1 -->Self test

NC

STUFF R5930 TO USE U5920
STUFF R5931 TO USE U5930

C5920

1

2

402

X5R

10%

0.1UF

16V

2

1

402

MF-LF

1/16W

5%

10K

R5921

U5920

4

1

13
14

2

5
7
6

8

11

10

9

15

3

12

CRITICAL

KXPA42050

DFN

C5905

1

2

X5R

0.033UF

402

16V

10%

C5906

1

2

X5R

0.033UF

402

16V

10%

0.1UF

10%
16V
X5R
402

2

C5932

1

R5930

10K

5%
1/16W
MF-LF
402

2

1

NOSTUFF

R5931

10K

5%
1/16W
MF-LF
402

2

1

C5931

16V
CERM-X5R
402

2

1

0.022UF

10%

BMA150

U5930

CRITICAL

LGA

9

8

7

11

2

1

3

4

6

10

5

12

C5904

1

2

0.033UF

402

X5R

16V

10%

051-7455

7651

SYNC_DATE=08/23/2005

SYNC_MASTER=SMC

01

SMS

SMS_ACC_SELFTEST

=PP3V3_S3_SMS

SMS_ONOFF_L

SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS

=PP3V42_G3H_SMC

=I2C_SMS_SDA

SMC_SMS_INT

=I2C_SMS_SCL

=PP3V3_S3_SMBUS_SMC_MGMT

45D8 45D4 45C1 44D4

47C3

7A4

44A5

44A8

44A8

44A8

7C1

47B1

44B5

47B1

7A4

SO

VDD

CE*

SCK

VSS

HOLD*

SI

WP*

OUT

IN

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

R6193 close to SB

R6114 close to u6100

R6190 close to SB

R6191 close to SB

C6100

1

2

402

0.1UF

16V
X5R

10%

R6101

1

2

1/16W

5%

402

3.3K

MF-LF

R6100

1

2

1/16W

5%

402

MF-LF

3.3K

R6114

1 2

1/16W

5%

402

MF-LF

15

PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100

U6100

1

7

6

5

2

8

4

3

SST25VF016B

SOI

16MBIT

OMIT

CRITICAL

23C5 73A3

R6190

1 2

MF-LF

15

1/16W

5%

402

PLACEMENT_NOTE=Place R6190 within 12.7mm of U2300

R6191

1 2

MF-LF

402

5%

1/16W

15

PLACEMENT_NOTE=Place R6191 within 12.7mm of U2300

23C5 73A3

23C5 73A3

R6193

1 2

15

402

MF-LF

5%

1/16W

PLACEMENT_NOTE=Place R6193 within 12.7mm of U2300

23C5 73A3

SYNC_DATE=04/26/2006

SYNC_MASTER=WFERRY

SPI ROMs

52 76

01

051-7455

SPI_SO

SPI_SI_R

SPI_A_SI_R

SPI_A_SO_R

SPI_SCLK_R

SPI_CE_R_L<0>

SPI_CE_L<0>

SPI_A_SCLK_R

=PP3V3_S5_ROM

SPI_A_WP_L
SPI_A_HOLD_L

73A3

73A3

73A3

73A3

7D1

IN

IN
IN

IN

OUT

THRM_PAD

NC

IN1

EN

IN2

OUT1
OUT2

NR/FB

GND

PORT-B-VREFO2

PORT-A-VREFO/DCVOL

PORT-E-L

THRM_PAD

AVSS1

SYNC

CD-R

PORT-F-VREFO

PORT-E-VREFO
PORT-B-VREFO

PORT-C-VREFO

PORT-B-R

PORT-B-L

PORT-E-R

PORT-H-R

PORT-H-L

PORT-G-R

PORT-G-L

JDREF

VREF

PORT-D-R

PORT-D-L

PORT-C-R

PORT-C-L

SPDIFO

PORT-F-R

PORT-F-L

DVSS

CD-GND

BEEP

AVSS2

AVDD2

AVDD1

SDATA_IN

CD-L

SENSE_A
SENSE_B

GPIO1/DMIC-L

BCLK

DVDD

NC

SPDIFI/EAPD/MIDI-I/DMIC-R

PORT-A-L
PORT-A-R

RESET*

GPIO0/DMIC-CLK

SDATA_OUT

DVDD_IO

REV B3

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

APPLE P/N 353S1576

AUDIO 4.5V REGULATOR

VOUT=1.2246V*[1+(R6210/R6211)]=4.58V

PLACE R6210, R6211, AND C6224 CLOSE TO U6201

AUDIO CODEC

APPLE P/N 353S1538

C6208

1

2

10%
16V

402

X5R

CRITICAL

0.1UF

R6204

1 2

1/16W

402

39

MF-LF

5%

C6212

1

2

CERM
402

0.001UF

10%
50V

C6206

1

2

402

10%
50V
CERM

0.001UF

C6203

1

2

0.001UF

402

50V
CERM

10%

C6207

2

50V

20%
CERM

402

0.001UF

L6201

1 2

FERR-220-OHM

0402

R6205

1

2

1/16W
402

1%
MF-LF

20.0K

C6200

1UF

1

2

402

10%

CRITICAL

6.3V

C6205

1

2

150UF

6.3V

20%

POLY

CRITICAL

CASE-B2

C6204

1

2

20%

POLY

6.3V

CASE-B2

150UF

CRITICAL

L6200

1 2

FERR-220-OHM

0402

C6221

1

2

6.3V
X5R

CRITICAL

603

10UF

20%

R6202

1 2

MF-LF

5%

1/16W

1K

402

C6220

1

2

16V
X5R

10%

402

0.1UF

R6200

1 2

NO STUFF

0

1/16W
MF-LF

402

5%

C6223

1

2

402

0.001UF

10%
50V
CERM

L6202

1 2

0402

R6211

1

2

1%
MF-LF

29.4K

1/16W
402

R6210

1

2

402

80.6K

MF-LF

1%
1/16W

R6206

1 2

5%
1/16W
MF-LF

402

39

R6209

1

2

MF-LF

1/16W

100K

5%

402

U6201

8

6

1
2

7

5

3
4

9

LREG_TPS79501DRB

SON

27

U6200

25

38

26

42

6

12

19

18

20

1

9

4

7

2
3

40
37

39
41

33

21
22

28

32

23
24

29

35
36 14

15
31

16
17
30

43
44

45
46

11

8

5

13
34

47

48

10

49

ALC885Q-VB3-GR

QFN

CRITICAL

R6271

1

2

5%
1/16W

402

10K

MF-LF

2

R6270

1

NO STUFF

5%
1/16W
MF-LF
402

100K

C6224

1

2

CERM
402

5%

15PF

50V

C6210

1

2

16V
TANT
SMA-LF

CRITICAL

10%

3.3UF

C6201

1

2

CERM

50V

10%

402

0.001UF

R6203

1

2

5%

402

MF-LF

1/16W

100K

R6201

1

2

1/16W
402

NO STUFF

0

5%
MF-LF

AUDIO: CODEC

SYNC_MASTER=M70AUDIO

051-7455

76

01

53

MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

CODEC_DVDD

AUD_CODEC_VREF

NO_TEST

NC_AUD_BI_PORT_H_R

NO_TEST

NC_AUD_BI_PORT_H_L

AUD_BI_PORT_G_R

NO_TEST

NC_AUD_BI_PORT_G_L

AUD_BI_PORT_B_R

AUD_BI_PORT_B_L

AUD_VREF_PORT_B

AUD_VREF_PORT_A

AUD_REG_SHDN_L

NC_VRP

NO_TEST

AUD_BI_PORT_D_R

NO_TEST

NC_BAL_IN_L

ACZ_RST_L

AUD_BI_PORT_C_R

=PP3V3_S0_AUDIO

=GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=5V

=PP5V_S0_AUDIO

MIN_NECK_WIDTH=0.20 MM

BEEP

AUD_GPIO_0

ACZ_BITCLK

AUD_BI_PORT_C_L

=GND_AUDIO_CODEC

AUD_BI_PORT_A_L

NC_AUD_VREF_PORT_F

NO_TEST

NC_AUD_BI_PORT_F_R

NO_TEST

AUD_SENSE_B

AUD_SPDIF_OUT

AUD_SENSE_A

AUD_SPDIF_I

AUD_BI_PORT_A_R

AUD_4V5_REG_IN

4V5_REG_FB

PP4V5_AUDIO_ANALOG

NC_AUD_BI_PORT_F_L

NO_TEST

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V

AVDD_ADC_DAC

MIN_NECK_WIDTH=0.20MM

AUD_GPIO_1

ACZ_SYNC

CODEC_DVDD

ACZ_SDATAIN<0>

AUD_SPDIF_O

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S0_AUDIO

VOLTAGE=3.3V

NO_TEST

NC_AUD_BI_PORT_E_R

NO_TEST

NC_BAL_IN_R

NO_TEST

NC_AUD_VREF_PORT_E

NO_TEST

NC_AUD_BI_PORT_E_L

NO_TEST

NC_BAL_IN_COM

NO_TEST

NC_AUD_VREF_PORT_C

NO_TEST

NC_AUD_VREF_PORT_D

AUD_CODEC_JDREF

AUD_BI_PORT_D_L

=GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

MIN_LINE_WIDTH=0.30 MM

CODEC_SDATA_IN

ACZ_SDATAOUT

CERM

1

FERR-220-OHM

OMIT OMIT

56C4

56C4

56C4

56B8

56B8

56B8

56B5

56B5

56B5

56B4

56B4

56B4

56B1

56B1

56B1

56A8

56A8

56A8

56A4

56A4

56A4

55B3

55B3

55B3

54C8

54C8

54C8

54B8

54B8

54B8

56B5

54A8

54A8

56B5

54A8

55D8

53D3

56C4

53B7

55D8

53D3

8A5

53D7

53B7

7A7

8A5

53A7

56C8

8A5

8A5

53A7

53A7

8A5

53C8

54A8

56A4

56A4

56B4

56C2

54C8

6C1

56A1

7C4

8B4

6D1

54A8

6C1

56B1

8B4

56C4

56C8

55D3

56A8

55B3

56C4

53D3

53A3

6C1

53D6

6D1

7C4

54B8

8B4

6D1

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SATELLITE & SUB TWEETER AMPLIFIER

APN:353S1595

169 HZ < FC < 282 HZ
80 HZ < FC < 132 HZ

12DB

SATELLITE

GAIN

RIGHT SATELLITE

SUB-TWEETER

LEFT SATELLITE

SUB

R6610

1

2

5%

402

10K

1/16W
MF-LF

C6610

1 2

CRITICAL

0.047UF

10%
X7R

402

16V

C6620

1 2

402

CRITICAL

0.047UF

X7R

16V

10%

C6631

1

2

0.1UF

X5R

CRITICAL

10%

402

16V

L6611

1 2

0402

FERR-1000-OHM

53C7

53C7

53C7

C6607

1

2

6.3V

10%

402

CERM

1uF

R6600

402

5%

MF-LF

1/16W

0

L6620

1 2

FERR-1000-OHM

0402

L6610

1 2

FERR-1000-OHM

0402

6B1

55C2

6B1

55C2

6B1

55C2

6B1

55C2

C6606

1

2

402

CERM

10%

1UF

6.3V

6A1

55C2

6A1

55C2

C6630

1 2

0.1UF

X5R
402

16V

CRITICAL

10%

L6630

1 2

0402

FERR-1000-OHM

53B2

C6621

1

2

402

0.047UF

16V

CRITICAL

10%
X7R

C6609

1

2

CERM

10%

6.3V

1uF

402

C6605

1

2

20%
CASE-B2

120UF

6.3V

POLY

CRITICAL

U6630

4

3

2

9

8

7

10

5

6

11

1

TDFN1

CRITICAL

MAX9705

U6610

4

3

2

9

8

7

10

5

6

11

1

TDFN1

MAX9705

CRITICAL

U6620

4

3

2

9

8

7

10

5

6

11

1

TDFN1

MAX9705

CRITICAL

C6611

1

2

402

0.047UF

CRITICAL

16V

10%
X7R

C6608

1

2

402

6.3V

CERM

10%

1uF

C6602

1

2

402

CERM

10%

1UF

6.3V

2

R6601

1

2

5%

100

MF-LF

1/16W
402

C6603

1

2

CASE-B3-SM

CRITICAL

47UF

POLY

6.3V

20%

C6604

1

2

402

CERM

10%

1UF

6.3V

R6660

12

1/16W
MF-LF

5%

402

0

R6661

12

1/16W

0

402

5%

MF-LF

R6670

12

1/16W
MF-LF

5%

402

0

R6671

12

1/16W

0

402

5%

MF-LF

R6680

12

1/16W
MF-LF

5%

402

0

R6681

12

0

402

5%

MF-LF

1/16W

R6602

1

2

1/16W
MF-LF

100

5%

402

XW6600

1 2

SM

051-7455

SYNC_MASTER=M70AUDIO

AUDI0: SPEAKER AMP

SYNC_DATE=03/12/2007

7654

01

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=5V
MIN_LINE_WIDTH=0.60 MM

=PP5V_S0_AUDIO_AMP

AUD_BI_PORT_D_R

AUD_SPKRAMP_INR

=GND_AUDIO_CODEC

PP5V_S0_AUDIO_F

VOLTAGE=5V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM

=GND_AUDIO_CODEC

AUD_SPKRAMP_SHUTDOWN_L

MAX9705_SUB_N

=GND_AUDIO_AMP

=GND_AUDIO_AMP

PP5V_S0_AUDIO_F

SPKRAMP_THERMPLANE

=GND_AUDIO_AMP

=PP5V_S0_AUDIO_AMP

=PP5V_S0_AUDIO_AMP

PP5V_S0_AUDIO_F

AUD_SPKRAMP_INSUB_L

AUD_SPKRAMP_INSUB

SPKRAMP_SYNC1

=GND_AUDIO_AMP

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.60 MM

SPKRAMP_THERMPLANE

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_R_P_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_L_P_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_P_OUT

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_SUB_P_OUT

MIN_NECK_WIDTH=0.20 MM

SPKRCONN_R_N_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_L_N_OUT

MIN_NECK_WIDTH=0.20 MM
SPKRCONN_SUB_N_OUT

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_THERMPLANE

MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT

MIN_LINE_WIDTH=0.30 mm

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_SUB_N_OUT

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_R_N_OUT

MIN_NECK_WIDTH=0.20 MM

AUD_BI_PORT_D_L

SPKRAMP_SYNC2

SPKRAMP_SUB_P_OUT

AUD_GPIO_0

AUD_BI_PORT_G_R

SPKRAMP_SYNC1

MAX9705_L_N

AUD_SPKRAMP_INL

MAX9705_R_N

AUD_SPKRAMP_INR_L

AUD_SPKRAMP_INL_L

AUD_SPKRAMP_SHUTDOWN_L

AUD_SPKRAMP_SHUTDOWN_L

SPKRAMP_SUB_N_OUT

=GND_AUDIO_CODEC

CRITICAL

C6601

POLY

SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT

SPKRAMP_THERMPLANE

SPKRAMP_L_P_OUT

SPKRAMP_SYNC2

SPKRAMP_L_N_OUT

CASE-B3-SM

6.3V

20%

47UF

1

OMIT

OMIT

OMIT

56C4

56C4

56C4

56B8

56B8

56B8

56B5

56B5

56B5

56B4

56B4

56B4

56B1

56B1

56B1

56A8

56A8

56A8

56A4

56A4

56A4

55B3

55B3

55B3

54B8

54C8

54C8

54A8

54B8

54A8

54C8

53D3

53D3

54C8

54B8

54C8

54D8

54D8

54C8

53D3

54B8

53B7

53B7

54B8

54A8

54A8

54B8

54C8

54B8

54C4

54C4

53B7

7A7

53A7

54C8

53A7

54C8

54A5

54A5

54C4

54C4

54A5

7A7

7A7

54C8

54A8

54B4

54B4

54B4

54C8

54B8

53A7

6D1

8B4

54B8

8B4

54B8

8A4

8A4

54B8

54A4

8A4

6D1

6D1

54C4

54C4

8A4

54A4

54B4

54D3

54C4

54A4

54A4

54B4

54A4

54C4

54B4

54B3

54A4

54A6

54A6

54B3

54C3

8B4

54A4

54C3

54A4

54C3

IN
IN
IN
IN

IN

IN

VCC
GND

VOUT
SHLD_PIN
SHLD_PIN

VIN

GND

VCC

SHLD_PIN
SHLD_PIN

OUT

OUT

OUT

BI

BI

OUT

IN

BI

BI

OUT

OUT

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

APN:514-0458

APN:514-0459

AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX

AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX

APN:518S0521

APN:518S0519

SPEAKER CONNECTOR

MIC EMI FILTER

MIC CONNECTOR

APN:518S0392

L6700

1 2

FERR-120-OHM-1.5A

0402-LF

L6702

1 2

FERR-1000-OHM

0402

L6703

1 2

FERR-1000-OHM

0402

1

L6705

2

FERR-1000-OHM

0402

L6707

1 2

FERR-1000-OHM

0402

C6700

1

2

402

CERM

6.3V

1UF

10%

6A1

54B1

6A1

54B1

6B1

54D1

6B1

54C1

XW6700

1 2

SM

XW6701

1 2

SM

R6749

1 2

MF-LF

1/16W

5%

402

10

C6751

1

2

X5R

10uF

20%

603

6.3V

L6790

1 2

FERR-220-OHM

0402

6B1

54C1

6B1

54C1

1/16W

R6791

1 2

402

0

5%

MF-LF

F-RT-TH

3

4

6
9
10

7

8

1

5

2

AUDIO-IN-MG3-M71

OMIT

CRITICAL

J6750

XW6705

1 2

SM

J6701

4

5

1
2
3

CRITICAL

M-RT-SM1

48227-0301

2
3
4

5
1
7
6

9
10

8

F-RT-TH

OMIT

CRITICAL

J6700

AUDIO-OUT-M71-MG3

J6703

5

6

1
2
3
4

M-RT-SM

78171-0004

CRITICAL

J6702

3

4

1
2

78171-0002

CRITICAL

M-RT-SM

L6770

1 2

FERR-1000-OHM

0402

L6772

1 2

FERR-1000-OHM

0402

6B1

56A6

6B1

56A6

L6750

1 2

FERR-120-OHM-1.5A

0402-LF

L6751

1 2

FERR-120-OHM-1.5A

0402-LF

R6740

1

2

MF-LF

1/16W
402

5%

0

L6771

1 2

FERR-1000-OHM

0402

L6773

1 2

0402

FERR-1000-OHM

DZ6770

1

2

6.8V-100PF

CRITICAL

402

DZ6771

1

2

CRITICAL

6.8V-100PF

402

DZ6702

1

2

402

CRITICAL

6.8V-100PF

DZ6704

1

2

6.8V-100PF

CRITICAL

402

DZ6705

1

2

CRITICAL

402

6.8V-100PF

DZ6703

1

2

402

CRITICAL

6.8V-100PF

DZ6753

1

2

402

6.8V-100PF

CRITICAL

DZ6752

1

2

6.8V-100PF

402

CRITICAL

L6754

1 2

FERR-1000-OHM

0402

DZ6754

1

2

402

CRITICAL

6.8V-100PF

DZ6755

1

2

CRITICAL

402

6.8V-100PF

NO STUFF

DZ6700

1 3

2 4

0405

5.6V-15A

DZ6701

1 3

2 4

0405

5.6V-15A

NO STUFF

DZ6750

1 3

2 4

NO STUFF

5.6V-15A

0405

DZ6751

1 3

2 4

NO STUFF

5.6V-15A

0405

L6756

1 2

FERR-1000-OHM

0402

R6750

1 2

MF-LF

402

10K

5%

1/16W

R6751

1 2

MF-LF

4.7

402

5%

1/16W

C6756

1

2

100PF

5%

50V

402

CERM

L6755

1 2

FERR-1000-OHM

0402

L6753

1 2

0402

FERR-1000-OHM

L6752

1 2

FERR-1000-OHM

0402

L6757

1 2

FERR-1000-OHM

0402

C6750

1

2

1UF

10%

402

6.3V

CERM

53C2

56A2

56B2

56A8

53C2

56C1

56C1

L6701

1 2

FERR-120-OHM-1.5A

0402-LF

L6704

1 2

FERR-1000-OHM

0402

L6706

1 2

0402

FERR-1000-OHM

56B6 56B8

56C8

R6700

1 2

5%

10K

402

MF-LF

1/16W

R6701

1 2

1/16W

5%

MF-LF

402

4.7

C6705

1

2

5%
402

CERM

50V

100PF

514-0479

CONN, 3.5MM COMBO AUDIO OUT, RA, BLACK, LF

CRITICAL

J6700 FANCY

1

514-0478

1

CONN, 3.5MM COMBO AUDIO IN, RA, BLACK, LF

J6750

CRITICAL

FANCY

514-0458 CRITICAL

1

J6750

NORMAL

CONN, 3.5MM COMBO AUDIO IN, RA, MG3, LF

514-0459

CONN, 3.5MM COMBO AUDIO OUT, RA MG3, LF

1

CRITICAL

J6700

NORMAL

AUDIO: JACK

051-7455

55

01

76

SYNC_DATE=03/12/2007SYNC_MASTER=M70AUDIO

AUD_SPDIF_OUT

CHASSIS_AUDIO_JACK_ISOL

AUD_CONNJ1_SLEEVEDET

AUD_CONNJ1_TIP

AUD_CONNJ1_RING

AUD_CONNJ1_SLEEVE

AUD_CONNJ1_TIPDET

AUD_CONNJ1_TIPDET_F

MIC_LO

AUD_J2_COM

AUD_CONNJ2_SLEEVE_F

AUD_CONNJ2_TIPDET_F

AUD_J1_TIPDET_R

MIC_LO_CONN_F

MIC_HI_CONN_F

CHASSIS_AUDIO_JACK_ISOL

AUD_J2_TIPDET_R

AUD_CONNJ2_SLEEVEDET_F

CHASSIS_AUDIO_JACK_ISOL

AUD_CONNJ2_TIP_F

AUD_CONNJ1_SLEEVEDET_F

AUD_J1_COM

AUD_CONNJ1_TIP_F

AUD_PORTC_R

AUD_SPDIF_I

MIC_SHLD_CONN

MIC_HI

CHASSIS_AUDIO_JACK_ISOL

MIC_HI_CONN

SPKRCONN_L_N_OUT

AUD_CONNJ1_SLEEVE_F

SPKRCONN_SUB_P_OUT

AUD_PORTA_R

AUD_PORTA_L

AUD_J1_SLEEVEDET_R

=PP3V3_S0_AUDIO

SPKRCONN_R_N_OUT

SPKRCONN_SUB_N_OUT
SPKRCONN_R_P_OUT

MIC_SHLD_CONN

SPKRCONN_L_P_OUT

MIC_LO_CONN

GND_AUDIO_SPDIF_DGND

AUD_J2_OPT_OUT

PP3V3_S0_AUDIO_SPDIF

AUD_CONNJ2_TIPDET

AUD_CONNJ2_SLEEVE

AUD_CONNJ2_RING

AUD_CONNJ2_TIP

AUD_CONNJ2_RING_F

AUD_CONNJ2_SLEEVEDET

GND_AUDIO_SPDIF_DGND

=GND_CHASSIS_AUDIO_JACK

AUD_PORTC_L

MIC_LO_CONN

MIC_HI_CONN

AUD_CONNJ1_RING_F

=GND_AUDIO_CODEC

PP3V3_S0_AUDIO_SPDIF

56C4 56B8 56B5

56B4 56B1 56A8 56A4 54C8 54B8 54A8

56B5

53D3

55C1

55C8

55C8

56A6

55C8

53D7

56A6

53B7

55A8

55C1

55C1

55D3

55A8

55B1

53A7

55A1

55B1

55D3

55D3

53A7

55A3

55A8

55A3

6B1

55A3

6B1

7C4

6B1

6B1

55A8

55D8

55C8

8D8

6B1

6B1

8B4

55B8

IN

OUT

OUT

IN

OUT

IN

IN

IN

IN

OUT

IN

IN

D

G S

D

SG

D

SG

D

SG

D

SG

OUTL

INR
INL

OUTR

SHDN*

CEXT

VCC

GND PAD

THM

IN

OUT

IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

HP OUT

0X1A (26,PORTC)

VREF_B (80%)

0X06 (6)

0X04 (4)

0X15 (21,PORTA)

VREF

N/A

N/A

N/A

N/A

DET ASSIGNMENT

0X1F (31,SPDIF IN)

0X18 (24,PORTB)

0X1A (26,PORTC)

0X0A (10)

0X07 (7)

0X08 (8)

CONVERTER

PIN COMPLEX

N/A

VOLUME
0X08 (8)
0X07 (7)

N/A

0X08 (8)
0X07 (7)

MUTE CONTROL

0X24 (36)

0X23 (35)

CODEC INPUT SIGNAL PATHS

MIXER

N/A

0X1B (27,PORTE)

0X26 (38)

VREF_A(100%)
GPIO 0

MUTE CONTROL

N/A

GPIO 0

N/A

N/A

DET ASSIGNMENT

0X1E (30,SPDIF OUT)

0X14 (20,PORTD)
0X16 (22,PORTG)

0X15 (21,PORTA)

0X25 (37)

0X05 (5)

0X0E (14)

SUB SPKR

SAT SPKR

FUNCTION

SPDIF OUT

PORT C LI

NC

NC

NC

SPDIF IN

LINE IN

Line-in (PORT C) DETECT

PORT A HP/LO

MIC INPUT CIRCUITRY

PLACE C6852 NEAR U6200

N/A

PORT A DETECT

PLACE L6800/C6800 CLOSE TO Q6800

PORT E DETECT(SPDIF DELEGATE)

FUNCTION

CONVERTER

PIN COMPLEX

VOLUME

MIC IN

0X0F (15)

CODEC OUTPUT SIGNAL PATHS

APN:353S1459

HP/LO DE-POP SWITCH

C6801

1

2

402

10%
X5R

16V

0.1UF

R6802

1 2

47K

1/16W
MF-LF

402

5%

1 2

20%

6.3V

POLY

B2

100UF

C6831

1 2

CRITICAL

B2

6.3V

20%

100UF

POLY

53C2

55C3

55C3

53C2 53C2 56A8

55C3

C6850

1 2

16V

402

10%

0.1uF

CRITICAL

X5R

R6853

1 2

NO STUFF

MF-LF

1/16W

5%

402

0

XW6800

1 2

SM

R6854

1 2

0

NO STUFF

5%

1/16W

402

MF-LF

R6855

1 2

2.2K

1/16W

5%

402

MF-LF

R6852

1

2

402

100K

5%
MF-LF

1/16W

R6851

1 2

402

5%

1/16W
MF-LF

330

C6851

1

2

CRITICAL

402

CERM

50V

10%

680PF

6B1

55B3

6B1

55B3

6B1

55A1 55D3

C6800

1

2

10%

402

0.1UF

X5R

16V

L6800

1 2

FERR-1000-OHM

0402

R6806

1

2

39.2K

MF-LF

1%
1/16W

402

R6803

1 2

MF-LF

402

5%

100K

1/16W

R6861

1

2

1/16W

5%
MF-LF

402

270K

C6802

1

2

0.01UF

402

16V

10%
CERM

53C2

55C3 56B6

R6813

1

2

402

5%
1/16W
MF-LF

10K

C6811

1

2

10%

16V

X5R

0.1UF

402

1 2

1/16W

47K

MF-LF

5%

55A3

C6835

1

2

16V

0.1UF

402

X5R

10%

C6852

1

2

402

CRITICAL

CERM

5%

50V

NO STUFF

100PF

R6850

1 2

1/16W
MF-LF

6.81K

402

1%

C6836

1

2

402

10%

1UF

6.3V

CERM

C6853

1

2

603

X5R

10UF

6.3V

20%

CRITICAL

Q6802

3

1

2

SOD-VESM

SSM3K15FV

Q6800

3

5

4

SSM6N15FE

SOT563

Q6800

6

2

1

SSM6N15FE

SOT563

Q6801

3

5

4

SSM6N15FE

SOT563

Q6801

6

2

1

SOT563

SSM6N15FE

C6832

12

3.3UF

CRITICAL

TANT

SMA-LF

10%
16V

C6833

12

CRITICAL

3.3UF

10%
16V
TANT

SMA-LF

R6805

1

2

39.2K

1/16W
402

1%
MF-LF

U6801

MAX9890BETA+

TDFN

CRITICAL

R6839

1

2

MF-LF

402

10K

1/16W

5%

53C2

R6801

1

2

270K

402

MF-LF

5%
1/16W

R6811

1

2

MF-LF

270K

402

5%
1/16W

53C7 55B3

R6836

1

2

27.4K

1%

402

MF-LF

1/16W

55B3

R6837

1

2

402

27.4K

1%
1/16W
MF-LF

53C7

R6835

1

2

27.4K

1%
1/16W
MF-LF

402

R6834

1

2

402

27.4K

1%
1/16W
MF-LF

R6856

1 2

NO STUFF

MF-LF

0

402

1/16W

5%

SYNC_MASTER=M70AUDIO

AUDIO: JACK TRANSLATORS

051-7455

7656

01

SYNC_DATE=03/12/2007

=GND_AUDIO_CODEC

AUD_PORTC_L

AUD_PORTC_R

AUD_BI_PORT_C_R

AUD_BI_PORT_C_L

AUD_PORTA_DET_L

=GND_AUDIO_CODEC

=GND_AUDIO_CODEC

AUD_INJACK_INSERT_L

AUD_J2_DET_RC

MAX9890_CEXT

PP3V3_S0_AUDIO_F

AUD_J2_TIPDET_R

PP3V3_S0_AUDIO_F

AUD_SENSE_A

AUD_PORTA_L

PP3V3_S0_AUDIO_F

AUD_BI_PORT_B_L
MAKE_BASE=TRUE

AUD_BI_PORT_B_R

VREF_PORT_B_R

MAX9890_OUTR

AUD_BI_PORT_A_R

AUD_VREF_PORT_A

AUD_BI_PORT_A_L

MIC_IN

=GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

AUD_J1_TIPDET_R

=GND_AUDIO_CODEC

AUD_J1_SLEEVEDET_R

AUD_J1_SLEEVEDET_R

AUD_PORTE_DET_L

AUD_SENSE_B

AUD_OUTJACK_INSERT_L

AUD_VREF_PORT_B

=GND_AUDIO_CODEC

MAX9890_OUTL

AUD_PORTA_R

=GND_AUDIO_CODEC

=PP5V_S0_AUDIO

PP3V3_S0_AUDIO_F

=GND_AUDIO_CODEC

AUD_SENSE_A

MIC_HI

MIC_SHLD_CONN

=GND_CHASSIS_AUDIO_MIC

MIC_LO

AUD_J1_SLEEVEDET_INV

AUD_J1_DET_RC

R6812

402

C6830

CRITICAL

OMIT

OMIT

56C4

56C4

56C4

56C4

56C4

56B8

56B8

56C4

56B8

56C4

56B8

56B8

56B8

56B5

56B5

56B8

56B5

56B8

56B5

56B4

56B5

56B4

56B4

56B5

56B4

56B5

56B4

56B1

56B4

56B1

56B1

56B1

56B1

56B4

56A8

56A8

56B1

56A8

56A8

56A8

56A8

56B1

56A4

56A4

56A4

56A4

56A4

56A4

56A4

56A8

55B3

55B3

55B3

55B3

55B3

55B3

55B3

55B3

54C8

54C8

54C8

54C8

54C8

54C8

54C8

54C8

54B8

54B8

54B8

54B8

54B8

54B8

54B8

54B8

54A8

54A8

54A8

54A8

54A8

54A8

54A8

54A8

53D3

53D3

53D3

53D3

55D8

53D3

53D3

53D3

53D3

53B7

53B7

53B7

56B8

56C8

56C8

53B7

53D7

53B7

53B7

53B7

53A7

56C8

53B7

53A7

53A7

53A7

56B3

56B8

56C8

56B8

53A7

53A7

53A7

56B8

53A7

53A7

7A7

56B3

53A7

8B4

8B4

8B4

56A8

56B3

53C2

56A8

53C2

53C2

8B4

7C4

8B4

55C3

53C2

8B4

8B4

6D1

56A8

8B4

8D8

V-

V+

D

SG

D

SG

D

SG

D

GS

NC

Y

B

A

G

D

S

NC

V-

V+

-

+

D

S G

VOID

D1

D3

D4

S3
S2

GATE

S1

D2

TABLE_ALT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

ACIN DETECTION

NC

OVP

PIN 1

MLB TOP VIEW

NCNC

BATTERY INTERFACE

INRUSH LIMITER

518S0526

LID HALL EFFECT SENSOR

DC-JACK INTERFACE

R6932

1

2

24.3K

1%
1/16W
MF-LF
402

C6930

1

2

10%
402

X5R

25V

0.1UF

R6933

1

2

MF-LF

100K

5%
402

1/16W

R6931

1

2

5%

100K

402

MF-LF

1/16W

U6990

2

4

1

3

5

CRITICAL

LM397

SOT23-5

J6900

1
2
3
4
5

M-RT-SM

87438-0563

CRITICAL

R6900

1

2

402

MF-LF

1/16W

100K

5%

C6903

1

2

402

CERM

50V

0.001UF

10%

R6901

1

2

1%
1/16W
MF-LF
402

1K

R6903

1

2

5%

10K

1/16W
MF-LF
402

R6904

1

2

1/16W

47K

5%
402

MF-LF

D6900

3

1

2

CRITICAL

RCLAMP2402B

SC-75

R6911

1 2

1/16W

5%
402

MF-LF

100K

R6905

1 2

47

5%
1/8W

805

MF-LF

R6902

1 2

1K

1/16W
MF-LF

5%
402

C6907

1

2

0.001UF

50V
CERM

10%
402

Q6920

6

2

1

SOT563

SSM6N15FE

Q6910

6

2

1

SOT563

SSM6N15FE

Q6910

3

5

4

SOT563

SSM6N15FE

Q6999

3

1

2

SOD-VESM

SSM3K15FV

D6901

1

3

5

4

2

SOT665

HN2D01JEF

CRITICAL

R6940

1 2

805

MF-LF

47

5%
1/8W

U6950

2

1

3

5

4

SOT665

CRITICAL

TC7SZ08AFEF

Q6940

3

1

2

NTK3142P

SOT723-3

U6900

4

6

3

1

5

2

SC70

TLV7211

CRITICAL

Q6920

3

5

4

SOT563

SSM6N15FE

L6901

1 2

FERR-50-OHM

SM-LF

L6902

1 2

120-OHM-0.3A-EMI

0402-LF

L6903

1 2

0402-LF

120-OHM-0.3A-EMI

L6904

1 2

0402-LF

120-OHM-0.3A-EMI

L6905

1 2

SM-LF

FERR-50-OHM

C6906

1

2

CERM

50V

5%

47pF

402

C6915

1

2

CERM

50V

5%

47pF

402

C6909

1

2

402

CERM

50V

10%

0.001UF

C6905

1

2

0.001UF

10%
CERM

402

50V

C6911

1

2

402

10%
CERM

50V

0.001UF

J6950

1

10

1112
1314
1516
1718
19

2

20

34
56
78
9

F-ST-SM

CRITICAL

127216FA020

L6909

1 2

600-OHM-300MA

0402

L6907

1 2

600-OHM-300MA

0402

C6921

1

2

402

CERM

16V

0.01uF

10%

L6908

1 2

600-OHM-300MA

0402

C6920

1

2

402

10%

0.01uF

16V
CERM

C6918

1

2

10%
25V

0.1UF

402

X5R

R6908

1

2

1%

102K

402

MF-LF

1/16W

R6910

1 2

1M

1/16W
MF-LF
402

5%

R6909

1

2

MF-LF

1%

51.1K

1/16W
402

R6907

1

2

10.7K

MF-LF

1/16W

1%
402

R6906

1

2

MF-LF

102K

402

1/16W

1%

R6914

1

2

330K

5%
1/16W
MF-LF
402

R6913

1

2

470K

5%
MF-LF

402

1/16W

C6917

1

2

0.22UF

X5R

25V
603

20%

Q6950

5

6

7

8

4

1

2

3

CRITICAL

AO4409

SOI

C6902

1

2

0.01uF

X7R
402

25V

10%

F6900

1 2

6AMP-24V

CRITICAL

1206-1

?

376S0543

AOS MOSFET

Q6950

376S0466

SYNC_DATE=07/13/2005

SYNC_MASTER=POWER

DC-In & Battery Connectors

57 76

051-7455

01

TI & NATIONAL

353S1717?353S1297

U6990

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=2 MM

PP18V5_DCIN_F

SMC_BC_ACOK

VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.20 MM

=PP18V5_G3H_INRUSH

SMC_ADAPTER_EN

ACIN_1V20_REF

ACIN_DIV

PPVBATT_G3H_R

BATT_POS_F

=PPDCIN_G3H

SYS_ONEWIRE

SMC_BC_ACOK_ONEWIRE_R

ACIN_ENABLE_L

SYS_ONEWIRE_BILAT

ONEWIRE_EN

ONEWIRE_PWR_EN_L

ONEWIRE_PWR_EN_L_DIV

=GND_DCIN_CHGND

PP18V5_DCIN_ONEWIRE

ONEWIRE_OV

ONEWIRE_ESD

ONEWIRE_DCIN_DIV

ACIN_ENABLE_GATE

ADAPTER_SENSE

SMC_BS_ALRT_L

=SMBUS_BATT_SDA

BATT_POS_F

=SMBUS_BATT_SCL

SMBUS_BATT_SDA_F

SMC_BS_ALRT_L_F

=GND_BATT_CHGND

SMBUS_BATT_SCL_F

GND_SMC_LID_F

SMC_LID_F

PP3V42_G3H_LIDSWITCH_F

=GND_BATT_CHGND

=PP3V42_G3H_LIDSWITCH

SMC_LID

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.20 MM

VOLTAGE=18.5V

PP18V5_DCIN

BATT_POS

=PP3V42_G3H_ACIN

SMC_BC_ACOK

PPDCIN_G3H_R

ACIN_ENABLE_L_DIV

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

BATT_NEG

45B3

66A6

44D5

66A6

57C3

38C6

45C5

66B8

57C7

45B6

35C7

45D5

45C5

44B5

66A8

45B6

44C5

33C7

66B2

44B8

66A6

44C5

66B2

57A6

57A6

42C3

66A5

44C5

6C1

7B3

6C1

57B2

7B3

6C1

8C8

6C1

6D1

47C1

57D5

47C1

6D1

8D8

6D1

8D8

7B1

6B2

6D1

7B1

6C1

6D1

NC

NC

NC

NC

UVLO_D

UVLO_C

UVLO_B

UVLO_A

RESET*

DLY_OFF_C
DLY_OFF_D

DLY_OFF_A
DLY_OFF_B

DLY_ON_D

DLY_ON_C

DLY_ON_B

DLY_ON_A

GATE_D

GATE_C

GATE_B

GATE_A

VDD

ENABLE_1

PAD

THML

GND

SENSE

CT

VDD

GND

RESET*

MR*

D

SG

D

SG

D

G

S

D

G

S

D

SG

D

SG

G

S

D

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_ALT_ITEM

NC

NC

AFTER UVLO_D VALID

33 mOhm @4.5V

RDS(ON)

1.8V S0 FET

CHANNEL

1.810 A

33 mOhm @4.5V

LOADING

1.05V S0 RUN/SS CONTROL

5V S0 FET

DEASSERTED 160MS

U7002.3 has int 90K pull-up

1.25V S0 RUN/SS CONTROL

FDC655BN

FDC655BN

0.260 A

1.5V S0 RUN/SS CONTROL

FDM6296
N-TYPE

4.348 A

~26MS

MOSFET

N-TYPE

MOSFET

RDS(ON)

3.3V S0 FET

CHANNEL N-TYPE

MOSFET

NC

NC

15 mOhm @4.5V

LOADING

RDS(ON)

CHANNEL

LOADING

LATEST ISSUE: 2007/01/02

S0 FETS & POWER SEQUENCING & PGOOD

C7003

1 2

CERM

0.0022UF

10%
50V

402

C7004

1 2

CERM

50V

0.0022UF

10%

402

C7005

1 2

402

50V

10%

0.0022UF

CERM

U7000

18
13
3
4

21
8
16
15

1

2
5
6
7

10

11
19
22

9

24

25

20
12
17
14

23

CRITICAL

QFN

ISL6130IRZA

R7002

1

2

4.87K

MF-LF

1%
1/16W

402

R7001

12

1%
1/16W

402

MF-LF

30.9K

R7004

1

2

MF-LF
402

7.5K

1%
1/16W

R7006

1

2

13.7K

1/16W
402

MF-LF

1%

C7023

1

2

10%

0.022UF

16V
402

CERM-X5R

C7022

1

2

0.01UF

10%

NOSTUFF

16V
CERM
402

C7021

1

2

10%
402

CERM

16V

NOSTUFF

0.01UF

C7000

1

2

6.3V
10%

1UF

CERM
402

U7002

4

2

3

1 5

6

SOT23-6

TPS3808-1.25V

CRITICAL

C7001

1

2

0.1UF

10%
16V
X5R
402

C7002

1

2

0.001UF

10%
50V

402

CERM

Q7007

3

5

4

SSM6N15FE

SOT563

R7012

1

2

402

100K

MF-LF

5%
1/16W

R7003

12

MF-LF
402

1%
1/16W

28.7K

R7005

12

1/16W
MF-LF

1%

22.1K

402

R7040

12

330

5%
MF-LF

1/16W
402

Q7007

6

2

1

SSM6N15FE

SOT563

R7030

12

100K

5%
1/16W
MF-LF
402

R7031

12

1/16W
402

330

5%
MF-LF

C7030

1

2

10%
16V

402

CERM

0.01UF

R7050

12

402

1/16W

5%

10K

MF-LF

C7040

1

2

0.0012UF

10%
50V
CERM
402

R7051

12

1/16W
MF-LF

5%

330

402

C7050

1

2

50V

0.001UF

402

10%
CERM

R7041

12

100K

1/16W

5%
MF-LF

402

C7024

1

2

CERM

0.01UF

402

10%
16V

NOSTUFF

R7007

1 2

MF-LF

1/16W

5%

47

402

Q7001

1
2
5
6 3

4

CRITICAL

SOT6

FDC655BN

Q7004

1
2
5
6 3

4

CRITICAL

SOT6

FDC655BN

Q7006

3

5

4

SSM6N15FE

SOT563

Q7006

6

2

1

SOT563

SSM6N15FE

R7061

1

2

5%

470K

1/16W
MF-LF
402

Q7000

5

4

1

2

3

CRITICAL

MICROFET3X3

FDM6296

SYNC_DATE=05/31/2006

SYNC_MASTER=DSIMON-WF

S0 FETS & Power Sequencing

58

01

76

051-7455

376S0445376S0448

Q7000

?

RUNSS_GATE_D

S0SEQ_BEGIN

TP_DLY_ON_C

PGOOD_1V05S0

P3V3S0_EN

DLY_OFF_C
DLY_OFF_D

DLY_OFF_A
DLY_OFF_B

TP_DLY_ON_D

TP_DLY_ON_B

TP_DLY_ON_A

=PP5V_S5_FET

ALL_SYS_PWRGD

=PP3V3_S0_FET

ALL_SYS_PWRGD_AND

MAKEBASE=TRUE

1V05S0_RUNSS

=PP3V3_S0_FET

=PP5V_S0_FET

ALL_SYSPWRGD_DLY

PGOOD_1V5S0

=PP1V8_S3_FET

1V5S0_RUNSS_BUF

RUNSS_GATE_D_L

=PP5V_S5_FET

1V05S0_RUNSS_BUF

1V25S0_RUNSS_BUF

RUNSS_GATE_D_L

1V25S0_RUNSS

=PP3V3_S0_FET

=PP3V3_S0_FET

1V5S0_RUNSS

RUNSS_GATE_D_L

=PP3V3_S0_FET

=PP3V3_S0_FET

=PP3V3_S5_FET

=PP1V8_S0_FET

=PP1V25_S0_FET

PGOOD_1V8S3

PM_SLP_S3_L

S0PWRGD_5V_DIV
S0PWRGD_3V3_DIV
S0PWRGD_1V8_DIV

=PP1V8_S0_FET

P1V8S0_EN

P5VS0_EN

PGOOD_SEQUENCER

=PP5V_S0_FET

=PP5V_S5_FET

58D3

58D3

58D3

58D3

58D3

58C4

62B8

58C4

58C4

58C4

58C4

58C3

58C3

45A6

65B5

58C3

58C3

65B5

58C3

58B8

58B8

58B8

44C5

65B5

58D5

44D8

58B8

58B3

58D5

58B8

58B3

58B3

58B3

65C4

35C7

58C6

58B3

27A5

58B3

58A3

58D4

58C6

58C2

58A3

58A3

61B5

58C2

58A3

58A3

65A5

58C4

33C7

58B8

58C8

58B3

61A6

7C1

6B2

7D6

61B5

7D6

7A8

61A3

7B4

58C2

7C1

58B2

64B6

7D6

7D6

6D7

58B2

7D6

7D6

7D1

7B8

7C7

62A3

24D3

7B8

7A8

7C1

IN

IN

OUT

IN

OUT

IN

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT*
NTC

VR_ON
PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3
VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1
BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

LATEST ISSUE: 2007/01/23

MIN_LINE_WIDTH

IMVP6 CPU VCORE REGULATOR

(IMVP6_COMP)

NOTE 1: C7132,C7133 = 27.4 OHM FOR VALIDATING CPU ONLY.

(IMVP6_VO)

PWM FREQ. = 300 kHz
MAX CURRENT = 44A

MPC1055LR36
DCR=0.8mOhm

(IMVP6_ISEN1)

MIN_NECK_WIDTHMIN_LINE_WIDTH

MIN_NECK_WIDTH

(IMVP6_PHASE1)

(IMVP6_ISEN2)

(IMVP6_PHASE2)

1

(IMVP6_VSUM)
(IMVP6_VO)

ERT-J1VR103J

1-Phase DCM

1-Phase CCM

0

DPRSLPVR

1
0

PSI*

0

10 1

DPRSTP*

MIN_NECK_WIDTH

1

1-Phase DCM

(IMVP6_FB)

1

2-Phase CCM

Operation Mode

0

(GND)

0

(GND)

FROM SMC

ERT-J0EV474J

MPC1055LR36
DCR=0.8mOhm

(IMVP6_VW)

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

MIN_LINE_WIDTH

C7100

1

2

0.0022UF

NO STUFF

10%
CERM

402

50V

XW7100

1

2

SM

OMIT

C7190

1

2

0.0022UF

CERM

50V

10%

402

NO STUFF

R7100

1 2

MF-LF

1%

402

1/16W

10K

R7101

1

2

3.65K

1/16W
MF-LF
402

1%

C7115

1

2

0.1UF

X5R

16V
402

10%

R7116

1

2

1/16W

1%
MF-LF

13.7K

402

R7115

1

2

402

MF-LF

1/16W

11K

1%

R7105

1 2

MF-LF

1%

10K

1/16W
402

C7104

1 2

402

6.3V
CERM-X5R

10%

0.22uF

R7143

1

2

MF-LF

3.65K

402

1%
1/16W

L7101

1 2

CRITICAL

0.36UH-30A-0.80MOHM

MPC1055-SM

L7100

1 2

0.36UH-30A-0.80MOHM

CRITICAL

MPC1055-SM

C7102

1

2

0.0022UF

10%
50V
CERM

402

NO STUFF

C7192

1

2

50V
CERM

NO STUFF

10%

402

0.0022UF

C7127

1

2

0.1UF

402

X5R

16V

10%

R7120

1 2

MF-LF

1/16W
402

5%

10

R7112

1 2

10

1/16W
402

MF-LF

5%

C7126

1

2

402

10%

1UF

CERM

6.3V

C7196

1

2

0.01UF

16V

10%
CERM

402

R7121

1 2

MF-LF

1/16W

10

5%

402

C7130

1

2

X5R

16V

0.1uF

402

10%

R7113

1 2

1K

NO STUFF

MF-LF

1/16W

1%

402

R7109

1

2

1K

MF-LF

1/16W

1%

402

R7111

1

2

255

MF-LF

1/16W

1%

402

C7114

1

2

CERM

50V

470PF

402

10%

R7114

1

2

97.6K

MF-LF

1/16W

1%

402

C7113

1

2

220PF

5%
25V

402

CERM

C7107

1

2

10%
CERM

50V

0.001UF

402

R7110

1

2

402

1%
1/16W
MF-LF

6.81K

R7117

1 2

402

4.32K

1%
1/16W
MF-LF

R7118

1

2

1/16W
402

1%

1K

MF-LF

C7129

1

2

50V

5%

402

CERM

180pF

C7128

1

2

402

0.22UF

6.3V

10%
CERM-X5R

C7131

1 2

10%

0.068UF

402

CERM

10V

C7132

1 2

NO STUFF

0.01UF

10%
16V

402

CERM

C7133

1 2

X7R
402

10%
16V

0.018UF

R7122

1

2

402

5%

0

1/16W
MF-LF

R7123

1

2

402

5%

0

1/16W
MF-LF

C7134

1

2

10%
X5R

16V
402

0.033UF

C7135

1

2

X5R

10UF

6.3V

20%

603

R7127

1 2

402

1%
1/16W
MF-LF

4.02K

NO STUFF

C7110

1 2

CERM

0.01uF

NO STUFF

16V
402

10%

C7105

1 2

0.015uF

16V

10%

402

X7R

R7108

1 2

147K

402

1%
1/16W
MF-LF

C7106

1

2

0.001UF

50V
CERM
402

10%

C7116

1

2

NO STUFF

50V

10%

CERM
402

0.001UF

R7130

1

2

1/16W
MF-LF

1%

402

3.92K

C7121

1 2

10%

6.3V
402

0.22uF

CERM-X5R

C7103

1 2

10%

402

6.3V
CERM-X5R

0.22uF

R7104

1 2

MF-LF

1/16W
402

1

5%

R7107

1 2

402

MF-LF

1/16W

1

5%

R7131

1

2

CRITICAL

10KOHM-5%

0603-LF

R7145

1

2

1%

MF-LF

499

1/16W

402

R7126

1 2

NO STUFF

CRITICAL

470K

402

R7125

1 2

402

0

5%
1/16W
MF-LF

R7124

1 2

402

MF-LF

0

5%
1/16W

R7106

1 2

NO STUFF

0

402

1/16W
MF-LF

5%

C7109

1

2

16V

33UF

CRITICAL

POLY

20%
CASED2E-SM

C7117

1

2

33UF

20%

CRITICAL

CASED2E-SM

POLY

16V

C7101

1

2

CASED2E-SM

CRITICAL

33UF

20%
16V
POLY

C7108

1

2

20%

33UF

CASED2E-SM

POLY

CRITICAL

16V

C7118

1

2

X5R

1UF

603

25V

10%

C7199

1

2

1UF

25V

10%
X5R

603

Q7100

5

4

1 2 3

RJK0305DPB

CRITICAL

LFPAK

Q7101

5

4

1 2 3

CRITICAL

LFPAK

RJK0301DPB

Q7104

5

4

1 2 3

CRITICAL

RJK0301DPB

LFPAK

Q7102

5

4

1 2 3

CRITICAL

LFPAK

RJK0305DPB

Q7103

5

4

1 2 3

CRITICAL

RJK0301DPB

LFPAK

Q7105

5

4

1 2 3

RJK0301DPB

CRITICAL

LFPAK

U7100

48

36
26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

ISL9504BCRZ

CRITICAL

QFN

R7146

1 2

1%
MF-LF

1/16W
402

4.53K

NO STUFF

R7152

1 2

402

MF-LF

1/16W

1%

10K

NO STUFF

R7151

1 2

NO STUFF

10K

1%

402

MF-LF

1/16W

SYNC_MASTER=POWER

SYNC_DATE=07/13/2005

051-7455

IMVP6 CPU VCore Regulator

59 76

01

128S0093

KEMET T520V336M016ATE0457650

C7101,C7108

?

128S0092

128S0093

KEMET T520V336M016ATE0457650

128S0092

C7109,C7117

?

1.5 MM

0.25 MM

IMVP6_LGATE1

1.5 MM

0.25 MM

IMVP6_PHASE1

IMVP6_COMP

IMVP6_VO

IMVP6_RTN

IMVP6_VSEN

IMVP6_VSUM

IMVP6_DROOP

IMVP6_OCSET

IMVP6_ISEN2

IMVP6_LGATE2

IMVP6_PHASE2

IMVP6_UGATE2

IMVP6_ISEN1

IMVP6_LGATE1

IMVP6_PHASE1

IMVP6_UGATE1

IMVP6_BOOT2_RC

IMVP6_BOOT1_RC

0.25 MM

1.5 MM

IMVP6_UGATE1

0.25 MM0.25 MM

IMVP6_ISEN1

IMVP6_FB

IMVP6_VDIFF_RC

IMVP6_VR_TT

IMVP6_BOOT1
IMVP6_BOOT2

IMVP6_FB2

MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM

0.25 MM0.25 MM

IMVP6_ISEN2

IMVP6_UGATE2

0.25 MM0.25 MM

0.25 MM 0.25 MM

IMVP6_LGATE2

0.25 MM

IMVP6_VSEN

0.25 MM

0.20 MM

IMVP6_OCSET

0.25 MM

CPU_VCCSENSE_N

IMVP6_VSUM

0.20 MM0.25 MM

0.50 MM 0.20 MM

GND_IMVP6_SGND

0.25 MM 0.20 MM

IMVP6_VO

0.20 MM0.25 MM

IMVP6_DROOP

0.20 MM0.25 MM

IMVP6_DFB

0.20 MM0.25 MM

IMVP6_SOFT

IMVP6_BOOT2

0.25 MM0.25 MM

0.20 MM0.25 MM

IMVP6_FB2

0.20 MM0.25 MM

IMVP6_FB
IMVP6_VW

0.25 MM0.25 MM

=PP3V3_S0_IMVP

0.20 MM0.25 MM

IMVP6_RBIAS

IMVP6_COMP_RC

IMVP6_BOOT1

0.25 MM 0.25 MM

IMVP6_RTN

0.25 MM0.25 MM

IMVP6_COMP

0.20 MM0.25 MM

IMVP_VR_ON

=PPVIN_S5_CPU_IMVP

CPU_VID<1>

IMVP6_VO_R

=PPVIN_S5_CPU_IMVP

IMVP6_VDIFF

0.20 MM0.25 MM

CPU_VCCSENSE_N

0.25 MM0.25 MM

CPU_VCCSENSE_P

0.25 MM 0.25 MM

VR_PWRGD_CK505_L

VR_PWRGOOD_DELAY

IMVP6_NTC

IMVP6_SOFT

CPU_PROCHOT_L

=PPVORE_S0_CPU_REG

IMVP6_NTC_R

IMVP6_VW

GND_IMVP6_SGND

IMVP6_RBIAS

IMVP_DPRSLPVR

IMVP6_PMON

IMVP6_PSI_L

CPU_DPRSTP_L

IMVP6_DFB

PM_DPRSLPVR

CPU_VCCSENSE_P

0.25 MM 0.25 MM

IMVP6_PHASE2

IMVP6_VDIFF

CPU_VID<0>

CPU_VID<2>

CPU_VID<3>

CPU_VID<4>

PP3V3_S0_IMVP6_3V3

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

GND_IMVP6_SGND

=PPVIN_S5_CPU_IMVP

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM
VOLTAGE=5V

PP5V_S0_IMVP6_VDD

=PP5V_S0_CPU_IMVP

CPU_VID<5>

SMC_CPU_ISENSE

CPU_VID<6>

59D8

59D8

70C3

70B3

59D4

70A3

59D4

59C2

70A3

70A3

45C3

22C4

70B3

70A3

59C2

59A4

59A4

59A4

59A4

59C8

59B6

59B6

59B7

59B7

48D7

70A3

48D7

59A5

59A5

27B5

45B5

59C8

59A4

15B6

24C3

59A4

70A3

70A3

70A3

70A3

59B7

48D7

70A3

48C1

70A3

59C6

59C6

6D7

48C5

59A4 59A4

59A4

48D5

59A4

59A6

59A6

59A6

59A6

59A8

59A8

59A8

59A8

59C6

59C6

59A4

59A8

59A6

59A4

59C6

59C6

59C6

59B5

59B6

10A6

59C6

59B7

48C5

48D5

59B6

59C7

59C6

59B7

59B7

59B7

7C4

6D7

59C6

59B6

6D7

7B1

10B7

7B1

59B7

10A6

10A6

27A7

15B6

59A4

9C5

7D8

59A4

59A4

6D7

70B3

27B2

9B2

59A4

15A6

10A6

59C6

59A4

10B7

10B7

10B7

10B7

59A4

7B1

7A7

10B7

44C5

10B7

R1-

R1+

R2

V-

V+

+

SOFT

VW

VSUM

VSS

VSEN

VR_ON

VO

VIN

VID1

VID0

VDIFF

UGATE

THRM_PAD

RTN

PVCC

PHASEPGOOD

PGND

OCSET

LGATE

FDE

FB

DROOP

DFB

COMP

BOOT

AF_EN

VDD

RBIAS

VID2
VID3
VID4

IMON

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

RENDER VCORE POWER SUPPLY

MIN_NECK_WIDTHMIN_LINE_WIDTHMIN_NECK_WIDTHMIN_LINE_WIDTH

PLACE C7221 NEAR U7201 PIN 7

PLACE RC CLOSE TO SMC

Placement Note:

NC

MAX CURRENT = 7.7A

PWM FREQ. = 333 kHz

LATEST ISSUE: 2006/12/22

I103
I104
I105
I106
I107
I108
I109
I110
I111
I112
I113
I114

I115
I116
I117
I118
I119
I120
I121
I122
I123
I124
I125

C7201

12

0.1UF

402

X5R

16V

10%

2

402

1/16W

1%
MF-LF

750

C7222

1

2

0.22UF

402

X5R

6.3V

20%

R7226

1 2

100

1%
1/16W

MF-LF

402

R7227

1 2

402

MF-LF

1/16W

1%

4.53K

C7223

1

2

402

0.1UF

X5R

16V

10%

U7201

3

2

6

1

8

5

4

7

CRITICAL

MSOP

INA326EA-250

C7203

1

2

470PF

CERM
402

10%
50V

R7200

1 2

MF-LF
402

5%
1/16W

10

R7207

1

2

402

MF-LF

1/16W

1%

200K

R7206

1

2

402

1/16W
MF-LF

1%

2.21K

R7205

1 2

0.002

CRITICAL

1206

MF-LF

1/4W

1%

U7200

30

17

5

11

10

6

32

28

21

3

20

31 19

22

1

9

2

33

18

16

7

23
24
25
26
27

14

12

29

8

15

13

4

QFN

CRITICAL

ISL6263B

R7201

1 2

1/16W
MF-LF
402

0

5%

R7220

1

2

1/16W
MF-LF

5%

30K

402

1

2

6.3V

20%
X5R

10UF

603

Q7200

5

4

1 2 3

LFPAK

CRITICAL

RJK0305DPB

Q7201

5

4

1 2 3

RJK0303DPB

CRITICAL

R7225

1 2

5%
402

1/16W
MF-LF

100K

L7200

1 2

CRITICAL

0.82UH-16.5A

IHLP2525EZ-SM

C7200

1

2

10%

0.01UF

X7R
402

25V

C7204

1

2

CERM
402

47PF

50V

5%

R7208

1 2

MF-LF

1/16W

1%

15.8K

402

C7205

12

0.001UF

CERM
402

10%
50V

C7206

1

2

16V
402

10%

0.1UF

X5R

R7209

1 2

402

MF-LF

1/16W

1%

1K

R7210

1 2

402

MF-LF

1/16W

2.94K

1%

C7207

12

10%
50V
CERM
402

330PF

R7212

1 2

402

MF-LF

1/16W

1%

2.21K

C7208

12

0.0018UF

50V
CERM

10%
402

R7211

1 2

402

MF-LF

1/16W

1.1K

1%

R7213

1 2

402

MF-LF

1/16W

1%

150K

C7209

12

50V

10%

680PF

CERM
402

R7214

1

2

402

MF-LF

1/16W

1%

6.98K

C7211

1

2

10%

0.001UF

CERM

50V
402

C7210

1

2

402

50V

5%
CERM

150PF

C7212

12

0.001UF

402

CERM

50V

10%

R7215

1

2

402

MF-LF

1/16W

0

5%

R7216

1

2

402

MF-LF

1/16W

0

5%

R7217

1 2

1/16W

1%

150K

402

MF-LF

C7215

12

16V

0.015UF

X7R

10%
402

R7218

1 2

402

MF-LF

1/16W

1%

4.53K

NO STUFF

R7203

1 2

1/16W

5%
MF-LF

402

1

R7202

1 2

402

1/16W

10

5%
MF-LF

C7202

1

2

2.2UF

6.3V

20%
CERM1

603

C7221

12

1UF

6.3V
CERM
402

10%

C7214

1

2

0.001UF

CERM

10%
50V

402

C7213

1

2

0.001UF

10%
50V
CERM
402

C7217

1

2

CRITICAL

POLY

16V

20%
CASED2E-SM

33UF

C7218

1

2

1UF

10%
603

25V
X5R

2

CASE-D2E-LF

2.5V

330UF

CRITICAL

20%
POLY

XW7200

1 2

SM

R7224

1 2

10K

1/16W
402

5%
MF-LF

R7221

1

2

NO STUFF

1%

10K

1/16W
MF-LF
402

R7223

1 2

5%
402

10K

1/16W
MF-LF

R7222

1

2

402

MF-LF

1/16W

1%

10K

NO STUFF

128S0092128S0093

?

KEMET T520V336M016ATE0457650

C7217

01

7660

SYNC_DATE=06/29/2006

Render VCore Supplies

051-7455

SYNC_MASTER=GPU

GCORE_VSUM

GCORE_VSEN

GFX_VID<1>

GFX_VID<0>

GCORE_VDIFF

GCORE_UGATE

GCORE_PVCC

GCORE_FB

GCORE_DROOP

GCORE_COMP

GCORE_BOOT

GCORE_AF_EN

GCORE_VDD

GCORE_RBIAS

GFX_VID<2>
GFX_VID<3>
GFX_VID<4>

0.3 MM

0.25 MM

GCORE_VSEN

0.3 MM

0.25 MM

GCORE_OCSET

0.3 MM

0.25 MM

GCORE_VW

0.3 MM

0.25 MM

GCORE_RTN

0.3 MM

GCORE_RBIAS

0.25 MM

0.3 MM

0.25 MM

GCORE_SOFT

0.3 MM

0.25 MM

GCORE_COMP
GCORE_FB

0.3 MM

0.25 MM

0.3 MM

GCORE_VDIFF

0.25 MM

0.3 MM

GCORE_FB_RC

0.25 MM

0.3 MM

GCORE_VDIFF_RC

0.25 MM

1 MM

GCORE_PHASE

0.25 MM

0.3 MM

GCORE_BOOT

0.25 MM

1 MM

GCORE_UGATE

0.25 MM

1 MM

GCORE_LGATE

0.25 MM

0.3 MM

GCORE_BOOT_RC

0.25 MM

0.6 MM

GND_GCORE_SGND

0.25 MM

0.3 MM

GCORE_VDD

0.25 MM

0.3 MM

GCORE_PVCC

0.25 MM

0.3 MM

GCORE_VIN

0.25 MM

0.3 MM

GCORE_DROOP

0.25 MM

0.3 MM

GCORE_VSUM

0.25 MM

GCORE_DFB

0.3 MM

0.25 MM

GND_SMC_AVSS

GPU_ISENSE_R1_N

GND_GCORE_SGND

=PP5V_S0_NB_GFX_IMVP

SMC_GPU1_ISENSE

GPU_ISENSE_VCC

GPU_ISENSE_R2

=PPVIN_S5_NB_GFX_IMVP

GCORE_VSUM_R

=PP3V3_S0_PDCISENS

GPU_ISENSE_R1_P

GPU_ISENSE

GCORE_BOOT_RC

GCORE_FB_RC

GCORE_VDIFF_RC

SMC_GPU1_ISENSE

=PP3V3_S0_NB_GFX_IMVP

GND_GCORE_SGND

GCORE_VIN

GCORE_SOFT

GFX_VR_EN

GCORE_PMON

GCORE_PHASE

GCORE_RTN

GCORE_VW

GCORE_LGATE

GCORE_FDE

=PPVCORE_S0_NB_GFX_IMVP

GCORE_OCSET
GCORE_DFB

GND_GCORE_SGND

C7220

1

C7219

R7204

1

LFPAK

OMIT

66C2 66B1 62C2 61C5 48C6 48C1 48B1

60D7

48A1

60D7

66C3

60C5

60D7

21B6

21B6

21B6

21B6

60C5

45B6

60A7

60C7

61C5

60B2

60A7

60C5

60A7

60A5

15B3

15B3

60A5

60A7

60A7

60A5

60A7

60A5

60A7

60A7

60A5

15B3

15B3

15A3

60C6

60B5

60B6

60B6

60D6

60C6

60B6

60B6

60B6

60B6

60B6

60C5

60C5

60C5

60C5

60C5

60A5

60D5

60D5

60C5

60B5

60B5

60B5

44C1

60A5

7A7

44A2

7B1

7C4

60A5

60A5

44A2

7C4

60A5

60A7

60A5

8B1

60A7

60A5

60A5

60A7

7B8

60A5

60A7

60A7

R1-

R1+

R2

V-

V+

+

V5FILT

DR_VH1

VO2VO1

VFB2VFB1

VBST2VBST1

V5IN

TRIP2TRIP1

TONSEL

THRM_PAD

PGOOD2PGOOD1

LL2

GND

EN2

EN1

DR_VL2

DR_VH2

PGND

DR_VL1

LL1

SYM(1 OF 2)

S

D

G

S

D

G

S

D

G

JUMPER

D

S

G

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

<Rd>

Vout = 0.758V * (1 + Ra / Rb)

"note: pu on pgood page"

put 6 vias under the thermal

1.5V/1.05V POWER SUPPLY

<Rc>

Routing Note:

The discharge path (VO1) should have
a dedicated trace to the output cap;
separate from the output voltage
sensing trace,

MAX CURRENT = 8A

Placement Note:

Placement Note:

R7361,C7305 close to U7300 pin 15.

separate from the output voltage

The discharge path (VO2) should have
a dedicated trace to the output cap;

Note: pu on PGOOD page

S0

Routing Note:

NC

C7301 close to U7600 pin 16.

sensing trace,

<Rb>

<Ra>

PLACE C7303 NEAR U7301 PIN 7

State

PM_SLP_S3_L

0.0V

LOW

PP1V05_S0

1.5VHIGH

S3/S5/G3Hot

PP1V5_S0

1.05V

0.00V

PLACE C7390,C7391

Placement Note:

NEAR NB

PWM FREQ. = 300 kHz

PWM FREQ. = 360 kHz
MAX CURRENT = 4A

pad (pin 25)

Routing Note:

LATEST ISSUE: 2006/12/22

PLACE RC CLOSE TO SMC

Vout = 0.758V * (1 + Rc / Rd)

C7306

1

2

0.22UF

6.3V

20%
X5R

402

R7305

1 2

4.53K

1%
1/16W
MF-LF
402

R7390

1 2

402

MF-LF

1/16W

1%

100

C7303

1

2

0.1UF

X5R

16V

10%

402

U7301

3

2

6

1

8

5

4

7

CRITICAL

MSOP

INA326EA-250

C7399

1

2

50V
CERM

470PF

402

10%

R7391

1

2

1%
MF-LF

402

1/16W

200K

C7390

1

2

6.3V
CERM

22UF

20%
805

R7302

1

2

0.002

CRITICAL

1/4W
1206

MF-LF

1%

R7392

1

2

2.21K

1/16W
MF-LF

1%
402

U7300

21 10

19 12

23

8

3

20 11

18

13

24 7

25

4

17 14

15

16

22 9

2 5

1 6

CRITICAL

TPS51124

QFN

Q7361

5

4

1 2 3

CRITICAL

SI7110DN

PWRPK-1212-8

R7364

1 2

MF-LF

1/16W

5%

0

402

C7364

12

X5R

10%
402

16V

0.1UF

L7360

1 2

CRITICAL

1.0UH-13A-5.6M-OHM

SM-IHLP

C7392

1

23

CRITICAL

2.0V

330UF

10%
TANT

D2T

C7380

1

2

33UF

POLY

16V

20%
CASED2E-SM

CRITICAL

C7381

1

2

25V

1UF

10%
X5R

603

R7367

1

2

20.0K

1/16W
MF-LF
402

1%

R7368

1

2

1%
1/16W
MF-LF
402

20.5K

R7365

1

2

402

3.74K

1%
MF-LF

1/16W

C7389

1

2

CERM
402

25V

220PF

5%

R7324

1 2

MF-LF

0

5%
1/16W

402

C7324

12

10%
402

X5R

16V

0.1UF

C7369

1

2

50V
CERM

5%

100PF

NO STUFF

402

Q7320

5

4

123

CRITICAL

PWRPK-1212-8

SI7110DN

5

4

123

CRITICAL

C7340

1

33UF

20%
POLY

16V

CRITICAL

C7341

1

2

25V
603

1UF

10%
X5R

1

R7325

1

2

1%

6.65K

1/16W
MF-LF
402

R7327

1

2

402

MF-LF

1/16W

1%

7.68K

R7328

1

2

20.0K

402

MF-LF

1/16W

1%

C7329

1

2

NO STUFF

50V

100PF

5%
402

CERM

C7301

1

2

6.3V
X5R

20%

10UF

603

R7361

1 2

1/16W

3.3

MF-LF

5%
402

C7305

1

2

1UF

402

10V

10%
X5R

XW7320

1 2

OPEN-SAWTOOTH

C7350

1

2

6.3V

20%

10UF

X5R
603

XW7300

1

2

SM

R7326

1

2

1/16W

274K

NO STUFF

1%
MF-LF

402

C7325

1

2

NO STUFF

16V
X5R

10%

0.1UF

402

C7328

1

2

NO STUFF

0.001UF

402

50V
CERM

10%

1 2

SM-IHLP

Q7360

5

4

1 2 3

FDM6296

MICROFET3X3

CRITICAL

C7398

1

2

25V

5%
402

CERM

220PF

C7351

1

2

603

X5R

20%

10UF

6.3V

KEMET T520V336M016ATE0457650

128S0093?128S0092

C7380,C7340

Q7360

?

376S0448 376S0445

1.5V / 1.05V Supplies

SYNC_MASTER=POWER

SYNC_DATE=07/13/2005

051-7455

61 76

01

NB_ISENSE_VCC

VOLTAGE=1.5V
MIN_LINE_WIDTH=1.5 mm
MIN_NECK_WIDTH=0.25 mm

PP1V5_S0_REG_P

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm

1V5S0_VH

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm

1V5S0_LL

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm

1V5S0_VL

PGOOD_1V5S0

=PPVIN_S5_1V05S0

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=1.05V
MIN_LINE_WIDTH=1.5 mm

=PP1V05_S0_REG

GND_SMC_AVSS

NB_ISENSE_R2

NB_ISENSE_R1_N

GND_1V51V05S0_SGND

1V05S0_VBST_RC

1V51V05S0_V5FILT

=PP1V5_S0_REG

=PP5V_S5_1V51V05S0

1V5S0_RUNSS

1V05S0_VH

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

1V5S0_VBST

1V5S0_VBST_RC

1V05S0_LL_RC

1V05S0_VBST

1V05S0_VL

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm

=PPVIN_S5_1V5S0

1V05S0_RUNSS

1V05S0_TRIP

NB_ISENSE

1V5S0_TRIP

NB_ISENSE_R1_P

1V05S0_LL

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm

=PP3V3_S0_PDCISENS

=PP1V05_S0_REG_R

SMC_NB_CORE_ISENSE

PGOOD_1V05S0

GND_1V51V05S0_SGND

1V05S0_VFB

1V5S0_VFB

2

PWRPK-1212-8

SI7108DNS

Q7321

1.0UH-13A-5.6M-OHM

L7320

CRITICAL

CASED2E-SM

2

C7352

330UF

20%

2.5V
POLY
CASE-D2E-LF

CRITICAL

OMIT

66C2 66B1 62C2

60B2 48C6 48C1 48B1 48A1

66C3

7D8

45B6

62C5

58B1

60C2

58A5

7A1

6B2

44C1

61A3

7C8

7C1

6D7

7A1

58D1

7C4 7D8

44A8

58A5

61B6

R1-

R1+

R2

V-

V+

+

VDDQSET

S3

COMP

VTT

THRM_PAD

DRVH

LL

PGND

CS_GND

CS

PGOOD

NC1

S5

NC0

GND

VTTGND

MODE

DRVL

VTTREF VLDOIN

VBST V5IN

VDDQSNS

VTTSNSV5FILT

SYM (1 OF 2)

S

D

G

S

D

G

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

using separate trace.

CONNECT VTTSNS TO C7507 PIN1

put 6 vias under the thermal pad

Routing Note:

Routing Note:

S3
S5/G3Hot

Routing Note:

using separate trace.

PLACE C7504 NEAR U7501 PIN 7

Placement Note:

Placement Note:

<Rb>

Q7521 PIN1,2.3
using Kevin connection.

Connect CS_GND to

Routing Note:

Placement Note:

PLACE XW7500,XW7501 NEAR C7542 PIN 2

NC

NC

S0

HIGH

PM_SLP_S4_L

HIGH

LOW

LOW

HIGH

LOW

1.8V

0.0V

1.8V

0.0V

0.9V

0.0V

PWM FREQ. = 400 kHz

PLACE RC CLOSE TO SMC

PM_SLP_S3_L

PP1V8_S3 PP0V9_S0

CONNECT VDDQSNS TO C7542 PIN1

PLACE C7543 NEAR NB

LATEST ISSUE: 2006/12/22

<Ra>

Vout = 0.75V * (1 + Ra / Rb)

State

1.8V/0.9V POWER SUPPLY

MAX CURRENT = 10.75A

R7561

1 2

5%

MF-LF

1/16W

100

402

C7505

1

2

402

0.22UF

X5R

6.3V

20%

R7503

1 2

1%

4.53K

402

MF-LF

1/16W

U7501

3

2

6

1

8

5

4

7

MSOP

CRITICAL

INA326EA-250

C7564

1

2

470PF

10%
CERM

50V
402

R7563

1

2

1%
1/16W

402

MF-LF

200K

R7560

1

2

1%
1/16W
MF-LF
402

2.94K

R7502

1

2

MF-LF

1/4W

1%
1206

CRITICAL

0.002

U7500

6

16

17

21

19

3

20

4
7

12

18

1310

11

25

141522

9

8

23

24

1

5

2

CRITICAL

TPS51116

QFN

1 2

SM-IHLP

R7500

1 2

402

MF-LF

5%

0

1/16W

C7509

1

2

0.1uF

10%
16V
X5R
402

1

2

16V

C7542

1

2

CASE-D2E-LF

2.5V

330UF

CRITICAL

POLY

20%

C7541

1

2

20%

10UF

6.3V
603

X5R

C7502

1

2

6.3V

20%

10UF

X5R
603

R7510

1

2

1%
1/16W
MF-LF
402

8.25K

R7507

1 2

402

MF-LF

1/16W

4.7

5%

XW7500

1 2

SM

R7521

1 2

402

MF-LF

1/16W

1%

28K

R7522

1 2

402

MF-LF

1/16W

20.0K

1%

C7503

1 2

CERM
402

5%
50V

C7501

1

2

10UF

6.3V
X5R
603

20%

C7540

1 2

X5R

0.033UF

10%
402

16V

C7507

1

2

10UF

X5R

6.3V

20%
603

C7508

1

2

603

20%

6.3V
X5R

10UF

C7500

1 2

1UF

10V
402

10%
X5R

XW7501

1 2

SM

C7543

1

2

330UF

POLY
CASE-C2

20%

2.5V

CRITICAL

1

2

X5R

10%
25V

603

1UF

C7504

1

2

402

10%
16V
X5R

0.1UF

Q7520

5

4

1 3

CRITICAL

Q7521

5

4

1 2 3

SI7108DNS

CRITICAL

PWRPK-1212-8

R7599

1 2

1/16W

402

MF-LF

5%

100K

01

7662

1.8V/0.9V Supplies

SYNC_MASTER=POWER

SYNC_DATE=07/13/2005

051-7455

KEMET T520V336M016ATE0457650

C7530

128S0093 128S0092

?

1V8S3_DRVH

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

1V8S3_LL

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.25 mm

=PP1V8_S3_REG

MIN_LINE_WIDTH=1.5 mm

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25 mm

=PP1V5_S0_REG

MEMVTT_VREF

MEM_ISENSE_R1_N

GND_1V8S3_VTTGND

1V8S3_VBST

PGOOD_1V8S3

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

1V8S3_DRVL

=PP1V8_S3_REG_R

MEM_ISENSE_R1_P

1V8S3_RUNSS

=PP3V3_S3_PDCISENS

1V8S3_CS

MEM_ISENSE

=PP3V3_S3_PDCISENS

GND_1V8S3_VTTGND

GND_1V8S3_SGND

MEM_ISENSE_R2

SMC_NB_1V8_ISENSE

MEM_ISENSE_VCC

GND_SMC_AVSS

=PP5V_S5_1V8S30V9S0

=PP0V9_S0_REG

1V8S3_VBST_RC

PM_SLP_S3_L

1V8S3_V5FILT

100PF

NO STUFF

1V8S3_VDDQSET

=PPVIN_S5_1V8S30V9S0

CRITICAL

20%

C7530

C7531

CASED2E-SM

POLY

33UF

SI7110DN

PWRPK-1212-8

2

1.0UH-13A-5.6M-OHM

L7520

CRITICAL

OMIT

OMIT

66C2 66B1 61C5 60B2

58B7

48C6

45A6

48C1

44C5

48B1

35C7

48A1

61B1

33C7

62A2

45B6

7B6

7C8

62A6

58B6

7B5

7A1

65C2

24D3

7A4

62C5

44A8

44C1

7D8

JUMPER

DRVL2

LL2

DRVH2

VBST2

EN2

EN3

EN5

VO2

PGOOD2

VREG5

CS1

PGND1

VIN

V5FILT

VREG3

CS2

PGND2

DRVL1

LL1

DRVH1

VBST1

EN1

PGOOD1

TONSEL

SKIPSEL

PWPD

VO1

VFB1

VREF2

VFB2

COMP2

COMP1

SYM (2 OF 3)

GND

JUMPER

S

D

G

S

D

G

S

D

G

D

S

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

MAX CURRENT = 7.5A

5V/3.3V POWER SUPPLY

S0/S3/S5

HIGH

0.0V

5.0V 3.3V

LOW

0.0V3.3V

3.3V

G3H

separate from the output voltage

NC

The discharge path (VO2) should have
a dedicated trace to the output cap;

Routing Note:

sensing trace,

<Rc>

NC

<Rb><Ra>

a dedicated trace to the output cap;

Routing Note:

State

PP3V3_G3H PP5V_S5 PP3V3_S5

PWM FREQ. = 280 kHz

LATEST ISSUE: 2006/12/22

Placement Note:

R7601,C7605 close to U7600 pin 20.
C7602 close to U7600 pin 22.
C7604 close to U7600 pin 21.
C7603 CLOSE TO U7600 PIN 19.
R7605,R7603 close to U7600.

MAX CURRENT = 5A

PWM FREQ. = 430 kHz

SMC_PM_G2_EN

The discharge path (VO1) should have

sensing trace,

separate from the output voltage

put 6 vias under the thermal pad

Routing Note:

(pin 33)

<Rd>

Vout = 1V * (1 + Rc / Rd)Vout = 1V * (1 + Ra / Rb)

XW7620

1 2

OPEN-SAWTOOTH

C7620

12

X5R

0.1UF

402

10%
16V

C7651

1

2

150UF

20%
CASE-B2

POLY

6.3V

CRITICAL

U7600

2

7

23

18

27

14

25 16

29 12

10

9

5

26 15

24

17

30 11

32

33

31

20

28 13

3

6

22

1

8

4

19

21

LLP

CRITICAL

TPS51120

C7650

1

2

603

10UF

X5R

6.3V

20%

C7622

1

2

5%
CERM

50V

22PF

402

C7605

1

2

1UF

402

10%
10V
X5R

R7603

1

2

5.90K

MF-LF
402

1%
1/16W

C7604

1

2

X5R
603

10UF

20%

6.3V

C7603

1

2

20%
603

10UF

X5R

6.3V

C7640

1

2

33UF

CRITICAL

POLY

20%
16V

CASED2E-SM

L7660

1 2

3.3UH

IHLP

CRITICAL

XW7660

1 2

R7627

1 2

CRITICAL

20K

0.1%
MF

1/16W
402

C7627

12

50V

NO STUFF

5%
CERM

100PF

402

R7628

1 2

CRITICAL

0.1%
MF

1/16W

8.66K

402

R7620

1 2

5%
402

1/16W
MF-LF

0

C7641

1

2

10%
X5R

1UF

25V
603

C7652

1

2

150UF

CRITICAL

20%

6.3V
POLY
CASE-B2

R7660

1 2

1/16W
MF-LF

5%
402

0

C7660

12

0.1UF

402

X5R

10%
16V

R7667

1 2

CRITICAL

20K

0.1%
MF

1/16W
402

R7668

1 2

CRITICAL

0.1%
MF

4.99K

1/16W
402

C7667

12

NO STUFF

CERM

50V

100PF

402

5%

C7600

1

2

10%
CERM

50V

0.001UF

402

C7681

1

2

10%
X5R

1UF

25V
603

C7680

1

2

CASED2E-SM

CRITICAL

POLY

16V

20%

33UF

C7692

1

2

150UF

6.3V
POLY

1

2

150UF

POLY

6.3V

20%

C7690

1

2

2.2UF

10%
16V

603

X5R

C7682

1

2

CASED2E-SM

POLY

16V

20%

33UF

CRITICAL

C7602

1

2

1UF

603

X5R

10%
25V

R7605

1

2

1%
MF-LF

402

7.87K

1/16W

R7601

1 2

4.7

1/16W

5%
MF-LF

402

XW7601

1 2

SM

Q7621

5

4

1 2 3

SI7110DN

PWRPK-1212-8

CRITICAL

Q7660

5

4

123

PWRPK-1212-8

SI7110DN

CRITICAL

L7620

1 2

IHLP

4.7UH

Q7661

5

4

123

PWRPK-1212-8

R7670

1

2

NO STUFF

100K

MF-LF

1/16W

5%
402

C7671

1

2

0.01UF

CERM
402

16V

10%

R7671

1

2

MF-LF

5%

100K

1/16W

NO STUFF

402

R7610

1 2

MF-LF

5%
1/16W

402

0

C7670

1

2

CERM

220PF

NO STUFF

5%
25V

402

Q7620

5

4

1 2 3

CRITICAL

MICROFET3X3

FDM6296

01

7663

5V/3.3V Supplies

051-7455

SYNC_DATE=07/13/2005

SYNC_MASTER=POWER

128S0093

KEMET T520V336M016ATE0457650

?

128S0092

C7682,C7680

128S0092128S0093

KEMET T520V336M016ATE0457650

C7640

?

Q7620

376S0445376S0448

?

KEMET T520V336M016ATE0457650

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

5VS5_DRVH

RSMRST_PWRGD

5V3V3S5_VREF

5V3V3S5_TONSEL

5VS5_DRVL

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm

=PPVIN_S5_3V3S5

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

3V3S5_LL

RSMRST_PWRGD

5V3V3S5_V5FILT

GND_5V3V3S5_SGND

=PP3V3_S5_REG

3V3S5_VBST

3V3S5_VBST_RC

5VS5_CS

5VS5_VBST_RC

=PP5V_S5_REG

GND_5V3V3S5_SGND

GND_5V3V3S5_SGND

5VS5_VREG

5V3V3S5_V5FILT

=PPVIN_S5_5VS5

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1 mm

5VS5_LL

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm

3V3S5_DRVH

5VS5_RUNSS

5V3V3S5_VREG3

3V3S5_CS

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm

3V3S5_DRVL

3V3S5_VFB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=1.5 mm

VOLTAGE=3.3V

PP3V3_S5_REG_P

3V3S5_RUNSS

5VS5_VBST

=PPVIN_S5_5VS5

PP5V_S5_REG_P

GND_5V3V3S5_SGND

5VS5_VFB

CRITICAL

OMIT OMIT

CRITICAL

CRITICAL

SI7110DN

20%

MIN_LINE_WIDTH=1.5 mm

OMIT

OPEN-SAWTOOTH

VOLTAGE=5V

OMIT

MIN_NECK_WIDTH=0.25 mm

CRITICAL

CASE-B2CASE-B2

C7691

63B4

63B5

63C4

63C4

63C4

63B6

45D5

45D5

63B6

63B6

63B4

63B6

65C5

63B4

44D8

7A1

44D8

63A4

63B4

7D3 7C3

63A4

63A4

63C4

7A1

6D7

65C5

63A4

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

RT
RUN/SS

SYNC/MODE

ITH

VFB

PGOOD

PVINSVIN

THERM

PAD

PGNDSGND

SW

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

<Rc>

NOTE: Be aware of pull-up on this signal.

Continuous

1.25V S0 REGULATOR

Connect RUNSS off-page to control
If unconnected, powers up with PVIN.

3.0A max output
(Switcher limit)

Vout = 0.8V * (1 + Ra / (Rb + Rc))

<Rb>

<Ra>

Vout = 1.2516V

3.425V G3H SUPPLY

LATEST ISSUE: 2007/3/8

NC

Supply needs to guarantee 3.31V delivered to SMC VRef generator

<Rb>

Vout = 1.25V * (1 + Ra / Rb)

<Ra>

PWM FREQ. = 1 MHz @16.5V

MAX CURRENT = 0.2A

Burst

C7793

1

2

805

22UF

6.3V

20%
CERM

R7791

1

2

402

MF-LF

1/16W

1%

348K

C7792

1

2

402

22pF

CERM

5%
50V

R7792

1

2

1%
402

MF-LF

1/16W

200K

L7790

1 2

CRITICAL

CDPH4D19F-SM

33uH

C7791

1

2

402

CERM-X5R

6.3V

10%

0.22uF

U7790

7

6

8

4

2

1 5

3

TSOT23-8

CRITICAL

LT3470

C7790

1

2

CRITICAL

10UF

10%
25V
X5R
1206-1

C7730

1

2

CERM-X5R
0805

4V

47UF

20%

C7729

1

2

CERM-X5R

4V

20%

47UF

0805

C7728

1

2

402

25V

1000PF

X7R

10%

R7723

1

2

47.0K

402

1/16W
MF-LF

1%

R7724

1

2

1/16W

402

MF-LF

1%

60.4K

R7725

1

2

402

1/16W
MF-LF

1%

23.2K

C7720

1

2

0805

CERM-X5R

4V

20%

47UF

U7720

13

6

7

12

10

3

15

1

2

11

4
5
8
9

16

17

14

CRITICAL

LTC3412A

QFN

L7720

2.2UH-3.25A

CRITICAL

IHLP1616BZ-SM

XW7700

1 2

SM

R7726

1

2

309K

402

1/16W
MF-LF

1%

C7725

1

2

470PF

402

50V

10%

CERM

R7727

1

2

NO STUFF

402

5%

0

MF-LF

1/16W

R7722

1

2

5%

1M

1/16W

402

MF-LF

R7728

1

2

1/16W

0

MF-LF
402

5%

C7724

1

2

402

100PF

5%

CERM

50V

R7721

1

2

402

1/16W

8.25K

1%

MF-LF

C7723

1

2

402

25V

1000PF

X7R

10%

3.42V/1.25V Switcher

7664

051-7455

SYNC_DATE=12/06/2005

SYNC_MASTER=ENET

01

GND_P1V2S3_SGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=0V

P1V25S0_VFB

P1V25S0_VFB_DIV

P1V25S0_ITH_RC

P1V25S0_MODE

P1V25S0_ITH

1V25S0_RUNSS

P1V25S0_RT

=PP3V3_S5_1V25S0

=PP1V25_S0_REG

MIN_LINE_WIDTH=0.6 mm

P1V25S0_SW

MIN_NECK_WIDTH=0.25 mm

=PPVIN_G3H_P3V42G3H

PP3V42G3H_SW

=PP3V42_G3H_REG

P3V42G3H_FB

P3V42G3H5_BOOST

58C1

7C1

7C8

7B1

7C3

NC

D

SG

IN

D

SG

IN

IN

D

SG

D

SG

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LATEST ISSUE: 2006/12/22

48 mOhm @4.5V

FDC638P
P-TYPE
65 mOhm @2.5V

0.098 A

3.3V S3 FET

RDS(ON)

0.051 A

FDC638P
P-TYPE

5V S3 FET

5V/3.3V S5 RUN/SS CONTROL

Open drain output

MOSFET

RDS(ON)

CHANNEL

LOADING

CHANNEL

MOSFET

LOADING

NC

S3 FETS & S3/S5 CONTROL

1.8V S3 RUN/SS CONTROL

U7870

2

31

5

4

SC70

CRITICAL

74LVC1G07

R7875

1

2

1/16W
MF-LF

10K

1%
402

Q7865

1

2

5

6

3

4

FDC638P

SM-LF

CRITICAL

C7801

1

2

50V

0.0022uF

10%

402

CERM

Q7866

1

2

5

6

3

4

CRITICAL

SM-LF

FDC638P

Q7859

3

5

4

SOT563

SSM6N15FE

R7806

1 2

402

MF-LF

1/16W

5%

10K

C7802

1 2

402

0.01UF

16V

10%
CERM

R7808

1 2

402

10K

MF-LF

1/16W

5%

R7805

1 2

5%

100K

1/16W
402

MF-LF

R7807

1

2

100K

5%

402

1/16W
MF-LF

Q7859

6

2

1

SOT563

SSM6N15FE

R7857

1 2

5%

470K

402

MF-LF

1/16W

R7856

1

2

402

1/16W

100K

5%
MF-LF

Q7860

3

5

4

SOT563

SSM6N15FE

Q7860

6

2

1

SOT563

SSM6N15FE

01

7665

S3 FET & S3/S5 Control

051-7455

SYNC_MASTER=DSIMON-WF

SYNC_DATE=06/12/2006

1V8S3_RUNSS

=PP3V3_S3_FET

PM_S4_STATE_L

3V3S5_RUNSS

=PP5V_S5_PWRCTL

P5VS3_EN_L

5VS5_RUNSS

SMC_PM_G2_EN

=PP3V42_G3H_PWRCTL

=PP5V_S3_FET

=PP3V3_S5_FET

SMC_PM_G2_EN_L

=PP5V_S5_FET

=PP3V3_S3_FET

P3V3S3_EN_L

=PP3V3_S5_FET

PM_SLP_S4_LS5V

PM_S4_STATE_L

65A6

58D5

65C4

44C5

65A5

58C6

65C4

44C5

65A4

33B7

63B5

58C5

58B3

65C3

58C5

33B7

62B8

7A6

24D3

63B4

7C1

6D7

44D5

7B1

7A5

7D1

7C1

7A6

7D1

24D3

GND

OUT

VIN+ VIN-

V+

GND

OUT

VIN+ VIN-

V+

ACSET

EN

CSIP

DCPRN

THRML_PAD

PGND

DCSET

LGATE

UGATE

BOOT

BGATE

DCIN

CSIN

SGATE

VREF

ACPRN

CSON

CSOP

VCOMP

ICOMP

VDDP

CELLS

VADJ

VDD

CHLIM

PHASE

FB

ACLIM

GND

D

SG

D

SG

D

SG

D

S G

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

V+

V-

GND

VCC

PGOOD

OUT

FB

IN

SHDN*

I.C.

THRML

PAD

D

G

S

D1

D3

D4

S3
S2

GATE

S1

D2

D1

D3

D4

S3
S2

GATE

S1

D2

D1

D3

D4

S3
S2

GATE

S1

D2

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PWM FREQ. = 300 kHz

LATEST ISSUE: 2006/12/22

Placement Note:

PLACE RC CLOSE TO SMC

PLACE RC CLOSE TO SMC

Placement Note:

PLACE NEAR R7908

NC

NC

NC

NC

NC

PLACE NEAR R7997

PBUS SUPPLY / BATTERY CHARGER

F7900

1 2

1206

7AMP

CRITICAL

XW7900

1 2

SM

R7903

1

2

NO STUFF

100K

5%
MF-LF

402

1/16W

D7900

12

SOD-123

B0530WXF

CRITICAL

C7940

1

2

10%

0.1UF

X5R
402

25V

R7997

1

2

0612

1W

0.5%

0.02

MF

CRITICAL

R7940

1

2

1%

88.7K

1/16W
402

MF-LF

C7975

1

2

402

6.3V
CERM

1UF

10%

R7941

1

2

402

MF-LF

1/16W

10K

1%

U7970

2

15

3 4

CRITICAL

SOT23-5

INA193

C7970

1

2

402

6.3V
CERM

10%

1UF

C7971

1

2

20%
X5R

6.3V
402

0.22UF

C7972

1

2

0.22UF

402

X5R

6.3V

20%

C7900

1 2

0.033uF

402

10%
16V
X5R

R7900

1 2

MF-LF

4.7

1/16W

5%
402

R7905

1 2

1/16W

402

18

MF-LF

5%

R7944

1

2

MF-LF

1/16W

1%

402

100K

R7902

1 2

NO STUFF

5%

100K

1/16W
MF-LF

402

C7903

1

2

10%

0.1UF

X5R
402

25V

R7970

1 2

1%

1/16W
MF-LF

402

4.53K

R7908

1 2

1W

0.5%

CRITICAL

0612

0.01

MF

R7971

1 2

4.53K

1%

1/16W
MF-LF

402

R7925

1 2

402

MF-LF

1/16W

1%

10K

R7920

1 2

3W
MF

5%
2525

27

C7941

1

2

X5R

10%

402

25V

0.1UF

C7916

1

2

NO STUFF

10%
50V

402

CERM

0.001UF

R7910

1 2

2.2

5%

1/16W
MF-LF

402

C7917

1

2

10%

NO STUFF

25V
X5R

0.1UF

402

C7902

1

2

1UF

10%
402

X5R

10V

C7981

1

2

50V

10%
CERM

0.0022UF

402

R7981

1 2

603

1%

49.9

MF-LF

1/10W

C7918

1

2

CERM

10V

0.22UF

10%

402

C7908

1

2

33UF

16V

20%
POLY

CASED2E-SM

CRITICAL

U7975

2

15

3 4

CRITICAL

INA193

SOT23-5

C7928

1

2

10%

0.01UF

CERM

16V
402

R7962

1 2

1/16W
MF-LF

1%

15.0K

402

R7963

1

2

1%
1/16W
MF-LF

44.2K

402

R7979

1 2

10K

5%
1/16W

MF-LF

402

C7927

1

2

402

10%
CERM-X5R

16V

0.022UF

R7960

1 2

1%

1/16W
MF-LF

15.0K

402

R7961

1

2

402

20.0K

1%
1/16W
MF-LF

R7969

1 2

402

MF-LF

5%

10K

1/16W

R7950

1

2

1%

100K

1/16W
MF-LF
402

C7967

1

2

10%
50V
CERM
402

470PF

U7900

8

23
27

17

14

2

7

20

19

22

21

25

24
28

1

5

10

3

12

11

16

18

29

15

9

4

26

13

6

CRITICAL

ISL6257HRZ

QFN

R7909

1 2

1%

1/16W
MF-LF

100K

402

R7968

1 2

2.37K

1%

MF-LF

402

1/16W

C7980

1

2

0.1UF

X5R

16V
402

10%

C7910

1

2

603

1UF

25V

10%
X5R

5

4

1 2 3

LFPAK

RJK0305DPB

Q7901

CRITICAL

Q7902

5

4

1 2 3

CRITICAL

LFPAK

RJK0305DPB

R7901

1 2

402

MF-LF

1/16W

56.2K

1%

R7967

1 2

MF-LF

1%

3.01K

1/16W

402

C7901

1 2

402

50V
CERM

10%

0.001UF

C7911

1 2

10%

1UF

402

10V
X5R

R7951

1

2

402

MF-LF

1/16W

1%

100K

R7906

1

2

5%

2.2

1/16W
MF-LF
402

D7922

1

3

SOT23

MMBD914XXG

Q7922

3

5

4

SOT563

SSM6N15FE

Q7922

6

2

1

SOT563

SSM6N15FE

Q7924

3

5

4

SOT563

SSM6N15FE

Q7924

6

2

1

SSM6N15FE

SOT563

Q7960

6

2

1

SSM6N15FE

SOT563

Q7960

3

5

4

SOT563

SSM6N15FE

Q7961

6

2

1

SSM6N15FE

SOT563

Q7961

3

5

4

SOT563

SSM6N15FE

C7950

1

2

1UF

25V

10%
603

X5R

C7907

1

2

603

1UF

10%
25V
X5R

C7905

1

2

22UF

20%

CRITICAL

25V
POLY
CASE-D2-LF

C7906

1

2

25V

20%

22UF

CRITICAL

CASE-D2-LF

POLY

R7964

1 2

MF-LF

1/16W

1%

NOSTUFF

402

2.43K

Q7950

6

2

1

SSM6N15FE

SOT563

Q7950

3

5

4

SSM6N15FE

SOT563

R7965

1 2

1%

MF-LF

1/16W
402

100K

U7901

1

2

3

4

5

6

CRITICAL

SOT563

TLV341

U7950

3

2

7

1

8

5

6

9

4

TDFN

MAX8719

CRITICAL

C7952

1

2

10%

603

X5R

25V

1UF

R7954

1

2

5%
MF-LF

1/16W

100K

402

C7951

1

2

603

25V
X5R

1UF

10%

R7953

1

2

402

22.6K

0.1%
MF

1/16W

CRITICAL

R7952

1 2

CRITICAL

0.1%-50PPM
MF-LF

1/16W

221K

402

D7950

1

2

3

BAT54CW-X-F

SOT-323

Q7940

3

1

2

FDN360P_NL

SOT-23

C7912

1

2

X5R

10V

1UF

402

10%

Q7900

5

6

7

8

4

1

2

3

CRITICAL

AO4409

SOI

C7904

1

2

X5R
402

10%

0.1UF

25V

CRITICAL

3

2

1

L7900

4.7UH

FDA1254-3SM

C7909

1

2

ELEC

16V

20%

6.3X5.5SM1

CRITICAL

100UF

Q7920

5

6

7

8

4

1

2

3

CRITICAL

AO4409

SOI

Q7921

5

6

7

8

4

1

2

3

AO4409

CRITICAL

SOI

R7930

1

2

470K

1%
1/16W
MF-LF
402

R7931

1

2

MF-LF

1/16W

330K

5%

402

R7922

1

2

1%

39.2K

1/16W
MF-LF
402

R7923

1

2

1%

35.7K

1/16W
MF-LF
402

C7920

1

2

CERM

16V

10%

0.01uF

402

C7921

1

2

X5R

16V
402

10%

0.1UF

C7924

1

2

CERM

16V

10%

402

0.01uF

NO STUFF

C7922

1

2

NO STUFF

0.01UF

16V
402

10%
CERM

C7923

1

2

0.1UF

X5R

16V

10%

402

128S0092128S0093

C7908,C7910

?

KEMET T520V336M016ATE0457650

AOS MOSFET

?

Q7900,Q7920,Q7921

376S0543376S0466

SYNC_DATE=08/19/2005

051-7455

01

66 76

SYNC_MASTER=SMC

PBUS Supply/Battery Charger

CHGR_DCIN

CHGR_VDD

=PP18V5_G3H_CHGR

GND_CHGR_SGND

PPVBAT_G3H_CHGR_REG

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

SMC_ENRGYSTR_LDO_EN

SMC_ENRGYSTR_LDO_PGOOD

LDO_FDBK

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PP18V5_S5_CHGR_SW_R

PPVBATT_G3H_PRE

BATT_POS_F

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

BYPASS_R_GATE

PPVBAT_G3H_CHGR_OUT

BATT_FET_GATE

PPVDCIN_G3H_PRE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

CHGR_SGATE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

CHGR_ACLIM_R

SMC_SYS_ISET_L

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

LDO_OUT

PPVBAT_G3H_CHGR_OUT

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

DCIN_ISENSE

CHGR_LGATE

GND_CHGR_SGND

CHGR_PHASE

CHGR_CSIN

CHGR_VREF

BATT_RC

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

BATT_ENABLE_L

CHGR_FB

CHGR_ACSET

SMC_BATT_ISET_L

CHGR_BOOT

=PP3V42_G3H_ACIN

CHGR_ACSET_RC

=PP3V42_G3H_ACIN

SMC_SYS_ISET

=PP3V3_S0_PBATTISENS

SMC_BATT_CHG_EN

GND_SMC_AVSS

GND_SMC_AVSS

SMC_BATT_TRICKLE_EN_L

CHGR_VDD

SMC_BATT_ISENSE

BYPASS_R_DRV

BATT_ISENSE

CHGR_VCOMP_RC

=PPBUSB_G3H

CHGR_PHASE_RC

CHGR_CHLIM_R

SMC_BC_ACOK

GND_CHGR_SGND

ACIN_ENABLE_GATE

=PPBUSA_G3H

CHGR_BGATE

CHGR_FB_R

CHGR_UGATE

CHGR_VCOMP

CHGR_ICOMP

CHGR_VDDP

CHGR_CSOP

CHGR_BOOT_RC

SMC_DCIN_ISENSE

CHGR_ACPRN

P3V42_G3H_ACIN_R

=PP3V3_S0_PDCISENS

CHGR_EN

=PP3V42_G3H_ACIN

CHGR_CHLIM

CHGR_ACLIM

CHGR_VREF_VF

SMC_BATT_ISET

66C2

66B1

62C2

62C2

61C5

61C5

60B2

60B2

48C6

48C6

48C1

48C1

57C7

66A8

66B8

48B1

48B1

57C3

66B8

66A5

66A5

45B6

48A1

48A1

45B6

45B6

61C5

66A8

66B8

45C5

57D5

66C2

66B5

66B8

57C4

57C4

44C8

45B6

45B6

44C8

44C5

66B5

60C2

57C4

44B5

66B5

7B1

66A8

44A2

44A2

57B2

6B1

6B1

66B5

7B1

7B1

44B5

7C4

6C1

44C1

44C1

6C1

66C6

44C5

7B3

6C1

66A8

7B3

44C5

7C4

7B1

6C1

IN

IO

IO

IN

SYM_VER-1

IO

IO

IO

IO

IO

IO
IO

IO

D

G S

D

G S

Y

B

A

G

D

S

SYM_VER-1

OUT

OUT

OUT

SGD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

THIS GND CONECTS TO CHASSIS GND

LCD I/F

Plexi: 516S0212

*Enclosure: 518S0364

CAMERA I/F

LCD + CAMERA CONNECTOR

(LVDS DDC POWER)

LVDS REFERENCE CURRENT,2.37K OHM PULL DOWN RESISTOR NEEDED

INVERTER CONNECTOR

518S0521

C9014

1 2

50V
402

CERM

10%

0.0022UF

R9000

1

2

1%
MF-LF

1/16W
402

100K

R9013

1 2

1%
1/16W
MF-LF

2.37K

402

R9016

1

2

1/16W

5%

10K

NOSTUFF

MF-LF
402

R9015

1

2

MF-LF

10K

5%
1/16W

402

NOSTUFF

C9012

1

2

X5R

6.3V

20%

10UF

603

C9011

1

2

0.1UF

402

10%
X5R

16V

L9005

1 2

0402-LF

FERR-120-OHM-1.5A

C9016

1

2

10%
50V

0.001UF

CERM

402

R9002

1

2

1/16W

5%
MF-LF

402

100K

L9007

1

2 3

4

CRITICAL

90-OHM-200MA

SM

L9008

1 2

120-OHM-0.3A-EMI

0402-LF

R9023

1 2

402

1/16W
MF-LF

5%

10K

J9001

1

10
11
12
13
14
15
16
17
18
19

2

20
21
22

23

24

25

26

3
4
5
6
7
8
9

F-RT-SM

CRITICAL

S-050162B

L9002

1 2

0402-LF

FERR-120-OHM-1.5A

L9003

1 2

0402-LF

FERR-120-OHM-1.5A

R9001

1 2

402

1%

100K

MF-LF

1/16W

Q9006

3

1

2

SOD-VESM

SSM3K15FV

Q9004

3

1

2

SOD-VESM

SSM3K15FV

U9053

2

1

3

5

4

CRITICAL

TC7SZ08AFEF

SOT665

C9059

1

2

402

16V

10%

0.1UF

X5R

Q9005

3

1

2

SOT723-3

NTK3142P

R9014

1

2

1%
MF-LF

1/16W

100K

402

C9002

1

2

100PF

CERM

5%
50V

402

C9003

1

2

402

CERM

100PF

5%
50V

C9000

1

2

402

50V

5%

100PF

CERM

C9015

1

2

402

CERM

10%

0.001UF

50V

C9010

1

2

10%

CERM

50V

0.001UF

402

C9008

1

2

0.001UF

50V

CERM

10%
402

J9000

5

6

1
2
3
4

CRITICAL

78171-0004

M-RT-SM

L9006

1

2 3

4

CRITICAL

90-OHM-200MA

SM

DZ9001

1

2

8V-100PF

NOSTUFF

402-1

CRITICAL

DZ9000

1

2

CRITICAL

402-1

8V-100PF

NOSTUFF

L9010

1 2

FERR-1000-OHM

0402

NOSTUFF

L9011

1 2

FERR-1000-OHM

NOSTUFF

0402

L9012

1 2

FERR-1000-OHM

0402

NOSTUFF

Q9003

1

2

5

6

3

4

CRITICAL

SOT-6

FDC606P

C9001

1

2

402

50V

5%

100PF

CERM

L9000

1 2

0402-LF

120-OHM-0.3A-EMI

L9001

1 2

0402-LF

120-OHM-0.3A-EMI

C9009

1 2

10%

CERM

50V
402

0.001UF

R9009

1

2

10K

5%
MF-LF

402

1/16W

R9008

1

2

10K

MF-LF
402

1/16W

5%

L9004

1 2

FERR-120-OHM-1.5A

0402-LF

C9013

1 2

50V

10%

CERM

402

0.0033UF

INVERTER,LVDS,TMDS

SYNC_DATE=06/23/2006

SYNC_MASTER=GPU

051-7455

67 76

01

=GND_CHASSIS_LVDS

MIC_HI_LVDS_CONN

MIC_LO_LVDS_CONN

LVDS_CTRL_DATA

=PP3V3_S5_LCD

LVDS_DDC_DATA

=GND_CHASSIS_LVDS

=GND_CHASSIS_LVDS

MIC_HI_LVDS_CONN

MIC_LO_LVDS_CONN

PP5V_S3_CAMERA_F

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

VOLTAGE=5V

VOLTAGE=3.3V

PP3V3_LCDVDD_SW_F

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

=USB2_CAMERA_N

=USB2_CAMERA_P

PP3V3_LCDVDD_SW

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

PLT_RST_L

=PP5V_S0_LCD

LCDVDD_PWREN_L_R

=PPBUS_S5_INV

INVT_CHGND

INV_BKLIGHT_PWM_L

VOLTAGE=5V

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM

PP5V_INV_F

LVDS_A_DATA_P<2>

LVDS_A_DATA_N<0>

LVDS_A_DATA_P<1>

LVDS_A_DATA_N<1>

LVDS_A_DATA_P<0>

USB2_CAMERA_CONN_P

USB2_CAMERA_CONN_N

LVDS_A_CLK_F_P

LVDS_A_CLK_F_N

LVDS_A_DATA_N<2>

LCDVDD_PWREN_L

LVDS_A_CLK_P

LVDS_BKLT_EN

INV_PWREN_F_L

=PP3V3_S0_LCD

LVDS_VDD_EN

=PP3V3_S0_LCD

LVDS_CTRL_CLK

LVDS_IBG

=PP5V_S3_CAMERA

MIC_LO_LVDS

MIC_SHIELD_LVDS

MIC_HI_LVDS

LVDS_A_CLK_N

=GND_CHASSIS_LVDS

PP3V3_S0_LCD_F

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

LVDS_DDC_CLK

=PP3V3_S0_LCD

=PP3V3_S0_LCD

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=5V

PP5V_INV

INV_PWREN_L

LVDS_BKLT_CTL

BKLIGHT_CTL

PPBUS_ALL_INV_CONN

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

INV_GND

67B2

67B2

67B2

67C6

67A6

67C6

67A4

67A6

67A6

67B7

67C6

67A4

67B7

67B7

67A2

14D5

67A2

67A4

27D4

71D3

71D3

71D3

71D3

71D3

71D3

71D3

67B5

67B5

14D5

71C3

71D3

67A2

67B5

67B5

8C8

67A2

12B1

7D1

14D5

8C8

8C8

67A4

67A4

8C2

8C2

23A6

7A7

7B1

8D8

6B1

6B1

14C5

14C5

14C5

14C5

14C5

14C5

14C5

14D5

7C4

14D5

7C4

12B1

14D5

7A4

14C5

8C8

14D5

7C4

7C4

14D5

6B1

6B1

OUT

OUT

OUT
OUT

OUT

OUT
OUT

TX0_P
TX0_N

TX1_N

TX1_P

TX2_P
TX2_N
TXC_P

SCLDDC
SDADDC

SDG_P

TEST

EXT_SWING

TXC_N

SGND1

SGND0

PGND2

AGND0

AGND1

AGND2

GND1

SPGND

GND0

HTPLG

A1

SDSDA

SDSCL

RESET*

EXT_RES

SDI_P
SDI_N

SDC_P
SDC_N

SDB_P
SDB_N

SDR_N

SDR_P

SDG_N

VCC1

VCC0

VCC2

AVCC0

AVCC1

PVCC1

PVCC2

SVCC0

SVCC1

SPVCC

OVCC

CORE

SDVO RCVR

I2C MASTER

INTER

TEXT MODE

CONFIG/

PRGRM

DIFF SIG

DATA

OUT

IN

IN

IN

IN

IN

IN

IN

IN

NC

OUT

OUT

IO

IO

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

R9200 INSURES ESD DIODE
CURRENT IS SMALL

5.5V TOL INPUT

MINI DVI CONN J9401

3.3V ACTIVE OUTPUT

PLACE R9200,U9201 CLOSE TO

TMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH

TMDS_I2C_SCL AND TMDS_I2C_SDA DON’T NEED TO CONNECT

ONE 0.1UF AND 1000PF FOR EACH PIN

ONE 0.1UF AND 1000PF FOR EACH PIN

MCH SDVO CHANNEL R,G,B,CLK SIGNAL TO TMDS CHIP

IF HIGH, ADDRESS=0X72

ADDRESS=0X70

NC

PLACE THE CAP NEAR THE NB SIDE

ONE 0.1UF AND 1000PF FOR EACH PIN

"Place R9250 near U2300.F12"

=PP3V3_S0_TMDS

402

MF-LF

1/16W

5%

100K

R9250

402X5R

16V10%

0.1UF

C9220

402X5R

10% 16V

0.1UF

C9219

402

MF-LF

1/16W

5%

10K

R9200

402

MF-LF

1/16W

270K

5%

R9213

2

TMDS_HTPLG_BUF

TMDS_HTPLG_R

TMDS_SDB_P

TMDS_SDC_P
TMDS_SDC_N

SDVO_CTRLCLK

PEG_D2R_N<1>

DVI_HOTPLUG_DET

=PP3V3_S0_TMDS

TMDS_TX_P<0>

TMDS_I2C_SCL

TMDS_TX_N<2>

TMDS_TX_P<2>

TMDS_TX_N<1>

TMDS_TX_P<1>

TMDS_TX_CLK_P

TMDS_EXT_SWING

TMDS_I2C_SDA

TMDS_TX_CLK_N

TMDS_TX_N<2>

TMDS_TX_P<1>

DVI_HOTPLUG_DET

=PP1V8_S0_TMDS

PEG_R2D_C_N<1>

PEG_R2D_C_P<1>

TMDS_SDR_N

TMDS_SDB_N

TMDS_TX_N<0>

TMDS_TX<1>

TMDS_TX<2>

TMDS_TX_CLK

PP1V8_S0_ANALOG_SDVO_F

PP3V3_S0_PVCC2_TMDS_F

PP3V3_S0_ANALOG_TMDS_F

PP1V8_S0_TMDS_F

TMDS_SDG_P
TMDS_SDG_N

TMDS_INT_P
TMDS_INT_N

PEG_R2D_C_N<0>

PP3V3_S0_PVCC1_TMDS_F

PP3V3_S0_ANALOG_SDVO_F

PEG_R2D_C_P<0>

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

VOLTAGE=3.3V

PP3V3_S0_PVCC1_TMDS_F

PP3V3_S0_ANALOG_SDVO_F

VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

=PP3V3_S0_TMDS

MIN_LINE_WIDTH=0.3MM

VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25MM

PP3V3_S0_PVCC2_TMDS_F

TMDS_RST_L

TMDS_TX_N<1>

TMDS_TX_CLK_N

TMDS_TX_CLK_P

PP1V8_S0_ANALOG_SDVO_F

MIN_NECK_WIDTH=0.25MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.5MM

PP3V3_S0_ANALOG_TMDS_F

=PP3V3_S0_TMDS

=PP3V3_S0_TMDS

=PP3V3_S0_TMDS

=PP1V8_S0_TMDS

TMDS_TX_P<0>

MIN_NECK_WIDTH=0.25MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5MM

PP3V3_S0_ANALOG_TMDS_F

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V8_S0_TMDS_F

TMDS_SDR_P

TMDS_TX_N<0>

TMDS_TX<0>

TMDS_TX_P<2>

=PP3V3_S0_TMDS

PEG_R2D_C_N<3>

PEG_R2D_C_P<3>

TMDS_EXT_RES

PEG_R2D_C_N<2>

PEG_R2D_C_P<2>

SDVO_CTRLDATA

76

SYNC_DATE=06/06/2005

EXTERNAL TMDS

01

68

SYNC_MASTER=GRAPHIC

051-7455

49.9

1%

MF-LF

1/16W

402

21

R9207

PEG_D2R_P<1>

21

10%
X5R

16V
402

0.1UF

2

1

C9221

10UF

20%
X5R

6.3V
603

2

1

C9204

10UF

20%
X5R

6.3V
603

2

1

C9213

1K

5%
MF-LF

1/16W
402

2

1

R9203

SOT-553

CRITICAL

74LVC1G17DRL

4

5

1 3

U9201

2

1

2

1

21

MF-LF
402

1/16W

5%

10K

2

1

R9206

1/16W
MF-LF

1%

49.9

402

21

R9210

49.9

1%

MF-LF

1/16W

402

21

R9240

1/16W

1%

402

MF-LF

49.9

21

R9239

MF-LF

1/16W

402

49.9

1%

21

R9209

1/16W
MF-LF

1%

49.9

402

21

R9208

49.9

1%

MF-LF

1/16W

402

21

R9238

1/16W
MF-LF

1%

49.9

402

21

R9237

21

16V

0.1UF

X5R

10%
402

2

1

C9248

402

10%
X5R

0.1UF

16V

2

1

C9247

0.1UF

16V

X5R

10%
402

2

1

C9246

X5R
402

0.1UF
10%

16V

2

1

C9245

16V

0.1UF

X5R

10%
402

2

1

C9244

0.1UF
10%

X5R
402

16V

2

1

C9243

16V

10%
X5R

0.1UF

402

2

1

C9242

16V
X5R

10%

0.1UF

402

2

1

C9203

0.1UF

10%
X5R

16V
402

2

1

C9202

16V
X5R

10%

0.1UF

402

2

1

C9211

0.1UF

10%
X5R

16V
402

2

1

C9209

0.1UF

10%
16V

402

X5R

2

1

C9207

5%

10K

MF-LF
402

1/16W

2

1

R9205

10%
X5R

16V
402

0.1UF

2

1

C9235

16V
X5R

10%

0.1UF

402

2

1

C9206

0.1UF

10%
X5R

16V
402

2

1

C9233

16V
X5R

10%

0.1UF

402

2

1

C9214

0.1UF

10%
X5R

16V
402

2

1

C9231

16V
X5R

10%

0.1UF

402

2

1

C9239

10%
CERM

50V

0.001UF

402

2

1

C9225

0.001UF

10%
402

50V
CERM

2

1

C9222

0.001UF

50V
CERM

10%
402

2

1

C9224

10%
CERM

50V
402

0.001UF

2

1

C9223

0.001UF

50V
CERM

10%
402

2

1

C9201

10%
CERM

50V

0.001UF

402

2

1

C9200

10%
CERM

50V

0.001UF

402

2

1

C9212

50V
CERM

10%
402

0.001UF

2

1

C9210

10%
CERM

50V
402

0.001UF

2

1

C9208

CERM

10%
50V

0.001UF

402

2

1

C9234

0.001UF

50V
CERM

10%
402

2

1

C9232

0.001UF

10%
CERM

50V
402

2

1

C9230

402

0.001UF

50V
CERM

10%

2

1

C9237

X5R

6.3V

20%

10UF

603

2

1

C9205

1%

249

MF-LF

1/16W
402

2

1

R9204

CRITICAL

LQFP

SIL1362ACLU

34

28

10

14
13

23
22

20
19

17
16

30

423648

3

45

39

4

5

37
38

32
33

40
41

46
47

43
44

9

8

2

26

11

27

1

29

31

7

25

35

21

15

24

18

12

6

U9200

0402-LF

FERR-120-OHM-1.5A

21

L9205

0402-LF

FERR-120-OHM-1.5A

21

L9204

0402-LF

FERR-120-OHM-1.5A

21

L9203

0402-LF

FERR-120-OHM-1.5A

21

L9206

0402-LF

FERR-120-OHM-1.5A

21

L9200

0402-LF

FERR-120-OHM-1.5A

21

L9201

10%
CERM

50V

0.001UF

402

2

1

C9236

0.1UF

10%
X5R

16V
402

2

1

C9238

10UF

20%

6.3V
X5R
603

2

1

C9240

402

10%
X5R

0.1UF

16V

2

1

C9241

TMDS_HTPLG

R9201

1%

1/16W

MF-LF

2.94K

R9202

1%

1/16W

MF-LF

2.94K

R9211

1%

1/16W

MF-LF

9.09K

MF-LF

1/16W

1%

R9212

9.09K

402

2

1

402

2

1

402

2

1

402

2

1

69C8

69C8

69C8

69C8

69C8

69C8

69C2

69C2

69C2

69C2

69C8

69C2

69C2

69B7

69B7

69B7

69B7

69C2

69B7

69B7

68D8

68D8

68D8

68D8

69B7

68D8

68D8

68C8

68C8

68C8

68C8

68D8

68C8

68C8

68B7

68B7

68B7

68B7

68C8

68B2

68B7

68B2

68B2

68B2

68B2

68B7

68B1

68B8

68B1

69B2

69B2

69B2

69B2

69B2

69A2

69A2

69B2

69B2

68D6

71D3

71D3

69B2

68D6

71D3

71D3

68B1

69B2

69A2 69A2

68D6

68B1

68B1

68B1

68D6 69B2 68B4

69B2

69B2

68B2

71D3

71D3

71D3

71D3

71D3

7C4

15A3

23A6

7C4

68D3

68C1

68C3

68D1

68D3

68C3

68C1

68B2

68B2

7B7

14C3

14B3

68D1

68D3

68C7

68B1

68D3

14C3

68C6

68D6

14B3

68C4

68C4

7C4

68C4

27D1

68B2

68B2 68B2

68C4

68B4

7C4

7C4

7C4

7B7

68B2 68B1

68B4

68B2

68B2

7C4

14B3

14B3

14C3

14B3

15A3

14C3

69C6

VCC

125

GND

A

Y

VCC

125

GND

A

Y

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

D

S G

D

S G

GND

VCC

DA

S1A
S2A

S1B
S2B

S1C
S2C

S1D
S2D

IN

EN_L

DD

DC

DB

IO

IO

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_5_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

NOTE: CRT_DDC_* ARE NOT 5V COMPLIANT

NC

PLACE R9452 R9453 CLOSE TO GMCH

PLACE R9454 R9455 CLOSE TO GMCH

PLACE R9450 R9451 CLOSE TO GMCH

NB VIDEO ALIASES

PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR THE CONNECTOR

TMDS(MINI DVI) INTERFACE

NC

Video Connectors

Isolation required for DVI power switch

EXTERNAL VIDEO (VGA) INTERFACE

PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR CONNECTOR

AND GROUND

A 1.3K OHM 1% RESISTOR IS REQUIRED BETWEEN CRT_IREF

DVI power DIODE on page 95 (D9500)

514-0376

F9404

1 2

0.5AMP-13.2V

CRITICAL

SM-LF

C9410

1

2

CERM

50V

10%
402

0.001UF

C9460

1

2

402

CERM

10V

20%

0.1UF

R9462

1

2

2.2K

5%

402

MF-LF

1/16W

R9463

1

2

5%

2.2K

402

1/16W
MF-LF

C9442

1

2

402

50V
CERM

33PF

5%

NOSTUFF

C9411

1

2

402

5%
CERM

50V

100PF

C9443

1

2

402

50V
CERM

5%

33PF

NOSTUFF

402

X5R

10%

C9421

1

2

0.1UF

16V

U9404

5

4

7

8

3

US

SN74LVC2G125DCU

CRITICAL

U9404

2

4

1

8

6

SN74LVC2G125DCU

US

CRITICAL

L9405

1

2 3

4

CRITICAL

1210-4SM1

90-OHM-100MA

L9406

1

2 3

4

1210-4SM1

90-OHM-100MA

CRITICAL

300-OHM-50MA

L9404

1

2 3

4

1210-4SM

CRITICAL

L9407

1

2 3

4

CRITICAL

90-OHM-100MA

1210-4SM1

Q9401

3

5

4

SSM6N15FE

SOT563

Q9401

6

2

1

SSM6N15FE

SOT563

R9422

1

2

402

2.2K

5%

MF-LF

1/16W

R9461

1 2

MF-LF

402

39

5%

1/16W

R9470

1 2

402

1/16W
MF-LF

5%

39

R9471

1 2

402

39

5%

MF-LF

1/16W

C9439

1

2

10%
16V
X5R

0.1UF

402

C9412

1

2

5%
CERM

100PF

50V
402

U9401

4

7

9

12

15

8

1

2

5

11

14

3

6

10

13

16

TS3V330

SOP

CRITICAL

R9451

1

2

75

402

1%
MF-LF

1/16W

R9453

1

2

75

MF-LF

1/16W

1%
402

R9450

1

2

75

1%
1/16W
MF-LF
402

R9452

1

2

75

1%
402

MF-LF

1/16W

R9455

1

2

402

MF-LF

1/16W

1%

75

R9454

1

2

402

MF-LF

1/16W

1%

75

R9466

1

2

1/16W
402

5%
MF-LF

2.2K

R9467

1

2

5%
1/16W
MF-LF

2.2K

402

FL9400

2 7

3 6

4 5

1 8

CRITICAL

MEA2010P-SM

210MHZ

D9401

12

1SS418

SOD-723

CRITICAL

MINI-DVI-M42-BLK

F-RT-TH

OMIT

31

27
19

363534

33

24

29

22

16

15

14

13

12

11

32

30

28

10

9

25

18

26

1

2

3

4

5

6

7

8

20

17

J9401

C9404

1

2

0.1UF

20%
10V
CERM
402

L9444

1 2

600-OHM-300MA

0402

R9460

1 2

402

1/16W
MF-LF

5%

39

R9469

1 2

1%

MF-LF

1/16W

1.21K

402

R9421

1

2

402

1/16W
MF-LF

5%

2.2K

740S0044 740S0028

F9404

?

514-0481

FANCY

CRITICAL

J9401

CONN,REC,MINI-DVI,32P,RA,TABS,BLK

1

051-7455

MINI-DVI CONNECTOR

SYNC_DATE=05/21/05SYNC_MASTER=EUGENE

7669

01

514-0480

NORMAL

CRITICAL

J9401

CONN,REC,MINI-DVI,32P,RA,TABS,MG3

1

=GND_CHASSIS_TMDS_DOWN

CRT_DDC_CLK

=PP3V3_S0_TMDS

TMDS_HTPLG

CRT_VSYNC_R

MAKE_BASE=TRUE

=GND_CHASSIS_TMDS_UPPER

TMDS_TX_CONN_N<0>

TMDS_TX_CONN_CLK_P

TMDS_TX_CONN_CLK_N

VGA_B

VGA_HSYNC

VGA_G

VGA_VSYNC

VGA_R

TMDS_TX_CONN_P<2>

TMDS_TX_CONN_N<1>

TMDS_TX_CONN_P<0>

PP5V_S0_DVIPORT_D

CRT_RED

MAKE_BASE=TRUE

CRT_BLUE

MAKE_BASE=TRUE

TV_C_DAC

=TV_C_RTN

=CRT_GREEN_L

=TV_B_RTN

=CRT_BLUE_L

=TV_A_RTN

TV_A_DAC

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

PP5V_S0_TMDS_FUSE

MAKE_BASE=TRUE

TV_A_DAC

=CRT_TVO_IREF

=TV_A_DAC

=TV_C_DAC

=CRT_VSYNC_R

CRT_HSYNC_R

MAKE_BASE=TRUE

=CRT_RED

=CRT_GREEN

CRT_GREEN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CRT_TVO_IREF

MAKE_BASE=TRUE

TV_C_DAC

CRT_HSYNC_LS_R

CRT_VSYNC_LS

CRT_HSYNC_R

SB_CRT_TVOUT_MUX_L

EXT_Y_G

EXT_C_R

CRT_GREEN

TMDS_TX_P<2>

TMDS_TX_P<1>

TMDS_TX_N<0>

TMDS_TX_P<0>

TMDS_TX_CLK_P

=CRT_RED_L

TMDS_TX_CLK_N

CRT_DDC_DATA

=GND_CHASSIS_TMDS_UPPER

VOLTAGE=5V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

PP5V_S0_DVIPORT

TV_DCONSEL<1>

=PP3V3_S0_NB

CRT_TVO_IREF

VGA_HSYNC

VGA_VSYNC

=PP3V3_S0_TMDS

CRT_HSYNC_LS

CRT_VSYNC_R

CRT_VSYNC_LS_R

CRT_BLUE

EXT_COMPVID_B

MIN_LINE_WIDTH=0.30 MM

=PP5V_S0_TMDS

VOLTAGE=5V

MIN_NECK_WIDTH=0.20 MM

MAKE_BASE=TRUE

TV_B_DAC

TV_DCONSEL<0>

=CRT_BLUE

=PP3V3_S0_TMDS

CRT_RED

TV_B_DAC

=TV_B_DAC

TMDS_TX_N<1>

TMDS_TX_N<2>

TMDS_TX_CONN_P<1>

TMDS_TX_CONN_N<2>

=CRT_HSYNC_R

PP5V_S0_DVIPORT

GPU_CRT_DDC_CLK

GPU_CRT_DDC_DATA

69C2

69C8

69C8

69B7

69B7

69C2

68D8

68D8

68D8

68C8

68C8

68C8

68B7

68B7

68B7

68B2

68B2

68B2

68B1

71C3

69C4

71C3

71C3

71C3

71C3

71C3

71C3

71C3

71C3

71C3

71C3

71C3

68C3

68D3

68D1

68D3

68C3

68C1

69A4

71C3

68B1

71C3

71C3

68B1

71C3

71C3

68D1

68C1

8A6

14B5

7C4

68A8

69C3

8C8

69C1

69C1

69A8

69B8

69D7

14B5

14B5

14B5

14B5

14B5

69D7

69B8

14A5

14C5

14B5

14A5

69C3

14B5

14B5 69A8

69D8

69A8

69D5

24D2

69D5

68B2

68B2

68B2

68B2

68B2

14B5

68B2

14B5

8C8

69B4

14B5

7C4

69D7

69B4

69B4

7C4

69D5

69D5

7A7

14B5

14B5

7C4

69D5

69D7

14B5

68B2

68B2

14B5

69D4

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

(FSB_CPURST_L)

(See above)

specifying a target differential impedance.

Intel says to route with 7 mil spacing without

NOTE: 7 mil gap is for VCCSense pair, which

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

(See above)

Most CPU signals with impedance requirements are 55-ohm single-ended.

ELECTRICAL_CONSTRAINT_SET

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3

CPU Signal Constraints

All FSB signals with impedance requirements are 55-ohm single-ended.

NOTE: Design Guide allows closer spacing if signal lengths can be shortened.

Some signals require 27.4-ohm single-ended impedance.

Design Guide recommends FSB signals be routed only on internal layers.

Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.

Design Guide recommends each strobe/signal group is routed on the same layer.

DG recommends at least 25 mils, >50 mils preferred

SPACING

NET_TYPE

PHYSICAL

CPU / FSB Net Properties

(See above)

(See above)

FSB (Front-Side Bus) Constraints

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.

DSTB complementary pairs are spaced 1:1 and routed as differential pairs.

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.

?

=2:1_SPACING

FSB_ADDR2ADDR

*

=1:1_DIFFPAIR=1:1_DIFFPAIR

FSB_DSTB_55S

=55_OHM_SE

*

=55_OHM_SE

Y

=55_OHM_SE

?

FSB_ADDR =3:1_SPACING

*

FSB_ADDR2ADDR

*

FSB_ADDR FSB_ADDR

FSB_ADDR2ADSTB

FSB_ADDR

FSB_ADSTB

*

FSB_DSTBFSB_DATA

*

FSB_DATA2DSTB

CPU_55S

=55_OHM_SE=55_OHM_SE

*

=55_OHM_SE

Y

=STANDARD =STANDARD

?*

CPU_GTLREF

25 MIL

051-7455

76

CPU/FSB Constraints

SYNC_DATE=06/08/2006

SYNC_MASTER=WFERRY

70

01

?

=3:1_SPACING

FSB_ADSTB

*

FSB_DATA2DATA

FSB_DATA

*

FSB_DATA

?

=2:1_SPACING

*

CPU_ITP

25 MIL

?

CPU_COMP

*

=2:1_SPACING

*

FSB_DATA2DATA

?

?

CPU_2TO1

*

=2:1_SPACING

=3:1_SPACING

*

FSB_DSTB

?

* Y

=27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE

CPU_27P4S

7 MIL 7 MIL

=3:1_SPACING

*

FSB_DATA2DSTB

??

=3:1_SPACING

*

FSB_ADDR2ADSTB

?

CPU_VCCSENSE

*

25 MIL

?

=2:1_SPACING

*

FSB_COMMON

=3:1_SPACINGFSB_DATA

* ?

=STANDARD

FSB_55S

=55_OHM_SE

*

=55_OHM_SE

Y

=55_OHM_SE

=STANDARD

CPU_55S CPU_ITP

XDP_TDI

XDP_TDI

CPU_55S CPU_ITP

XDP_TDO

XDP_TDO

CPU_55S CPU_ITP

XDP_TMS

XDP_TMS

CPU_55S CPU_ITP

XDP_TCK

XDP_TCK

CPU_55S CPU_ITP

XDP_TRST_L

XDP_TRST_L

XDP_BPM_L<4..0>

XDP_BPM_L

CPU_ITPCPU_55S

IMVP6_VSEN_P

CPU_VCCSENSE

CPU_27P4S
CPU_27P4S

IMVP6_VSEN_N

CPU_VCCSENSE

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_27P4S

IMVP6_VID<6..0>

CPU_2TO1

CPU_55S

CPU_2TO1

CPU_VID<6..0>

CPU_55S

ITP_CPURST_L

CPU_ITPCPU_55S

XDP_CLK_P

CLK_FSB_100D

CLK_FSB
CLK_FSB

CLK_FSB_100D

XDP_CLK_N

CPU_55S CPU_ITP

XDP_BPM_L5

XDP_BPM_L<5>

CPU_55S

NB_BSEL<2>

CPU_2TO1

CPU_COMP<3>

CPU_COMP

CPU_55S

CPU_COMP

NB_BSEL<0>

CPU_2TO1

CPU_55S

CPU_55S

CPU_GTLREF

CPU_GTLREF

CPU_GTLREF

CPU_55S

CPU_2TO1

IMVP_DPRSLPVR

PM_DPRSLPVR

CPU_2TO1

PM_DPRSLPVR

CPU_55S

CPU_55S

FSB_CPUSLP_L

FSB_CPUSLP_L

PM_THRMTRIP_L

CPU_2TO1

CPU_55S

PM_THRMTRIP_L

CPU_IERR_L

CPU_55S

CPU_IERR_L

CPU_2TO1

CPU_55S

CPU_BSEL2

CPU_BSEL<2>

FSB_DATA

FSB_DATA_GROUP2

FSB_D_L<47..32>

FSB_55S

FSB_DATA_GROUP1

FSB_DATA

FSB_D_L<31..16>

FSB_55S

FSB_COMMON

FSB_TRDY_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_55S

FSB_BPRI_L

FSB_COMMON

FSB_COMMON

FSB_ADS_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_55S

FSB_DBSY_L

FSB_COMMON

FSB_COMMON

FSB_55S

FSB_BREQ0_L

FSB_COMMON

FSB_DATA_GROUP0

FSB_55S

FSB_DATA

FSB_DINV_L<0>

FSB_COMMON

FSB_RS_L<2..0>

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_LOCK_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DRDY_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DPWR_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_HITM_L

FSB_COMMON

FSB_55S

FSB_CPURST_L

FSB_CPURST_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DEFER_L

FSB_COMMON

FSB_55S

FSB_ADDR

FSB_ADDR_GROUP0

FSB_55S

FSB_REQ_L<4..0>

FSB_DSTB_L_P<3>

FSB_DSTB

FSB_DSTB3

FSB_DSTB_55S

FSB_D_L<63..48>

FSB_DATA_GROUP3

FSB_55S

FSB_DATA

FSB_DSTB

FSB_DSTB_L_N<0>

FSB_DSTB_55S

FSB_DSTB0

FSB_DSTB

FSB_DSTB_L_P<0>

FSB_DSTB_55S

FSB_COMMON

FSB_BNR_L

FSB_COMMON

FSB_55S

FSB_DINV_L<3>

FSB_DATA_GROUP3

FSB_55S

FSB_DATA

FSB_DSTB_L_N<1>

FSB_DSTB

FSB_DSTB_55S

FSB_55S

FSB_DATA_GROUP0

FSB_DATA

FSB_D_L<15..0>

FSB_DSTB1

FSB_DSTB

FSB_DSTB_L_P<1>

FSB_DSTB_55S

FSB_DATA_GROUP1

FSB_DATA

FSB_55S

FSB_DINV_L<1>

FSB_COMMON

FSB_HIT_L

FSB_55S

FSB_COMMON

FSB_DINV_L<2>

FSB_DATA_GROUP2

FSB_DATA

FSB_55S

FSB_DSTB_L_P<2>

FSB_DSTB

FSB_DSTB2

FSB_DSTB_55S

FSB_DSTB_L_N<2>

FSB_DSTB_55S

FSB_DSTB

FSB_DSTB_L_N<3>

FSB_DSTB

FSB_DSTB_55S

FSB_ADDR_GROUP0

FSB_55S

FSB_A_L<16..3>

FSB_ADDR

FSB_ADSTB

FSB_ADSTB1

FSB_ADSTB_L<1>

FSB_55S

FSB_A_L<35..17>

FSB_ADDR_GROUP1

FSB_55S

FSB_ADDR

FSB_55S

FSB_ADSTB

FSB_ADSTB_L<0>

FSB_ADSTB0

CPU_FERR_L

CPU_FERR_L

CPU_55S

CPU_PROCHOT_L

CPU_PROCHOT_L

CPU_2TO1

CPU_55S

CPU_PWRGD

CPU_PWRGD

CPU_55S
CPU_55S

CPU_INTR

CPU_FROM_SB
CPU_FROM_SB

CPU_NMI

CPU_55S

CPU_INIT_L

CPU_55S

CPU_INIT_L

CPU_FROM_SB

CPU_SMI_L

CPU_55S

CPU_COMP

CPU_27P4S

CPU_COMP<0>

CPU_COMP

CPU_55S

CPU_STPCLK_L

CPU_FROM_SB

CPU_BSEL0

CPU_BSEL<0>

CPU_2TO1

CPU_55S

CPU_FROM_SB

CPU_DPSLP_L

CPU_55S

CPU_COMPCPU_COMP

CPU_COMP<1>

CPU_55S

CPU_COMP<2>

CPU_COMP CPU_COMP

CPU_27P4S

CPU_DPRSTP_L

CPU_55S

CPU_2TO1

CPU_DPRSTP_L

NB_BSEL<1>

CPU_55S

CPU_2TO1

CPU_FROM_SB

CPU_A20M_L

CPU_55S

CPU_FROM_SB

CPU_IGNNE_L

CPU_55S

CPU_2TO1

CPU_BSEL<1>

CPU_BSEL1

CPU_55S

12B3

45B3

59C8

59C7

12B3

12B5

12B2

12B2

12B3

12B3

59A5

59A5

59D8

22C2

13C5

13C5

13A5

13A3

13B5

13D5

13D3

45C3

22C4

46B2

22C4

9C6

9C6

9C6

9C6

9C6

12B2

59A4

59A4

59C7

12B2

29B8

29C8

24C3

13A5

15A6

29A6

13B5

9C4

13B3

13C3

13C3

13B3

13B3

13B3

13A3

13B3

13B3

13B3

13B3

12B5

13B3

9D8

13A3

9C2

13B3

13B3

13C3

13B3

13B3

13C5

13B3

13B3

13B3

13B3

13A3

13B3

13B3

13C3

13C3

13C3

13C3

22C2

45B5

12B1

22C4

22C4

22C4

22C4

22C4

29C6

22C4

15B6

29B8

22C4

22C4

29B6

9B7

9A7

9B7

9A7

9A7

9C6

10A6

10A6

10B7

75C3

75C3

9C5

15B6

9B3

15C6

9B4

59C7

15A6

9A2

9C6

9D6

9A4

9C2

9B4

9D6

9D6

9D6

9D6

9D6

9C4

9D6

9D6

9D6

9B2

9C6

9D6

9D6

9C8

9B2

9B2

9C4

9C4

9D6

9B2

9B4

9C4

9B4

9B4

9C6

9C2

9C2

9C2

9B2

9D8

9C8

9C8

9D8

9C8

9C5

9B2

9B8

9B8

9D6

9B8

9B3

9B8

9B4

9B2

9B3

9B3

9B2

15C6

9C8

9C8

9A4

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5

Video Signal Constraints

DG Says 30 mil spacing minimum

LVDS signals are 100-ohm +/- 20% differential impedence.

- 50-ohm +/- 15% from first to second termination resistor.

- 55-ohm +/- 15% from second termination resistor to connector.

CRT & TVDAC signal single-ended impedence varies by location:

DG Says 40 mil spacing minimum

DG Says 40 mil spacing minimum

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.

CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.

- 37.5-ohm +/- 15% from GMCH to first termination resistor.

PCI-Express / DMI Bus Constraints

CRT_SYNC

25 MIL

* ?

?*

25 MIL

TVDAC

*

TVDAC TVDAC

TVDAC_2TVDAC

?*

25 MIL

CRT

=STANDARD=STANDARD

Y*

=55_OHM_SE

CRT_55S

=55_OHM_SE =55_OHM_SE

LVDS_100D

=100_OHM_DIFF

Y*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

* Y

=100_OHM_DIFF

DMI_100D

=100_OHM_DIFF

CRT_50S

=50_OHM_SE

=STANDARD

* Y

=STANDARD

=50_OHM_SE =50_OHM_SE

?*

LVDS

20 MIL

01

SYNC_DATE=06/12/2006

NB Constraints

SYNC_MASTER=WFERRY

71

051-7455

76

20 MIL

?*

CRT_2CRT

?*

PCIE

20 MIL

CRT_SYNC2SYNC

CRT_SYNCCRT_SYNC

*

*CRT CRT

CRT_2CRT

20 MIL

CRT_SYNC2SYNC

?*

=100_OHM_DIFF

=100_OHM_DIFF

Y*

PCIE_100D

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

* ?

20 MIL

DMI

20 MIL

?*

TVDAC_2TVDAC

PEG_D2R_P<1>

PCIE_100D

PCIE

PEG_D2R_N<1>

PEG_R2D

PCIE_100D

PCIE

DMI_N2S_P<3..0>

DMI

DMI_N2S

DMI_100D

DMI_N2S_N<3..0>

DMI

DMI_100D

DMI_S2N

DMI_S2N_P<3..0>

DMI_100D

DMI

LVDS_100D

LVDS

LVDS_A_CLK_P

LVDS_A_CLK

LVDS_100D

LVDS_A_CLK_N

LVDS_A_CLK

LVDS

LVDS

LVDS_100D

LVDS_A_DATA_N<2..0>

LVDS_A_DATA

LVDS_100D

LVDS

LVDS_A_DATA_P<3>

LVDS_A_DATA3

LVDS_100D

LVDS

LVDS_A_DATA_N<3>

LVDS_A_DATA3

LVDS

LVDS_100D

LVDS_A_DATA_P<2..0>

LVDS_A_DATA

CRT_TVO_IREF

CRT_TVO_IREF

CRT

DMI_S2N_N<3..0>

DMI_100D

DMI

PEG_R2D_C_N<3..0>

PCIE_100D

PCIE

TV_B_DAC

TVDAC

TV_B_DAC

CRT_50S

CRT_HSYNC_R

CRT_SYNC

CRT_55S

CRT_SYNC

PEG_R2D_C_P<3..0>

PCIE_100D

PCIE

LVDS

LVDS_IBG

LVDS_IBG

CRT_BLUE

CRT_50S

CRT

CRT_BLUE

CRT_GREEN

CRT_50S

CRT

CRT_GREEN

CRT_RED

CRT_50S

CRT

CRT_RED

CRT_VSYNC_R

CRT_SYNC

CRT_55S

CRT_SYNC
TV_A_DAC

TV_A_DAC

TVDAC

CRT_50S

TV_C_DAC

TVDAC

TV_C_DAC

CRT_50S

68C6

23D2

68B6

68C6

68B6

68B6

23D2

23D2

23D2

67B3

67B3

67B2

67B2

69D8

15C3

14C3

69D7

69D5

68B6

67A8

69D5

69D5

69D5

69D5

69D7

69D7

14C3

14D3

15B3

15B3

15B3

14C5

14C5

14C5

14C5

69D7

15B3

14B3

69A8

69C3

14B3

14D5

69B8

69A8

69A8

69C3

69B8

69A8

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

Need to support MEM_*-style wildcards!

DDR2 Memory Bus Constraints

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

SPACING

NET_TYPE

Memory Net Properties

MEM_DATA2MEMMEM_DATA

*

MEM_DQS

MEM_DATA2MEMMEM_DATA

*

MEM_CMD

*

MEM_CLK2MEM

MEM_CTRL

MEM_CLK

*

MEM_CLK2MEM

MEM_CLKMEM_CLK

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

MEM_2OTHER

MEM_CTRL

* *

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_DATA

* *

MEM_2OTHER

MEM_DQS

**

MEM_2OTHER

MEM_CLK

**

MEM_DQS

MEM_DQS2MEM

*

MEM_CLK

MEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS MEM_CMD

*

MEM_DQS2MEM

MEM_DQS MEM_DQS

*

=4:1_SPACING

MEM_CLK2MEM

?

MEM_DATA2DATA

MEM_DATAMEM_DATA

*

MEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

MEM_CTRL2CTRL

=2:1_SPACING

* ?

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

MEM_CTRL

MEM_CMD2MEM

*

=3:1_SPACING

?

MEM_DATA2MEM =3:1_SPACING

* ?

MEM_DATA MEM_CTRL2MEM

*

MEM_CTRL

051-7455

72 76

01

Memory Constraints

SYNC_MASTER=WFERRY

SYNC_DATE=06/08/2006

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

MEM_CTRL MEM_CTRL2MEM

MEM_CLK

*

MEM_DQS2MEM

*

=3:1_SPACING

?

MEM_CMD

*

MEM_CTRL2MEMMEM_CTRL

*

MEM_DATA2MEMMEM_DATA

MEM_CLK

=1.5:1_SPACING

MEM_DATA2DATA

* ?

MEM_CTRL2MEM

*

=3:1_SPACING

?

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

25 MIL

MEM_2OTHER

* ?

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

=45_OHM_SE=45_OHM_SE

Y

=STANDARD

=45_OHM_SE

=STANDARD

*

MEM_45S

*

MEM_DATA MEM_DATA2MEMMEM_CTRL

MEM_CMD2CMD

*

=1.5:1_SPACING

?

*

MEM_CMD MEM_CMD

MEM_CMD2CMD

=55_OHM_SE =55_OHM_SE

* Y

MEM_55S

=STANDARD =STANDARD

=55_OHM_SE

=70_OHM_DIFF =70_OHM_DIFF

Y*

=70_OHM_DIFF =70_OHM_DIFF

=70_OHM_DIFF

MEM_70D

=85_OHM_DIFF

Y

MEM_85D

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

*

MEM_CMD

*

MEM_CMD2MEM

MEM_CLK

MEM_55S

MEM_DATA

MEM_B_DM3

MEM_B_DM<3>

MEM_A_CNTL

MEM_45S

MEM_CTRL

MEM_CKE<1..0>

MEM_A_CMD

MEM_A_CAS_L

MEM_55S MEM_CMD

MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_55S

MEM_DATA

MEM_55SMEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE1

MEM_A_DQ<15..8>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_55S

MEM_DATA

MEM_55S

MEM_A_DM1

MEM_DATA

MEM_A_DM<1>

MEM_DATA

MEM_55S

MEM_A_DM0

MEM_A_DM<0>

MEM_55S

MEM_DATA

MEM_A_DM2

MEM_A_DM<2>

MEM_A_DM<4>

MEM_55S

MEM_DATA

MEM_A_DM4

MEM_55S

MEM_DATA

MEM_A_DM3

MEM_A_DM<3>

MEM_A_DM<6>

MEM_55S

MEM_DATA

MEM_A_DM6

MEM_A_DQS_P<0>

MEM_A_DQS0

MEM_DQSMEM_85D

MEM_A_DQS_N<0>

MEM_DQSMEM_85D

MEM_A_DQS_N<1>

MEM_DQSMEM_85D

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_DQSMEM_85D

MEM_A_DQS3

MEM_A_DQS_P<3>

MEM_DQSMEM_85D

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_DQSMEM_85D

MEM_A_DQS_N<2>

MEM_DQSMEM_85D

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_DQSMEM_85D

MEM_A_DQS_N<3>

MEM_DQSMEM_85D

MEM_A_DQS_N<5>

MEM_DQSMEM_85D

MEM_A_DQS_N<4>

MEM_DQSMEM_85D

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_DQSMEM_85D

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_DQSMEM_85D

MEM_70D MEM_CLK

MEM_CLK_N<5..3>
MEM_CKE<4..3>

MEM_CTRL

MEM_45S

MEM_B_CNTL

MEM_CTRL

MEM_45S

MEM_CS_L<3..2>

MEM_B_CNTL

MEM_CMDMEM_55S

MEM_B_A<14..0>

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_WE_L

MEM_B_CMD

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_DATA

MEM_55SMEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_B_DQ<39..32>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DQ<47..40>

MEM_DATA

MEM_55S

MEM_B_DM0

MEM_B_DM<0>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_55S

MEM_DATA

MEM_B_DM2

MEM_B_DM<2>

MEM_55S

MEM_DATA

MEM_B_DM1

MEM_B_DM<1>

MEM_55S

MEM_DATA

MEM_B_DM5

MEM_B_DM<5>

MEM_55S

MEM_DATA

MEM_B_DM4

MEM_B_DM<4>

MEM_55S

MEM_DATA

MEM_B_DM6

MEM_B_DM<6>

MEM_55S

MEM_DATA

MEM_B_DM7

MEM_B_DM<7>

MEM_DQSMEM_85D

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_DQSMEM_85D

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_DQSMEM_85D

MEM_B_DQS_N<0>

MEM_DQSMEM_85D

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_DQSMEM_85D

MEM_B_DQS_N<1>

MEM_DQSMEM_85D

MEM_B_DQS_N<2>

MEM_B_DQS_N<3>

MEM_DQSMEM_85D

MEM_DQSMEM_85D

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_DQSMEM_85D

MEM_B_DQS_N<4>

MEM_DQSMEM_85D

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_DQSMEM_85D

MEM_B_DQS5

MEM_B_DQS_P<5>

MEM_DQSMEM_85D

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_DQSMEM_85D

MEM_B_DQS_N<5>

MEM_DQSMEM_85D

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_DQSMEM_85D

MEM_B_DQS_N<6>

MEM_DQSMEM_85D

MEM_B_DQS_N<7>

MEM_CLK_N<2..0>

MEM_CLKMEM_70D

MEM_A_CNTL

MEM_CS_L<1..0>

MEM_45S

MEM_CTRL

MEM_A_CNTL

MEM_ODT<1..0>

MEM_CTRL

MEM_45S

MEM_55S

MEM_A_CMD

MEM_A_A<14..0>

MEM_CMD

MEM_55S

MEM_A_CMD

MEM_A_BS<2..0>

MEM_CMD

MEM_A_CMD

MEM_A_RAS_L

MEM_55S MEM_CMD

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE3

MEM_A_DQ<31..24>
MEM_A_DQ<39..32>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_A_DQ<47..40>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE5

MEM_A_DM<7>

MEM_A_DM7

MEM_55S

MEM_DATA

MEM_A_DM<5>

MEM_55S

MEM_DATA

MEM_A_DM5

MEM_CLK_P<2..0>

MEM_A_CLK

MEM_70D MEM_CLK

MEM_A_DQS_N<7>

MEM_85D MEM_DQS

MEM_70D MEM_CLK

MEM_B_CLK

MEM_CLK_P<5..3>

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_DQSMEM_85D

MEM_A_DQS_N<6>

MEM_DQSMEM_85D

MEM_CMDMEM_55S

MEM_B_CAS_L

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_RAS_L

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_CMD

MEM_B_BS<2..0>

MEM_CTRL

MEM_45S

MEM_ODT<3..2>

MEM_B_CNTL

32B5 32A5

32C6

31C6

30C6

31C4

30C4

32D6

32D6

31B6

31B6

30B6

32C6

30D6

30B6

32A6

32D6

30A6

32D5

31B6

31B4

31B6

31B4

31A6

32D6

32D6

30B4

30C6

30D4

30B6

30B4

31C6

32D6

30C6

32B6

32B6

30D6

30C6

30D6

30A6

30A4

31D4

31C6

31B4

16C1

32A6

31D6

31D6

31C6

31C6

31B4

31A6

31A6

31A4

30D4

30B6

30B6

16C5

30B6

32B6

30C6

30B4

30A6

30D4

31D4

32A6

32A6

31B6

31B6

31C6

30C4

30B6

30B6

30D4

30C4

30D4

30A4

16B8

30D4

30D4

30C6

30B4

30C4

30A6

30D6

30D6

30D6

30D6

30C6

30C4

30C4

30B6

30C6

30B4

30B6

30B4

30A4

31A4

31C4

15D3

16B1

31B6

31D4

31D4

31C4

31C4

16C4

31A4

31A4

31D4

16B4

31C4

31D4

31A6

31B4

31A4

31A6

31D6

31D6

31D6

31C6

31D6

31C6

31C4

31C4

31B6

31B6

31A4

31A6

31B4

31A4

31A6

31A4

30A4

30B4

30B4

16B5

30B4

30B4

30C4

16C8

30A4

30A4

30B6

30A4

30A6

31A4

30A6

30A4

31B6

31B4

31B4

31B4

16C1

15D3

16D5

16B5

16D8

16C8

16C8

16B8

16A8

16D5

16D5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

16C5

15D3

15D3

15C3

15C6

16B1

16C4

16D4

16C4

16C4

16B4

16B4

16B4

16D1

16A4

16C1

16D1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

16C1

15D3

15D3

15C3

15C6

16D5

16B5

16C8

16B8

16B8

16C5

16C5

15D3

16C5

15D3

16C5

16C5

16D1

16B1

16D1

15C3

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Disk Interface Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9

SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17

HD Audio Interface Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1

Internal Interface Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

DG says minimum spacing 50 mils to clocks

USB 2.0 Interface Constraints

* ?USB

20 MIL

HDA

=1.8:1_SPACING

?*

Y

=55_OHM_SE =55_OHM_SE

SPI_55S

*

=55_OHM_SE

=STANDARD =STANDARD

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

* Y

USB_90D

USB_2CLK

25 MIL

* ?

SMB_55S

* Y

=55_OHM_SE=55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

01

7673

SYNC_DATE=06/12/2006

SB Constraints (1 of 2)

SYNC_MASTER=WFERRY

051-7455

*SPI

=1.8:1_SPACING

?

SATA

*

20 MIL

?

=1.8:1_SPACING

IDE * ?

=3:1_SPACING

SMB * ?

SATA_55S

=55_OHM_SE

=STANDARD

Y

=55_OHM_SE =55_OHM_SE

*

=STANDARD

*

=55_OHM_SE

IDE_55S

=STANDARD

=55_OHM_SE=55_OHM_SE

Y

=STANDARD

HDA_55S

=55_OHM_SE

* Y

=55_OHM_SE =55_OHM_SE

=STANDARD=STANDARD

=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

SATA_100D

=100_OHM_DIFF

=100_OHM_DIFF

Y

USB_60S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD=STANDARD

* Y

SPI_55S

SPI

SPI_CE_L<0>
SPI_CE_R_L<1>

SPI_CE_L1

SPI

SPI_55S

SPI_A_SO_R

SPI

SPI_55S

SPI

SPI_55S

SPI_SO

SPI_SO

SPI_55S

SPI

SPI_CE_L0

SPI_CE_R_L<0>

SPI_SI_R

SPI_SI

SPI_55S

SPI

SPI_55S

SPI

SPI_A_SI_R

SPI_A_SCLK_R

SPI_55S

SPI

HDA_SDOUT_R

HDA_55S

HDA

HDA_SDOUT

HDA_SDOUT

HDA

HDA_55S

HDA_SDIN0

HDA

HDA_55S

HDA_SDIN0

HDA_55S

HDA

HDA_RST_L_R

HDA_55S

HDA

HDA_SYNC_R

HDA_BIT_CLK_R

HDA_55S

HDA

HDA_BIT_CLK

HDA_55S

HDA

HDA_BIT_CLK

SATA

SATA_A_D2R_C_N

SATA_100D

HDA_SYNC

HDA_55S

HDA

HDA_SYNC

HDA_55S

HDA_RST_L

HDA

HDA_RST_L

USB_90D

USB

USB_EXTA_P

USB_EXTA

USB_EXTA_MUXED_N

USB

USB_90D

USB_MINI_N

USB

USB_90D
USB_90D

USB

USB_3G_P

USB_3G

USB_90D

USB

USB_3G_N
USB_CAMERA_P

USB_CAMERA

USB_90D

USB

USB_CAMERA_N

USB_90D

USB

USB_BT_P

USB_BT

USB_90D

USB

USB_BT_N

USB_90D

USB

USB_TPAD_P

USB_TPAD

USB_90D

USB

USB_IR_P

USB_IR

USB_90D

USB

USB_IR_N

USB_90D

USB

USB_EXTB_N

USB

USB_90D

USB_EXCARD_P

USB_EXCARD

USB

USB_90D

USB_EXCARD_N

USB

USB_90D

USB_EXTC_P

USB_EXTC

USB

USB_90D

SMB_55S

SMB

SMB_SB_SCL

SMB_CLK

SMB_SB_SDA

SMB

SMB_55S

SMB_DATA

SMB_55S

SMB

SMB_ME_DATA

SMB_SB_ME_SDA

SATA

SATA_A_D2R_C_P

SATA_100D

SATA_A_D2R_N

SATA

SATA_100D

SATA_A_D2R

SATA_A_D2R_P

SATA_100D

SATA

IDE_PDA<2..0>

IDE_55SIDE_PDA

IDE

IDE_PDCS1_L

IDE_55S

IDE

IDE_PDCS

IDE_55S

IDE

IDE_PDIOR_L

IDE_PDIOR_L

IDE_IRQ14

IDE_IRQ14

IDE_55S

IDE

SATA_A_R2D_C_N

SATA

SATA_100D

SATA_A_R2D_P

SATA_100D

SATA

SATA_A_R2D_N

SATA

SATA_100D

USB_90D

USB

USB_TPAD_N

USB_MINI_P

USB_MINI

USB_90D

USB

USB_EXTA_MUXED_P

USB

USB_90D

USB_90D

USB

USB_EXTA_N

ODD_RST_5VTOL_L

IDE_RST_L

IDE_55S

IDE

IDE_PDIOW_L

IDE

IDE_55S

IDE_CNTL

IDE_PDCS3_L

IDE_55S

IDE

IDE_PDCS

IDE_PDDREQ

IDE_CNTL

IDE

IDE_55S

IDE_PDD<15..0>

IDE_55S

IDE

IDE_PDD

IDE_PDIORDY

IDE_PDIORDY

IDE_55S

IDE

SATA_A_R2D_C_P

SATA_A_R2D

SATA_100D

SATA

IDE_CNTL

IDE_55S

IDE

IDE_PDDACK_L

USB_EXTB_P

USB_EXTB

USB

USB_90D

USB_90D

USB_EXTC_N

USB

USB_RBIAS

USB_RBIAS

USB_60S

SMB

SMB_55S

SMB_ME_CLK

SMB_SB_ME_SCL

SPI_SCLK

SPI_55S

SPI

SPI_SCLK_R

39C5

23C2

23C2

23C2

23C2

39B5

39C3

52C3

52C7

52C3

22B8

22C8

22C8

22C8

22C8

23C2

23C2

23C2

23C2

8C2

8B2

23C2

8C2

8C2

23C2

23C2

23C2

23C2

47D8

47D8

47A8

40D4

40C4

39B3

39B5

39C3

39B5

40D4

23C2

23C2

23C2

39A8

39B5

39B3

39C3

22C4

39B5

40D4

39B3

23C2

23C2

47A8

52C7

52C6

52C4

23C5

23C5

23C5

52C4

52C5

22B6

8A6

8A6

22C6

22C6

22C6

8A6

40D7

8A6

8A6

8C1

8C1

8C1

8C1

8C1

8B1

8C1

8C1

8C1

8B1

8B1

8B1

8B1

24D5

24D5

24D5

40C7

22B6

22B6

22B4

22B4

22B4

22B4

22B6

40D7

40D7

8C1

8C1

8C1

23B6

22B4

22B4

22A4

22B4

22A4

22B6

22B4

8B1

8B1

23B3

24D5

23C5

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

Controller Link (AMT) Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

DG says 30 mils min separation.

Platform LAN (Nineveh) Constraints

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19

PCI Bus Constraints

?*

ENET_CLK

=2.5:1_SPACING

=55_OHM_SE

=STANDARD

*

=55_OHM_SE

=STANDARD

=55_OHM_SE

Y

CLINK_55S

?PCI *

=2:1_SPACING

?*

CLINK_VREF

12 MILS

?

CLINK

*

=1.8:1_SPACING

25 MILS

ENET_MDI

* ?

LAN_55S

=55_OHM_SE

=STANDARD

*

=55_OHM_SE

Y

=55_OHM_SE

=STANDARD

GLAN_100D

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

Y*

?*

ENET_LAN

=1.5:1_SPACING

* ?

ENET_GLAN

20 MILS

Y

=55_OHM_SE

=STANDARD

=55_OHM_SE

*

PCI_55S

=55_OHM_SE

=STANDARD

* Y

ENET_100D

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

01

7674

SYNC_DATE=06/12/2006

SYNC_MASTER=WFERRY

SB Constraints (2 of 2)

051-7455

=STANDARD

*

=STANDARD

Y

12 MILS

5 MILS

300 MILS

CLINK_12MIL

PCIE_E_R2D_C_P

PCIE_E_R2D

PCIE

PCIE_100D

PCIE_E_R2D_C_N

PCIE

PCIE_100D

GLAN_COMP

GLAN_COMP

ENET_LAN

LAN_55S

LAN_RSTSYNC

ENET_LAN

ENET_LANENET_LAN

LAN_55S

LAN_R2D<2..0>

ENET_LAN

LAN_55S

ENET_LAN

LAN_D2R<2..0>

INT_PIRQF_L

PCI_55S

INT_PIRQF_L

PCI

INT_PIRQE_L

PCI_55S

INT_PIRQE_L

PCI

INT_PIRQD_L

INT_PIRQD_L

PCI_55S

PCI

INT_PIRQC_L

INT_PIRQC_L

PCI_55S

PCI

INT_PIRQB_L

INT_PIRQB_L

PCI_55S

PCI

INT_PIRQA_L

PCI_55S

PCI

INT_PIRQA_L

PCI_GNT2_L

PCI_55S

PCI

PCI_GNT2_L

PCI_REQ2_L

PCI_55S

PCI

PCI_REQ2_L

PCI_GNT1_L

PCI_55S

PCI

PCI_GNT1_L

PCI_55S

PCI

PCI_FW_GNT_L

PCI_FW_GNT_L

PCI_55S

PCI

PCI_FW_REQ_L

PCI_FW_REQ_L

PCI_CNTL

PCI_55S

PCI

PCI_FRAME_L

PCI_REQ1_L

PCI_55S

PCI

PCI_REQ1_L

PCIE_E_D2R_P

PCIE_E_D2R

PCIE_100D

PCIE

PCIE_100D

PCIE

PCIE_E_D2R_N

PCI_AD

PCI

PCI_55S

PCI_AD<18..0>

PCI_AD19

PCI_55S

PCI

PCI_AD<19>

PCI_AD20

PCI_55S

PCI

PCI_AD<20>

PCI_AD

PCI_55S

PCI

PCI_PAR

PCI_C_BE_L

PCI_55S

PCI

PCI_C_BE_L<3..0>

PCI_CNTL

PCI_55S

PCI

PCI_IRDY_L

PCI_CNTL

PCI

PCI_55S

PCI_SERR_L

PCI_CNTL

PCI_55S

PCI

PCI_STOP_L

PCI_CNTL

PCI_55S

PCI

PCI_DEVSEL_L

PCI_LOCK_L

PCI_55S

PCI

PCI_LOCK_L

PCI_CNTL

PCI_55S

PCI

PCI_TRDY_L

ENET_MDI_P<2>

ENET_MDI2 ENET_100D

ENET_MDI

ENET_MDI3

ENET_MDI_P<3>

ENET_MDI

ENET_100D

CLINK_NB

CLINK_NB_DATA

CLINK_55S

CLINK

CLINK_WLAN

CLINK_WLAN_CLK

CLINK_55S

CLINK

CLINK_55S

CLINK

CLINK_WLAN

CLINK_WLAN_DATA

CLINK_VREF

CLINK_12MIL

NB_CLINK_VREF

NB_CLINK_VREF

ENET_CLK

ENET_GLAN_CLK

LAN_55S

ENET_MDI1

ENET_MDI

ENET_MDI_P<1>

ENET_100D
ENET_100D

ENET_MDI_N<1>

ENET_MDI

SB_CLINK_VREF1

CLINK_12MIL

CLINK_VREF

SB_CLINK_VREF1

SB_CLINK_VREF0

CLINK_12MIL

CLINK_VREF

SB_CLINK_VREF0

CLINK

CLINK_WLAN_RESET_L

CLINK_55S

CLINK_WLAN_RESET_L

CLINK_NB_RESET_L

CLINK_NB_RESET_L

CLINK

CLINK_55S

CLINK_55S

CLINK_NB

CLINK

CLINK_NB_CLK

ENET_MDI_N<3>

ENET_MDI

ENET_100D

ENET_MDI_N<2>

ENET_MDI

ENET_100D

ENET_MDI

ENET_100D

ENET_MDI_N<0>

ENET_MDI0 ENET_100D

ENET_MDI

ENET_MDI_P<0>

PCI_AD

PCI_55S

PCI

PCI_AD<31..21>

PCI_CNTL

PCI_55S

PCI

PCI_PERR_L

ENET_GLAN_CLK

ENET_CLK

ENET_GLAN_CLK_R

LAN_55S

37C5

37A5

37A5

37A5

37B5

37A5

37A5

37A5

37A5

37A5

37A5

33B6

33B6

23A6

23A6

23A8

23A8

23A8

23A8

23B6

37A5

23B6

23A6

23B6

33C5

23B8

37B6

37B5

37B5

37B5

23A6

23A6

23A6

23A6

23A6

23A6

36B7

36C7

24C3

36C7

36C7

24C3

24C3

36C7

36C7

36B7

36B7

37B5

23A6

33B5

33B5

22C6

23A4

23A4

23A4

23A4

23A4

23A4

23A4

23B5

23A4

23A4

23A4

33B5

33B5

23A8

23A8

23A8

23A6

23B6

23A4

23A4

23A4

23A4

23A4

23A4

34B8

34B8

15A3

24C3

24C3

15A4

34B8

34B8

24C3

24C3

24D5

15A3

15A3

34B8

34B8

34B8

34B8

23A8

23A4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6

(CK505_CPU)

(CK505_CPU)

Clock Net Properties

(CK505_NB)
(CK505_ITP)

(CK505_PCI2)

(CK505_PCI1)

(CK505_DOT96)
(CK505_DOT96)

(CPU_BSEL0)
(CPU_BSEL2)

(CK505_PCI3)

(CK505_SRC5)

(CK505_SRC3)

(CK505_SRC4)

(CK505_SRC2)
(CK505_SRC2)
(CK505_SRC3)

(CK505_SRC4)

(CK505_SRC5)
(CK505_SRC6)
(CK505_SRC6)

(CK505_LVDS)

(CK505_LVDS)

(CPU_BSEL2)

(CK505_SRC1)

(CK505_SRC1)

(CPU_BSEL0)

(CK505_ITP)
(CK505_PCIF0)

(CK505_PCIF1)

(CK505_NB)

CK505 SRC7 is project-specific

CK505 SRC8 is project-specific

CK505 PCI4 is project-specific

PHYSICAL

(CPU_BSEL0)
(CPU_BSEL2)

Clock Signal Constraints

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

CK505 PCI5 is project-specific

051-7455

SYNC_DATE=06/12/2006

01

7675

SYNC_MASTER=WFERRY

Clock Constraints

=55_OHM_SE

* Y

=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

CLK_SLOW_55S

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

* Y

CLK_FSB_100D

=STANDARD

=55_OHM_SE=55_OHM_SE

CLK_MED_55S

Y

=STANDARD

=55_OHM_SE

*

=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

* Y

=100_OHM_DIFF

10 MIL

* ?

CLK_SLOW

20 MIL

CLK_PCIE

?*

20 MIL

*

CLK_MED

?

25 MIL

*

CLK_FSB

?

CLK_PCIE_100D

CK505_SRC8

CLK_PCIE

CK505_SRC8_P

CLK_PCIE

CK505_SRC8_N

CLK_PCIE_100D

CLK_PCIE

CK505_SRC6

CLK_PCIE_100D

CK505_SRC6_P

CLK_PCIE_100D

CLK_PCIE

CK505_SRC4_N

CK505_SRC4

CLK_PCIE_100D

CLK_PCIE

CK505_SRC4_P

CLK_PCIE

CK505_SRC5_N

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CK505_SRC6_N

CLK_PCIE

CK505_SRC7

CLK_PCIE_100D

CK505_SRC7_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_N

CLK_FSB_100D

CLK_FSB

FSB_CLK_NB_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_NB_N
XDP_CLK_P

CLK_FSB

CLK_FSB_100D

CLK_MED_55S

CLK_MED

PCI_CLK33M_TPM

CLK_MED

CLK_MED_55S

CK505_FSC

SB_CLK100M_DMI_N

CLK_PCIE

CLK_PCIE_100D

SB_CLK14P3M_TIMER

CLK_MED

CLK_MED_55S

CLK_PCIE

CLK_PCIE_100D

NB_CLK96M_DOT_P

CLK_PCIE

CLK_PCIE_100D

NB_CLK96M_DOT_N

CLK_PCIE

PEG_CLK100M_P

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_MINI_N

CLK_PCIE

CLK_PCIE_100D

NB_CLK100M_PCIE_N

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_P

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_SATA_N

CLK_PCIE_100D

CLK_PCIE

NB_CLK100M_PCIE_P

CLK_PCIE

CLK_PCIE_100D

SB_CLK100M_SATA_P

PCIE_CLK100M_EXCARD_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_EXCARD_N

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_DMI_P

CLK_PCIE_100D

CLK_PCIE

PEG_CLK100M_N

NB_CLK100M_DPLLSS_N

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE_100D

CLK_PCIE

NB_CLK100M_DPLLSS_P

CLK_MED

CLK_MED_55S

CK505_FSA

CLK_MED_55S

SB_CLK48M_USBCTLR

CLK_MED

CLK_MED_55S

CLK_MED

PCI_CLK33M_SMC

CLK_MED_55S

CLK_MED

PCI_CLK33M_FW

CLK_MED_55S

CLK_MED

PCI_CLK33M_LPCPLUS

CLK_MED_55S

CLK_MED

PCI_CLK33M_SB

CLK_PCIE_100D

CLK_PCIE

CK505_SRC3_N

CLK_PCIE

CK505_SRC5

CLK_PCIE_100D

CK505_SRC5_P

CK505_LVDS

CLK_PCIE_100D

CLK_PCIE

CK505_LVDS_P

CK505_SRC1

CLK_PCIE_100D

CLK_PCIE

CK505_SRC1_P

CLK_MED_55S

CK505_PCIF0_CLK

CK505_PCIF0

CLK_MED

CK505_PCIF1

CK505_PCIF1_CLK

CLK_MED_55S

CLK_MED

CK505_PCI1

CK505_PCI1_CLK

CLK_MED_55S

CLK_MED

CK505_PCI2_CLK

CLK_MED_55S

CK505_PCI2

CLK_MED

CK505_PCI3_CLK

CK505_PCI3

CLK_MED_55S

CLK_MED

CK505_PCI4_CLK

CK505_PCI4

CLK_MED_55S

CLK_MED

CK505_PCI5_FCTSEL1

CLK_MED_55S

CK505_PCI5

CLK_MED

CK505_SRC1_N

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CK505_LVDS_N

CK505_DOT96_27M_N

CLK_PCIE

CLK_PCIE_100D

CK505_USB48_FSA

CLK_MED_55S

CLK_MED

CK505_NB

CLK_FSB

CK505_CPU1_N

CLK_FSB_100D

CK505_CPU2_ITP_SRC10_P

CLK_FSB

CLK_FSB_100D

CK505_ITP

CLK_FSB

CK505_CPU2_ITP_SRC10_N

CK505_ITP

CLK_FSB_100D

CK505_CPU

CLK_FSB

CK505_CPU0_N

CLK_FSB_100D

CLK_FSB

CK505_CPU1_P

CLK_FSB_100D

CK505_NB

CK505_CPU

CK505_CPU0_P

CLK_FSB

CLK_FSB_100D

CLK_MED_55S

CLK_MED

CK505_CLK14P3M_TIMER

CK505_DOT96

CLK_PCIE_100D

CLK_PCIE

CK505_DOT96_27M_P

CLK_PCIE_100D

CLK_PCIE

CK505_SRC2_N

CK505_SRC2

CLK_PCIE_100D

CLK_PCIE

CK505_SRC2_P

CLK_PCIE_100D

CLK_PCIE

CK505_SRC3

CK505_SRC3_P

CLK_PCIE_100D

CLK_PCIE

CK505_SRC7_N

XDP_CLK_N

CLK_FSB_100D

CLK_FSB

29B6

29B6

29C6

29C6

29C6

29C6

29B6

29D6

29D6

44C8

37A5

46C4

29B3

29C6

29C6

29B6

29C6

29B6

29D6

29D6

29D6

29D6

29D6

29D6

29B6

29C6

29C6

28A4

28A4

28B4

28B4

28B4

28B4

28B4

29D3

29D3

29D3

29D3

29D6

29C3

29A5

29B3

29B3

33C5

29C3

33C5

29C3

29C3

29C3

29C3

29C3

29C3

29D6

29A5

29A5

29B3

29B3

29A5

28B4

28B4

29B6

28B6

29B6

28B6

29A6

28B6

29B2

28B4

28A4

29D8

28C4

28C4

28C4

28C4

28C4

28C4

29D8

28A4

28B4

28B4

6B7

6B7

6C7

6C7

6C7

6C7

6C7

9B6

9B6

13B3

13B3

70A3

29A8

23D2

24D3

8B1

8B1

29B3

15C3

29C3

22B6

15C3

22B6

23C2

8A1

8B1

29C8

24D3

29A3

29A5

6C2

23A6

6C7

6C7

28B8

6C7

28B6

8C4

28B6

8C4

28B6

6C7

6C7

28A4

6C7

6C7

6C7

6C7

6C7

6C7

28A4

6C7

6C7

6C7

70A3

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FireWire Interface Constraints

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

FireWire Net Properties

SPACING

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMC SMBus Net Properties

Port 2 Not Used

FW_LPS

FW_LPS

FW

FW_55S
FW_55S

FW

FW_LREQ

FW_LREQ

FW_55S

FW

FW_PINT

FW_PINT

CLK_MED_55S

CLK_MED

FWPHY_CLK98P304M_XI

CLK98P304M_FW_XI_R

FW_D_CTL

FW_55S

FW

FW_LINK<7..0>

CLK_MED_55S

CLK_MED

CLKFW_PHY_PCLK

FW_PCLK CLK_MED

CLK_MED_55S

CLKFW_LINK_PCLK

CLK_MED

CLK_MED_55S

CLKFW_PHY_LCLK

FW_LCLK CLK_MED

CLK_MED_55S

CLKFW_LINK_LCLK

FW

FW_55S

FW_CTL<1..0>

FW_D_CTL

FW_55S

FW

FW_LKON

FW_LKON

FW

FW_55S

FW_LKON_R

FW_TP

FW_110D

FW_0_TPA

FW_0_TPA_P

SMB_55S

SMB

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SDA

SMB_55S

SMB

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SDA

SMB_55S

SMB

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SDA

SMB_55S

SMB

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SCL

SMB

SMB_55S

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SCL

SMB

SMB_55S

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SCL

SMB

SMB_55S

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SCL

SMB_55S

SMB

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SDA

SMB

SMB_55S

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SCL

FW_110D

FW_0_TPB_N

FW_TP

FW_110D

FW_TP

FW_0_TPA

FW_0_TPA_N

FW_TP

FW_110D

FW_1_TPB_N

FW_TP

FW_110D

FW_1_TPB

FW_1_TPB_P

FW_TP

FW_110D

FW_1_TPA_P

FW_1_TPA

FW_TP

FW_110D

FW_1_TPA_N

FW_1_TPA

FW_110D

FW_TP

FW_0_TPB_P

FW_0_TPB

CLK_MED

CLK_MED_55S

CLK98P304M_FW_XI

=55_OHM_SE

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE

FW_55S

* Y

?*FW

=2:1_SPACING

* Y

=110_OHM_DIFF

=110_OHM_DIFF =110_OHM_DIFF

FW_110D

=110_OHM_DIFF =110_OHM_DIFF

*

=3:1_SPACING

?

FW_TP

051-7455

76

01

76

SYNC_MASTER=WFERRY

SYNC_DATE=06/12/2006

FireWire & SMC Constraints

47C5

47C5

6B2

47D5

47C2

47D2

6B2

47D5

47C2

47D2

47B2

47B2