Apple A1181, K36 Schematics

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK
APPD

DATE

ENG
APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

8/9/2007

MK

MK

REFERENCED FROM M70

MK

MM-MARY(YUAN) MA

LD-LINDA DUNN

LT-LAWRENCE TAN

MK-MARC KLINGELHOFER

RC-RAY CHANG

DK-DINESH KUMAR

RX-RAYMOND XU

ES

Schematic / PCB #’s

LT

LD

RX

LT

ES

ES

MK

MK

MK

MK

RX

ES

RX

ES

LD

ES

ES

RX

RX

DK

RX

RX

ES

RX

ES

ES

MK

MK

MK

RX

RX

RX

ES

ES

LD

LD

LD

LT

LT

RX

DK

LD

LT

LT
LT

LT

RX
RX

DK
DK

RX

LD

ES

RX

MK

ES

RX

RX

RX

RX

LD

RX
MK

MKRX

RX

ES

RX

RX

LD

K36 MLB SCHEMATIC

ES

K36 EE DRIS:

LT

DVT BUILD

22

SB Power & Ground

Page

07/17/2006

45

50

GPU

SMC SUPPORT

10/30/2006

44

49

T9_MLB

SMC

09/05/2006

43

48

USB

IR CONTROLLER & BT INTERFACE

06/29/2006

42

47

USB

CONNECTOR MISC

06/30/2006

41

46

USB

USB EXTERNAL CONNECTORS

07/17/2006

40

45

GPU

SATA CONNECTOR

07/17/2006

39

44

GPU

PATA CONNECTOR

07/17/2006

38

43

GPU

FIREWIRE PORT

08/30/2005

37

40

ENET

FIREWIRE CONTROLLER

09/14/2006

36

39

USB

ETHERNET CONNECTOR

10/07/2006

35

38

USB

Yukon Power Control

10/07/2006

34

37

USB

Ethernet (Yukon)

08/19/2005

33

34

ENET

06/20/2005

33

MEMORY

Memory Active Termination

06/20/2005

31

32

MEMORY

DDR2 SO-DIMM Connector B

06/20/2005

30

31

MEMORY

DDR2 SO-DIMM Connector A

06/06/2006

29

30

DSIMON-WF

Clock Termination

06/06/2006

28

29

DSIMON

Clock (CK505)

07/26/2005

27

28

NB

SB Misc

06/01/2006

26

27

WFERRY

SB Decoupling

10/30/2006

25

26

T9_MLB

10/30/2006

24

25

T9_MLB

SB Pwr Mgt, GPIO, Clink

10/30/2006

23

24

T9_MLB

SB PCI, PCIe, DMI, USB

10/30/2006

23

T9_MLB

SB Enet, Disk, FSB, LPC

06/15/2006

21

22

WFERRY

NB Graphics Decoupling

06/15/2006

20

21

WFERRY

NB Standard Decoupling

10/30/2006

19

20

T9_MLB

NB Grounds

10/30/2006

18

19

T9_MLB

NB Power 2

10/30/2006

17

18

T9_MLB

NB Power 1

10/30/2006

16

17

T9_MLB

NB DDR2 Interfaces

10/30/2006

15

16

T9_MLB

NB Misc Interfaces

10/30/2006

14

15

T9_MLB

NB PEG / Video Interfaces

10/30/2006

13

14

T9_MLB

NB CPU Interface

5/23/05

12

13

MASTER

CPU ITP700FLEX DEBUG

04/26/2006

11

12

MSARWAR

CPU Decoupling & VID

11/12/2006

10

11

T9_MLB_NOMECPU Power & Ground

11/12/2006

9

10

T9_MLB_NOME

CPU FSB

07/17/2006

8

9

GPU

SIGNAL ALIAS /RESET

06/15/2006

7

8

WFERRY

Power Aliases

07/25/2005

6

7

TP

FUNC TEST 1 OF 2

N/A

5

5

N/A

Revision History

07/18/2005

4

4

SMC

06/30/2005

3

3

POWER

Power Block Diagram

05/11/2006

2

2

WFERRY-WF

System Block Diagram

76

06/12/2006

WFERRY

106

FireWire & SMC Constraints

75

06/12/2006

WFERRY

105

Clock Constraints

74

06/12/2006

WFERRY

104

SB Constraints (2 of 2)

73

06/12/2006

WFERRY

103

SB Constraints (1 of 2)

72

06/08/2006

WFERRY

102

Memory Constraints

71

06/12/2006

WFERRY

101

NB Constraints

70

06/08/2006

WFERRY

100

CPU/FSB Constraints

69

05/21/05

EUGENE

94

MINI-DVI CONNECTOR

68

06/06/2005

GRAPHIC

92

EXTERNAL TMDS

67

06/23/2006

GPU

90

INVERTER,LVDS,TMDS

66

08/19/2005

SMC

79

65

06/12/2006

DSIMON-WF

78

S3 FET & S3/S5 Control

64

12/06/2005

ENET

77

3.42V/1.25V Switcher

63

07/13/2005

POWER

76

5V/3.3V Supplies

62

07/13/2005

POWER

75

1.8V/0.9V Supplies

61

07/13/2005

POWER

73

1.5V / 1.05V Supplies

60

06/29/2006

GPU

72

Render VCore Supplies

59

07/13/2005

POWER

71

IMVP6 CPU VCore Regulator

58

05/31/2006

DSIMON-WF

70

S0 FETS & Power Sequencing

57

07/13/2005

POWER

69

DC-In & Battery Connectors

56

03/12/2007

M70AUDIO

68

AUDIO: JACK TRANSLATORS

55

03/12/2007

M70AUDIO

67

AUDIO: JACK

54

03/12/2007

M70AUDIO

66

AUDI0: SPEAKER AMP

53

03/12/2007

M70AUDIO

62

AUDIO: CODEC

52

04/26/2006

WFERRY

61

SPI ROMs

51

08/23/2005

SMC

59

SMS

50

11/10/2005

ENET

56

Fan

49

06/21/2006

GPU

55

TEMPERATURE SENSE

48

07/17/2006

GPU

53

CPU Current & Voltage Sense

47

06/01/2006

WFERRY

52

SMBUS CONNECTIONS

SCHEM,MLB,K36

?

? ??

?

761

01

051-7455

46

06/01/2006

WFERRY

51

LPC+ Debug Connector

09/05/2006

1

1

USB

Table of Contents

Page

Contents

Sync

(.csa)

Date

SCHEM,MLB,K36

051-7455 CRITICAL

SCH

1

PCBF,MLB,K36

820-2279 CRITICAL

PCB

1

Contents

Sync

(.csa)

Date

CONFIGURATION OPTIONS

32

PBUS Supply/Battery Charger

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Core ~1.2V

2.? GHz

U1000

PG 49

PG 49

HEAT-PIPE/FIN

U5920 SUDDEN MOTION DETECT PG 51

J5100

PG 44

POWER SENSE PG 48

FAN CONN PG 50

PG 46

Bluetooth

J4810

PG 41PG 43PG 42PG 43

J4850

PG 56

PG 55

PG 54

Pg 53

Pg 37

PG 38

Pg 34

Pg 36

PG 39

PG 40

J4501

PG 57-67

PG 57

PCI-E

1.05 - 1.25V

Core

NB-GMCH

CPU

800/1066? MHz

Pg 14

TMDS

U9200

SDVO

J9401

DVI-I

GPIO

PG 68

GPIOs

CONTROLLER

U4800

Pg 22

Pg 15

J9001

MUX

Out

RGB

LVDS

Pg 14

DMI

Pg 17,18,19

U1400

64-Bit

J4600

USB

Connectors

J4601

J4700

Geyser

Trackpad/Keyboard

3G

CONNECTOR

IR

PG 44

Pg 22

J3201

J3101

Pg 13

U5500

U5520

J5601

8

Core 1.05V

SB-ICH8

CLnk 0

Pg 24

97

CAMERA

SATA-0

U2300

Pg 23

Codec

Audio

Conns

Audio

Amps

Speaker

U6600/10/20

TRANSLATORS

JACK

J6702/03 INTERNAL SPEAKER

J6701 INTERNAL MIC
J6750/00 LINE IN/OUT

J4300

FW32306

J3900

J4401

PG 54

J3201

J3101

ITP CONN

PG 12

J1302

FSB

Main Memory

x4 DMI

2.5 GHz

TV

Boot ROM

DC/Batt

Supply

Conn

533/667/800? MHz

Pg30,31

Pg 24

LPCSMB

Pg 24

Pg 22

SATA

SATA-2SATA-1

Pg 23

PCI-E

UATA

Pg 22

Ln6Ln5Ln4Ln3Ln2Ln1

Conn

FireWire

U4000

32-Bit

33 MHz

E-NET

Conn

E-NET

NINEVEH

U3700

AirPort

Mini PCI-E

Pg 33

J3400

U6200

CPU

Temp Sense

Power

J6900/50

LPC Conn

Prt

Ser

Fan

SPI

U6100/50

UC500

U2900

Clk Gen

DIMM’s

Pg 23

USB

AZALIA

Pg 23

PCI

Pg 24

CLnk 1

Pg 22

E-NET

Pg 25

Core

4321 5 6

Pg 23

SPIDMI

Conn

UATA

Conn

SATA

Pg 15/16

DIMM

1.8V - 64 Bits

DDR2 - Dual Channel

Pg 15

Pg 15

CLnk 0

Pg 32

Term

Parallel

Misc

Clocks

U2900

CK 505

Pg 29

TERMS

Pg 28

Pg 9

Pg 10

A

B,0 BSA BSB

ADC

SMC

U4900

PG 69

Int Disp

PG 67

Conn

01

76

SYNC_DATE=05/11/2006

System Block Diagram

2

SYNC_MASTER=WFERRY-WF

051-7455

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

K36 POWER SYSTEM ARCHITECTURE

Q7859

07

5VS5_RUNSS

3.3V

Q3810

Q7001

TPS62510

1.25V S0

ENA

PP4V5_AUDIO_ANALOG

VOUT

(PAGE 21)

U2265

TPS731125

MCH DPLL

R7502

18

VOUT2

PP1V5_S0_REG

PP1V8_S3_REG

Q7006

19

15

PP1V8_S3_REG_R

PP3V3ENET_SS

15

P1V25_S0_NB_DPLL

15

Q7007

(10.75A MAX CURRENT)

0.9V

1V25S0_RUNSS

RUNSS_GATE_D

Q7006

START

(S0)

GFX_VR_EN

Q7004

CHGR_EN

Q7860

17-1

PM_ENET_EN_L

PPBUS_G3H

SMC_BATT_ISENSE

01

U7970

A

VOUT

MAX8719

VIN

U7950

D7950

U7975

ENRGYSTR LDO

SMC_ENRGYSTR_LDO_EN

6A FUSE

SHGN*

(PAGE 66)

VOUT

GPU_VCORE

U7200

ISL6263

(PAGE 60)

02

ENA

VIN

21

(7.7A MAX CURRENT)

PPVCORE_S0_NB_GFX_IMVP

(PAGE 62)

TPS51116

1.8V

02

15

P1V8S0_EN

SMC_PM_G2_EN

LOGIC

PPVBAT_G3H_CHGR_REG

IMVP_VR_ON

ENA2

TPS51120

(PAGE 63)

PP1V2_ENET_REG

RSMRST_PWRGD

PGOOD1,2

(PAGE 59)

U7100

VR_ON

02

PGOOD

CLKEN#

VOUT

CPUVCORE

ISL9504

VIN

CHGR_EN

(S5)

ENABLES

VIN

ISL6257HRZ

U7900

(PAGE 66)

VOUT

SMC_DCIN_ISENSE

A

BATTERY

3S2P

BATT_POS_F

Q7860

11

PM_SLP_S4_L

PM_SLP_S3_L

PM_S4_STATE_L

ICH

DELAY

(S3)

12

P3V3S3_EN_L

RC

RC
DELAY

(S3)

P5VS3_EN_L

12

Q3802

Q3801

PM_ENET_EN_L

IN

AC

ADAPTER

DCIN

ENA1

(S5)

3V3S5_RUNSS

PP1V05_S0_REG

VR_PWRGD_CK505_L

PGOOD_1V05S0

PGOOD2

VOUT2

PP3V42_G3H_REG

VOUT2

VOUT1

02

PPBUS_G3H

PPDCIN_G3H

D6901

SMC_ADAPTER_EN

PM_SLP_S3_L

1V8S3_RUNSS

S5

1V5S0_RUNSS
(S0)

WOL_EN

04-1

START

SOFT

P25

06

(S5)

17

17

A

12

S3

U7870

14

18

17

18

18

16

15

17

SOFT
START

U7500

PP0V9_S0_REG

U5300

PPVCORE_CPU_S0

(36A MAX CURRENT)

P5VS0_EN

(7.5A MAX CURRENT)

09

CURRENT)

PP3V3_S5_REG

Q7865

(4A MAX CURRENT)

PP1V5_S0_REG

(8A MAX CURRENT)

PGOOD_1V5S0

SMC_CPU_VSENSE

Q7000

Q7866

(5A MAX

PP5V_S5_REG

24

29

28

27

26

30

23

22

20

19

VOUT1

14

(PAGE 45)

VLDOIN

13

P1V8_S0_FET

16

P5VS3_EN_L

PP5V_S3

4.5V AUDIO
TPS79501

U6201

TPS51124

U7300

VOUT

(PAGE 35)

PP3V3_S5

CLK_PWRGD

PM_SB_PWROK

17

17

15

13

15

15

15

15

14

GATE B

GATE D

P3V3S0_EN

P1V8S0_EN

RUNSS_GATE_D

ISL6130IRZA

5V

13

12

10

CPUPWRGD(GPIO49)

PWROK

09

05

08

PP5V_S5

VR_PWRGOOD_DELAY

08

07

04

03

02

02

7A FUSE

FSB_CPURST_L

RSMRST_OUT(P15)

IMVP_VR_ON(P16)

PLT_RST*

PWR_BUTTON(P90)

P17(BTN_OUT)

SLP_S3_L

SLP_S5_L

BATTERY ONLY:

SMC_ONOFF_L

ALL_SYS_PWRGD

U2801

PP1V8_S0_FET

PM_SLP_S3_L

PP3V3_S0_FET

PGOOD_1V8S3
PP5V_S0_FET

(PAGE 58)

ENA*

U7000

P5VS0_EN

VOUT

SMC_CPU_ISENSE

U4900

RST*

RSMRST_IN(P13)

(PAGE 9)

PWRGOOD

U2300

(PAGE 22)

RSMRST*

PWRBTN*

PLTRST*

(PAGE 28)

U2900

SLG8LP537V

CLOCK

PP1V05_S0_REG_R

R7302

3.425V G3HOT

PGOOD1

VOUT1

1V5S0_RUNSS

(S0)

(S0)

1V05S0_RUNSS

(S5)

SMC

U4900

Q7007

1V05S0_RUNSS
(S0)

SOFT

VIN

ADAPTER IN :

VREG3

1.2V YUKON

ENA

ENA

VIN

IMVP_VR_ON

HCPURST*

99ms DLY

Q7859

MAX8516

U7790

U7600

(PAGE 44)

SMC_RESET_L

SLP_S5_L(P95)

PM_RSMRST_L

PM_PWRBTN_L

P60

VIN

1.05V

VIN

SLP_S4_L

SLP_S4_L(P94)
SLP_S3_L(P93)

(PAGE 13)

U1400

CRESTLINE

CPU

VIN

RESET*

PLT_RST_L

ENA1

ENA2

CPU_PWRGD

SMC

ENA

U3830

V

SMC_RESET_L

U5000

RN5VD30A-F

SMC PWRGD

ENABLE

(PAGE 64)

(PAGE 45)

LT3470

PBUSB_VSENSE

(PAGE 61)

Q5350

1.5V

ICH8M

VRMPWRGD

CK_PWRGD

PWRGD

VIN

PWROK

U1000

VR_PWRGOOD_DELAY

25

V

18

U2803

VR_PWRGD_CK505

PP5V_S0_FET

PM3V3ENET_SS

P3V3_ENET_FET

GATE C

RST*

19

RESET*

SENSE

PP1V25_S0_REG

PP1V9_ENET_REG

17

18

RSMRST_PWRGD

PWRGD(P12)

TPS3808-1.25V

U7200

VIN

VIN
ENA

PP3V3_ENET_FET

16

GATE A

P3V3S0_EN

12

(PAGE 58)

MR*

VOUT

U3820

TPS79501DRB

1.9V S3

(PAGE 64)

U7720

VOUT

(PAGE 53)

P3V3S3_EN_L

1V25S0_RUNSS

(PAGE 35)

PGOOD_SEQUENCER

UVLO_A
UVLO_B
UVLO_C
UVLO_D

PBUS CONVERTER/
BATTERY CHARGER

23

01

06-1

10-1

17-1

PP1V25_S0_FET

PP3V3_S3

PP3V3_S0_FET

16

PGOOD_1V05S0

PGOOD_1V5S0

3

01

SYNC_DATE=06/30/2005

SYNC_MASTER=POWER

Power Block Diagram

76

051-7455

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

SIGNAL

Signal aliases required by this page:

NBCFG_PEG_REVERSE

0.031

0.076

Page Notes

(NONE)

NBCFG_DMI_X2

>

>
>

>

>

>

>

BOMOPTION

0.014

0.014

TOTAL

0.014

L8-L9

>> > >

BOM OPTION

630-7935

TRACE WIDTH

(MM)

>
>

>> >>

>>

>

>

>

>

>

>

> >

>

>> >>

>

>>
>

CONCEPT

>

L4 SIGNAL

INVERTER_UNBUF

>

ISL6130

NBCFG_SDVO_AND_PCIE

ITP

0.1

YUKON_ULTRA

>>

> >

> > > >

LAYER

COMMON

LPCPLUS

0.018

L7-L8

BETTER

L1-L2

YUKON_EC

ISL6126

NBCFG_DMI_REVERSE

L1 SIGNAL(TOP)

CONFORMAL_COAT

GOOD

BEST

---

0.07

L11-L12

L12 SIGNAL(BOTTOM)

L6-L7

L7 POWER

L5-L6

L4-L5

L5 GND

L6 POWER

L2 GROUND

L2-L3

L3 SIGNAL

THICKNESS

0.014

0.076

0.014

0.014

1.276

0.156

0.047

0.07

0.076

(MM)

0.047

0.1

0.1

---

0.1

0.1

---

---

(NONE)

(NONE)

L3-L4

0.156

0.014

0.076

0.07

MLB STACKUP

---

0.079

ODD_PWR_RESUME

ODD_PWR_CORE

STANDOFF

FANCY

NORMAL

M70 GOOD

ARB_ONLY

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

BOM OPTION REMOVED

K36

K36_PGM

K36 GOOD

K36 BETTER K36 BEST

630-9104 630-9105 630-9106

EVT

EVT EVT

L10 SIGNAL

0.031

0.07

0.079

NBCFG_DYN_ODT_DISABLE

NO_REBOOT_MODE

INVERTER_BUF

ALTERNATE

Power aliases required by this page:

BOM options provided by this page:

GROUND

POWER
POWER

GROUND
SIGNAL(High Speed)
SIGNAL(High Speed)

GROUND

GROUND

SIGNAL

BOTTOM

11

10

9

8

7

6

5

3

2

Top

L9-L10

L9 SIGNAL

BOARD STACK-UP AND CONSTRUCTION

LOCKED BOOTROM PN 341S2197

L11 GROUND

L10-L11

0.076

SIGNAL(High Speed)

SIGNAL(High Speed)

4

BOM TABLE FOR HF POSCAPS

---

0.014

L8 GROUND

CONFORMAL_COAT

0.018

PAGE_BORDER=TRUE

SYNC_MASTER=SMC

01

4 76

SYNC_DATE=07/18/2005

051-7455

K36
K36

CRITICAL

EEE:Z57

1

CRITICAL BEST

826-4393

EEE:Z56

CRITICAL1BETTER

826-4393

EEE:Z55

826-4393

1

CRITICAL GOOD

CRITICAL

K36

GOOD

BEST

U1000

2

CRITICAL

1

1

CRITICAL

CRITICAL

BETTER

CRITICAL

U1000

1

1

U1000

U2300

U1400

516-0162

338S0434

343S0448

LBL,P/N LABEL,PCB,28MMX6MM

LBL,P/N LABEL,PCB,28MMX6MM

LBL,P/N LABEL,PCB,28MMX6MM

1

IC,16MBIT 8PIN SPI SERIAL FLASH,SOIC8

341S2196

K36_PGM

CRITICAL

IC,CYPRESS,CY7C63833,ENCORE_II,USB_CONTR

341S2093

K36_PGM

U4800

1

341S2198

IC,SMC,HS8/2116

1

CRITICAL

U4900

341S2060

IC,EEPROM,SERIAL IIC,8KBIT,SO8

1

K36_PGM

CRITICAL

CONFIGURATION OPTIONS

CRITICAL

4

C4610,C4611,C6830,C6831

K36

128S0147 HF VERSION OF 128S0057

CRITICAL

K36

HF VERSION OF 128S0085

C6605

K36

CRITICAL

HF VERSION OF 128S0111

C7220,C7352,C7542

CRITICAL

K36

C2130,C2716,C7543

K36

CRITICAL

3

128S0164

6

HF VERSION OF 128S0115

C6204,C6205,C7651,C7652,C7691,C7692

CRITICAL

K362

HF VERSION OF 128S0113

C2173,C2700

CRITICAL

K36

128S0157

1

HF VERSION OF 128S0122

C2220

IN-LINE SODIMM CONNECTOR

IC,ICH8,BGA

IC,CRESTLINE,GM965,667

IC,MDC,SR,E1,2.0G,800FSB,4M,BGA

IC,MDC,SR,G0,2.2G,800FSB,4M,BGA

IC,MDC,SR,G0,2.2G,800FSB,4M,BGA

1

337S3463

337S3500

337S3500

J3101,J3201

U6100
U3780

CRITICAL

K36_PGM

CRITICAL

K361

128S0162 HF VERSION OF 128S0123

C2140

K36

CRITICAL

128S0135 HF VERSION OF 128S0129

2

C6601,C6603

HF VERSION OF 128S0073

1
3

128S0150

128S0160

128S0148

128S0169

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- ALL 128S0122 BECOME 128S0157.

- ALL 128S0115 BECOME 128S0150.

- ADD ISOLATION BUFFER FOR ODD_RESET_L SIGNAL, ADD 100K PULL-DOWN TO ODD_PWR_EN_L, ADD ’DRAG’ CIRCUIT TO

- LOWER RDS(ON) MOSFET (FDC606P - APN: 376S0552) FOR ODD AND LCD POWER - RADAR: TBD

- HIGH-PRECISION 0.1% RESISTORS TO INCREASE OUTPUT VOLTAGE REGULATION (5V, 3.3V, PBUS_LDO) ACCURACY - RADAR:4972500

- FIX LINDA CARD POWER ALIAS (NEED TO CONNECT TO PP3V42_G3HOT INSTEAD OF PP3V3_S5) - RADAR: 4927858

- CHANGE BOM STUFFING TO SPEED UP PORT POWER SHUT-OFF RESPONSE TIME DURING ACTIVE LATE-VG EVENT (RADAR: 4985252)

- CHANGE BOM STUFFING TO ENABLE ON-BOARD MICROPHONE CONNECTOR (M42/M42A SOLUTION) INSTEAD OF ROUTING

- CHANGE BEST CPU FROM 337S3465(2.4GHZ) TO 337S3464(2.2GHZ).

- ADD BOM OPTION TABLE FOR ALL SANYO POSCAP TO USE HF PARTS.

CSA PAGE 4:

- ADD OMIT TO ALL ABOVE PARTS SO THE HF PARTS IN BOM TABLE TAKE OVER.

- ALL 128S0129 BECOME 128S0135.

- ALL 128S0123 BECOME 128S0162.

- ALL 128S0113 BECOME 128S0160.

- ALL 128S0111 BECOME 128S0169.

- ALL 128S0085 BECOME 128S0148.

- ALL 128S0073 BECOME 128S0164.

- ALL 128S0057 BECOME 128S0147.

PER CE, ALL SANYO POSCAPS HAVE NEW HF PART NUMBERS.

8/9/2007

M70 EVT TO DVT CHANGES

M70 EVT TO DVT CHANGES

- TEST POINT MOVEMENTS REQUESTED BY ICT AND MAC-1 GROUPS - RADAR: 4924481

- MODIFY FIREWIRE CONNECTOR SYMBOL TO SUPPORT MINI-DVI CONNECTOR WITH TAB

- CHANGE 10UF, 16V CPU VCORE CAPS TO 10UF, 6.3V CAPS - RADAR: 4952553

- CHANGE LOAD CAP STUFFING OPTION FOR RTC AND ETHERNET CRYSTALS TO MEET 5XESR (-R) REQUIREMENT

PROPERLY DISCHARGE ODD POWER WHEN IT’S TURNED OFF - RADAR: 4923903

M70 PROTO TO EVT CHANGES

- ADD 270K PULL-DOWN RESISTOR ON HTPLG - RADAR: 4888755

- MOVE SMC RESET BUTTON PAD TO TOP SIDE OF MLB - RADAR: 4920913

CSA PAGE 8:

- 4954357 BREAK OUT =PP3V3_S3_AIRPORT_AUX(J3400,PIN 24) FROM PP3V3_S3_AP_AUX AGAIN.

- 4954357 MOVE C3409 AND C3410 FROM PP3V3_S3_AP_AUX RAIL TO =PP3V3_S3_AIRPORT_AUX RAIL.

- NORMAL CHANGES FROM 514-0409 TO 514-0459, FANCY CHANGES FROM 514-0411 TO 514-0479.

- CHANGE J6750 FROM 514-0408 TO 514-0458 (DIFFERENT JEDEC, SAME LANDPATTERN).

- UPDATE BOM OPTION TABLE FOR J6750.

- NORMAL CHANGES FROM 514-0408 TO 514-0458, FANCY CHANGES FROM 514-0410 TO 514-0478.

- CHANGE J6700 FROM 514-0409 TO 514-0459 (DIFFERENT JEDEC, SAME LANDPATTERN).

- CHANGE R9201 AND R9202 FROM 5.23K TO 2.94K.

- NORMAL CHANGES FROM 514-0375 TO 514-0480, FANCY CHANGES FROM 514-0376 TO 514-0481.

- CHANGE L7900 FROM 152S0302 TO 152S0670 FOR CORRECT AVL.

- SMC PART NUMBER CHANGES FROM 341S2088 TO 341S2198.

CSA PAGE 29:

- ADD ALIAS =PP3V3_S3_SMBUS_SMC_MGMT TO PP3V3_S3.

- UPDATE EEE CODES, Z55 FOR GOOD, Z56 FOR BETTER, Z57 FOR BEST.

CSA PAGE 32:

- STUFF C3110 AND C3111.

CSA PAGE 31:

CSA PAGE 9:

- FIX MOJO-CARD SMC TX, RX REVERSAL - RADAR: 4910888

CSA PAGE 90:

- CHANGE SB FROM 338S0427 TO 338S0434.

- CHANGE J3900 FROM 514S0143 TO 514-0443.

- REMOVE NO_TEST=TRUE FOR 1V8S3_COMP, 1V8S3_FSET, 3V3S5_COMP, 3V3S5_FSET, 1V05S0_COMP, 1V05S0_FSET, IMVP6_RBIAS, IMVP6_COMP, 5VS5_RUNSS, 1V5S0_RUNSS.

- REMOVE ALIASES FOR GND_CHASSIS_AUDIO_SPKRCONN,GND_CHASSIS_AUDIO_SHIELD1,GND_CHASSIS_AUDIO_SHIELD2,GND_CHASSIS_AUDIO_SHIELD3,MIC_SHIELD_LVDS_R,MIC_SHLD_CONN.

- ADD FUNC_TEST=TRUE FOR THRM_FINSTACK_P/N.

7/6/2006

- CHANGE U5500 FROM M70 EMC1033 CIRCUIT TO M71 EMC1043 CIRCUIT.

- CHANGE J4810 FROM 518S0369 TO 518S0521.

- CHANGE C2700 FROM 128S0051 TO 128S0113 PER CE.

7/5/2006

- CHANGE R2514 TO 100K.
CSA PAGE 29:

- RENAME CPU_VID_R<6:0> TO CPU_VID<6:0>.

CSA PAGE 71:

- ADDED R6856 NO STUFF.

- CONNECTED MIC_SHLD_CONN TO GND_CHASSIS_AUDIO_MIC THROUGH R6854.

CSA PAGE 68:

- ADDED R6740 NO STUFF.

- REMOVED DZ6772.

- ADDED L6771 AND L6773 TO MIC INPUT EMI FILTER.

- CHANGED ALL TRANSIENT SUPPRESSORS TO 6.8V/100PF DEVICES (WERE ORIGINALLY 8V/100PF DEVICES).

CSA PAGE 67:

- ADDED SMALL 15PF COMPENSATION CAP. TO U6201 FEEDBACK NETWORK (C6224).

- ADDED A NO STUFF PULL-UP TO CODEC_DVDD AT GPIO1.

- RE-CONNECTED /SHDN INPUT OF U6801 SO THAT IT’S CONTROLLED BY U6200 PORTA VREF. - DISCONNECTED GPIO1 AND TERMINATED IT WITH A 10K PULL DOWN.

CSA PAGE 62:

- RE-DRAW CPU VOLTAGE SENSE RC FILTERING.

CSA PAGE 53:

- REMOVE TEXT NOTE WILL CHANGE TO 606P.

CSA PAGE 44:

- CHANGE R2902 FROM 1OHM TO 0OHM.

- CHANGE R2900, R2901 FROM 2.2OHM TO 0OHM.

- NOSTUFF C2907, C2910, C2916, C2911, C2914.

- CHANGE L2902 AND L2903 FROM 155S0302 TO 0OHM R2906 AND R2907.

- ADD R2597 AND R2596 FOR 10K PU ON GPIO6 AND GPIO17(EXTGPU_RST_L).

CSA PAGE 25:

- RENAME LVDS_VREFH/L TO TP_LVDS_VREFH/L.

CSA PAGE 15:

- DELETE TEXT NOTE AND WITH RESET BUTTON.

CSA PAGE 13:

- REMOVE R1290 TO R1296 ON CPU_VID<0:6>.

CSA PAGE 12:

- ADD SPN ALIASES FOR CK505_PCI2/4_CLK.

- ADD SPN ALIASES FOR TP_CK505_SRC7_N/P.

- REMOVE ALIAS FOR =FWPWR_PWRON.

CSA PAGE 9:

- ADD FUNC_TEST=TRUE FOR PP1V05_S0_R.

- REMOVE NO_TEST=TRUE FOR CK505_PCI4_CLK_SPN, CK505_SRC1_N/P_SPN, CK505_SRC3_N/P_SPN, CK505_SRC7_N/P_SPN, CK505_SRC_CLKREQ1/3_L?SPN.

CSA PAGE 8:

- CHANGE J9000 FROM 518S0369 TO 518S0521.

CSA PAGE 90:

- CHANGE J6703 FROM 518S0369 TO 518S0521.

- CHANGE J6702 FROM 518S0487 TO 518S0519.

CSA PAGE 67:

- CHANGE J5601 FROM 518S0369 TO 518S0521.

CSA PAGE 56:

- J5550 CHANGES FROM 2PIN TO 4PIN.

CSA PAGE 55:

CSA PAGE 48:

6/29/2007

M70 DVT TO K36 CHANGES

- REMOVE R4660 AND R4601 (U4675 BYPASS RESISTORS).

CSA PAGE 46:

- CHANGE J2800 FROM 518S0487 TO 518S0519.

CSA PAGE 28:

CSA PAGE 27:

- CHANGE C2173 FROM 128S0051 TO 128S0113 PER CE.

CSA PAGE 21:

- REPLACE ALL M70 WITH K36 (TEXT, BOM OPTIONS, 630 NUMBERS).

CSA PAGE 4:

- 5040728 CHANGE L9404 FROM 155S0303 TO 155S0348.

CSA PAGE 94:

- REPLACE BATTERY INTERFACE CIRCUIT WITH THE ONE ON M42B ESTAR.

- CHANGE J6900 FROM 518S0287 TO 518S0526.

CSA PAGE 69:

- CHANGE J4700 FROM 516S0251 TO 516S0588.

CSA PAGE 47:

- ADD NOSTUFF R4660 AND R4661.

- REMOVE MIN_NECK_WIDTH=0.3MM FROM PP5V_S3_USB2_EXTA/B.

- CHANGE U4600 FROM 353S1245 TO 353S1728.

CSA PAGE 46:

- EDIT BOM OPTION TABLE.

CSA PAGE 39:

- CHANGE STRAPPING FROM 0010 ON GFX_VID<1:4> TO 0001 ON GFX_VID<0:3>.

- CHANGE GFX_VID<1:4> TO GFX_VID<0:3>.

- SIZING DOWN R2205 FROM 0603 TO 0402 FOR PLACEMENT.

- 5282756 ADD C2207 (0.1UF, 0402).

CSA PAGE 22:

- ADD R1600 (0OHM, 0402) TO CONNECT GFX_VID<4> TO GND.

- CONNECT GFX_VID<0:3> TO GFX_VID0:3 ON NB.

- DISCONNECT GFX_VID<0> TO GND.

CSA PAGE 16:

- CHANGE NB FROM 338S0426(500M) TO 343S0448(667M).

- CHANGE BEST CPU FROM 337S3457(2.2G) TO 337S3465(2.4G).

- CHANGE BETTER CPU FROM 337S3456(2.0G) TO 337S3464(2.2G).

- CHANGE GOOD CPU FROM 337S3471(1.8G) TO 337S3463(2.0G).

CSA PAGE 4:

CSA PAGE 49:

- 5040728 STUFF C9421 FOR EMI.

3/5/2007

- 5048817 SYNC 1P25V REGULATOR CIRCUIT FROM M82, CHANGE R AND C TO 0402, CHANGE =PP3V3_S5_P1V25S0 TO =PP3V3_S5_1V25S0,
C7723 FROM 2.2NF TO 10000PF, C7724 FROM 22PF TO 100PF, C7728 FROM 2.2NF TO 10000PF,
AND REVERT REFERENCE DESIGNATORS. (CHANGE FROM TPS62510 TO LTC3412A)

3/12/2007

- 4924443 CHANGE R2514 FROM 100K PULL-UP TO 47K PULL-UP.

CSA PAGE 45:

- 4924443 CHANGE R2514 FROM 100K PULL-DOWN TO 10K PULL-UP TO 3.3V_S5.

- 4986074 CHANGE L2205 TO R2205(100OHM,5%,1/10W,0603).

CSA PAGE 69:

- ADD TEXT NOTE TO UPDATE J4700 FROM 516S0251 TO 516S0588 WHEN SYMBOL IS READY.

- 4986074 CHANGE R9469 FOR CRT_TVO_IREF FROM 1.3K TO 1.21K.

- ADD TEXT NOTE TO UPDATE J6900 FROM 518S0287 TO 518S0526 WHEN SYMBOL IS READY.

- DELETE LVDS_VREFH AND LVDS_VREFL TO GROUND TO FIX LVDS GLITCH.

- ADD TEXT NOTE TO CHANGE L9404 FROM 155S0303 TO 155S0348 WHEN SYMBOL IS READY.

CSA PAGE 77:

- SYNC FROM AUDIO TEAM.

3/14/2007
CSA PAGE 47:

CSA PAGE 94:

CSA PAGE 79:

- UPDATE SYMBOL FOR J4501.

CSA PAGE 22:

- NO STUFF 3G CONNECTOR CIRCUITRY

CSA PAGE 62,66,67,68:
CSA PAGE 67:

CSA PAGE 25:

3/8/2007

CSA PAGE 25:

CSA PAGE 62,66,67,68:

- SYNC FROM AUDIO TEAM.

CSA PAGE 94:

MICROPHONE THROUGH LVDS CABLE

CSA PAGE 34:

- 5029811 CHANGE Q7940 FROM 376S0326 TO 376S0558.

- 4999533 SWAP PIN 2 AND PIN 3 OF MIC CONNECTOR, BACK TO M42 PIN OUT.

Revision History

- WAKE-ON-WIRELESS SUPPORT - RADAR: 4954357

CSA PAGE 4:

CSA PAGE 8:

- ADD CRITICAL TO U2900.
CSA PAGE 44:

- ADD CRITICAL TO U4401.
CSA PAGE 46:

CSA PAGE 49:

CSA PAGE 52:

- STUFFED R6740.
CSA PAGE 68:

- NO STUFFED R6854
CSA PAGE 72:

CSA PAGE 50:

- SMC MANAGEMENT SMBUS CONNECTION:

7/10/2007

- BOOTROM PART NUMBER CHANGES FROM 341S2085 TO 341S2196.

- SMB_ME_CLK AND SMB_ME_DATA ON SOUTHBRIDGE DISCONNECTED FROM SMB_MGMT_CLK AND SMB_MGMT_DATA FROM SMC.B

- THE 10K PULL-UP RESISTORS (R5230 AND R5231), AND STILL REMAIN CONNECTED TO PP3V3_S5_SMBUS_SB_ME AND STAY ON THE SB SIDE.

- ADD TWO NEW 10K PULL-UP RESISTOR (R5232 & R5233) TO =PP3V3_S3_SMBUS_SMC_MGMT.B
CSA PAGE 59:

- ICH8-M ME SMBUS:

- CHANGE R5077 FROM PULL-UP TO A PULL-DOWN RESISTOR AND NAME IT SMC_SMS_INT.

- REMOVE ALIAS FOR =SMC_SMS_INT TO SMC_PG1 - SIGNAL SHOULD JUST BE CALLED SMC_SMS_INT.

- ADD R4670 & R4671. (USB BYPASS ROUTING).

- CHANGE U4675 FROM APN 353S1505 TO APN 353S1742. (SMALL PACKAGE)

CSA PAGE 59:

CSA PAGE 46:

CSA PAGE 67:

CSA PAGE 39:
CSA PAGE 50:

CSA PAGE 62:

CSA PAGE 67:

7/11/2007

- CHANGE R7208 FROM 8.66K TO 15.8K.

- MADE DZ6702, DZ6703, DZ6704, DZ6705, DZ6752, DZ6753, DZ6754, DZ6755, DZ6770, DZ6771B CRITICAL.

- REMOVED NO STUFF RESISTORS R6730, R6731, AND R6732. ALSO REMOVED L6774.

- MADE NO_TEST ATTRIBUTE VISIBLE FOR NET NC_VRP CONNECTED TO PIN 37 OF U6200.

- CHANGED C6210 FROM A CASE-R 10UF TANT. CAP. TO A SMA-LF 3.3UF TANT. CAP.

-ADD 2ND SMS (U5930).

- THE PULL-UP RESISTORS SHOULD BE CONNECTED BETWEEN SMB_MGMT_CLK AND SMB_MGMT_DATA TO =I2C_SMS_SCL AND =I2C_SMS_SDA OF THE NEW ACCELEROMETER.

- STUFF U5930 (DIGITAL ACCELEROMETER) CIRCUIT.

- STUFF C3210 AND C3211.

- REMOVE R5077 (BECOMES R5931).

- ADD R5931 (WAS R5077 BEFORE), 10K PD ON SMC_SMS_INIT.

- ADD R5930, 10K PU ON SMC_SMS_INT.

- UPDATE PN FOR FANCY RJ45 CONNECTOR, 514-0475.

- CHANGE Z0901 AND Z0906 FROM 998-1178 TO 998-1186 (NON-PLATED).

- 4954357 ADD =PP3V3_S3_AIRPORT_AUX BACK TO PP3V3_S3 ALIAS.

- UPDATE BOM OPTION TABLE FOR J6700.

7/17/2007
CSA PAGE 59:

CSA PAGE 43:

7/12/2007

- UPDATE SYMBOL FOR U5930, VENDOR PART NUMBER CHANGES FROM SMB380 TO BMA150.

CSA PAGE 38:

CSA PAGE 4:

7/13/2007

- UPDATE BOM OPTION TABLE FOR J9401.

CSA PAGE 94:

CSA PAGE 79:

- CHANGE C3831 AND C3832 FROM 138S0582 TO 138S0554 (DON’T NEED LOW-PROFILE PARTS).

7/24/2007
CSA PAGE 4:

- CHANGE BETTER AND BEST CPU TO G0 STEPPING PARTS (FROM 337S3464 TO 337S3500).
CSA PAGE 22:

- STUFF R2242 AND NOSTUFF R2247.
CSA PAGE 92:

- CHANGE R9211 AND R9212 FROM 16.5K TO 9.09K.

CSA PAGE 62:

- CHANGE J4300 FROM 514-0289 TO 514-0456 (SAME JEDEC).

- UPDATE BOM OPTION TABLE FOR J4600 AND J4601.

- ADD PAGE_TITLE AUDIO: CODEC.

- NORMAL CHANGES FROM 514-0288 TO 514-0457, FANCY CHANGES FROM 514-0315 TO 514-0477.

- CHANGE J4600 AND J4601 FROM 514-0288 TO 514-0457 (DIFFERENT JEDEC, SAME LANDPATTERN).

- NORMAL CHANGES FROM 514-0359 TO 514-0456, FANCY CHANGES FROM 514-0316 TO 514-0476.

- UPDATE BOM OPTION TABLE FOR J4300.

051-7455

Revision History

5 76

01

SYNC_MASTER=N/A

SYNC_DATE=N/A

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FUNC_TEST

INVERTER CONNECTOR FUNC_TEST

Battery charger FUNC_TEST

DC-JACK FUNC_TEST

MIC FUNC_TEST

USB FUNC_TEST

Battery FUNC_TEST

SMC FUNC_TEST

FIREWIRE FUNC_TEST

SMBus FUNC_TEST

Other Func Test Points

Fan Connectors

SLEEP LED FUNC_TEST

Battery Digital Connector

NO_TEST

FUNC_TEST

NO_TEST

NO_TEST

Audio FUNC_TEST

Functional Test Points

FUNC_TEST

FUNC_TEST

LPC+ Debug Connector

SPEAKER FUNC_TEST

THERMAL FUNC_TEST

Power Supply FUNC_TEST

Power Supply NO_TESTs

NO_TEST

CLOCK NO_TESTS

NO_TEST

FIREWARE NO_TESTS

LVDS NO_TESTS

I1

I10

I11

I111
I112
I113

I114

I115

I116
I117
I118
I119

I12

I120

I122

I125

I15

I151

I152

I153
I154

I155

I156

I157
I158
I159

I16

I160
I161

I162
I163
I164

I166
I167
I168

I169

I17

I171
I172
I173

I174

I175
I176

I177

I178

I18

I180

I181

I182

I183

I186
I187
I188
I189

I19

I190
I191

I194
I195

I199

I20

I200
I201
I202
I203
I204
I205
I206
I207
I208

I209

I21

I210
I211
I212
I213
I214
I215

I219

I22

I220

I221

I222

I223

I224
I225

I226

I227

I228

I229

I23

I230

I231

I232
I233
I234
I235

I236

I237

I238

I239

I24

I240

I241

I242

I243

I244

I25

I29

I3

I31

I32

I33
I36
I38

I4

I44

I45

I46

I47

I48

I57

I58

I59

I60

I61
I63

I71
I72
I73
I74
I75
I76
I77
I78
I79
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89

I9

I90

I91

I92

I93
I94

I95
I96

051-7455

76

01

6

FUNC TEST 1 OF 2

IMVP6_RBIAS

TRUE

CK505_CPU1_N

CK505_DOT96_27M_N

TRUE
TRUE

CK505_DOT96_27M_P

TRUE

CK505_CPU2_ITP_SRC10_N

TRUE

CK505_CPU1_P
CK505_CPU2_ITP_SRC10_P

TRUE

TRUE

CK505_CPU0_P

TRUE

CK505_CPU0_N

TRUE

SMC_TMS
DEBUG_RESET_L

TRUE

SMC_TRST_L

TRUE

TRUE

LPC_AD<1>

TRUE

=PP5V_S0_LPCPLUS

TRUE

LPC_AD<0>

TRUE

ACZ_BITCLK

TRUE

ACZ_SDATAOUT

TRUE

MIC_HI

MIC_LO

TRUE

MIC_SHIELD

TRUE

MIC_HI_CONN

TRUE

TRUE

INV_BKLIGHT_PWM_L

TRUE

PP5V_INV_F

PPVBAT_G3H_CHGR_OUT

TRUE

TRUE

ACIN_ENABLE_GATE

PPBUS_ALL_INV_CONN

TRUE

TRUE

USB2_3G_F_N

TRUE

USB2_BT_F_N

TRUE

USB2_BT_F_P

TRUE

TP_USB_EXTC_N

TRUE

TP_USB_EXTC_P

TP_USB_EXCARD_N

TRUE

TP_USB_EXCARD_P

TRUE

ACZ_RST_L

TRUE

TRUE

USB2_3G_F_P

TRUE

INV_GND

TRUE

SYS_ONEWIRE

LPC_AD<3>

TRUE

SMC_TCK

TRUE

TRUE

LVDS_B_DATA_P1_SPN

TRUE

FW_C_TPA_P_SPN

TRUE

FW_B_TPBIAS_SPN

TRUE

PP3V3_S5

TRUE

PP1V8_S3

TRUE

SMC_LID

SPKRCONN_R_P_OUT

TRUE

SPKRCONN_L_N_OUT

TRUE

SPKRCONN_L_P_OUT

TRUE

TRUE

PPFW_SWITCH

TRUE

SYS_LED_ANODE

SMBUS_SMC_B_S0_SDA

TRUE

SMBUS_SMC_B_S0_SCL

TRUE

LINDACARD_GPIO

TRUE

SMC_TDI

TRUE

TRUE

SMC_MD1

TRUE

SMC_TX_L

TRUE

FWH_INIT_L
PCI_CLK33M_LPCPLUS

TRUE

LPC_AD<2>

TRUE

INT_SERIRQ

TRUE

PM_SUS_STAT_L

TRUE

SMC_RESET_L

TRUE

TRUE

SMC_TDO

TRUE

BOOT_LPC_SPI_L

=PP5V_S0_FAN_RT

TRUE

FAN_RT_PWM

TRUE

FAN_RT_TACH

TRUE
TRUE

SMC_FAN_1_CTL

TRUE

SMC_ADAPTER_EN

TRUE

SMC_BC_ACOK

GND_BT_F

TRUE

TRUE

PP0V9_S0

TRUE

BATT_POS

SMBUS_BATT_SCL_F

TRUE

SMBUS_BATT_SDA_F

TRUE

TRUE

BATT_NEG

SMC_FAN_3_TACH

TRUE

LVDS_B_DATA_P2_SPN

TRUE

TRUE

LVDS_B_DATA_N0_SPN

TRUE

FW_C_TPB_P_SPN

TRUE

=PP3V3_S0_FAN_RT

TRUE

FW_C_TPB_N_SPN

TRUE

LVDS_B_CLK_N_SPN

LVDS_B_DATA_N1_SPN

TRUE

TRUE

FW_C_TPA_N_SPN

TRUE

FW_B_TPB_P_SPN

TRUE

FW_C_TPBIAS_SPN

TRUE

LVDS_B_CLK_P_SPN

TRUE

FW_B_TPB_N_SPN

TRUE

FW_B_TPA_N_SPN

=PP5V_S0_AUDIO

TRUE

GND_AUDIO_AMP

TRUE
TRUE

GND_AUDIO_CODEC

=PP5V_S0_AUDIO_AMP

TRUE

TRUE

SMC_BS_ALRT_L

TRUE

LVDS_B_DATA_N2_SPN

SMC_BATT_CHG_EN

TRUE

TRUE

SMC_BATT_TRICKLE_EN_L

TRUE

ACZ_SYNC

TRUE

ACZ_SDATAIN<0>

TRUE

SMC_BATT_ISET

SMC_NMI

TRUE

SMC_RX_L

TRUE

TRUE

=PP1V05_S0_REG

PP18V5_G3H

TRUE

TRUE

=PP3V42_G3H_LPCPLUS

TRUE

SMC_FAN_1_TACH

PM_CLKRUN_L

TRUE

TRUE

LPC_FRAME_L

TRUE

CK505_SRC8_N

TRUE

CK505_LVDS_P

TRUE

CK505_SRC2_P

TRUE

CK505_SRC2_N

TRUE

CK505_SRC4_N

TRUE

CK505_SRC4_P

TRUE

CK505_SRC5_N
CK505_SRC5_P

TRUE

TRUE

CK505_SRC8_P

TRUE

CK505_SRC6_N
CK505_SRC6_P

TRUE

TRUE

THRM_DIMM_DX_F_N

SPKRCONN_SUB_P_OUT

TRUE

SPKRCONN_SUB_N_OUT

TRUE

MIC_SHLD_CONN

TRUE

MIC_LO_CONN

TRUE

THRM_HEATPIPE_P

TRUE

THRM_HEATPIPE_N

TRUE

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PP3V3_S3_BT_F

TRUE

TRUE

THRM_FINSTACK_P

TRUE

THRM_DIMM_DX_F_P

PP5V_S3

TRUE

PP3V3_S3

TRUE

SMC_MANUAL_RST_L

TRUE
TRUE

SMC_CPU_VSENSE

SPKRCONN_R_N_OUT

TRUE

TRUE

PP3V42_G3H

TRUE

PP1V2_ENET_S0

PP5V_S0

TRUE

PP3V3_S0

TRUE

TRUE

ALL_SYS_PWRGD

TRUE

PP1V5_S0

TRUE

PP1V8_S0

TRUE

PP1V05_S0

PPVCORE_S0_CPU

TRUE
TRUE

PP1V05_S0_R

TRUE

THRM_FINSTACK_N

IMVP6_COMP
5VS5_RUNSS

1V5S0_RUNSS

CK505_LVDS_N

TRUE

TRUE

CK505_PCIF1_CLK

TRUE

FW_B_TPA_P_SPN

57C4

46B6

45B3

66A6

46B4

57A8

45D5

44D5

57C7

54D8

45D5

46B6

75D3

75D3

75D3

75D3

75D3

75D3

75D3

75D3

46B6

46C6

46C6

57C8

46C4

46B4

45C5

46B4

46B4

44C5

75C3

46C4

46B4

46B4

46B4

46B6

38C6

57C3

56C4

54C8

57A2

66A4

66A3

44C5

44C5

46B6

75C3

75D3

75C3

75C3

75C3

75C3

75C3

75C3

75C3

75C3

75C3

56A6

58A3

75C3

75D3

59B7

29D6

29B6

29B6

29D6

29D6

29D6

29D6

29D6

45C5

46B6

46B6

44C8

46C6

44C8

53C7

53C7

56A6

56A6

55D3

66C2

66A6

53B7

45D5

44C8

45C5

44B5

55C2

55C2

55C2

45A3

76C3

76C3

24D5

45C5

46B6

44B8

46C4

44C8

44C8

44C5

45D7

45C5

46B6

50C4

50B4

35C7

45B6

44A8

50C4

53A7

54B8

45C5

45B6

45B6

53C7

53C7

66A8

46B4

44B8

61B8

46C6

50C4

37A5

44C8

29B6

29C6

29C6

29C6

29C6

29C6

29C6

29C6

29B6

29B6

29C6

55C2

55C2

55D3

55D3

48B1

55C2

45D1

44D8

45D2

59B7

65C5

61B5

29C6

29B6

59A4

28C4

28A4

28A4

28C4

28C4

28C4

28C4

28C4

44B5

27D1

44C1

22D4

7A7

22D4

8A5

8A5

55B3

55B3

55B1

67D2

67D3

66B5

57C3

67D3

43A4

43C2

43C2

8B2

8B2

8B2

8B2

8A5

43A4

67D2

44B8

22D4

44B5

8D5

8D1

8D1

7D1

7B4

42C3

54D1

54C1

54C1

38D3

40C5

47C5

47C5

24A7

44B5

44D1

41A8

46C5

29B3

22D4

24C8

24D5

44C3

44B5

23B5

7A7

50B3

50C3

44A8

33C7

44C5

43C2

7D7

57B5

57A5

57A5

57A5

44A4

8D5

8D5

8D1

7C4

8D1

8D5

8D5

8D1

8D1

8D1

8D5

8D1

8D1

7A7

8A4

8B4

7A7

44C5

8D5

44C8

44C8

8A5

8A5

44B5

44C1

41A8

7D8

7B1

7B1

44A8

24C8

22D4

28A4

28B4

28B4

28B4

28B4

28B4

28B4

28B4

28A4

28B4

28B4

49B6

54B1

54B1

55A1

55B1

49D6

49D6

7C1

7B1

43D2

49C6

49B6

7A4

7A4

45D8

44C5

54C1

7C1

7B5

7A7

7D4

27A5

7C7

7B7

7D7

7D7

7D7

49C6

59A4

63B5

58B1

28B4

28B6

8D1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"G3H" RAILS

"S5" RAILS

"S0,S0M" RAILS

(REGULATOR OUTPUT CPU 0.90V PWR)

(DDR2 TERMINATION 0.9V PWR)

(REGULATOR OUTPUT CPU VCORE PWR)

(CPU VCOR PWRE)

"S3" RAILS

051-7455

76

SYNC_DATE=06/15/2006

Power Aliases

SYNC_MASTER=WFERRY

01

7

MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=3.3V

PP3V3_S3

=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_ENET_P3V3ENETFET

=PPVCORE_S0_NB_GFX

=PP5V_S0_3G
=PP5V_S0_LPCPLUS
=PP5V_S0_ISENSECAL
=PP5V_S0_FAN_RT
=PP5V_S0_AUDIO
=PP5V_S0_AUDIO_AMP

=PP5V_S0_CPU_IMVP

=PP5V_S0_SB

VOLTAGE=5V

PP5V_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

=PP5V_S0_NB_GFX_IMVP

=PP5V_S0_LCD
=PP5V_S0_TMDS
=PP5V_S0_NB_TVDAC

=PP5V_S0_SATA

VOLTAGE=1.25V

PPVCORE_S0_NB_GFX

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

=PP1V8_S0_NB_DPLL

MAKE_BASE=TRUE

PP1V8_S0

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

=PP1V5_S0_NB_FOLLOW

=PP1V5_S0_AIRPORT

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_CPU

VOLTAGE=1.5V

PP1V5_S0

MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

=PP1V25_S0_FET

=PP1V25_S0_NB_VCCA

=PP1V25_S0_NB_VCC

=PP1V25_S0_NB_PLL

=PP1V25_S0_NB_VCCAXF

=PP1V25_S0_NB_VCCDMI

=PP1V25_S0_NB_PLL

MAKE_BASE=TRUE

PP1V25_S0

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 mm

=PP1V05_S0M_NB_VCCAXM

=PP1V25R1V05_S0_NB_VTT

=PP1V25R1V05_S0_FSB_NB

=PPVCORE_S0_NB

=PP1V05_S0_NB_PCIE

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V05_S0_R

=PPVCORE_S0_SB

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.05V

MAKE_BASE=TRUE

PP1V05_S0

=PP0V9_S3M_MEM_TERM

=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_VCCPCORE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP3V3_S5

=PP3V3_S5_FET

=PP3V3_S5_SB

=PP3V3_S5_SB_GPIO

=PP3V3_S5_SB_USB

=PP3V3_S5_SB_PM

=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_S5_FWLATEVG

=PP3V3_S5_SMBUS_SB_ME
=PP3V3_S5_ROM
=PP3V3_S5_LCD

=PP3V3_S5_1V25S0
=PP3V3_S5_AIRPORT_AUX

VOLTAGE=5V

PP5V_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

=PP5V_S5_SB

=PP5V_S5_USB

=PP5V_S5_PWRCTL
=PP5V_S5_FET

VOLTAGE=3.42V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V42_G3H

=PP3V42_G3H_SMC

=PP3V42_G3H_SMCVREF
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_ACIN
=PP3V42_G3H_LIDSWITCH
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SB_RTC
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_LPCPLUS

VOLTAGE=18.5V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.6 MM

PP18V5_G3H

=PP18V5_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

=PPVIN_G3H_P3V42G3H

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5V

MAKE_BASE=TRUE

=PPDCIN_G3H

=PPBUSA_G3H

=PP5V_S5_PATA

=PP5V_S5_1V8S30V9S0

=PP3V3_S0_AIRPORT

=PP3V3_S0_SB

=PP3V3_S5_REG

=PP3V3_S0_THRM_SNR

=PP18V5_G3H_INRUSH

=PP3V3_S5_SB_CLINK1

=PP3V3_S0_NB

=PP3V3_S0MWOL_SB_CLINK0

=PPSPD_S0_MEM

MIN_NECK_WIDTH=0.2 mm

PP1V2_ENET_S0

MAKE_BASE=TRUE

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 mm

=PP1V2_ENET_PHY

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S0_PBATTISENS

=PPBUS_S5_FWPWRSW

=PP5V_S5_1V51V05S0

=PP3V3_S0_NB_FOLLOW
=PP3V3_S0_SB_GPIO

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_PM
=PP3V3_S0_RSTBUF

=PP3V3_S0_SMC_LS

=PP3V3_S0_LPCPLUS
=PP3V3_S0_SMBUS_SB

=PP3V3_S0_LCD

=PPVIN_S5_IMVP

=PPVIN_S5_1V5S0
=PPVIN_S5_1V05S0

=PPVIN_S5_5VS5
=PPVIN_S5_3V3S5

=PPVIN_S5_1V8S30V9S0

=PPBUS_S5_INV

=PP3V3_S0_PATA

=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_FW

=PP3V3_S0_SB_VCC3_3_DMI

PPVCORE_S0_CPU

VOLTAGE=0.9V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 MM

=PPVORE_S0_CPU_REG

=PP0V9_S0_REG

=PPVCORE_S0_CPU

=PPVIN_S5_NB_GFX_IMVP

=PPVIN_S5_CPU_IMVP

=PPVCORE_S0_NB_GFX_IMVP

=PP1V8_S0_TMDS

=PP1V8_S0_FET

=PP1V5_S0_REG

=PP5V_S3_IR

=PP5V_S3_GEYSER

=PP5V_S3_SYSLED

=PP3V42_G3H_REG

=PP5V_S5_REG

=PP5V_S3_CAMERA

=PP1V25_S0_REG

=PP5V_S0_FET

=PP1V05_S0_REG

=PP1V05_S0_REG_R

=PP3V3_S0_SB_VCCGLAN3_3

=PP3V3_S0_PDCISENS

=PP3V3_S0_CPUPOWER

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V9_ENET_S0

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=2.5V

=PPBUSB_G3H

=PP3V3_S0MWOL_SB_VCCLAN3_3

=PPVIN_S0_NB_DPLL

=PP3V3_S0MWOL_SB_VCCCL3_3

=PP3V3_S0_FET

=PP3V3_S0_NB_VCCHV

=PP3V3_S0_SB_VCC3_3_SATA

=PP5V_S3_FET

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP3V3_S0

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

=PP3V3_S0_SB_PCI

=PP3V3_S0_TMDS

=PP3V3_S0_AUDIO

=PP3V3_S0_FAN_RT
=PP3V3_S0_ENET

=PP3V3_S0_IMVP

=PP3V3_S0_NB_GFX_IMVP

=PP1V8_S0_YUKON

=PP1V8R2V5_ENET_PHY

PP3V3_ENET_FET

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP1V8_S0_NB_LVDS

=PP5V_S0_IDE_RESET

=PP3V3R1V5_S0_SB_VCCHDA

=PP3V3_S0_NB_VCCA_PEG_BG

=PP3V3_S0_CK505
=PP3V3_S0_NB_VCCSYNC

=PP3V3_S0_TMDS

=PP1V9_ENET_REG

=PP1V8_S3_MEMVREF

=PP1V8_S3_FET

=PP1V8_S3_MEM

=PP1V8_S3M_MEM_NB

=PP1V8_S3_REG

=PP1V8_S3_NB_VCC

=PP3V3_S3_PDCISENS

=PP3V3_S3_SMBUS_SMC_A_S3

VOLTAGE=1.8V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PP1V8_S3_MEM_NB

PP5V_S3

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_S3_ENETPWRCTL

=PP3V3_S3_FET

VOLTAGE=0.9V

PP0V9_S0

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_SB_CPU_IO

=PP1V05_S0_CPU

=PP1V25_S0_SB_DMI

=PP1V2_ENET_REG

=PP3V3_ENET_PHY

=PP1V8_S3_REG_R

=PP3V3_S3_AIRPORT_AUX
=PP3V3_S3_FW
=PP3V3_S3_PCI
=PP3V3_S3_BT
=PP3V3_S3_SMS

=PP1V8_ENET_P1V8ENETFET

PP1V8_S3

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.8V

69C8

69C8

69C2

69C2

12C5

69B7

69B7

12B3

58D3

68D8

68D8

31D6

11A3

51B8

48B5

58C4

21B7

68C8

29D2

68C8

31D4

31D2

10C7

48B3

54D8

20D8

35C7

65B5

45D8

66B8

24D8

48B3

59D8

58C3

20A8

68B7

56B5

29B2

68B7

31B2

30D2

9D5

21C5

56C4

54C8

26D6

20D3

20D3

20D8

29C6

20B4

26C6

65C4

26D8

26D2

33D7

58D5

45D4

66A8

31A7

24B3

67C6

11D7

59D4

66C3

58B8

18B3

68B2

55D8

28D8

68B2

30D6

20C8

26C4

9C5

51B6

17D5

46C6

50C4

53A7

54B8

26B6

26C2

26D5

26C8

11B3

20B4

20A8

20B4

17C1

20C8

29B6

17D7

26D2

45D2

26B4

26A6

65A5

24A8

26D2

26B6

26B2

38A8

33D6

58C6

45C1

66A5

46C6

39C8

49D2

31A3

26C6

22D7

26B4

27B8

67B7

63B6

26A8

10D7

59C2

58C4

62C5

45A4

58D4

61B8

61C5

26D3

26B2

58B3

15C7

26B8

26C2

45D1

68B1

53D7

50C4

26C4

20A6

28D3

21B5

68B1

35D1

20A6

30D4

17D7

62C2

65C3

25C3

9B6

26A6

6A2

47C3

35D3

17B7

43B5

6D2

48B8

6D2

6D1

6D1

59D8

26D8

6A2

60D2

67D7

69D7

21D6

40C6

21A7

6B2

21D5

33D2

25A6

25B6

25B6

26A8

21D8

10B7

6B2

58A3

20B8

20A8

7C7

20D4

18C3

7C7

17B3

18D3

13B7

17D3

20D5

6B2

25D3

6B2

32D4

25C3

25C3

6A2

58C5

24A3

24D8

23C8

27C5

25A3

25A3

25B3

38A6

47A7

52C6

67C7

64B6

33C7

6A2

26D8

41C8

65B6

58B3

6A2

44D4

45C8

47C3

57C4

57A8

65C7

27D7

41A6

6D2

6A2

66D8

64C6

6A2

57D3

66C2

39D6

62C5

33C6

26D8

63B1

49C2

57D1

24B1

69C8

24C1

30A7

6A2

34D6

25B6

66B3

38D5

61C4

20B2

22D2

25B3

27B6

27D4

45D4

46C4

47D8

67B5

45A6

61B3

61B5

63A6

63B3

62B3

67D4

39C2

47D5

47C5

38C6

25C3

6B2

59D1

62B8

10B5

60C2

48D7

60C2

68D6

58B8

61B1

43D8

42D6

40B6

64C4

63B8

67A5

64B2

58C8

6B2

61C7

25A6

60C2

48D2

66C2

25A3

25A6

58A3

15B7

25C3

65B4

25B6

6A2

23A3

7C4

53A7

6D2

8A4

59D8

60C7

36D8

34C7

35D4

21C5

39B7

25B3

18C6

28C8

18D6

7C4

35B2

20A5

58C5

30B2

15D2

62B2

20A4

62A2

47D3

6A2

35D7

65A4

6A2

22D2

9B5

25C3

35C1

34D6

62C4

33C2

37D5

37C5

43D3

51C7

35C3

6A2

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FOR LAYOUT PLACEMENT
BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL

CPU HEATSINK STANDOFF SCREW HOLE

Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL

NB CFG ALIASES

DCIN CONNECTOR CHASSIS GND

NO-CONNECT UNUSED LVDS INTERFACE PORTS

(EMI PAD FOR INVERTER GONNECTOR)

DIP DIMM CONNECTOR CHASSIS GND

USB PORT [0] = External USB2.0 Port A

USB PORT [1] = PCI-E Mini Card

USB PORT [2] = 3G USB

USB PORT [3] = CAMERA

USB PORT [4] = IR CONTROLLER

USB PORT [5] = Trackpad(Geyser)

USB PORT [6] = BLUETOOTH

NO-CONNECT UNUSED FIREWIRE INTERFACE PORTS

ANALOG SWITCH GPIO

NB ALIASES

USB PORT [9] = Unused

USB PORT [8] = Unused

USB PORT [7] = External USB2.0 Port B

SO-DIMM ALIASES

PCI_EXP ALIASES

SATA ALIASES

NO-CONNECT UNUSED SATA INTERFACE PORTS

NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS

NO-CONNECT UNUSED SDVO INTERFACE PORTS

NO-CONNECT UNUSED ADDRESS INTERFACE PORTS

FIREWIRE ALIASES

DIP DIMM CONNECTOR CHASSIS GND

NC NC

I/O CONNECTOR CHASSIS GND

PCI_EXPRESS GRAPHICS ALIASES

AIRPORT CARD STANDOFF SCREW HOLE

Ethernet ALIASES

SATA,LVDS CONNECTOR CHASSIS GND

LVDS ALIASES

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

CLOCK ALIASES

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

SB ALIASES

BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND

CHASSIS GND

1

5R2P3-7SQBNP

OMIT

Z0906

Z0902

1

7X7R2P3-5B

OMIT

C0908

1

2

0.01UF

10%
16V
CERM
402

C0907

1

2

X5R

16V

10%
402

0.1UF

1

5R2P3-7SQBNP

OMIT

Z0901

Z0909

1

5R2P3-7SQB

OMIT

Z0911

1

OMIT

5R2P3-7B

Z0910

1

OMIT

5R2P3-7SQB

R0912

1

2

5%

0

1/16W
MF-LF
402

Z0913

1

OMIT

STDOFF-4.2OD3.95H-5.52R3.37-6B

Z0912

1

OMIT

STDOFF-4.2OD2.15H-1.2-3.2-TH

Z0908

1

OMIT

5P0R2P3-7BLB

ZS0920

1

EMI-SPRING

CLIP-SM-M42

Z0904

1

OMIT

STDOFF-4.2OD3.95H-5.52R3.37-7SQB

Z0921

1

OMIT

STDOFF-4.5OD3.95H-1.1-3.2-TH

Z0907

1

OMIT

6P5R2P6-7SQB

Z0903

1

OMIT

STDOFF-4.2OD3.95H-5.52R3.37-6B

C0930

1

2

0.1UF

X5R

10%
16V

402

C0910

1

2

16V
X5R
402

10%

0.1UF

C0911

1

2

402

CERM

16V

10%

0.01UF

C0916

1

2

402

16V

10%

0.1UF

X5R

C0917

1

2

0.01UF

10%
16V

402

CERM

C0914

1

2

16V

10%
402

0.1UF

X5R

C0915

1

2

10%
402

0.01UF

16V
CERM

C0912

1

2

X5R

0.1UF

10%
16V

402

C0913

1

2

402

10%

0.01UF

CERM

16V

C0918

1

2

402

10%
X5R

16V

0.1UF

C0919

1

2

0.01UF

10%
16V
CERM
402

R0910

1

2

MF-LF

5%
1/16W

402

0

R0921

1

2

1/16W
MF-LF
402

5%

0

Z0905

1

OMIT

STDOFF-4.5OD3.95H-1.1-3.2-TH

R0911

1

2

1/16W

0

5%
MF-LF

402

XW0802

1 2

SM

XW0801

1 2

SM

4

STANDOFF

Z0903,Z0904,Z0905,Z0921

860-0876

THERMAL STANDOFF

1

860-0723 STANDOFF

Z0912

STANDOFF WIRELESS

860-0749

1

STANDOFF

Z0913

STANDOFF W/THRU HOLES,WIRELESS

051-7455

SYNC_DATE=07/17/2006

76

01

8

SIGNAL ALIAS /RESET

SYNC_MASTER=GPU

=GND_CHASSIS_DIPDIMM_LEFT

=GND_CHASSIS_AUDIO_MIC

=GND_CHASSIS_AUDIO_JACK

=GND_BATT_CHGND

GND_CHASSIS_IO

SATA_C_R2D_C_P_SPN

MAKE_BASE=TRUE

SATA_C_D2R_N_SPN

MAKE_BASE=TRUE

FW_B_TPA_P

TP_HDA_SDIN2

CPU_THERMAL_SCREW_UP

=GND_CHASSIS_TMDS_UPPER

=GND_CHASSIS_RJ45

GND_CHASSIS_DCIN

MAKE_BASE=TRUE

VOLTAGE=0V

=GND_CHASSIS_LVDS

=GND_CHASSIS_3GPOWER

MAKE_BASE=TRUE

LVDS_B_CLK_P_SPN
LVDS_B_DATA_N0_SPN

MAKE_BASE=TRUE

=GND_CHASSIS_FW_DOWN
=GND_CHASSIS_USB

USB_EXTA_P
USB_EXTA_N

MAKE_BASE=TRUE

USB2_3G_P

=USB2_3G_P

MAKE_BASE=TRUE

EXTAUSB_OC_L

USB2_AIRPORT_N

MAKE_BASE=TRUE

USB2_CAMERA_P

MAKE_BASE=TRUE

USB2_CAMERA_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB_IR_P

MAKE_BASE=TRUE

USB_IR_N

MAKE_BASE=TRUE

USB2_GEYSER_P

MAKE_BASE=TRUE

USB2_GEYSER_N

USB_BT_P

MAKE_BASE=TRUE

USB_BT_N

MAKE_BASE=TRUE

=USB2_IR_P

MEM_CLK_P_5_SPN

MAKE_BASE=TRUE

=PP3V3_S0_ENET
=YUKON_EC_PP2V5_ENET

MAKE_BASE=TRUE

HDN_SPIN3_SPN

MAKE_BASE=TRUE

HDN_SPIN2_SPN

MAKE_BASE=TRUE

HDN_SDIN1_SPN

TP_HDA_SDIN3

NB_CFG<3>
NB_CFG<4>
NB_CFG<6>

NB_CFG<7>
NB_CFG<8>

=GND_CHASSIS_TMDS_DOWN

=GND_CHASSIS_FW_UPPER

MAKE_BASE=TRUE

TP_NB_CFG<3>

MAKE_BASE=TRUE

ACZ_SYNC

ACZ_BITCLK

MAKE_BASE=TRUE

MEM_A_A15_SPN

MAKE_BASE=TRUE

=NB_TDB_FORCE

=NB_TDE_SENSE

=NB_CLK96M_DOT_P

=GFX_VR_EN

MAKE_BASE=TRUE

PM_EXTTS_L<1>

MAKE_BASE=TRUE

TP_USB_EXTC_N

=USB2_EXTA_N

TP_MEM_CLKN5

MEM_CLK_N_5_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PEG_D2R_P10_SPN

PEG_D2R_P<9>

PEG_D2R_P<8>

PEG_D2R_P<7>

PEG_D2R_P<5>

PEG_D2R_P<4>

PEG_D2R_P<0>

PEG_D2R_N<15>

PEG_D2R_N<13>

PEG_D2R_N<6>

TP_LVDS_B_DATAP3

=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N

=NB_TDE_FORCE

=NB_CLK96M_DOT_N

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_N

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_P

MAKE_BASE=TRUE

NB_CLK96M_DOT_N

NB_CLK96M_DOT_P

MAKE_BASE=TRUE

CLINK_MPWROK

MAKE_BASE=TRUE

GFX_VR_EN

MAKE_BASE=TRUE

PM_EXTTS_L<0>

MAKE_BASE=TRUE

MEM_CLK_N_2_SPN

MAKE_BASE=TRUE

MEM_B_A15_SPN

MAKE_BASE=TRUE

SATA_B_R2D_C_N

SATA_C_D2R_P

MAKE_BASE=TRUE

TP_USB_EXCARD_P

MAKE_BASE=TRUE

TP_USB_EXCARD_N

EXTBUSB_OC_L

MAKE_BASE=TRUE

USB2_EXTB_N

MAKE_BASE=TRUE

USB2_EXTB_P

MAKE_BASE=TRUE

=USB2_BT_N

MAKE_BASE=TRUE

SATA_B_D2R_N_SPN

SATA_C_R2D_C_N_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCIE_A_D2R_N_SPN

TP_PCIE_A_D2R_N

=NB_CLINK_MPWROK

DIMM_OVERTEMPA_L

DIMM_OVERTEMPB_L

MAKE_BASE=TRUE

LVDS_A_DATA_N3_SPN

LVDS_B_DATA_N2_SPN

MAKE_BASE=TRUE

=GND_AUDIO_AMP

MEM_CLK_P_2_SPN

MAKE_BASE=TRUE

USB_EXTC_P

USB_EXTC_N

HDA_SDOUT

PEG_R2D_C_P<15>

HDA_RST_L
HDA_SDIN0

MAKE_BASE=TRUE

PEG_R2D_C_P7_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P8_SPN
PEG_R2D_C_P9_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PEG_R2D_C_P4_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N15_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N8_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N6_SPN

PEG_R2D_C_N4_SPN

MAKE_BASE=TRUE

PEG_D2R_P14_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N5_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>

PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>

MAKE_BASE=TRUE

PEG_R2D_C_N13_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P5_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P6_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N9_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N7_SPN

MAKE_BASE=TRUE

PEG_D2R_P13_SPN

PEG_D2R_P12_SPN

MAKE_BASE=TRUE

PEG_D2R_P11_SPN

MAKE_BASE=TRUE

TP_PCIE_A_R2D_C_P

TP_PCIE_B_D2R_P

TP_PCIE_FW_R2D_C_P

MAKE_BASE=TRUE

PEG_D2R_P5_SPN

MAKE_BASE=TRUE

PEG_D2R_N14_SPN

MAKE_BASE=TRUE

PCIE_D_R2D_C_P_SPN

MAKE_BASE=TRUE

PCIE_D_R2D_C_N_SPN

MAKE_BASE=TRUE

PCIE_C_D2R_P_SPN

TP_PCIE_B_D2R_N

MAKE_BASE=TRUE

PCIE_B_R2D_C_P_SPN

MAKE_BASE=TRUE

PCIE_C_D2R_N_SPN

TP_PCIE_A_R2D_C_N

SATA_C_D2R_P_SPN

MAKE_BASE=TRUE

SATA_B_R2D_C_N_SPN

MAKE_BASE=TRUE

SATA_B_R2D_C_P

SATA_B_R2D_C_P_SPN

MAKE_BASE=TRUE

SATA_B_D2R_P

MAKE_BASE=TRUE

SATA_B_D2R_P_SPN

SATA_B_D2R_N

MAKE_BASE=TRUE

PEG_D2R_N0_SPN
PEG_D2R_N2_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P<7>

MAKE_BASE=TRUE

LVDS_B_DATA_P0_SPN

FW_C_TPB_N

PEG_D2R_P4_SPN

MAKE_BASE=TRUE

PEG_D2R_P<6>

MAKE_BASE=TRUE

PEG_D2R_N15_SPN

FW_B_TPBIAS_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

FW_B_TPA_P_SPN

MAKE_BASE=TRUE

FW_B_TPB_N_SPN

FW_C_TPA_P
FW_C_TPA_N
FW_C_TPB_P

GND_CHASSIS_CPU

MAKE_BASE=TRUE

FW_C_TPB_N_SPN

FW_C_TPB_P_SPN

MAKE_BASE=TRUE

FW_C_TPA_N_SPN

MAKE_BASE=TRUE

FW_C_TPA_P_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

FW_C_TPBIAS_SPN

MAKE_BASE=TRUE

FW_B_TPA_N_SPN

FW_B_TPB_N
FW_C_TPBIAS

FW_B_TPB_P

FW_B_TPBIAS

FW_B_TPA_N

PEG_D2R_P0_SPN

MAKE_BASE=TRUE

PEG_D2R_P<15>

=GND_CHASSIS_DIPDIMM_CENTER

GND_CHASSIS_FANSCREW

=GND_DCIN_CHGND

USB_TPAD_P
USB_TPAD_N

USB_IR_P
USB_IR_N

USB_BT_P
USB_BT_N

USB_EXCARD_P

USB_EXTB_OC_L

USB_EXTA_OC_L

MAKE_BASE=TRUE

USB2_EXTA_N

MAKE_BASE=TRUE

USB2_EXTA_P

=USB2_EXTA_P

=EXTAUSB_OC_L

USB_MINI_P
USB_MINI_N

MAKE_BASE=TRUE

USB2_AIRPORT_P

=USB2_AIRPORT_P
=USB2_AIRPORT_N

USB_EXTD_N

USB_EXTD_P

USB2_3G_N

MAKE_BASE=TRUE

=USB2_3G_N

USB_CAMERA_P
USB_CAMERA_N

=USB2_CAMERA_P

MAKE_BASE=TRUE

VOLTAGE=0V

GND_CHASSIS_RIGHT

=EXTBUSB_OC_L

=USB2_EXTB_P

=USB2_BT_P

=USB2_GEYSER_P

TP_PCIE_A_D2R_P

NB_RIGHT_DOWN_SCREW

MAKE_BASE=TRUE

PEG_R2D_C_N14_SPN

CPU_THERMAL_SCREW_DOWN

GND_CHASSIS_CENTER

MAKE_BASE=TRUE

VOLTAGE=0V

PEG_D2R_N<0>

=USB2_EXTB_N USB_EXTB_N

=USB2_IR_N

USB_EXCARD_N

PEG_D2R_P8_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

VOLTAGE=0V

GND_CHASSIS_IO

=USB2_CAMERA_N

=USB2_GEYSER_N

TP_LVDS_A_DATAP3

PEG_D2R_P6_SPN

MAKE_BASE=TRUE

PEG_D2R_N8_SPN

MAKE_BASE=TRUE

LVDS_B_CLK_N

LVDS_B_CLK_N_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

LVDS_B_DATA_N3_SPN

LVDS_B_DATA_N<0>

LVDS_B_CLK_P

MAKE_BASE=TRUE

LVDS_B_DATA_P1_SPN

LVDS_B_DATA_N1_SPN

MAKE_BASE=TRUE

LVDS_B_DATA_N<1>
LVDS_B_DATA_N<2>

TP_LVDS_B_DATAN3

LVDS_B_DATA_P<0>
LVDS_B_DATA_P<1>

PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_N<11>
PEG_D2R_N<12>

PEG_D2R_N<14>

PEG_D2R_P<2>
PEG_D2R_P<3>

PEG_D2R_P<10>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>

PEG_R2D_C_N<4>
PEG_R2D_C_N<5>

PEG_R2D_C_N<9>

PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>

PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>

PEG_R2D_C_P11_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P10_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PEG_R2D_C_N10_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N11_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N12_SPN

PEG_D2R_P9_SPN

MAKE_BASE=TRUE

PEG_D2R_P2_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PEG_D2R_N6_SPN

PEG_D2R_N3_SPN

MAKE_BASE=TRUE

SATA_C_D2R_N

PCIE_B_D2R_N_SPN

MAKE_BASE=TRUE

PCIE_A_R2D_C_P_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCIE_A_R2D_C_N_SPN

PCIE_A_D2R_P_SPN

MAKE_BASE=TRUE

SATA_C_R2D_C_P

SATA_C_R2D_C_N

TP_PCIE_FW_D2R_P

TP_HDA_SDIN1

HDA_SYNC

HDA_BIT_CLK

MAKE_BASE=TRUE

TP_USB_EXTC_P

PEG_R2D_C_P12_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P13_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P14_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P15_SPN

MAKE_BASE=TRUE

TP_NB_CFG<4>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_NB_CFG<6>

MAKE_BASE=TRUE

TP_NB_CFG<7>

MAKE_BASE=TRUE

TP_NB_CFG<8>

LVDS_B_DATA_P<2>

MAKE_BASE=TRUE

VOLTAGE=0V

GND_CHASSIS_SATA

VOLTAGE=0V

GND_CHASSIS_IO1

MAKE_BASE=TRUE

PEG_D2R_N7_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

ACZ_RST_L

MAKE_BASE=TRUE

ACZ_SDATAIN<0>

MAKE_BASE=TRUE

ACZ_SDATAOUT

=GND_AUDIO_CODEC

MEM_A_A<15>

TP_MEM_CLKP5

TP_LVDS_A_DATAN3

CPU_THERMAL_SCREW_RIGHT

MAKE_BASE=TRUE

FW_B_TPB_P_SPN

USB_EXTB_P

=NB_TDB_SENSE

MAKE_BASE=TRUE

LVDS_B_DATA_P3_SPN

MAKE_BASE=TRUE

LVDS_B_DATA_P2_SPN

MAKE_BASE=TRUE

LVDS_A_DATA_P3_SPN

PEG_D2R_N4_SPN

MAKE_BASE=TRUE

PEG_D2R_N5_SPN

MAKE_BASE=TRUE

PEG_D2R_N<5>

PEG_D2R_N<4>

PEG_D2R_N<3>

PEG_D2R_N<2>

VOLTAGE=0V

INVT_CHGND

MAKE_BASE=TRUE

TP_MEM_CLKN2

TP_MEM_CLKP2

=ENET_VMAIN_AVLBL

MAKE_BASE=TRUE

GND_AUDIO_AMP

MAKE_BASE=TRUE

GND_AUDIO_CODEC

MEM_B_A<15>

MAKE_BASE=TRUE

PEG_D2R_P7_SPN

MAKE_BASE=TRUE

PEG_D2R_P15_SPN

MAKE_BASE=TRUE

PCIE_D_D2R_P_SPN

MAKE_BASE=TRUE

PCIE_D_D2R_N_SPN

PCIE_C_R2D_C_P_SPN

MAKE_BASE=TRUE

TP_PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_R2D_C_N

TP_PCIE_EXCARD_R2D_C_P

PEG_D2R_N13_SPN

MAKE_BASE=TRUE

PEG_D2R_N9_SPN

MAKE_BASE=TRUE
MAKE_BASE=TRUE

PEG_D2R_N10_SPN

TP_PCIE_FW_R2D_C_N

TP_PCIE_FW_D2R_N

MAKE_BASE=TRUE

PCIE_C_R2D_C_N_SPN

MAKE_BASE=TRUE

PCIE_B_R2D_C_N_SPN

MAKE_BASE=TRUE

PCIE_B_D2R_P_SPN

MAKE_BASE=TRUE

CLINK_MPWROK=SB_CLINK_MPWROK

MAKE_BASE=TRUE

VR_PWRGD_CK505VR_PWRGD_CLKEN

MAKE_BASE=TRUE

SB_CLK100M_SATA_OE_L

SB_SATA_CLKREQ_L

MAKE_BASE=TRUE

TP_SB_GPIO17EXTGPU_RST_L

TP_CK505_SRC1_N
TP_CK505_SRC1_P
TP_CK505_SRC3_N

MAKE_BASE=TRUE

CK505_SRC1_N_SPN

CK505_SRC3_N_SPN

MAKE_BASE=TRUE

CK505_SRC1_P_SPN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CK505_PCI4_CLK_SPN

MAKE_BASE=TRUE

CK505_SRC7_P_SPN

MAKE_BASE=TRUE

CK505_PCI2_CLK_SPN

MAKE_BASE=TRUE

CK505_SRC7_N_SPN

CK505_PCI2_CLK

TP_CK505_SRC7_P

CK505_PCI4_CLK

TP_CK505_SRC7_N

CK505_SRC3_P_SPN

MAKE_BASE=TRUE

TP_CK505_SRC3_P

MAKE_BASE=TRUE

PEG_D2R_P3_SPN

MAKE_BASE=TRUE

PEG_D2R_N12_SPN

MAKE_BASE=TRUE

PEG_D2R_N11_SPN

TP_PCIE_EXCARD_D2R_N

TP_PCIE_B_R2D_C_P

TP_PCIE_B_R2D_C_N

MAKE_BASE=TRUE

ENET_CLKREQ_L

=ENET_CLKREQ_L

=GND_CHASSIS_DIPDIMM_RIGHT

56C4 56B8 56B5

56B4 56B1 56A8 56A4 55B3

54C8 54B8

67B2

41C4

73B3

73B3

54C8

54A8

67A6

41C2

23C2

23C2

54B8

73B3

73B3

73B3

73B3

53D3

69C4

67A4

43B5

41A4

73B3

73B3

8C1

8C1

53C7

53C7

44B8

75B3

75B3

75B3

75B3

27A6

44B8

54A8

73B3

73B3

73B3

73C3

73C3

31A5

73B3

73B3

23C2

23C2

23C2

23C2

73B3

73B3

73B3

73B3

73B3

73B3

73B3

73C3

73C3

53B7

53C7

53C7

53B7

73B3

27A6

24C5

75D3

75D3

34B8

30A5

56A4

55C3

57A6

37B3

22C8

69A4

36B2

67A2

43A5

6A7

6A7

38B1

41A2

23C2

23C2

43A4

43C4

7C4

34C7

22C8

15B6

15B6

15B6

15B6

15B6

69A3

38B1

6C1

6C1

19C2

19D2

15C3

15B3

15B7

6C1

41A8

15C6

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14D3

15C6

15C3
15C3

19C2

15C3

29C3

29C3

29B3

29B3

8B3

60C6

15B7

22B6

22B6

6C1

6C1

43C3

23D5

15A3

30C4

31C4

6A7

54A5

23C2

23C2

22B8

14A3

22C8

22C8

14B3

14B3

14B3

14B3

14B3

14B3

23D5

23D5

23D5

23D5

23D5

22B6

22B6

22B6

14B3

37B3

14C3

6B7

6B7

6B7

37B3

37B3

37B3

6B7

6B7

6B7

6B7

6B7

6B7

37B3

37B3

37B3

37B3

37B3

14C3

30D5

57C8

23C2

23C2

8C2

8C2

8C2

8B2

23C2

23C8

23C8

41A8

41C8

23C2

23C2

33B3

33B3

23C2

23C2

43A4

23C2

23C2

67B4

41C8

41B5

43C3

42C7

23D5

14D3

41B5 23C2

43C4

23C2

8D7

67A4

42C7

15C6

14C5

6A7

14C5

14C5

6A7

6A7

14C5

14C5

15C6

14C5

14C5

14D3

14D3

14D3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14C3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14B3

14A3

14A3

14A3

22B6

22B6

22B6

23D5

22C8

22C8

22C8

6C1

14C5

40C8

6C1

6D1

6D1

53A7

30C4

15C6

15C6

6B7

23C2

19C2

6A7

14D3

14D3

14D3

14D3

67C2

15C6

15C6

34C2

6D1

6D1

31C4

23D5

23D5

23D5

23D5

23D5

8B1

24C3

27A8 24C5

28B4 24C5

24B5

28B4

28B4

28B4

28B6

28B4

28B6

28B4

28B4

23D5

23D5

23D5

28A4

31D4

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN

OUT

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN
IN
IN
IN
IN

IN
IN

IN
IN

OUT

IN
IN

IN

IN

IN
IN

IN

IN

OUT

BI
BI
BI
BI

LOCK*

INIT*

A20M*

A6*

A3*
A4*

A14*

A16*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD9

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*
A21*
A22*
A23*
A24*

A26*
A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

NC

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

RESERVED

ADDR GROUP0ADDR GROUP1

ICH

DINV1*

D31*

D30*

D25*

D11*
D12*
D13*
D14*

DSTBP0*
DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

DATBP1*

D0*

D32*
D1*
D2*

D5*

D16*

D20*
D21*
D22*
D23*
D24*

D26*
D27*
D28*
D29*

DSTBN1*

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL0
BSEL1
BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*
DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4
PIN. MAKE SURE CPU_TEST4 IS

R1002

1

2

1%
1/16W

54.9

MF-LF
402

R1004

1

2

68

5%
1/16W

402

MF-LF

R1005

1

2

1/16W

1%

MF-LF

1K

402

R1006

1

2

1%

MF-LF

2.0K

1/16W

402

R1019

1%

MF-LF

1/16W

54.9

402

R1018

27.4

1/16W
MF-LF

1%

402

R1017

1%

MF-LF

1/16W

54.9

402

R1016

1%

MF-LF

1/16W

27.4

402

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B3 70C3

13A3 70C3

13B3 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B5 70C3

13B3 70C3

13A3 70C3

13B3 70C3

15B6 22C4 59C7 70B3

22C4 70B3

13B3 70D3

13A5 70B3

27B3

12B1 22C4 70C3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13D5 70D3

13C5 70D3

13C5 70D3

13C5 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13C5 70C3

13B3 70C3

13B3 70C3

13B3 70C3

29B6 70B3

29A6 70B3

29C6 70B3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13D3 70C3

13C3 70C3

13C3 70C3

13A3 70C3

13A3 70C3

13A3 70C3

13A3 70C3

13A3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70D3

13C3 70D3

13C3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

13B3 70D3

12B2 70A3

12B2 70A3

12B2 70A3

12B3 70A3

12B2 70A3

12B2 70A3

9A7

12B5 70B3

12B4 27C6

45B5 45C3 59C8 70C3

49B7

15A6 22C2 45B3 70B3

22C4 46B2 70B3

12B5 13A5 70D3

13A3 70D3

13A3 70D3

13A3 70D3

13B3 70D3

9A7

12B2 12B3 70B3

9B7

12B3 70B3

9B7

12B2 70B3

9A7

12B3 70A3

49C7

29D3 75C3

29D3 75C3

22C4 70C3

22C4 70B3

22C4 70C3

22C4 70C3

22C4 70B3

22C4 70B3

22C2 70C3

R1030

0

1/16W
MF-LF

5%

NOSTUFF

402

R1007

1

2

1/16W

5%

MF-LF

1K

NOSTUFF

402

R1003

1

2

1/16W

1%

MF-LF

54.9

402

R1020

1%

MF-LF

1/16W

54.9

402

R1021

54.9

1/16W
MF-LF

1%

402

R1022

54.9

1/16W
MF-LF

1%

402

13C3 70C3

13C3 70C3

13C3 70C3

13C3 70C3

R1023

649

1/16W
MF-LF

1%

402

R1012

1

2

1/16W

5%

1K

NOSTUFF

MF-LF

402

C1000

1

2

X5R

NOSTUFF

0.1uF

10%
16V

402

U1000

N3
P5

P2

L2
P4

P1
R1

Y2
U5

R3

W6

A6

U4

Y5

U1
R4

T5

T3
W2

W5
Y4

J4

U2

V4
W3

AA4

AB2
AA3

L5
L4

K5

M3
N2

J1

H1

M1

V1

A22

A21

E2

AD4

AD3
AD1

AC4

G5

F1

C20

E1

H5
F21

A5

G6

E4

D20

C4

B3

C6

B4

H4

B1

AC2
AC1

D21

K3
H2

K2

J3
L1

C1

F3
F4

G3

M4

N5
T2

V3
B2

C3

D2

D22

D3

F6

A3

D5

AC5

AA6
AB3

A24

B25

C7

AB5

G2

AB6

OMIT

MEROM

FCBGA

U1000

B22

B23
C21

R26

U26
AA1

Y1

E22
F24

J24

J23
H22

F26

K22
H23

N22

K25
P26

R23

E26

L23
M24

L22

M23
P25

P23

P22
T24

R24
L25

G22

T25

N25

Y22
AB24

V24

V26
V23

T22

U25
U23

F23

Y25

W22
Y23

W24
W25

AA23

AA24
AB25

AE24

AD24

G25

AA21

AB22

AB21
AC26

AD20

AE22
AF23

AC25

AE21
AD21

E25

AC22
AD23

AF22

AC23

E23

K24

G24

M26

H25

N24

U22

AC20

E5

B5
D24

J26

L26

Y26

AE25

H26

AA26

AF24

AD26

AE6

D6

D7

C23
D25

C24

AF26

AF1

A26

OMIT

MEROM

FCBGA

R1024

1%

MF-LF

1/16W

54.9

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

402

SYNC_DATE=11/12/2006

SYNC_MASTER=T9_MLB_NOME

76

051-7455

01

9

CPU FSB

TP_CPU_TEST5

FSB_DINV_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<25>

FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>

FSB_DSTB_L_P<0>
FSB_DINV_L<0>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<19>

FSB_D_L<18>

FSB_DSTB_L_P<1>

FSB_D_L<0>

FSB_D_L<32>
FSB_D_L<1>
FSB_D_L<2>

FSB_D_L<5>

FSB_D_L<16>

FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>

FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>

FSB_DSTB_L_N<1>

CPU_GTLREF
CPU_TEST1

CPU_TEST2
TP_CPU_TEST3
CPU_TEST4

TP_CPU_TEST6

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>

FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>

CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>

CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L

FSB_D_L<17>

FSB_D_L<4>

FSB_D_L<3>

FSB_DSTB_L_N<0>

FSB_D_L<15>

FSB_D_L<10>

FSB_LOCK_L

CPU_INIT_L

CPU_A20M_L

FSB_A_L<6>

FSB_A_L<3>
FSB_A_L<4>

FSB_A_L<14>

FSB_A_L<16>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD9

TP_CPU_RSVD8

TP_CPU_RSVD7

TP_CPU_RSVD6

TP_CPU_RSVD5

TP_CPU_RSVD4

TP_CPU_RSVD3

TP_CPU_RSVD2

TP_CPU_RSVD1

TP_CPU_RSVD0

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_STPCLK_L

CPU_FERR_L

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>

FSB_A_L<26>
FSB_A_L<27>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

FSB_A_L<25>

CPU_IGNNE_L

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

XDP_TCK

XDP_TDO

XDP_TMS

XDP_TDI

XDP_TRST_L

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

CPU_THERMD_N

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<2>

12C5

12C5

12C5

12C5

12B3

12B3

12B3

12B3

11A3

11A3

11A3

11A3

10C7

10C7

10C7

10C7

70B3

9D5

9D5

9D5

9C5

12B3

70B3

70B3

70B3

70A3

9C5

9B6

9C5

9B6

12B2

12B5

12B2

12B3

12B3

9B5

9B5

9B6

9B5

70B3 70B3

70B3

70B3

70B3

70C3

9C6

9C6

9C6

9C6

9C6

7C7

7C7

7C7

7C7

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

VCC

VSSSENSE

VCCSENSE

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VCCA

VCCP

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

11.5 A (Deeper Sleep)

25.0 A (Deep Sleep HFM)

27.4 A (Sleep HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

30.4 A (LFM)

25.5 A (SuperLFM)

9.4 A (Enhanced Deeper Sleep)

2500 mA (after VCC stable)

4500 mA (before VCC stable)

16.0 A (Deep Sleep SuperLFM)

16.8 A (Sleep SuperLFM)

41.0 A (HFM)

44.0 A (Design Target)

Standard Voltage:

(CPU CORE POWER)

130 mA

(CPU IO POWER 1.05V)

(CPU INTERNAL PLL POWER 1.5V)

Low Voltage:

Ultra Low Voltage:

17.0 A (Design Target)23.0 A (Design Target)

21.0 A (HFM)

18.7 A (LFM)
TBD A (SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Sleep HFM)
TBD A (Sleep SuperLFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep SuperLFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep) TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep HFM)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (HFM)
TBD A (LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep LFM)

TBD A (Deep Sleep LFM)

CPU_VID<2>
CPU_VID<3>

CPU_VID<5>

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<0>
CPU_VID<1>

=PPVCORE_S0_CPU

CPU_VID<6>

CPU_VID<4>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

SYNC_DATE=11/12/2006

SYNC_MASTER=T9_MLB_NOME

CPU Power & Ground

051-7455

01

10 76

MF-LF
402

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

1/16W

1%

100

2

1

R1100

FCBGA

MEROM

OMIT

V25

V22

V5

V2

U24

U21

U6

U3

T26

T23

B8

T4

T1

R25

R22

R5

R2

P24

P21

P6

P3

B6

N26

N23

N4

N1

M25

M22

M5

M2

L24

L21

AF2

L6

L3

K26

K23

K4

K1

J25

J22

J5

J2

A23

H24

H21

H6

H3

G26

G23

G1

G4

F25

F22

A19

F2

F19

F16

F13

F11

F8

F5

E24

E21

E19

A16

E16

E14

E11

E8

E6

E3

D26

D23

D19

D16

A14

D13

D11

D8

D4

D1

C25

C22

C2

C19

C16

A11

C14

C11

C8

AF25

A25

AF21

C5

AF19

AF16

AF13

AF11

AF8

AF6

A2

AE26

AE23

AE19

B24

AE16

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

B21

AD13

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

B19

AC11

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

B16

AB8

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

B13

AA5

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

B11

A8

A4

U1000

FCBGA

MEROM

AE7

AE2

AF3

AE3

AF4

AE5

AF5

AD6

AF7

N6

N21

M21

K21

J21

M6

K6

J6

W21

V21

T6

T21

R6

R21

V6

G21

C26

B26

AF20

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

B7

AE17

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

A20

AD12

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

A18

AC7

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

A17

AB9

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

A15

F20

F18

F17

F15

F14

F12

F10

F9

F7

E20

A13

E18

E17

E15

E13

E12

E10

E9

E7

D18

D17

A12

D15

D14

D12

D10

D9

C18

C17

C15

C13

C12

A10

C10

C9

B20

B18

B17

B15

B14

B12

B10

B9

A9

A7

U1000

70A3 59A5 59A4

70A3 59A5 59A4

70A3 59C7

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

MF-LF
402

100

1%
1/16W

2

1

R1101

70A3 59C7

70A3 59C7

70A3 59C7

70A3 59C7

70A3 59C7

70A3 59C7

OMIT

12C5 12B3 11A3

48B5

48B5

9D5

48B3

48B3

9C5

11D7

11D7

9B6

10D7

10B5

11B3

9B5

7D7

7D7

7C7

7C7

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

CPU VCORE HF AND BULK DECOUPLING

C1250, C1251, C1252 AND C1253 NEED TO USE 6mOHM CAPS.

PLACE ON BOTTOMSIDE

PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)

PLACE ON BOTTOMSIDE

LAYOUT NOTE:

LAYOUT NOTE:

LAYOUT NOTE:

LAYOUT NOTE:
PLACE C1235 CLOSE TO CPU

PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)

4x 330uF. 20x 10uF 0805

1X 330UF, 6X 0.1UF

VCCP (CPU I/O) DECOUPLING

VCCA (CPU AVdd) DECOUPLING

PLACE C1281 NEAR PIN B26 OF U1000

LAYOUT NOTE:

1x 10uF, 1x 0.01uF

C1235

1

2 3

CRITICAL

330uF

10%

2.5V
TANT

D2T

C1237

1

2

20%
10V
CERM

0.1UF

402

C1238

1

2

0.1UF

CERM

10V

20%

402

C1239

1

2

20%
10V
CERM

0.1UF

402

C1240

1

2

0.1UF

CERM

10V

20%

402

C1241

1

2

0.1UF

CERM

10V

20%

402

C1210

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1216

1

2

805-2

6.3V
X5R

CRITICAL

10%

10UF

C1201

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1202

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1203

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1204

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1205

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1206

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1207

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1208

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1209

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1214

1

2

805-2

6.3V
X5R

CRITICAL

10%

10UF

C1213

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1212

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1211

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1219

1

2

805-2

6.3V
X5R

CRITICAL

10UF

10%

C1200

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1236

1

2

402

0.1UF

CERM

10V

20%

C1215

1

2

805-2

6.3V
X5R

10UF

10%

CRITICAL

C1217

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1218

1

2

805-2

6.3V
X5R

10UF

CRITICAL

10%

C1281

1

2

0.01UF

16V
CERM
402

10%

C1280

1

2

10uF

20%

6.3V
X5R
603

C1250

1

23

D2T

2.0V

330UF

10%

CRITICAL

TANT

C1251

1

23

D2T

2.0V

330UF

TANT

10%

CRITICAL

C1252

1

23

2.0V

330UF

CRITICAL

TANT

10%

D2T

C1253

1

23

D2T

2.0V

330UF

TANT

10%

CRITICAL

CPU Decoupling & VID

76

01

SYNC_DATE=04/26/2006

SYNC_MASTER=MSARWAR

11

051-7455

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

12C5 12B3 10C7

48B5

9D5

48B3

9C5

10D7

9B6

10B5

9B5

10B7

7D7

7C7

7C7

OUT

IN
IN

OUT

OUT

OUT

OUT

IO

IN

OUT

IN

IO

IO

IO

IO

IO

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(FROM CK505 HOST 133/167MHZ)

516S0394

INDICATE THAT ITP IS USING TAP I/F, NC IN 965GM CHIPSET SYSTEM.

TO ICH8M SYS_RST*, AND WITH SYSTEM RESET LOGIC

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S

ITP TCK SIGNAL LAYOUT NOTE:

CONNECTOR’S FBO PIN.

TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

(DBA#)
(DEBUG PORT ACTIVE)

(DBR#)

(DEBUG PORT RESET)

(FBO)

CPU ITP700FLEX DEBUG SUPPORT

(TCK)

C1300

1

2

0.1UF

X5R

10%

ITP

16V
402

R1302

1 2

ITP

22.6

1%
1/16W
MF-LF

402

R1301

1

2

NOSTUFF

54.9

MF-LF
402

1/16W

1%

R1300

1 2

ITP

MF-LF

402

1/16W

1%

22.6

J1302

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

ITP

M-ST-SM

CRITICAL

QT500306-L021-9F

01

12 76

SYNC_DATE=5/23/05

CPU ITP700FLEX DEBUG

SYNC_MASTER=MASTER

051-7455

=PP1V05_S0_CPU

XDP_TDO

XDP_TRST_L

XDP_BPM_L<2>

CPU_PWRGD

XDP_BPM_L<1>

FSB_CPURST_L

XDP_BPM_L<4>

=PP1V05_S0_CPU

ITPRESET_L

ITP_TDO

XDP_TMS
LVDS_CTRL_DATA
LVDS_CTRL_CLK

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_BPM_L<3>

CPU_XDP_CLK_P

CPU_XDP_CLK_N

XDP_TCK

XDP_TDI

12B3

12C5

11A3

11A3

10C7

10C7

9D5

9D5

9C5

9C5

70B3

70B3

9B6

70B3

70A3

70C3

70D3

9B6

70B3

12B3

12B2

70B3

9B5

9C6

9C6

70A3

22C4

70A3

13A5 70A3

9B5

9C6

67A7

67A7

9C6

70A3

70A3

27C6

70A3

9C6

9C6

7C7

9A7

9A7

9C6

9B2

9C6

9D6 9C6

7C7

9B7

14D5

14D5

9A7

9C5

9C6

9C6

9C6

29D3

29D3

9A7

9B7

BI

BI
BI

OUT

OUT

BI

BI

BI

BI
BI

BI

BI
BI
BI
BI

BI
BI

BI

BI
BI

BI
BI
BI
BI

BI
BI

OUT

BI

OUT

OUT

OUT

BI
BI
BI
BI
BI

BI
BI

H_D0*

H_D3*

H_D2*

H_D33*
H_D34*
H_D35*

H_D1*

H_D4*

H_D10*

H_A4*
H_A5*
H_A6*
H_A7*
H_A8*

H_A9*
H_A10*
H_A11*
H_A12*
H_A13*
H_A14*
H_A15*
H_A16*
H_A17*
H_A18*
H_A19*
H_A20*
H_A21*
H_A22*
H_A23*
H_A24*
H_A25*
H_A26*
H_A27*
H_A28*
H_A29*
H_A30*
H_A31*
H_A32*
H_A33*
H_A34*
H_A35*

H_ADS*

H_ADSTB0*
H_ADSTB1*

H_A3*

H_D7*
H_D8*
H_D9*

H_D11*
H_D12*
H_D13*
H_D14*
H_D15*
H_D16*
H_D17*
H_D18*
H_D19*
H_D20*
H_D21*
H_D22*
H_D23*

H_D25*
H_D26*
H_D27*
H_D28*
H_D29*
H_D30*

H_D32*

H_D36*
H_D37* H_BNR*
H_D38*

H_BPRI*
H_D39*
H_D40*

H_DEFER*

H_D41*

H_DBSY*
H_D42*
H_D43*
H_D44*

H_DPWR*
H_D45*

H_DRDY*
H_D46* H_HIT*
H_D47*

H_HITM*
H_D48*

H_LOCK*

H_TRDY*

H_D51*
H_D52*
H_D53*

H_DINV0*

H_D54*

H_DINV1*

H_D55*

H_DINV2*

H_D56*

H_DINV3*

H_D57*
H_D58*

H_DSTBN0*

H_D59*

H_DSTBN1*

H_D60*

H_DSTBN2*

H_D61*

H_DSTBN3*

H_D62*
H_D63*

H_DSTBP0*
H_DSTBP1*

H_DSTBP2*
H_SWING
H_RCOMP

H_REQ0*
H_SCOMP H_REQ1*
H_SCOMP*

H_REQ2*

H_REQ3*
H_CPURST*

H_REQ4*
H_CPUSLP*

H_RS0*
H_RS1*

H_AVREF

H_RS2*

H_DVREF

H_D5*
H_D6*

H_D31*

H_BREQ*

H_D24*

H_D49*
H_D50*

H_DSTBP3*

HPLL_CLK

HPLL_CLK*

HOST

(1 OF 10)

BI
BI
BI
BI

BI

IN

IN

IN

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI

BI

BI

BI
BI
BI
BI
BI

BI

BI
BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

9D8

70C3

9D8

70C3

9C8

70C3

9D6

70D3

9D6

70D3

9D6

70D3

9D6

70D3

9D6

70D3

9B2

70D3

9D6

70D3

9D8

70C3

C1425

1

2

402

16V

10%

0.1uF

X5R

R1426

1

2

402

1/16W

1%

MF-LF

2.0K

R1425

1

2

402

1/16W

1%

MF-LF

1K

9C4

70D3

9B4

70C3

9C2

70C3

9B2

70C3

9C4

70D3

9B4

70C3

9D8

70C3

9C2

70C3

9B2

70C3

9C4

70D3

9B4

70C3

9C2

70C3

9B2

70C3

9C6

70D3

9C6

70D3

9D6

70D3

9D8

70C3

9D6

70D3

9D6

70D3

9D6

70D3

9D8

70C3

9D8

70C3

9D8

70C3

9D8

70C3

9C8

70C3

9D8

70C3

R1420

1

2

402

1/16W

1%

MF-LF

54.9

R1415

1

2

402

1/16W

1%

MF-LF

24.9

R1410

1

2

402

1/16W

1%

MF-LF

221

R1411

1

2

402

1/16W

1%

MF-LF

100

C1410

1

2

402

16V

10%

0.1uF

X5R

9D8

70C3

U1400

G17

C14

K16
B13

L16

J17
B14

K19

P15
R17

B16
H20

L19

D17
M17

N16

J19
B18

E19

B17

J13

B15

E17
C18

A19

B19
N19

B11
C11

M11

C15
F16

L13

G12
H17

G20

B9

C8
E8

F12

B6
E5

E2

G2

M10

N12

N9
H5

P13

K9
M2

W10

Y8

V4

G7

M3
J1

N5

N3
W6

W9

N2
Y7

Y9
P4

M6

W3

N1

AD12

AE3

AD9
AC9

AC7

AC14
AD11

AC11

H7

AB2

AD7

AB1

Y3

AC6

AE2
AC5

AG3

AJ9
AH8

H3

AJ14

AE9

AE11

AH12

AJ5

AH5

AJ6
AE7

AJ7

AJ2

G4

AE5

AJ3
AH2

AH13

F3

N8

H2

C10

D6

K5

L2
AD13

AE13

H8

K7

M7

K3
AD2

AH11

L7

K2
AC2

AJ10

A9

E4

C6

G10

C2

M14

E13

A11
H13

B12

E12

D7
D8

W1

W2

B3

B7

AM5
AM7

FCBGA

CRESTLINE

OMIT

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

R1421

1

2

402

1/16W

1%

MF-LF

54.9

9D6

70D3

29D3 75C3

29D3 75C3

9D6

12B5 70D3

9A2

70B3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C4

70D3

9D8

70C3

9D8

70C3

9D8

70C3

9D8

70C3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70C3

9B4

70C3

9C4

70C3

9C4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9D8

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9D8

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9D8

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9B2

70C3

9C2

70C3

9C2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9D8

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9D6

70D3

SYNC_MASTER=T9_MLB

13 76

01

051-7455

NB CPU Interface

SYNC_DATE=10/30/2006

=PP1V25R1V05_S0_FSB_NB

FSB_D_L<47>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>

FSB_D_L<1>

FSB_D_L<10>

FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>

FSB_D_L<11>

FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>

FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>

FSB_D_L<32>

FSB_D_L<36>
FSB_D_L<37>

FSB_D_L<39>
FSB_D_L<40>

FSB_D_L<42>

FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>

FSB_D_L<48>

FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>

FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

NB_FSB_SCOMP
NB_FSB_SCOMP_L

FSB_CPURST_L
FSB_CPUSLP_L

FSB_D_L<6>

FSB_D_L<31>

FSB_D_L<24>

FSB_D_L<49>
FSB_D_L<50>

FSB_D_L<12>

FSB_D_L<43>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<0>

FSB_D_L<38>

FSB_D_L<41>

FSB_D_L<59>

NB_FSB_SWING
NB_FSB_RCOMP

NB_FSB_VREF

FSB_A_L<3>

FSB_A_L<6>

FSB_A_L<4>
FSB_A_L<5>

FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>

FSB_A_L<32>

FSB_A_L<30>
FSB_A_L<31>

FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>

FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>

FSB_BPRI_L

FSB_BNR_L

FSB_BREQ0_L
FSB_DEFER_L
FSB_DBSY_L

FSB_DPWR_L

FSB_CLK_NB_P
FSB_CLK_NB_N

FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L

FSB_TRDY_L

FSB_LOCK_L

FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>

FSB_DSTB_L_N<0>
FSB_DSTB_L_N<1>
FSB_DSTB_L_N<2>
FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0>
FSB_DSTB_L_P<1>
FSB_DSTB_L_P<2>
FSB_DSTB_L_P<3>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_RS_L<2>

29C6 29B6

7C7

IN

IN

OUT

IN

OUT
OUT
OUT

IN
IN

OUT
OUT
OUT

OUT

IN

OUT

OUT

BI

L_BKLT_CTRL

L_VDD_EN

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX14

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX15

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_COMPI
PEG_COMPO

CRT_DDC_DATA

L_CTRL_DATA

LVDSB_DATA1
LVDSB_DATA2

LVDSB_DATA0

LVDSB_DATA2*

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA2

LVDSA_DATA0
LVDSA_DATA1

LVDSB_CLK*

LVDS_VREFL

LVDS_IBG

TVC_RTN

TVA_RTN
TVB_RTN

TVC_DAC

TVB_DAC

TVA_DAC

CRT_RED*

CRT_RED

CRT_GREEN*

CRT_GREEN

CRT_BLUE*

CRT_BLUE

CRT_VSYNC

CRT_TVO_IREF

CRT_HSYNC

CRT_DDC_CLK

L_BKLT_EN

L_DDC_CLK

TV_DCONSEL0
TV_DCONSEL1

LVDSA_DATA2*

L_DDC_DATA

LVDSA_DATA1*

LVDSA_DATA0*

LVDSB_CLK

LVDSA_CLK

LVDSA_CLK*

LVDS_VREFH

L_CTRL_CLK

LVDS_VBG

VGA

TV

LVDS

(3 OF 10)

PCI-EXPRESS GRAPHICS

BI

BI

OUT

OUT

IN

IN
IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

IN

BI
BI

OUT
OUT
OUT
OUT

OUT
OUT

IN

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

IN

OUT
OUT
OUT

OUT

OUT

OUT

BI
BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

rails must be filtered except for VCCA_CRT.

Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).

decoupling. Otherwise, tie VCCD_LVDS to GND also.

Can leave all signals NC if LVDS is not implemented.

S-Video: DACB & DACC only

Unused DAC outputs must remain powered, but can

share filtering with VCCA_CRT_DAC.

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.

Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

CRT & TV-Out Disable

All CRT/TVDAC rails must be powered. All

omit filtering components. Unused DAC outputs

VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,
VCCD_CRT, VCCD_QDAC and VCC_SYNC.

NOTE: Must keep VDDC_TVDAC powered
and filtered at all times!

Internal Graphics Disable

Follow instructions for LVDS and CRT & TV-Out Disable above.

TV_DCONSELx to GND.

Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and

Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.

Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).
Tie VCC_AXG and VCC_AXG_NCTF to GND.
Leave GFX_VID<3..0> and GFX_VR_EN as NC.

Tie TVx_DAC and TVx_RTN to GND. Must power all

TV-Out Disable / CRT Enable

CRT Disable / TV-Out Enable

VSYNC and CRT_TVO_IREF to GND.
Can tie the following rails to GND:

TV-Out Signal Usage:

Composite: DACA only

Component: DACA, DACB & DACC

should connect to GND through 75-ohm resistors.

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can

Tie VCC_TX_LVDS and VCCA_LVDS to GND.

LVDS Disable

If SDVO is used, VCCD_LVDS must remain powered with proper

SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP

SDVOB_BLUE
SDVOB_CLKP

SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVOC_RED#
SDVOC_GREEN#
SDVOC_BLUE#
SDVOC_CLKN

SDVOB_RED
SDVOB_GREEN

SDVO_FLDSTALL

SDVO_INT

SDVO_TVCLKIN

SDVO_INT#

SDVO_TVCLKIN#

SDVO Alternate Function

SDVO_FLDSTALL#

8C6

8C6

R1510

1

2

402

MF-LF

1/16W

1%

24.9

67B8

8C6

69B8

69A8

69A8

69D7

69D8

69D7

69A8

8C6

69B8

69A8

67A8 71C3

U1400

H32

G32

K33

G35

K29
J29

F33

F29

E29

C32

E33

J40
H39

E39

E40
C37

D35
K40

L41
L43

N41

N40

C45

D46

G50

G51

E50

E51

F48

F49

E42

D44

E44

G44

A47

B47

A45

B45

N43
M43

J50

J51

L50

L51

AC45

AD44

AC41

AD40

AH47

AG46

AG49

AH49

AH45

AG45

AG42

AG41

M47

N47

U44

T45

T49

T50

T41

U40

W45

Y44

W41

Y40

AB50

AB51

Y48

W49

M45

N45

T38

U39

AD47

AC46

AC50

AC49

AD43

AC42

AG39

AH39

AE50

AE49

AH43

AH44

T46

U47

N50

N51

R51

R50

U43

T42

W42

Y43

Y47

W46

Y39

W38

AC38

AD39

M35
P33

E27

F27

G27

J27

K27

L27

OMIT

CRESTLINE

FCBGA

12B1 67A7

12B1 67A7

69C8

69C8

8C6

8C6

8C6

8C6

8C6

8C6

8D6

68B6 71D3

8C6

8C6

8C6

8C6

8C6

8C6

8C6

8C6

8C6

68B6 71D3

8C6

8B6

8B6

8B6

68C6 71D3

68C6 71D3

8B6

8A6

8B6

8B6

8C6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8C6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8B6

8C6

68B6 71D3

68B6 71D3

68B6 71D3

68B6 71D3

68C6 71D3

68C6 71D3

67C6

67D8

8C6

67B6

67B6

67B3 71D3

67B3 71D3

8D6

8D6

67B2 71D3

67B2 71D3

8C6

67B2 71D3

8D6

8D6

8D6

67B2 71D3

67B2 71D3

67B2 71D3

8D6

8D6

8D6

8C6

69D8

69D8

69D8

69D7

69D7

69D7

69B8

69B8

SYNC_DATE=10/30/2006

14 76

01

051-7455

NB PEG / Video Interfaces

SYNC_MASTER=T9_MLB

=TV_B_RTN

=TV_B_DAC

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_CTRL_DATA

LVDS_CTRL_CLK

TP_LVDS_VBG

PEG_D2R_P<9>

PEG_D2R_P<11>

PEG_D2R_P<10>

PP1V05_S0_NB_VCCPEG

PEG_D2R_N<1>

PEG_D2R_N<6>

TP_LVDS_VREFH

LVDS_A_CLK_N
LVDS_A_CLK_P

LVDS_B_CLK_P

LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>

TV_DCONSEL<1>

TV_DCONSEL<0>

LVDS_BKLT_EN

CRT_DDC_CLK

=CRT_HSYNC_R
=CRT_TVO_IREF
=CRT_VSYNC_R

=CRT_BLUE
=CRT_BLUE_L
=CRT_GREEN
=CRT_GREEN_L
=CRT_RED
=CRT_RED_L

=TV_A_DAC

=TV_C_DAC

=TV_A_RTN

=TV_C_RTN

LVDS_IBG

TP_LVDS_VREFL

LVDS_B_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

CRT_DDC_DATA

PEG_COMP

PEG_D2R_N<0>

PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>

PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>

PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>

PEG_D2R_P<12>
PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>

PEG_D2R_P<14>

PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>

PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>

LVDS_BKLT_CTL

LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_VDD_EN

20D3 18B3

IN

IN

CLKREQ*

NC1

NC8

CL_CLK

CL_PWROK

CL_RST*

RSVD6

THERMTRIP*

PM_BM_BUSY*

RSVD4

RSVD3

RSVD7

SM_CKE1

SM_CK0*

SM_CKE0

SM_ODT0

SM_ODT2

SM_RCOMP

SM_RCOMP*

SM_VREF0
SM_VREF1

SM_RCOMP_VOL

SM_CS1*

SM_CS0*

RSVD14

RSVD11

RSVD10

RSVD9

RSVD5

RSVD8

RSVD2

DPLL_REF_CLK*

DPLL_REF_SSCLK

PEG_CLK

DMI_RXN1

DMI_RXN0

DMI_RXN3

DMI_RXN2

DMI_RXP0
DMI_RXP1
DMI_RXP2

DMI_TXN0

DMI_RXP3

DMI_TXN2

DMI_TXN1

DMI_TXP0

DMI_TXN3

DMI_TXP1
DMI_TXP2
DMI_TXP3

PEG_CLK*

RSVD12

CL_DATA

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

ICH_SYNC*

TEST1
TEST2

GFX_VID0
GFX_VID1
GFX_VID2

GFX_VR_EN

GFX_VID3

RSVD20
RSVD21

RSVD24
RSVD25

RSVD27

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39

RSVD41
RSVD42

RSVD40

RSVD43
RSVD44
RSVD45

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13

CFG16

CFG15

CFG14

CFG17
CFG18
CFG19
CFG20

PM_DPRSTP*
PM_EXT_TS0*

PWROK

PM_EXT_TS1*

RSTIN*

DPRSLPVR

NC2

NC4

NC3

NC5

NC7

NC6

NC10

NC9

NC12

NC11

NC13
NC14
NC15
NC16

DPLL_REF_CLK

SM_RCOMP_VOH

SM_ODT3

SM_ODT1

RSVD13

SM_CS2*
SM_CS3*

SM_CK3
SM_CK4

SM_CK4*

SM_CKE3

RSVD1

SM_CKE4

DPLL_REF_SSCLK*

SM_CK3*

SM_CK1*

SM_CK1

SM_CK0

SA_MA14

RSVD22
RSVD23

RSVD26

SB_MA14

SM_CK2
SM_CK2*
SM_CK5
SM_CK5*

(2 OF 10)

RSVD

DDR MUXING

CLK

CFG

DMI

PM

GRAPHICS VID

ME

MISC

NC

OUT
OUT
OUT
OUT
OUT

BI
BI

IN

OUT

BI

BI
OUT
OUT

IN

IN

OUT

OUT
OUT

IN
IN
IN
OUT

OUT
OUT
OUT

BI

OUT

BI

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT

IN

IN
IN

IN

IN

IN

IN

IN
IN
IN
IN

IN
IN

IN

IN

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

IPU

NB CFG<13:12> require ICT access

IPU

IPU

RESERVED

RESERVED

Low = DMIx2

NB_CFG<8>

IPU

IPU

IPU

IPU

IPU

IPU

IPU
IPU
IPU
IPU
IPD

IPD

IPD

IPU

RESERVED

NB_CFG<6>

NB_CFG<7>

RESERVED

RESERVED

RESERVED

High = Normal

Low = Reversed

NB_CFG<10>

NB_CFG<9>

PCIe Graphics
Lane Reversal

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

See Below

See Below

Low = Disabled

High = Enabled

10 = All-Z Mode Enabled

01 = XOR Mode Enabled

Low = Normal

High = Both active

NB_CFG<13:12>

Low = Only SDVO

High = Reversed

11 = Normal Operation

or PCIe x16

00 = RESERVED

NB_CFG<19>

NB_CFG<20>

Concurrent
SDVO/PCIe x1

Reversal

DMI Lane

NB_CFG<13>

NB_CFG<12>

NB_CFG<11>

NB_CFG<16>

NB_CFG<14>

NB_CFG<17>

ODT

FSB Dynamic

NB_CFG<15>

NB_CFG<18>

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
If ME/AMT is not used, short CL_PWROK to PWROK.

PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

NOTE: GMCH CL_PWROK input must be PWRGD signal for

DMI x2 Select

NB_CFG<5>

NB_CFG<4>

IPU

NB CFG<8:0> used for debug access

High = DMIx4

NB_CFG<3>

Clk used for PEG and DMI

27D1

20A4

C1616

1

2

402

CERM

20%

0.1uF

10V

C1615

1

2

402

CERM

20%

0.1uF

10V

U1400

P27
N27

R24

L23
J23

E23

E20
K23

M20

M24
L32

N33

N24

L35

C21
C23

F23

N23
G23

J20

C20

AM49

AK50
AT43

AN49
AM50

G39

AN47
AJ38

AN42

AN46

AM47
AJ39

AN41

AN45

AJ46
AJ41

AM40
AM44

AJ47

AJ42

AM39
AM43

B42

C42
H48

H47

G36

E35
A39

C38

B39
E36

G40

BJ51

E1
A5

C51

B50
A50

A49
BK2

BK51
BK50

BL50
BL49

BL3

BL2
BK1

BJ1

K44

K45

G41
L39

L36
J36

AW49

AV20

P36

AR37

AM36

AL36
AM37

D20

P37

H10

B51
BJ20

BK22

BF19
BH20

BK18
BJ18

R35

BH39

AW20
BK20

C48

D47

B44

N35

C44

A35

B37

B36

B34

C34

AR12

AR13

AM12
AN13

J12

BJ29
BE24

H35
K36

AV29

AW30

BB23

BA23

BF23

BG23

BA25

AW25

AV23

AW23

BC23

BD24

BE29

AY32

BD39
BG37

BG20

BK16

BG16
BE13

BH18

BJ15
BJ14

BE16

BL15

BK14

BK31
BL31

AR49

AW4

A37
R32

N20

CRESTLINE

FCBGA

OMIT

21B6 60C6

21B6 60C6

21B6 60C6

21B6 60C6

8B2

24C3 74A3

24C3 74A3

8B2

24C3 74A3

68A6

68A6

28B4

24B5

R1691

1

2

402

20K

MF-LF

1/16W

5%

R1690

1

2

402

0

MF-LF

1/16W

5%

24C3 59D8 70B3

8B2

44B8

R1631

1

2

402

10K

MF-LF

5%
1/16W

C1625

1

2

0.01UF

10%
16V

CERM

402

C1624

1

2

603

2.2UF

6.3V
CERM1

20%

R1624

1

2

1K

MF-LF

1%
1/16W

402

R1622

1

2

402

1%
1/16W
MF-LF

3.01K

C1622

1

2

603

6.3V
CERM1

2.2UF

20%

C1623

1

2

0.01UF

10%
16V

CERM

402

R1620

1

2

1K

402

1/16W

1%

MF-LF

R1641

1

2

402

392

MF-LF

1/16W

1%

R1640

1

2

402

MF-LF

1/16W

1K

1%

C1640

1

2

402

20%
10V

CERM

0.1uF

R1655

1

2

402

5%

3.9K

MF-LF

1/16W

NBCFG_DMI_X2

R1659

1

2

402

5%
1/16W
MF-LF

3.9K

NBCFG_PEG_REVERSE

R1666

1

2

402

NBCFG_DYN_ODT_DISABLE

3.9K

1/16W

5%

MF-LF

R1669

1

2

402

3.9K

MF-LF

1/16W

5%

NBCFG_DMI_REVERSE

R1670

1

2

402

5%
1/16W
MF-LF

3.9K

NBCFG_SDVO_AND_PCIE

60C6

30C4 32C6 72D3

31C4 32A5 72B3

29C8 70B3

29B8 70B3

29B8 70B3

8A6

8A6

8A6

8A6

15D7

24D5

8A6

R1600

1 2

0

5%
1/16W
MF-LF

402

9C6

22C2 45B3 70B3

8B2

44B8

9B2

22C4 59C7 70B3

27B5 59C7

30D4 72D3

31A4 72B3

31D4 72B3

30A4 72D3

30D4 72D3

31A4 72B3

31D4 72B3

30A4 72D3

30C6 32D6 72D3

30C4 32D6 72D3

31C6 32D6 72B3

30B4 32D6 72D3

31C4 32D5 72B3

30B6 32D6 72D3

31B4 32D6 72B3

31B6 32D6 72B3

30B4 32D6 72D3

30B6 32D6 72D3

31B4 32D6 72B3

31B6 32D6 72B3

R1610

1

2

MF-LF

1/16W

1%

20

402

R1611

1

2

1/16W

1%

MF-LF

20

402

20A5

29C3 75B3

29C3 75B3

8B2

8B2

8B2

8B2

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

23D2 71D3

R1630

1

2

402

MF-LF

1/16W

5%

10K

051-7455

01

7615

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

NB Misc Interfaces

GFX_VID<4>

DMI_N2S_P<0>

DMI_N2S_P<2>

CLINK_NB_CLK
CLINK_NB_DATA
=NB_CLINK_MPWROK
CLINK_NB_RESET_L

SDVO_CTRLCLK

TP_NB_RSVD<42>

TP_NB_RSVD<41>

TP_NB_RSVD<43>

NB_BSEL<1>

NB_CFG<3>

NB_CFG<9>

TP_NB_CFG<12>

TP_NB_CFG<15>
NB_CFG<16>

DMI_N2S_N<3>

DMI_N2S_P<1>

DMI_N2S_P<3>

GFX_VID<1>

=GFX_VR_EN

GFX_VID<3>

TP_LVDS_A_DATAP3

TP_NB_RSVD<34>

MEM_B_A<14>

TP_NB_RSVD<27>

TP_NB_RSVD<26>

TP_NB_RSVD<25>

NB_BSEL<0>

NB_CFG<5>

MEM_CKE<4>

TP_NB_RSVD<1>

MEM_CLK_P<0>

MEM_CLK_N<4>

MEM_CLK_N<3>

MEM_CLK_P<4>

MEM_CLK_P<3>

TP_NB_RSVD<13>

TP_NB_NC<16>

TP_NB_NC<15>

TP_NB_NC<14>

TP_NB_NC<13>

TP_NB_NC<11>
TP_NB_NC<12>

TP_NB_NC<9>
TP_NB_NC<10>

TP_NB_NC<6>
TP_NB_NC<7>

TP_NB_NC<5>

TP_NB_NC<3>

TP_NB_NC<2>

PM_EXTTS_L<0>

NB_CFG<20>

NB_CFG<19>

TP_NB_CFG<18>

TP_NB_CFG<14>

TP_NB_CFG<10>

TP_NB_RSVD<23>

TP_NB_RSVD<22>

TP_NB_RSVD<21>

TP_NB_RSVD<20>

NB_TEST2

NB_TEST1

TP_NB_RSVD<2>

TP_NB_RSVD<8>
TP_NB_RSVD<9>
TP_NB_RSVD<10>
TP_NB_RSVD<11>

MEM_CS_L<0>
MEM_CS_L<1>

MEM_CKE<0>

MEM_CLK_N<1>

MEM_CLK_P<1>

MEM_CLK_N<0>

TP_NB_RSVD<7>

TP_NB_RSVD<3>
TP_NB_RSVD<4>

TP_NB_NC<8>

TP_NB_NC<1>

NB_CLK100M_PCIE_P

DMI_S2N_P<0>

DMI_N2S_N<0>

SDVO_CTRLDATA
NB_CLKREQ_L
NB_SB_SYNC_L

TP_MEM_CLKN2
TP_MEM_CLKP5
TP_MEM_CLKN5

PM_BMBUSY_L
CPU_DPRSTP_L

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

MEM_CS_L<2>

MEM_ODT<2>
MEM_ODT<3>

MEM_CS_L<3>

MEM_ODT<0>
MEM_ODT<1>

TP_NB_RSVD<6>

TP_NB_RSVD<12>

TP_NB_NC<4>

DMI_S2N_P<3>

=PP0V9_S3M_MEM_NBVREFB

TP_NB_RSVD<5>

TP_NB_RSVD<24>

TP_MEM_CLKP2

TP_LVDS_A_DATAN3

TP_LVDS_B_DATAP3

MEM_A_A<14>

TP_NB_RSVD<35>
TP_NB_RSVD<36>

TP_LVDS_B_DATAN3

TP_NB_RSVD<45>

TP_NB_RSVD<14>

PM_DPRSLPVR

NB_RESET_L

PM_EXTTS_L<1>

NB_CFG<16>

=PP3V3_S0_NB_VCCHV

NB_CFG<19>

NB_CFG<20>

=PP3V3_S0_NB_VCCHV

TP_NB_CFG<11>

TP_NB_CFG<13>

=PP3V3_S0_NB_VCCHV

TP_NB_CFG<17>

PP1V25_S0M_NB_VCCAXD

NB_CLINK_VREF

NB_BSEL<2>

NB_CFG<6>
NB_CFG<7>
NB_CFG<8>

NB_CFG<5>

MEM_RCOMP_L

TP_NB_RSVD<44>

NB_CFG<4>

MEM_CKE<1>
MEM_CKE<3>

=PP0V9_S3M_MEM_NBVREFA

MEM_RCOMP_VOL

MEM_RCOMP

=PP1V8_S3M_MEM_NB

MEM_RCOMP_VOH

NB_CFG<9>

GFX_VID<0>

=NB_CLK96M_DOT_P
=NB_CLK96M_DOT_N
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N

NB_CLK100M_PCIE_N

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<1>
DMI_S2N_P<2>

DMI_N2S_N<1>
DMI_N2S_N<2>

GFX_VID<2>

21B7

21B7

20A8

20A8

21B7

31D2

18B3

18B3

20A8

30D2

15C7

15C7

18B3

20C8

15B7

15B7

15C7

20A6

17D7

15D7

15D7

8D6

15B6

15C7

15C7

8B4

8B4

8B4

8B4

8D6

8D6

8D6

15B6

7D4

15B6

15B6

7D4

7D4

18C3

74A3

7A4

15B6

BI

BI
BI
BI
BI
BI

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

BI
BI
BI

BI

BI
BI
BI
BI

BI BI

BI
BI
BI
BI
BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI
BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

BI

OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

BI

OUT

OUT

OUT

BI

BI

BI
BI
BI

BI

BI

BI

BI
BI
BI

BI
BI

BI

BI
BI

OUT

BI

BI

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

SA_DQ0
SA_DQ1
SA_DQ2

SA_DQ4

SA_DQ6

SA_DQ14

SA_CAS*

SA_BS2

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ34
SA_DQ35

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ30

SA_DQ28
SA_DQ29

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ20

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ13

SA_DQ11
SA_DQ12

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ3

SA_BS1

SA_BS0

SA_DQ45

SA_DM0
SA_DM1

SA_DM3

SA_DM2

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS1*

SA_DQS0*

SA_DQS2*

SA_DQS4*

SA_DQS3*

SA_DQS5*
SA_DQS6*
SA_DQS7*

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7

SA_MA9

SA_MA8

SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_RAS*

SA_RCVEN*

SA_WE*

DDR SYSTEM MEMORY A

(4 OF 10)

SB_DQ2

SB_DQ1

SB_DQ5

SB_DM0

SB_DQ0

SB_DQ4

SB_DQ6
SB_DQ7

SB_CAS*

SB_BS2

SB_BS0
SB_BS1

SB_DQ63

SB_DQ62

SB_DQ59

SB_DQ58

SB_DQ56

SB_DQ55

SB_DQ54

SB_DQ53

SB_DQ52

SB_DQ51

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ45
SB_DQ46

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ34
SB_DQ35

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ28
SB_DQ29

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQ24

SB_DQ23

SB_DQ22

SB_DQ21

SB_DQ20

SB_DQ19

SB_DQ18

SB_DQ17

SB_DQ16

SB_DQ15

SB_DQ14

SB_DQ13

SB_DQ11
SB_DQ12

SB_DQ10

SB_DQ9

SB_DQ8

SB_DQ3

SB_DQ57

SB_DQ61

SB_DQ60

SB_WE*

SB_RCVEN*

SB_RAS*

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA8
SB_MA9

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA2

SB_MA1

SB_MA0

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS3*
SB_DQS4*

SB_DQS2*

SB_DQS0*
SB_DQS1*

SB_DQS7

SB_DQS6

SB_DQS5

SB_DQS4

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS0

SB_DM6
SB_DM7

SB_DM4
SB_DM5

SB_DM2
SB_DM3

SB_DM1

(5 OF 10)

DDR SYSTEM MEMORY B

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT
OUT
OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

30A6 72D3

30C6 72C3

30B6 72C3

30B4 72C3

30A4 72C3

30A6 72C3

30A4 72C3

30A6 72C3

30B6 72C3

30B4 72C3

30C4 72C3

30A6 72D3

30C6 72C3

30D4 72C3

31A6 72B3

31A4 72B3

31A6 72B3

31A4 72B3

31A6 72B3

31A6 72B3

31A4 72B3

31A4 72B3

30A6 72D3 31A6 72B3

31A6 72B3

31A4 72B3

31A6 72B3

31A4 72B3

31A4 72B3

31B6 72B3

31A6 72B3

31A4 72B3

31A4 72B3

30A4 72D3

31B6 72B3

31A6 72B3

31B4 72B3

31B4 72B3

31A4 72B3

31A6 72B3

31B6 72B3

31B6 72B3

31B4 72B3

31B4 72B3

30A4 72D3

31B6 72B3

31C6 72B3

31C6 72B3

31B6 72B3

31B4 72B3

31B4 72B3

31C4 72B3

31C6 72B3

31C4 72B3

31C6 72B3

30A6 72D3

31C4 72B3

31C4 72B3

31C4 72B3

31C6 72B3

31C4 72B3

31C6 72B3

31C4 72B3

31C6 72B3

31C6 72B3

31C4 72B3

30A6 72D3

31D4 72B3

31D4 72B3

31D4 72B3

31D6 72B3

31D4 72B3

31D6 72B3

31D6 72B3

31D6 72B3

31D6 72B3

30A4 72D3

31D4 72B3

31D4 72B3

31D6 72B3

31D4 72B3

31D6 72B3

31D4 72B3

31D6 72B3

31B6 32A6 72B3

31B4 32A6 72B3

31B4 32A5 72B3

30A6 72D3

31C6 32A5 72B3

31B6 32B5 72B3

31C4 32A5 72B3

31C6 32B5 72B3

31C6 32B5 72B3

31C4 32B5 72B3

31B6 32B5 72B3

31C4 32B5 72B3

31B4 32B5 72B3

31B6 32B5 72B3

30A4 72D3

31B4 32B5 72B3

31B6 32B5 72B3

31B4 32B5 72B3

31A4 72A3

31A6 72A3

31C4 72A3

31B6 72A3

31B4 72A3

31C6 72A3

31D6 72A3

30A4 72D3

31A6 72A3

31A4 72A3

31D6 72A3

31B6 72A3

31A4 72A3

31C4 72A3

31D6 72A3

31C6 72A3

31A6 72A3

31D6 72A3

30A6 72D3

31A6 72B3

31A4 72A3

31C6 72B3

31B4 72B3

31C4 72B3

31D4 72B3

31D4 72B3

31B6 32A6 72B3

31C6 32A6 72B3

31B6 32A6 72B3

30A4 72D3

31B4 32A6 72B3

U1400

BB19

BK19

BF29

BL17

AT45

BD44
BD42

AW38

AW13
BG8

AY5
AN6

AR43

AW44

BG47
BJ45

BB47

BG50
BH49

BE45

AW43
BE44

BG42

BE40

BA45

BF44

BH45
BG40

BF40

AR40
AW40

AT39

AW36
AW41

AY41

AY46

AV38
AT38

AV13
AT13

AW11

AV11
AU15

AT11

BA13
BA11

AR41

BE10

BD10

BD8

AY9

BG10

AW9

BD7
BB9

BB5

AY7

AR45

AT5

AT7

AY6
BB7

AR5
AR8

AR9

AN3
AM8

AN10

AT42

AT9
AN9

AM9

AN11

AW47

BB45
BF48

AT46

AT47

BE48

BD47

BB43

BC41

BC37

BA37

BB16

BA16

BH6

BH7

BB2

BC1

AP3

AP2

BJ19
BD20

BC19

BE28
BG30

BJ16

BK27
BH28

BL24

BK28
BJ27

BJ25

BL28
BA28

BE18

AY20

BA19

OMIT

CRESTLINE

FCBGA

U1400

AY17

BG18

BG36

BE17

AR50

BD49
BK45

BL39

BH12
BJ7

BF3
AW2

AP49

AR51

BA49
BE50

BA51

AY49
BF50

BF49

BJ50
BJ44

BJ43

BL43

AW50

BK47

BK49
BK43

BK42

BJ41
BL41

BJ37

BJ36
BK41

BJ40

AW51

BL35
BK37

BK13
BE11

BK11

BC11
BC13

BE12

BC12
BG12

AN51

BJ10

BL9
BK5

BL5
BK9

BK10

BJ8
BJ6

BF4

BH5

AN50

BG1

BC2

BK3
BE4

BD3
BJ2

BA3

BB3
AR1

AT3

AV50

AY2
AY3

AU2

AT2

AV49

BA50
BB50

AT50

AU50

BD50

BC50

BK46

BL45

BK39

BK38

BJ12

BK12

BL7

BK7

BE2

BF2

AV2

AV3

BC18
BG28

BG17

BE37
BA39

BG13

BG25
AW17

BF25

BE25
BA29

BC28

AY28
BD37

AV16

AY18

BC17

OMIT

CRESTLINE

FCBGA

30B4 72D3

30A6 72D3

30B6 72D3

30B6 72D3

30B4 72D3

30B6 72D3

30B6 72D3

30D4 72D3

30B4 72D3

30B6 72D3

30B4 72D3

30B4 72D3

30B6 72D3

30B4 72D3

30C6 72D3

30C4 72D3

30D4 72D3

30C4 72D3

30A6 72D3

30C6 72D3

30C4 72D3

30C6 72D3

30D6 72D3

30C6 72D3

30C4 72D3

30C6 72D3

30C4 72D3

30C6 72D3

30C6 72D3

30A4 72D3

30C4 72D3

30C4 72D3

30D4 72D3

30D4 72D3

30D6 72D3

30D4 72D3

30D4 72D3

30D6 72D3

30D6 72D3

30D6 72D3

30A4 72D3

30D6 72D3

30D4 72D3

30D4 72D3

30D4 72D3

30D6 72D3

30D6 72D3

30D6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30C6 32C6 72D3

30A4 72D3

30B6 32B6 72D3

30D4 72C3

30B4 32C6 72D3

30B4 32B6 72D3

30B6 32B6 72D3

30C6 32C6 72D3

30C4 32C6 72D3

30B6 32C6 72D3

30C6 32C6 72D3

30A6 72D3

30C6 32C6 72D3

30C4 32C6 72D3

30C4 32C6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30D6 72C3

30A4 72D3

30D6 72C3

30C4 72C3

30C6 72C3

30B6 72C3

30B4 72C3

30A4 72C3

30A6 72C3

30D6 72C3

30D6 72C3

30C4 72C3

16 76

01

051-7455

NB DDR2 Interfaces

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

MEM_A_DQ<35>

TP_MEM_A_RCVEN_L TP_MEM_B_RCVEN_L

MEM_B_DQ<39>

MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>

MEM_B_DM<0>

MEM_B_CAS_L

MEM_B_DM<1>
MEM_B_DM<2>

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>

MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<1>

MEM_B_DQS_P<7>
MEM_B_DQS_N<0>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<7>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>

MEM_B_RAS_L

MEM_B_A<13>

MEM_B_WE_L

MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>

MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_CAS_L

MEM_A_BS<2>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_DM<0>
MEM_A_DM<1>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>

MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

VCC_SM20

VCC_AXG_NCTF42

VCC_SM9
VCC_SM10

VCC_SM17

VCC_SM16

VCC3

VCC_SM5

VCC_SM8

VCC_AXG_NCTF1
VCC_AXG_NCTF2
VCC_AXG_NCTF3
VCC_AXG_NCTF4
VCC_AXG_NCTF5
VCC_AXG_NCTF6

VCC_AXG_NCTF8

VCC_AXG_NCTF7

VCC_AXG_NCTF10

VCC_AXG_NCTF9

VCC_AXG_NCTF11
VCC_AXG_NCTF12
VCC_AXG_NCTF13
VCC_AXG_NCTF14
VCC_AXG_NCTF15
VCC_AXG_NCTF16

VCC_AXG_NCTF18

VCC_AXG_NCTF17

VCC_AXG_NCTF20

VCC_AXG_NCTF19

VCC_AXG_NCTF21
VCC_AXG_NCTF22

VCC_AXG_NCTF25
VCC_AXG_NCTF26

VCC_AXG_NCTF28

VCC_AXG_NCTF27

VCC_AXG_NCTF29
VCC_AXG_NCTF20
VCC_AXG_NCTF31
VCC_AXG_NCTF32
VCC_AXG_NCTF33
VCC_AXG_NCTF34
VCC_AXG_NCTF35
VCC_AXG_NCTF36

VCC_AXG_NCTF38

VCC_AXG_NCTF37

VCC_AXG_NCTF40

VCC_AXG_NCTF39

VCC_AXG_NCTF41

VCC_AXG_NCTF43
VCC_AXG_NCTF44
VCC_AXG_NCTF45
VCC_AXG_NCTF46

VCC_AXG_NCTF48

VCC_AXG_NCTF47

VCC_AXG_NCTF49
VCC_AXG_NCTF50
VCC_AXG_NCTF51

VCC_AXG_NCTF55

VCC_AXG_NCTF58

VCC_AXG_NCTF57

VCC_AXG_NCTF59

VCC_AXG_NCTF61

VCC_AXG_NCTF60

VCC_AXG_NCTF62
VCC_AXG_NCTF63
VCC_AXG_NCTF64

VCC_AXG_NCTF66

VCC_AXG_NCTF65

VCC_AXG_NCTF67
VCC_AXG_NCTF68
VCC_AXG_NCTF69

VCC_AXG_NCTF71

VCC_AXG_NCTF70

VCC_AXG_NCTF72
VCC_AXG_NCTF73
VCC_AXG_NCTF74

VCC_AXG_NCTF76

VCC_AXG_NCTF75

VCC_AXG_NCTF77
VCC_AXG_NCTF78
VCC_AXG_NCTF79

VCC_AXG_NCTF81

VCC_AXG_NCTF80

VCC_AXG_NCTF82
VCC_AXG_NCTF83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC_AXG_NCTF56

VCC_AXG_NCTF54

VCC_AXG_NCTF53

VCC_AXG_NCTF52

VCC_AXG1
VCC_AXG2
VCC_AXG3
VCC_AXG4
VCC_AXG5
VCC_AXG6
VCC_AXG7
VCC_AXG8
VCC_AXG9
VCC_AXG10
VCC_AXG11
VCC_AXG12
VCC_AXG13
VCC_AXG14
VCC_AXG15
VCC_AXG16
VCC_AXG17
VCC_AXG18
VCC_AXG19
VCC_AXG20
VCC_AXG21
VCC_AXG22
VCC_AXG23
VCC_AXG24
VCC_AXG25
VCC_AXG26
VCC_AXG27
VCC_AXG28
VCC_AXG29
VCC_AXG30
VCC_AXG31
VCC_AXG32
VCC_AXG33
VCC_AXG34

VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4

VCC_SM6
VCC_SM7

VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15

VCC_SM18
VCC_SM19

VCC_SM21
VCC_SM22
VCC_SM23

VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36

VCC_SM25

VCC_SM24

VCC1
VCC2

VCC7
VCC8
VCC9
VCC10
VCC11
VCC12

VCC13

VCC_AXG_NCTF24

VCC_AXG_NCTF23

VCC6

VCC5
VCC4

VCC GFX

VCC SM

VCC SM LF

(6 OF 10)

VCC CORE

POWER

VCC GFX NCTF

VCC_NCTF49

VCC_NCTF15

VCC_NCTF2

VCC_NCTF10

VCC_AXM7

VCC_AXM5

VCC_AXM4

VCC_AXM3

VCC_AXM2

VCC_AXM1

VSS_SCB6

VSS_SCB5

VSS_SCB4

VSS_SCB3

VSS_SCB2

VSS_SCB1

VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF12

VSS_NCTF11

VSS_NCTF13

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_NCTF22

VCC_NCTF27

VCC_NCTF50

VCC_NCTF47
VCC_NCTF48

VCC_NCTF44

VCC_NCTF43

VCC_NCTF39
VCC_NCTF40

VCC_NCTF38

VCC_NCTF37

VCC_NCTF34
VCC_NCTF35

VCC_NCTF33

VCC_NCTF32

VCC_NCTF31

VCC_NCTF29

VCC_NCTF28

VCC_NCTF26

VCC_NCTF24
VCC_NCTF25

VCC_NCTF23

VCC_NCTF21

VCC_NCTF18
VCC_NCTF19

VCC_NCTF16
VCC_NCTF17

VCC_NCTF3
VCC_NCTF4

VCC_NCTF41
VCC_NCTF42

VCC_NCTF45
VCC_NCTF46

VCC_AXM6

VCC_AXM_NCTF1
VCC_AXM_NCTF2
VCC_AXM_NCTF3
VCC_AXM_NCTF4
VCC_AXM_NCTF5
VCC_AXM_NCTF6
VCC_AXM_NCTF7
VCC_AXM_NCTF8
VCC_AXM_NCTF9
VCC_AXM_NCTF10
VCC_AXM_NCTF11
VCC_AXM_NCTF12
VCC_AXM_NCTF13
VCC_AXM_NCTF14
VCC_AXM_NCTF15
VCC_AXM_NCTF16
VCC_AXM_NCTF17
VCC_AXM_NCTF18
VCC_AXM_NCTF19

VCC_NCTF8

VCC_NCTF20

VCC_NCTF1

VCC_NCTF5
VCC_NCTF6
VCC_NCTF7

VCC_NCTF36

VCC_NCTF30

VCC_NCTF9

VCC AXM NCTF

VCC NCTF

VSS SCBVCC AXM

VSS NCTF

(7 OF 10)

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1395 mA (1 ch, 533MHz)

1700 mA (1 ch, 667MHz)

2700 mA (2 ch, 533MHz)

3300 mA (2 ch, 667MHz)

540 mA

1573 mA (Int Graphics)

1310 mA (Ext Graphics)

7700 mA (Int Graphics)

5 mA (standby)

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

Current numbers from Crestline EDS, doc #21749.

U1400

AT35

AH31
AH29

AF32

R30

AT34
AH28

AC31

AC32

AK32

AJ31
AJ28

AH32

R20

AB21
AB24

AB29

AC20
AC21

AC23

AC24
AC26

AC28

AC29

T14

AD20

AD23
AD24

AD28

AF21
AF26

AA31

AH20
AH21

AH23

W13

AH24
AH26

AD31
AJ20

AN14

W14

Y12
AA20

AA23

AA26
AA28

T17

U17
U19

U20

U21
U23

U26
V16

V17

V19
V20

T18

V21

V23
V24

Y15

Y16
Y17

Y19
Y20

Y21

Y23

T19

Y24

Y26

Y28
Y29

AA16

AA17
AB16

AB19
AC16

AC17

T21

AC19
AD15

AD16

AD17
AF16

AF19

AH15
AH16

AH17
AH19

T22

AJ16

AJ17
AJ19

AK16

AK19
AL16

AL17

AL19
AL20

AL21

T23

AL23

AM15

AM16
AM19

AM20

AM21
AM23

AP15

AP16
AP17

T25

AP19
AP20

AP21

AP23
AP24

AR20

AR21
AR23

AR24

AR26

U15

V26

V28
V29

Y31

U16

AU32

BA35

BB33

BC32
BC33

BC35

BD32
BD35

BE32
BE33

BE35

AU33

BF33
BF34

BG32

BG33
BG35

BH32

BH34
BH35

BJ32
BJ33

AU35

BJ34

BK32
BK33

BK34

BK35
BL33

AU30

AV33
AW33

AW35
AY35

BA32

BA33

AW45

BC39

BE39
BD17

BD4
AW8

AT6

OMIT

FCBGA

CRESTLINE

U1400

AT33

AT31
AK29

AK24

AK23
AJ26

AJ23

AL24

AP29

AP31

AP32
AP33

AL29

AL31
AL32

AR31

AR32
AR33

AL26

AL28

AM26
AM28

AM29

AM31
AM32

AM33

AB33

AF36
AH33

AH35

AH36
AH37

AJ33

AJ35
AK33

AK35
AK36

AB36

AK37

AD33
AJ36

AM35

AL33
AL35

AA33

AA35
AA36

AP35

AB37

AP36

AR35

AR36

Y32

Y33

Y35
Y36

Y37

T30
T34

AC33

T35
U29

U31

U32
U33

U35

U36
V32

V33

V36

AC35

V37

AC36

AD35
AD36

AF33

T27

AD19
AD37

AF17

AF35
AK17

AM17
AM24

AP26

AP28
AR15

T37

AR19

AR28

U24

U28
V31

V35

AA19
AB17

AB35

A3
B2

C1

BL1
BL51

A51

OMIT

CRESTLINE

FCBGA

C1806

1

2

402

0.1uF

10V

CERM

20%

C1807

1

2

402

0.1uF

10V

CERM

20%

C1804

1

2

402

X5R

0.22UF

6.3V

20%

C1805

1

2

402

X5R

0.22UF

6.3V

20%

C1802

1

2

402

10%

CERM

1uF

6.3V

C1803

1

2

402

10%

0.47UF

6.3V

CERM-X5R

C1801

1

2

402

10%

CERM

1uF

6.3V

17 76

01

051-7455

NB Power 1

SYNC_DATE=10/30/2006

SYNC_MASTER=T9_MLB

=PPVCORE_S0_NB

=PP1V05_S0M_NB_VCCAXM

=PPVCORE_S0_NB_GFX

=PP1V8_S3M_MEM_NB

=PPVCORE_S0_NB

=PPVCORE_S0_NB_GFX

NB_VCCSM_LF6

NB_VCCSM_LF4

NB_VCCSM_LF3

NB_VCCSM_LF2

NB_VCCSM_LF1

NB_VCCSM_LF7

NB_VCCSM_LF5

=PP1V05_S0M_NB_VCCAXM

31D2

20D8

48B3

30D2

20D8

48B3

20B4

20D8

21C5

20C8

20B4

21C5

20D8

17D7

17C1

17B7

15D2

17D3

17D5

17B3

7C7

7C7

7B7

7A4

7C7

7B7

7C7

VCCA_CRT_DAC1

VTT7
VTT8

VCC_AXD_NCTF

VCCD_CRT

VCC_RXR_DMI1
VCC_RXR_DMI2

VTT1

VCCA_SM_CK2 VCC_TX_LVDS

VCC_HV2

VCC_PEG1
VCC_PEG2
VCC_PEG3

VCC_AXF2

VCC_AXD1
VCC_AXD2

VSSA_LVDS

VCCA_SM5

VCCA_PEG_PLL

VCCA_MPLL

VCCA_HPLL VTT16

VTT17

VTT15

VCCD_LVDS2

VCCD_LVDS1

VCCD_PEG_PLL

VCCD_HPLL

VCCD_QDAC

VCCD_TVDAC

VCCA_TVC_DAC1
VCCA_TVC_DAC2

VCCA_TVB_DAC2

VCCA_TVB_DAC1

VCCA_TVA_DAC2

VCCA_TVA_DAC1

VCCA_SM_CK1

VCCA_SM2

VCCA_SM1

VCCA_SM_NCTF2

VCCA_SM_NCTF1

VCCA_SM11

VCCA_SM10

VCCA_SM9

VCCA_SM8

VCCA_SM7

VCCA_SM4

VCCA_SM3

VSSA_PEG_BG

VCCA_PEG_BG

VCCA_LVDS

VCCA_DPLLB

VCCA_DPLLA

VSSA_DAC_BG

VCCA_DAC_BG

VCC_AXF3

VCC_HV1

VCC_PEG5

VTTLF1

VTTLF3

VTTLF2

VCC_PEG4

VCC_SM_CK3

VCC_SM_CK2

VCC_SM_CK1

VCC_SM_CK4

VCC_DMI

VCC_AXF1

VTT22

VCC_AXD6

VCC_AXD5

VCC_AXD4

VCC_AXD3

VTT19

VTT2

VTT6

VTT5

VTT11

VTT10

VTT9

VTT13

VTT12

VTT14

VTT18

VTT21

VTT20

VTT3
VTT4

VCCA_CRT_DAC2

VCC_SYNC

CRT

AXD

PEG

HV

AXF

VTTLF

VTT

SM CK

DMI

TV/CRT

D

LVDS

A SMA CK

CRT A LVDS

A PEG

PLL

(8 OF 10)

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

100 mA

100 mA

100 mA

200 mA

5 mA

50 mA

100 mA

10 mA

40 mA

40 mA

40 mA

60 mA

250 mA

150 mA

5 mA

S0 or S3M is acceptable

S0 or S3M is acceptable

TBD mA @ 1067MHz FSB (1.25V)

150 mA

770 mA @ 667MHz FSB (1.05V)

1260 mA

260 mA

0.4 mA

80 mA

30 mA

60 mA

100 mA

35 mA

850 mA @ 800MHz FSB (1.05V)

495 mA

515 mA

Current numbers from Crestline EDS, doc #21749.

640 mA (667MHz DDR)
550 mA (533MHz DDR)

C1911

1

2

0.47UF

10%

CERM-X5R
402

6.3V

C1913

1

2

0.47UF

10%

6.3V
CERM-X5R
402

C1912

1

2

0.47UF

10%

6.3V
CERM-X5R
402

U1400

AT23

AU28
AU24

AT29

AT25
AT30

AR29

B23

B21
A21

AJ50

C40

B40

AD51
W50

W51

V49
V50

AH50

AH51

BK24

BK23

BJ24
BJ23

J32

A43

A33
B33

A30

B49

H49

AL2

A41

AM2

K50

U51

AW18

AT18

AT17

AV19

AU19
AU18

AU17

AT22

AT21

AT19

BC29

BB29

AR17

AR16

C25
B25

C27
B27

B28

A28

M32

AN2

J41
H42

U48

N28

L29

B32

B41

K49

U13

U1

T13
T11

T10
T9

T7

T6
T5

T3

T2

U12

R3

R2

R1

U11

U9

U8
U7

U5

U3
U2

A7
F2

AH1

OMIT

FCBGA

CRESTLINE

051-7455

01

7618

NB Power 2

SYNC_DATE=10/30/2006

SYNC_MASTER=T9_MLB

NB_VTTLF_CAP2

=PP1V8_S0_NB_VCCD_LVDS

PP1V25_S0_NB_VCCA_DPLLA

PP1V25_S0M_NB_VCCA_HPLL

PP3V3_S0_NB_VCCA_TVDACA

=PP1V5_S0_NB_VCCD_CRT
PP1V5_S0_NB_VCCD_TVDAC

PP1V5_S0_NB_VCCD_QDAC

=PP1V25_S0M_NB_VCCD_HPLL

=GND_NB_VSSA_LVDS

PP3V3_S0_NB_VCCA_DAC_BG

PP1V25_S0M_NB_VCCA_MPLL

NB_VTTLF_CAP1

NB_VTTLF_CAP3

=PP1V25_S0_NB_VCCDMI

=GND_NB_VSSA_DAC_BG

=GND_NB_VSSA_PEG_BG

PP1V8_S0_NB_VCCTXLVDS

PP1V05_S0_NB_VCCPEG

=PP3V3_S0_NB_VCCHV

PP1V05_S0_NB_VCCRXRDMI

PP1V25_S0_NB_VCCAXF

PP1V25_S0M_NB_VCCAXD

PP3V3_S0_NB_VCCA_TVDACC

PP1V25_S0_NB_VCCA_DPLLB

PP3V3_S0_NB_VCCA_TVDACB

=PP1V25R1V05_S0_NB_VTT

PP1V8_S0_NB_VCCTXLVDS

PP3V3_S0_NB_VCCA_CRTDAC

=PP3V3_S0_NB_VCCSYNC

PP1V25_S0M_NB_VCCA_SM_CK

PP1V25_S0_NB_PEGPLL

PP1V8_S3M_NB_VCCSMCK

PP1V25_S0M_NB_VCCA_SM

=PP3V3_S0_NB_VCCA_PEG_BG

21B7

20A8 15C7

20A8

21C3

20D3

15B7

20A6

20C8

21C3

21B5

20A6

21B3

21A3

20D1

21D1

21C7

21D6

21C5

20D1

21B3

21B1

20C1

7C7

21B1

20A6

18C6

14D2

7D4

20C3

20D5

15A2

21C1

21A3

21C1

7C7

18B3

21D1

7C4

20B5

20B2

20A2

20B5

7C4

VSS198VSS99

VSS197VSS98

VSS196VSS97

VSS195VSS96

VSS194VSS95

VSS193VSS94

VSS192VSS93

VSS191VSS92

VSS190VSS91

VSS189VSS90

VSS188VSS89

VSS187VSS88

VSS186VSS87

VSS185VSS86

VSS184VSS85

VSS183VSS84

VSS182VSS83

VSS181VSS82

VSS180VSS81

VSS179VSS80

VSS178VSS79

VSS177VSS78

VSS176VSS77

VSS175VSS76

VSS174VSS75

VSS173VSS74

VSS172VSS73

VSS171VSS72

VSS170VSS71

VSS169VSS70

VSS168VSS69

VSS167VSS68

VSS166VSS67

VSS165VSS66

VSS164VSS65

VSS163VSS64

VSS162VSS63

VSS161VSS62

VSS160VSS61

VSS159VSS60

VSS158VSS59

VSS157VSS58

VSS156VSS57

VSS155VSS56

VSS154VSS55

VSS153VSS54

VSS152VSS53

VSS151VSS52

VSS150VSS51

VSS149VSS50

VSS148VSS49

VSS147VSS48

VSS146VSS47

VSS145VSS46

VSS144VSS45

VSS143VSS44

VSS142VSS43

VSS141VSS42

VSS140VSS41

VSS139VSS40

VSS138VSS39

VSS137VSS38

VSS136VSS37

VSS135VSS36

VSS134VSS35

VSS133VSS34

VSS132VSS33

VSS131VSS32

VSS130VSS31

VSS129VSS30

VSS128VSS29

VSS127VSS28

VSS126VSS27

VSS125VSS26

VSS124VSS25

VSS123VSS24

VSS122VSS23

VSS121VSS22

VSS120VSS21

VSS119VSS20

VSS118VSS19

VSS117

VSS116VSS17

VSS115VSS16

VSS114VSS15

VSS113VSS14

VSS112VSS13

VSS111VSS12

VSS110VSS11

VSS109VSS10

VSS108

VSS9

VSS107VSS8

VSS106VSS7

VSS105VSS6

VSS104VSS5

VSS103VSS4

VSS102

VSS101

VSS100

VSS1

VSS18

VSS2
VSS3

VSS

(9 OF 10)

VSS202

VSS289
VSS290
VSS291
VSS292

VSS295

VSS199 VSS287
VSS200 VSS288
VSS201

VSS203
VSS204

VSS293
VSS294

VSS208 VSS296
VSS209 VSS297
VSS210 VSS298
VSS211 VSS299
VSS212 VSS300
VSS213 VSS301
VSS214
VSS215
VSS216 VSS302
VSS217
VSS218
VSS219 VSS303
VSS220
VSS221
VSS222 VSS304
VSS223
VSS224
VSS225 VSS305
VSS226
VSS227
VSS228
VSS229 VSS306
VSS230 VSS307
VSS231 VSS308
VSS232 VSS309
VSS233 VSS310
VSS234 VSS311
VSS235 VSS312
VSS236 VSS313
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243

VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286

VSS207

VSS206

VSS205

(10 OF 10)

VSS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TDE_SENSE

TDE_FORCE

TDB_FORCE

alias these nets directly to GND.

Mainly for investigation. If not used,

NOTE: TDB = _N

TDB_SENSE

Crestline Thermal Diode Pins

NOTE: TDE = _P

U1400

A13

AB26

AW24

AW29
AW32

AW5

AW7
AY10

AY24

AY37
AY42

AY43

AB28 AY45

AY47

AY50
B10

B20

B24
B29

B30

B35
B38

AB31

B43

B46
B5

B8
BA1

BA17

BA18
BA2

BA24

BB12

AC10

BB25

BB40

BB44
BB49

BB8
BC16

BC24

BC25
BC36

BC40

AC13

BC51
BD13

BD2

BD28
BD45

BD48
BD5

BE1

BE19
BE23

AC3

BE30

BE42
BE51

BE8

BF12
BF16

BF36
BG19

BG2

BG24

AC39

BG29

BG39

BG48
BG5

BG51

BH17
BH30

BH44
BH46

BH8

AC43

BJ11
BJ13

BJ38

BJ4
BJ42

BJ46

BK15
BK17

BK25
BK29

AC47

BK36

BK40
BK44

BK6

BK8
BL11

BL13

BL19
BL22

BL37

AD1

BL47

C12

C16
C19

C28

C29
C33

C36

C41

A15

AD21

AD26

AD29

AD3

AD41
AD45

AD49

AD5

AD50

AD8

A17

AE10
AE14

AE6

AF20
AF23

AF24
AF31

AG2

AG38
AG43

A24

AG47

AG50

AH3

AH40

AH41

AH7

AH9
AJ11

AJ13

AJ21

AA21

AJ24

AJ29

AJ32
AJ43

AJ45

AJ49
AK20

AK21
AK26

AK28

AA24

AK31
AK51

AL1

AM11
AM13

AM3

AM4
AM41

AM45

AN1

AA29

AN38

AN39
AN43

AN5

AN7

AP4

AP48

AP50
AR11

AR2

AB20

AR39

AR44

AR47

AR7

AT10

AT14
AT41

AT49

AU1
AU23

AB23

AU29

AU3

AU36

AU49
AU51

AV39

AV48

AW1

AW12

AW16

FCBGA

OMIT

CRESTLINE

U1400

C46

C50

C7

D13

D24

D3

D32

D39
D45

D49

E10
E16

E24
E28

E32

E47
F19

F36

F4
F40

F50

G1
G13

G16
G19

G24

G28
G29

G33

G42
G45

G48

G8
H24

H28

H4

H45

J11
J16

J2

J24
J28

J33

J35
J39

K12

K47

K8

L1

L17

L20
L24

L28

L3
L33

L49
M28

M42

M46
M49

M5

M50

M9

N11

N14
N17

N29
N32

N36

N39
N44

N49

N7
P19

P2

P23

P3

P50
R49

T39

T43
T47

U41

U45
U50

V2

V3

W11

W39
W43

W47

W5
W7

Y13

Y2
Y41

Y45

Y49
Y5

Y50
Y11

P29

T29

T31

T33

R28

AA32

AB32

AD32
AF28

AF29
AT27

AV25

H50

FCBGA

OMIT

CRESTLINE

051-7455

01

7619

NB Grounds

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

=NB_TDB_SENSE

=NB_TDB_FORCE

=NB_TDE_FORCE

=NB_TDE_SENSE

8A2

8A2

8A2

8A2

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

this is "1 of 2" 1.8V bulk decoupling caps.

spec requires "3.9uH ferrite,1A,32mohm max".

5.6nH,0.9A,45mohm max.no bigger than 0603

WF: Matanzas has 270uF

and DDR2 taps." (C2125)

Memory I/O logic and DLL voltage.

WF: 220-ohm

Memory voltage supply.

??? mA

540 mA

These supplies are still needed even using external GPU

250mA,0.5ohm

250mA,0.5ohm

MPLL Analog Supply

GMCH Core Power

100 mA

450 mA

Host PLL Analog Supply

200 mA

LAYOUT NOTE: PLACE THOSE COMPONENT CLOSE TO GMCH

200 mA

5 mA

Current numbers from Crestline EDS Addendum, doc #20127.

50 mA

150 mA

850 mA

GMCH FSB I/O Rail

200 mA

100 mA

100 mA

Memory clock logic voltage.

200 mA

250 mA

Host PLL Digital Supply

Layout Note: Route to caps, then GND

WF: Should be 1.0, 1%

100 mA

??? mA

1200 mA

Layout Note:

be close to MCH
on opposite side.

Analog PLL Voltage for PCI-E GPU

need to find "1uH,220mA,150mohm max"

I/O voltage Supply

350 mA

1450 mA

Layout Note:

??? mA

WF: "Place where LVDS

Place L and C
close to MCH

GMCH ME Core Power

GMCH Memory I/O Rail

2400 mA

WF: Should be 1.0, 1%

NOTE: This follower is redundant if VCORE is always 1.05V.

on opposite side.

be close to MCH

10uF caps should

Layout Note:

250 mA

RX and I/O Logic for DMI

10uF caps should

Analog,I/O logic,and Term Voltage for PCI-E Graphics

C2124

1

2

CERM-X5R

10%

0.47UF

6.3V
402

C2123

1

2

6.3V

CERM1

603

2.2uF

20%

C2121

1

2

4.7uF

6.3V
CERM

20%

603

C2100

1

2 3

470UF

20%

2.5V
TANT

D2T

C2112

1

2

402

X5R

6.3V

20%

0.22uF

C2111

1

2

402

6.3V

20%
X5R

C2122

1

2

20%

4.7uF

6.3V
CERM

603

C2131

1

2

805

CERM

22UF

PLACEMENT_NOTE=Place close to U1400

20%

6.3V

C2132

1

2

805

CERM

22UF

6.3V

20%

PLACEMENT_NOTE=Place close to U1400

C2135

1

2

CERM

20%

0.1UF

10V

R2183

1

2

1/16W
MF-LF

402

1%

0.51

R2190

1

2

MF-LF

1/16W

1%

402

1.1

1 2

C2190

1

2

X5R

20%

6.3V

10uF

1

2

C2174

1

2

10uF

20%

6.3V
X5R
603

C2173

1

2

20%

POLY

2.5V

220UF

CASE-B2

L2173

1 2

91NH

1210

R2195

1

2

402

1/16W
MF-LF

1%

1.1

L2195

1 2

1.0UH-0.23A

0603

C2195

1

2

6.3V

20%

10uF

X5R
603

C2196

1

2

CERM

22UF

805

20%

6.3V

C2171

1

2

402

1UF

10%

6.3V
CERM

C2170

1

2

10uF

20%

6.3V
X5R
603

C2151

1

1UF

402

CERM

10%

C2150

1

2

10uF

6.3V
X5R
603

20%

NOSTUFF

C2142

1

2

805

CERM

22UF

20%

6.3V

C2143

1

2

4.7UF

603

6.3V

10%
X5R-CERM

C2144

1

2

1UF

CERM

6.3V

10%

402

R2141

1 2

MF-LF

1/16W

0

5%

C2145

1

2

805

CERM

22UF

6.3V

20%

1 2

5%

0

C2147

1

2

402-LF

NOSTUFF

20%

2.2UF

6.3V
CERM

C2148

1

2

402

CERM

10V

20%

0.1UF

R2186

1 2

402

MF-LF

1/16W

1%

10

R2112

1

2

1%

1/16W

402

1K

1

2

1/16W
MF-LF

1%

402

1K

R2110

1

2

1%

MF-LF

1/16W

1K

402

R2111

1

2

1/16W
MF-LF

1%

402

1K

L2183

1 2

0402-LF

120-OHM-0.3A-EMI

C2113

1

2

20%

0.1UF

CERM

10V
402

C2114

1

2

CERM

10V

20%

0.1UF

402

C2115

1

2

20%
10V
CERM
402

1

2

CERM

10V

20%

0.1UF

402

C2161

1

2

402

20%
10V
CERM

2

402

CERM

10V

20%

C2197

1

2

0.1UF

402

CERM

10V

20%

C2191

1

2

CERM

10V

20%

0.1UF

402

C2192

1

2

0.1UF

10V
CERM
402

20%

C2182

1

2

402

0.1UF

CERM

10V

20%

C2180

1

2

0.1UF

402

CERM

10V

20%

C2110

1

2

805

CERM

22UF

20%

6.3V

R2109

1 2

MF-LF

402

0

1/16W

5%

D2186

12

1SS418

SOD-723

L2181

1 2

120-OHM-0.3A-EMI

0402-LF

C2104

1

2

402

20%
10V

0.1UF

CERM

C2177

1

2

10uF

20%

6.3V
X5R
603

C2103

1

2

PLACEMENT_NOTE=Place in GMCH cavity

6.3V

20%
X5R

402

0.22uF

C2102

1

2

402

PLACEMENT_NOTE=Place in GMCH cavity

X5R

20%

0.22uF

6.3V

C2184

1

2

10V
CERM
402

PLACEMENT_NOTE=Place C2184 by U1400.AM2

0.1UF

20%

C2181

1

2

CERM

22UF

6.3V

20%

805

C2183

1

2

22UF

CERM

805

20%

6.3V

C2101

1

2

805

CERM

22UF

PLACEMENT_NOTE=Place in GMCH cavity

6.3V

20%

76

01

20

SYNC_DATE=06/15/2006

SYNC_MASTER=WFERRY

NB Standard Decoupling

051-7455

PP1V25_S0M_NB_VCCA_SM

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

=PPVCORE_S0_NB

=PP1V25_S0_NB_VCC

=PP0V9_S3M_MEM_NBVREFB

=PP3V3_S0_NB_VCCHV

=PP1V8_S3_NB_VCC

=PP3V3_S0_NB_FOLLOW

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V

PP1V8_S3_NB_VCCSMCK_RC

=PP1V8_S3_MEMVREF

PP1V25_S0M_NB_VCCA_MPLL

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

=PP1V25_S0M_NB_VCCD_HPLL

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.4 MM

PP0V9_S3M_MEM_NBVREFB

=GND_NB_VSSA_PEG_BG

=PP1V25_S0_NB_VCCDMI

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.25 MM
VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_PEGPLL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM
VOLTAGE=1.05V

=PP1V25_S0_NB_PLL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.25V

PP1V25_S0_NB_VCCAXF

=PP1V25_S0_NB_VCCAXF

=PP1V05_S0_NB_PCIE

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V

MIN_LINE_WIDTH=0.25 MM

PP1V8_S3M_NB_VCCSMCK

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

=PP1V25_S0_NB_PLL

=PP1V25R1V05_S0_NB_VTT

=PPVCORE_S0_NB

PP1V25_S0M_NB_VCCA_HPLL

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0M_NB_MPLL_RC

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

PP1V25_S0M_NB_VCCA_SM_CK

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0_NB_PEGPLL_RC

VOLTAGE=1.25V

=PP1V05_S0M_NB_VCCAXM

PLACEMENT_NOTE=Place in GMCH cavity

0.22uF

0.1UF

CRITICAL

=PP1V25_S0_NB_VCCA

402

R2145

1/16W
MF-LF

402

PP1V25_S0M_NB_VCCAXD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

6.3V

2

=PP3V3_S0_NB_VCCA_PEG_BG

1

0.1UF 0.1UF

C2165

R2113

=PP0V9_S3M_MEM_NBVREFA

VOLTAGE=0.9V

MF-LF

PP0V9_S3M_MEM_NBVREFA

=PP1V8_S3_MEMVREF

603

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

0603

FERR-220-OHM-2.5A

L2190

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_NBCORE_FOLLOW_R

PP1V05_S0_NB_VCCRXRDMI

PP1V05_S0_NB_VCCPEG

CRITICAL

CRITICAL

OMIT

PLACEMENT_NOTE=Place close to U1400

402

C2160

CRITICAL

CASE-C2

POLY

2.5V

20%

330UF

C2130

=PP1V8_S3M_MEM_NB

CRITICAL

20%

POLY

330UF

2.0V

CASE-B2

2

1

C2140

OMIT

OMIT

21B7

31D2

20D8

18B3

20B4

30D2

17D7

15C7

17D7

17C1

17D7

17D3

18C3

15B7

20A6

20A5

18C3

20B4

18B3

20D3

18D3

17D3

17B3

15D2

18C6

18C6

7C7

15A2

7C7

15C2

7D4

7A4

7D4

7B4

7B4

18D6

18A6

18C6

7C7

18C6

18B3

7C7

18C3

7C7

7C7

18B3

14D2

7C7

7C7

7C7

7C7

18D6

7C7

7A4

18B6

7C4

OUT

EN

NR/FB

IN

GND

THRML

NC

EN

IN

OUT

NR

PAD

GND

OUT
OUT
OUT
OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Matanzas has 2x 330uF

NEED TO FIND A "1#GH, 500MA, 78MOHM" INDUCTOR

WF: Should be 1uH, 30%

260 mA

Layout Note: Route to cap, then GND

WARNING VOLTAGE DROP

VCCD_TVDAC also powers internal thermal sensors.

0011=1.21025V

1000=1.08150V

VID<3:0>=1001=1.05575V

65 mA

WF: Check part properties

10 mA

6 mA

5 mA

Vout = 1.204V * (Ra + Rb)/Rb

110 mA

Layout Note:

80 mA

80 mA

WF: Is this the best part to use?

These 2 caps should be
within 6.35 mm of NB edge

80 mA

125 mA

80 mA

Layout Note:
These 8 caps should be

Layout Note: Route to caps, then GND

within 6.35 mm of NB edge

40 mA

5 mA

40 mA

40 mA

80 mA

Layout Note:

Current numbers from Crestline EDS Addendum, doc #20127.

150 mA

60 mA

(1.7V - 5.5V)

NC

205 mA

Ra || Rb should be 19Kohms

7700 mA

WF: Check C2266 value, R2267 value

GMCH Graphics Core Power
These 4 caps should be
within 6.35 mm of NB edge

205 mA

NOTE: This filter is required even if using only external graphics.

C2289

2

1 3

CRITICAL

22000pF-1000mA

NFM18

16V

C2282

1

2

0.01UF

CERM

402

10%
16V

R2205

1

2

MF-LF

5%

100

1/16W
402

C2207

1

2

402

0.1UF

CERM

10V

20%

R2281

1

2

402

1/16W
MF-LF

5%

0

C2281

1

2

1UF

NO STUFF

CERM
402

6.3V

10%

C2280

1

2

402

CERM

6.3V

1UF

10%

C2292

2

1 3

CRITICAL

22000pF-1000mA

NFM18

16V

C2291

1

2

0.1UF

402

20%
10V
CERM

C2294

2

1 3

22000pF-1000mA

CRITICAL

NFM18

16V

C2293

1

2

402

20%
10V
CERM

0.1UF

C2288

1

2

402

20%
10V
CERM

0.1UF

C2296

2

1 3

CRITICAL

NFM18

22000pF-1000mA

16V

C2295

1

2

402

20%
10V
CERM

0.1UF

C2298

2

1 3

CRITICAL

22000pF-1000mA

NFM18

16V

C2297

1

2

402

20%
10V
CERM

0.1UF

C2290

1

2

10uF

603

X5R

20%

6.3V

L2290

1 2

120-OHM-0.3A-EMI

0402-LF

R2261

1 2

1/16W

5%

MF-LF

0

402

C2261

1

2

0.1UF

402

CERM

10V

20%

R2262

1 2

1/16W
MF-LF

5%

0

402

C2262

1

2

20%
10V
CERM

0.1UF

C2223

1

2

CERM

0.001uF

402

50V

20%

C2221

1

2

0.001uF

402

CERM

50V

20%

C2201

2

1 3

22000pF-1000mA

CRITICAL

16V

NFM18

C2206

2

1 3

NFM18

16V

22000pF-1000mA

CRITICAL

C2200

1

2

402

20%
10V
CERM

0.1UF

C2205

1

2

X5R

10%

1UF

10V
402

L2220

1 2

1007

C2220

1

CASE-B2-SM

220UF

20%

POLY

CRITICAL

C2217

1

2

PLACEMENT_NOTE=Place in GMCH cavity

20%

402

10V
CERM

0.1UF

C2216

1

2

402

20%
10V
CERM

0.1UF

PLACEMENT_NOTE=Place in GMCH cavity

C2215

1

2

402

CERM-X5R

6.3V

10%

0.47UF

PLACEMENT_NOTE=Place in GMCH cavity

C2213

1

2

603

X5R

6.3V

20%

10uF

PLACEMENT_NOTE=Place in GMCH cavity

C2212

1

2

6.3V
805

PLACEMENT_NOTE=Place in GMCH cavity

20%

22UF

CERM

C2210

1

2 3

CRITICAL

2.5V
D2T

TANT

470UF

20%

C2226

1

2

1UF

10%

6.3V
402

CERM

R2285

1 2

NO STUFF

1%

MF-LF

1/16W

402

10

L2288

1 2

120-OHM-0.3A-EMI

0402-LF

C2214

1

2

402

6.3V

10%
CERM

1UF

PLACEMENT_NOTE=Place in GMCH cavity

C2265

1

2

10%

1UF

CERM

6.3V
402

R2266

1

2

603

FF

0.300

5%
1/10W

C2266

1

2

603

10UF

20%
X5R

6.3V

C2230

1

2

10V
CERM
402

20%

0.1UF

C2285

1

2

20%

10UF

603

X5R

6.3V

U2265

3

2

1

4

5

CRITICAL

TPS731125

SOT23-5

C2267

1

2

10%
CERM

0.01UF

16V
402

D2285

12

1SS418

SOD-723

NO STUFF

U2280

4

3

6

5

2

1

7

CRITICAL

SON

TPS79933

15B3 60C6

15B3 60C6

15B3 60C6

15B3 60C6

R2245

1

2

1/16W
MF-LF

5%

22K

402

R2250

1

2

MF-LF
402

22K

5%
1/16W

NO STUFF

R2244

1

2

1/16W
MF-LF

5%

22K

402

NO STUFF

R2243

1

2

22K

5%
MF-LF

1/16W
402

NO STUFF

R2249

2

MF-LF

1/16W

5%

22K

402

1

2

1/16W
MF-LF
402

22K

5%

R2242

1

2

402

1/16W

22K

5%
MF-LF

1

2

402

1/16W
MF-LF

22K

NB Graphics Decoupling

01

76

SYNC_MASTER=WFERRY

SYNC_DATE=06/15/2006

21

051-7455

VOLTAGE=1.5V

PP1V5_S0_NB_VCCD_QDAC

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V5_S0_NB_QDAC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP3V3_S0_NB_TVDAC

PP1V8_S0_NB_VCCTXLVDS

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V

MIN_LINE_WIDTH=0.2 MM

=PP3V3_S0_NB_VCCHV

=GND_NB_VSSA_DAC_BG

P3V3TVDAC_EN_RC

=PP1V8_S0_NB_DPLL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V

PP3V3_S0_NB_VCCA_CRTDAC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PP3V3_S0_NB_VCCA_TVDACA

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM
VOLTAGE=3.3V

PP3V3_S0_NB_VCCA_TVDACC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM
VOLTAGE=3.3V

PP3V3_S0_NB_VCCA_DAC_BG

PP3V3_S0_NB_TVDAC_F

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

PP1V25_S0_NB_VCCA_DPLLB

MIN_LINE_WIDTH=0.3 MM

PP3V3_S0_NB_VCCA_TVDACB

MIN_LINE_WIDTH=0.3 MM
VOLTAGE=3.3V

P3V3TVDAC_NOISE

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_NB_TVDAC_FOLLOW

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

PP1V25_S0_NB_DPLL_RF

P1V25S0NBDPLL_FB

PP1V5_S0_NB_VCCD_CRT

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V

PP1V5_S0_NB_VCCD_TVDAC

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

PP1V5_S0_NB_VCCD_CRT

MAKE_BASE=TRUE

=PP1V5_S0_NB_VCCD_CRT

=GND_NB_VSSA_LVDS

=PP3V3_S0_NB_VCCSYNC

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0_NB_DPLL

VOLTAGE=1.25V

PP1V25_S0_NB_VCCA_DPLLA

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

=PPVCORE_S0_NB_GFX

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V

PP3V3_S0_NB_CRTDAC_F

GFX_VID<2>

GFX_VID<1>

GFX_VID<0>

GFX_VID<3>

R2247

1

R2248

5%

NO STUFF

=PP1V5_S0_NB_TVDAC

=PP1V8_S0_NB_VCCD_LVDS

402

MIN_NECK_WIDTH=0.2 MM

=PP1V5_S0_NB_FOLLOW

=PP5V_S0_NB_TVDAC

2

2.5V

1.0UH-0.5A-0.675A

=PP1V8_S0_NB_LVDS

OMIT

20A8 18B3

48B3

15C7

17D5

18C6

15B7

18D6

17B7

7A7

7B7

18B6

18B3

7D4

18D6

7B7

18D6

18B6

18B6

18D6

18D6

18B6

21C5

18B6

21D6

18B6

18C6

18A6

7B7

7C4

18D6

7B7

7B7

SATA0RXP

SATA0RXN

SATALED*

RTCRST*

HDA_BIT_CLK

DDREQ

RTCX1
RTCX2

DCS1*
DCS3*

IDEIRQ

DDACK*

IORDY

DIOR*
DIOW*

DD11
DD12

DD4

DD2

DD14

DD0

DD15

DD1

DD13

DD5

DD10

DD8

DD3

DD9

LDRQ0*

FWH2/LAD2
FWH3/LAD3

FWH1/LAD1

LDRQ1*/GPIO23

FWH0/LAD0

FWH4/LFRAME*

HDA_SDIN0

HDA_SYNC

SATA1TXN
SATA1TXP

HDA_SDIN1
HDA_SDIN2

RCIN*

SATA0TXP

SATA0TXN

CPUPWRGD/GPIO49

SMI*

A20M*

SATA1RXP

SATA1RXN

SATARBIAS

SATARBIAS*

IGNNE*

DPRSTP*

INTVRMEN

A20GATE

SATA2RXN
SATA2RXP

THRMTRIP*

DPSLP*

INIT*

HDA_RST*

HDA_SDOUT

HDA_DOCK_EN*/GPIO33

SATA2TXN
SATA2TXP

FERR*

NMI

HDA_SDIN3

INTR

SATA_CLKP

SATA_CLKN

DA2

DD6

STPCLK*

TP8

DA0
DA1

HDA_DOCK_RST*/GPIO34

INTRUDER*

LAN_TXD0

LAN100_SLP

LAN_RSTSYNC

LAN_RXD0
LAN_RXD1
LAN_RXD2

DD7

LAN_TXD2

LAN_TXD1

GLAN_DOCK*/GPIO13

GLAN_COMPI
GLAN_COMPO

GLAN_CLK

LAN/GLANIHDA

CPU

RTC

LPC

(1 OF 6)

SATA

IDE

OUT

IN

IN

IN

BI

BI
BI

BI

BI

OUT

OUT

IN

IN

OUT

OUT

IN

IN
OUT
OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT
OUT

IN

OUT

OUT
OUT
OUT

IN
IN
IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT
OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

IN

IN

OUT
OUT

OUT

OUT

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

INT PU

INT PU

INT PU

INT PD

HDA

24.000MHZ CLOCK W/INTERNAL WEAK PD

HDA_BIT_CLK

HDA_RST#

HDA_SDIN[0-2]

HDA_SDOUT

ACZ_SYNC

INTEGRATED PDs

INTEGRATED PD

INTEGRATED PD

INT PDINT PU

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PU

INT PU

INT PU

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

U2300

AF13
AG26

AG29

AA4

AA1
AB3

Y6

Y5

V1
U2

T4

V6
V5

U1
V2

U6

V3
T1

V4

T5
AB2

T6

T3
R2

Y2

W5

W4
W3

AF26

AE26

AD24

E5

F5
G8

F6

C4

B24

D25

C25

AH21

AJ16

AE10

AG14

AE14

AJ17
AH17

AH15

AD13

AE13

AJ15

Y3

AF27

AE24

AC20

AD22

AF25

Y1

AD21

D22

C21
B21

C22

D21

E20
C20

G9

E6

AD23

AH14

AF23

AG25

AF24

AF6

AF5

AH5
AH6

AG3

AG4

AJ4
AJ3

AF2
AF1

AE4

AE3

AB7
AC6

AF10

AG2

AG1

AG28

AA24

AE27

AA23

OMIT

BGA

ICH8M

27C8

27C8

27D5

27C5

6D2

44C8 46C6

6C2

44C8 46C4

6C2

44C8 46C4

6D2

44C8 46C6

6C2

44C8 46B6

9C8

70C3

R2304

1

2

402

MF-LF

1/16W

5%

2.2K

NO STUFF

R2302

1

2

402

1%

24.9

MF-LF

1/16W

R2301

1

2

1%

332K

MF-LF
402

1/16W

40C4 73D3

40D4 73D3

40D4 73D3

40D4 73D3

8D4

8D4

8D4

8D4

8D4

8D4

8D4

8D4

29C3 75B3

29C3 75B3

40D2

40D2

9B2

15B6 59C7 70B3

9B2

70B3

9C8

70C3

9B2

12B1 70C3

39C3 73D3

39B5 73D3

39B3 73D3

39B5 73D3

39B5 73D3

39C3 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C5 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39C3 73D3

39B5 73D3

39B5 73D3

39B3 73D3

9B8

70B3

9B8

70C3

9B8

70B3

9C8

70B3

9D6

46B2 70B3

9B8

70C3

R2306

1

2

10K

MF-LF
402

5%
1/16W

9C6

15A6 45B3 70B3

R2308

1 2

PLACEMENT_NOTE=Place R2308 within 50mm of U2300

1%

MF-LF

1/16W

24.9

402

8A6

73C3

R2300

1

2

1/16W

1%

332K

402

MF-LF

R2303

1

2

8.2K

5%
1/16W
MF-LF

402

8A6

73C3

8A6

73C3

8A6

73B3

8A6

73C3

R2310

1

2

402

MF-LF

1/16W

5%

8.2K

R2305

1

2

1%
1/16W
MF-LF

402

54.9

R2309

1

2

1%
1/16W
MF-LF
402

54.9

PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)

R2313

1 2

402

33

MF-LF1/16W

5%

R2314

1 2

5%

1/16W MF-LF33402

R2315

1 2

1/16W33MF-LF5%402

R2316

1 2

5%

1/16W MF-LF

402

33

R2311

1

2

1/16W

402

MF-LF

10K

5%

39B3 73D3

39B5 73D3

01

22 76

051-7455

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

SB Enet, Disk, FSB, LPC

PP3V3_G3_SB_RTC

SB_RTC_X1
SB_RTC_X2

HDA_DOCK_EN_L

LAN_ENERGY_DET

=PP3V3_S0_SB_GPIO

PP1V5_S0_SB_VCC1_5_B

GLAN_COMP

SB_INTVRMEN
SB_LAN100_SLP

SB_SM_INTRUDER_L

SB_RTC_RST_L

TP_LAN_R2D<2>

LPC_AD<2>

LPC_AD<0>
LPC_AD<1>

LPC_AD<3>

LPC_FRAME_L

EXTGPU_PWR_EN

PM_THRMTRIP_L

CPU_THERMTRIP_R

CPU_A20M_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD

CPU_IGNNE_L

CPU_INIT_L
CPU_INTR

CPU_NMI
CPU_SMI_L

CPU_STPCLK_L

IDE_PDD<0>

IDE_PDD<2>

IDE_PDD<1>

IDE_PDD<3>
IDE_PDD<4>
IDE_PDD<5>

IDE_PDD<7>

IDE_PDD<6>

IDE_PDD<8>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<12>

IDE_PDD<11>

IDE_PDD<13>

IDE_PDD<15>

IDE_PDD<14>

IDE_PDA<0>
IDE_PDA<1>
IDE_PDA<2>

IDE_PDCS3_L

IDE_PDCS1_L

IDE_PDIOW_L

IDE_PDIOR_L

IDE_PDDACK_L
IDE_IRQ14
IDE_PDIORDY
IDE_PDDREQ

=PP1V05_S0_SB_CPU_IO

=PP3V3_S0_SB_GPIO

CPU_FERR_L

SB_A20GATE

TP_LPC_DRQ0_L

SB_RCIN_L

TP_SB_TP8

TP_LAN_D2R<2>

SATA_A_D2R_P

TP_SB_SATALED_L

SATA_A_R2D_C_P

SATA_A_R2D_C_N

SATA_B_D2R_P

SATA_B_D2R_N

TP_HDA_DOCK_RST_L

TP_LAN_R2D<0>

TP_LAN_RSTSYNC

TP_LAN_D2R<0>

TP_LAN_R2D<1>

SATA_B_R2D_C_N
SATA_B_R2D_C_P

SATA_C_D2R_P

SATA_C_D2R_N

SATA_C_R2D_C_N
SATA_C_R2D_C_P

SB_CLK100M_SATA_P

SB_CLK100M_SATA_N

SATA_RBIAS_P

SATA_RBIAS_N

HDA_BIT_CLK_R
HDA_SYNC_R

HDA_RST_L_R

HDA_SDOUT_R

HDA_SYNC

HDA_BIT_CLK

HDA_RST_L

HDA_SDOUT

SATA_A_D2R_N

TP_HDA_SDIN1

TP_ENET_GLAN_CLK

TP_LAN_D2R<1>

HDA_SDIN0

TP_HDA_SDIN3

TP_HDA_SDIN2

24D8

26C6

24D8

27D4

24B3

26A4

26C4

24B3

26A5

22D2

25D6

25C3

22D7

25D6

7D4

23C2

74B3

7D7

7D4

73C3

73C3

73C3

73B3

8A6

8A6

8A6

SPI_CS1*

PETN1

PERP1

OC4*/GPIO43
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31
OC8*
OC9*

SPI_MOSI

OC0*
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42

PERN5

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI_CLKN
DMI_CLKP

PETP1

USBP9N
USBP9P

PERN2

USBP7N
USBP7P
USBP8N
USBP8P

PETN2

USBP6N
USBP6P

PERP3

USBP4N
USBP4P
USBP5N
USBP5P

PETN3

PETP3

USBP3N
USBP3P

PERN4
PERP4

USBP1N
USBP1P
USBP2N
USBP2P

PETN4
PETP4

USBP0N
USBP0P

PERP5

SPI_MISO

USBRBIAS

USBRBIAS*

PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0*

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI_IRCOMP

DMI_ZCOMP

PERN1

PERP2

PETP2

PERN3

PETN5

PCI_EXPRESS

DIRECT MEDIA INTERFACE

SPI

USB

(2 OF 6)

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

IN
OUT
OUT

IN

IN
OUT
OUT

BI
BI

BI

BI

AD4
AD5

AD9

PIRQF*/GPIO3

PIRQE*/GPIO2

AD13

PME*

PCIRST*

GNT2*/GPIO53

C/BE2*

PIRQG*/GPIO4

SERR*

PIRQA*

AD1

REQ1*/GPIO50

C/BE3*

AD11

C/BE1*

AD25
AD26

AD0

AD2

DEVSEL*

AD18

AD21

PAR

GNT0*

AD7

GNT1*/GPIO51

C/BE0*

STOP*

AD20

AD16

GNT3*/GPIO55

TRDY*

IRDY*

AD22

PIRQC*

REQ2*/GPIO52

AD19

PCICLK

PLOCK*

AD15

PIRQB*

PIRQH*/GPIO5

PLTRST*

AD3

AD6

AD8

FRAME*

AD14

AD12

AD10

REQ3*/GPIO54

PIRQD*

AD17

PERR*

REQ0*

AD31

AD27
AD28

AD30

AD29

AD24

AD23

(3 OF 6)

INTERRUPT I/F

PCI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

BI

BI

BI

BI

BI
BI

OUT

BI
BI
BI

BI

BI

BI

BI

OUT

IN

BI
BI

IN

IN

IN
IN
IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PCIe Mini Card

rises, or PCIe ports 5 & 6 will be disabled.

NOTE: GNT[0-3]# have internal 20K pull-ups

Provide a pull-down on this GPIO if not used.

R2415 pull-down on GNT0#

Nineveh-GLCI

Yukon-PCIE

enabled only when PCIRST# = 0 and PWROK = 1

If used, ensure GNT2# is not low when PWROK

INT PU

INT PU

FireWire INT*

SPI

I/F

LPC

NOTE:

0

GNT0#

1

INT PU

INT PU

INT PU

SB BOOT BIOS SELECT

GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

high for x2)

pull HDA_SYNC

(x2-capable,

Ethernet

(AirPort)

FireWire

ExpressCard

Spares

INT PD

INT PD

INT PD

EHCI1

INT PU

INT PU

INT PU

INT PU

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

EHCI0

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

INT PD

External C

Camera

AirPort (PCIe Mini-Card)

ExpressCard

External B

Geyser Trackpad/Keyboard

External A

External D / WWAN

Bluetooth

IR

NOTE: USBP[0-9]P/N have internal 15K pull-downs.

selects SPI ROM by default.

R2408

1

2

5%

10K

402

1/16W
MF-LF

R2407

1

2

1/16W
MF-LF
402

10K

5%

R2400

1

2

10K

402

5%
1/16W
MF-LF

R2409

1

2

1/16W
402

MF-LF

5%

10K

R2401

1

2

MF-LF
402

5%

10K

1/16W

R2402

1

2

402

5%
1/16W
MF-LF

10K

R2404

1

2

402

1/16W
MF-LF

10K

5%

R2403

1

2

10K

MF-LF
402

1/16W

5%

U2300

V27

V26
U29

U28

Y27

Y26

W29
W28

AB26
AB25

AA29
AA28

AD27
AD26

AC29

AC28

T26

T25

Y24

Y23

AJ19
AG16

AG15

AE15
AF15

AG17

AD12
AJ18

AD14
AH18

P27

M27

K27

H27

F27

D27

P26

M26

K26

H26

F26

D26

N29

L29

J29

G29

E29

C29

N28

L28

J28

G28

E28

C28

C23

B23

E22

F21

D23

G3
G2

H5

H4
H2

H1

J3
J2

K5
K4

K2

K1
L3

L2

M5
M4

M2

M1
N3

N2

F3

F2

BGA

ICH8M

OMIT

15B3 71D3

15B3 71D3

15C3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15C3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

15B3 71D3

29C3 75B3

29C3 75B3

R2413

1 2

1%

402

MF-LF1/16W

24.9

8C1

73B3

8C1

73B3

8C1

73B3

8C1

73B3

8C1

8C1

8C1

73B3

8C1

73B3

8C1 8C2

73B3

8C1 8C2

73B3

8C1

73B3

8C1

73B3

8B1 8B2

73B3

8C1 8C2

73B3

8B1

73B3

8B1

73B3

8B1

73B3

8B1

73B3

8B1

73B3

8B1

73B3

R2414

1 2

22.6

MF-LF

402

1%

1/16W

33B6

33B6

33B6

33B6

34C8

34C8

34C8

34C8

52C7 73A3

52C7 73A3

52C3 73A3

52C3 73A3

U2300

D20
E19

A12

E16
A14

G16

A15

B6

C11

A9
D11

B12

D19

C12

D10

C7
F13

E11

E13
E12

D8

A6

E8

A20

D6

A3

D17

A21

A19
C19

A18
B16 C17

E15

F16
E17

D16

A17

D7

C18

F18

C10

C8
D9

B10

G6

A7

F9

B5

C5
A10

F8

G11

F12
B3

B7

AG24

G7

A4

E18

B19

A11

F10

C16

C9

OMIT

BGA

ICH8M

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37C5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B6 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

23A4 74C3

23A4 74C3

23A4 74C3

23A4 37A5 74C3

23A4 74D3

23A4 37A5 74D3

23A4 74D3

37B5 74D3

37B5 74D3

37B5 74D3

37B5 74D3

23A4 37A5 74D3

37B5 74D3

37A6

23A4 37A5 74D3

23A4 37A5 74D3

23A4 74D3

23A4 37A5 74D3

23A4 37A5 74D3

23A4 37A5 74D3

23A4 37A5 74D3

27D4 67C6

29A5 29B3 75B3

23A4 74C3

R2405

1

2

5%

402

MF-LF

1/16W

10K

R2406

1

2

1/16W

5%

MF-LF

100K

402

NOSTUFF

R2415

1

2

MF-LF

1K

1/16W

5%

402

R2423

1 2

8.2K

R2424

1 2

8.2K

R2425

1 2

8.2K

R2426

1 2

8.2K

R2427

1 2

8.2K

R2428

1 2

8.2K

R2430

1 2

8.2K

R2429

1 2

8.2K

R2432

1 2

8.2K

R2431

1 2

8.2K

R2433

1 2

8.2K

R2437

1 2

8.2K

R2439

1 2

8.2K

R2438

1 2

8.2K

R2436

1 2

8.2K

R2440

1 2

8.2K

23A4 74C3

R2441

1 2

8.2K

8C1

8B1

23A4 39C8

68A4 68B8

37A5 74D3

39A8 73D3

6C2

46B6

R2442

1 2

8.2K

39B8

33B6

SYNC_DATE=10/30/2006

051-7455

7623

01

SYNC_MASTER=T9_MLB

SB PCI, PCIe, DMI, USB

SB_GPIO42

=PP3V3_S5_SB_USB

EXTGPU_LVDS_EN

MAKE_BASE=TRUE

PCI_FW_GNT_L

TP_SB_GPIO55

TP_SB_GPIO51

ODD_RST_5VTOL_L

SB_GPIO30

USB_EXTA_OC_L

USB_EXTB_OC_L
EXCARD_OC_L

SB_GPIO40
USB_EXTD_OC_L

USB_EXTC_OC_L

ODD_PWR_EN_L

INT_PIRQF_L

INT_PIRQE_L

PCI_FRAME_L

PCI_TRDY_L

PCI_STOP_L

PCI_LOCK_L

PCI_PERR_L

PCI_RST_L

PCI_PAR

PCI_FW_REQ_L

TP_SB_GPIO53

PCI_C_BE_L<0>

PCI_C_BE_L<2>

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

TP_SPI_CE_R_L<1>

PCI_DEVSEL_L

PM_LATRIGGER_L

TP_PCIE_A_R2D_C_P

PCI_AD<14>

PCI_AD<4>
PCI_AD<5>

PCI_AD<9>

PCI_AD<13>

INT_PIRQA_L

PCI_AD<1>

PCI_AD<11>

PCI_AD<25>
PCI_AD<26>

PCI_AD<0>

PCI_AD<2>

PCI_AD<18>

PCI_AD<21>

PCI_AD<7>

PCI_AD<20>

PCI_AD<16>

PCI_AD<22>

INT_PIRQC_L

PCI_AD<19>

PCI_AD<15>

INT_PIRQB_L

PCI_AD<3>

PCI_AD<6>

PCI_AD<8>

PCI_AD<12>

PCI_AD<10>

INT_PIRQD_L

PCI_AD<17>

PCI_AD<31>

PCI_AD<27>
PCI_AD<28>

PCI_AD<30>

PCI_AD<29>

PCI_AD<24>

PCI_AD<23>

BOOT_LPC_SPI_L

PCI_REQ1_L

PCI_C_BE_L<3>

PCI_SERR_L

PCI_REQ1_L

PCI_TRDY_L

INT_PIRQE_L

INT_PIRQD_L

INT_PIRQB_L

INT_PIRQA_L

PCI_REQ2_L

PCI_STOP_L

PCI_IRDY_L

PCI_FRAME_L

PCI_FW_REQ_L

PCI_LOCK_L

INT_PIRQF_L

INT_PIRQC_L

ODD_PWR_EN_L

PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L

=PP3V3_S0_SB_PCI

PP1V5_S0_SB_VCC1_5_B

USB_RBIAS

DMI_IRCOMP_R

TP_PCIE_A_R2D_C_N

TP_PCIE_A_D2R_P

SPI_SI_R

PCIE_MINI_D2R_N

TP_PCIE_B_D2R_N

TP_PCIE_B_R2D_C_N

TP_PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_R2D_C_N
TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_FW_D2R_N
TP_PCIE_FW_D2R_P
TP_PCIE_FW_R2D_C_N
TP_PCIE_FW_R2D_C_P

PCIE_MINI_D2R_P

PCIE_ENET_D2R_N

SPI_SCLK_R
SPI_CE_R_L<0>

TP_PCIE_A_D2R_N

TP_PCIE_B_D2R_P

TP_PCIE_B_R2D_C_P

TP_PCIE_EXCARD_D2R_N

USB_EXTC_P

USB_EXCARD_P
USB_EXTC_N

USB_EXCARD_N

USB_EXTB_P

USB_EXTB_N

USB_BT_P

USB_TPAD_P
USB_BT_N

USB_TPAD_N

USB_IR_P

USB_IR_N

USB_CAMERA_N
USB_CAMERA_P

USB_EXTD_P

USB_EXTD_N

USB_MINI_P

USB_MINI_N

USB_EXTA_P

USB_EXTA_N

SB_CLK100M_DMI_P

SB_CLK100M_DMI_N

DMI_S2N_P<3>

DMI_S2N_N<3>

DMI_N2S_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>

DMI_S2N_N<2>

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_S2N_P<1>

DMI_S2N_N<1>

DMI_N2S_P<1>

DMI_N2S_N<1>

DMI_S2N_P<0>

DMI_S2N_N<0>

DMI_N2S_P<0>

DMI_N2S_N<0>

PCI_IRDY_L

PCIE_ENET_R2D_C_N

SPI_SO

PCI_C_BE_L<1>

PLT_RST_L

PCI_REQ2_L

PCI_CLK33M_SB
TP_PCI_PME_L

DVI_HOTPLUG_DET

26C6

74D3

74C3

74D3

74D3

74D3

74D3

74D3

74D3

74D3

26A4

74D3

37A5

74C3

37A5

74C3

74C3

74D3

37A5

37A5

37A5

37A5

74D3

74C3

74C3

39C8

37A5

37A5

37A5

25D6

7D1

8D4

23B6

23A6

23A6

23A8

23A8

23A8

23B6

23A6

23A6

23A6

23B6

23A6

23A6

23A8

23A6

23A6

23A6

23A6

7C4

22D7

73B3

8D4

8D4

8D4

8C4

8C4

8C4

8C4

8C4

8C4

8C4

8C4

8D4

8D4

8C4

8C4