Apple A1181 Schematic RevH

8 7

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

6

5

4

3

K36A MLB SCHEMATIC

REFERENCED FROM K36

H

REV

2 1

ZONE

581757

DESCRIPTION OF CHANGE

ECN

PRODUCTION RELEASED

CK APPD

DATE

04/15/08

ENG APPD

?

DATE

02/15/2008

D

C

B

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

(.csa)

1

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

CONFIGURATION OPTIONS

5

Revision History

7

FUNC TEST 1 OF 2

8

Power Aliases

9

SIGNAL ALIAS /RESET

10

CPU FSB

11

CPU Power & Ground

12

CPU Decoupling & VID

13

CPU ITP700FLEX DEBUG

14

NB CPU Interface

15

NB PEG / Video Interfaces

16

NB Misc Interfaces

17

NB DDR2 Interfaces

18

NB Power 1

19

NB Power 2

20

NB Grounds

21

NB Standard Decoupling

22

NB Graphics Decoupling

23

SB Enet, Disk, FSB, LPC

24

SB PCI, PCIe, DMI, USB

25

SB Pwr Mgt, GPIO, Clink

26

SB Power & Ground

27

SB Decoupling

28

SB Misc

29

Clock (CK505)

30

Clock Termination

31

DDR2 SO-DIMM Connector A

32

DDR2 SO-DIMM Connector B

33

Memory Active Termination

34

AIRPORT CONNECTOR

37

Ethernet (Yukon)

38

Yukon Power Control

39

ETHERNET CONNECTOR

40

FIREWIRE CONTROLLER

43

FIREWIRE PORT

44

PATA CONNECTOR

45

SATA CONNECTOR

46

USB EXTERNAL CONNECTORS

47

CONNECTOR MISC

48

IR CONTROLLER & BT INTERFACE

49

SMC

50

SMC SUPPORT

Contents

RX RX MK RX RX RX MK RX RX RX RX ES ES ES ES ES ES ES ES ES ES RX RX RX RX RX RX DK DK LD LD LD LT LT LT LT LT LT DK RX LT LT LT LD LD

D

C

B

Page Sync

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

USB

WFERRY-WF

POWER

SMC

N/A

TP

WFERRY

GPU

T9_MLB_NOME

MSARWAR

MASTER

T9_MLB

WFERRY

T9_MLB

WFERRY

NB

DSIMON

DSIMON-WF

MEMORY

ENET

USB

ENET

GPU

USB

T9_MLB

GPU

Date

09/05/2006

05/11/2006

06/30/2005

07/18/2005

N/A

07/25/2005

06/15/2006

07/17/2006

11/12/2006

04/26/2006

5/23/05

10/30/2006

06/15/2006

10/30/2006

06/01/2006

07/26/2005

06/06/2006

06/20/2005

08/19/2005

10/07/2006

09/14/2006

08/30/2005

07/17/2006

06/30/2006

06/29/2006

09/05/2006

10/30/2006

07/17/2006

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

(.csa)

51

LPC+ Debug Connector

52

SMBUS CONNECTIONS

53

CPU Current & Voltage Sense

55

TEMPERATURE SENSE

56

Fan

59

SMS

61

SPI ROMs

62

AUDIO: CODEC

66

AUDI0: SPEAKER AMP

67

AUDIO: JACK

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

S0 FETS & Power Sequencing

71

IMVP6 CPU VCore Regulator

72

Render VCore Supplies

73

1.5V / 1.05V Supplies

75

1.8V/0.9V Supplies

76

5V/3.3V Supplies

77

3.42V/1.25V Switcher

78

S3 FET & S3/S5 Control

79

PBUS Supply/Battery Charger

90

INVERTER,LVDS,TMDS

92

EXTERNAL TMDS

94

MINI-DVI CONNECTOR

100

CPU/FSB Constraints

101

NB Constraints

102

Memory Constraints

103

SB Constraints (1 of 2)

104

SB Constraints (2 of 2)

105

Clock Constraints

106

FireWire & SMC Constraints

Contents

Sync

LD LD ES ES LD MK RX RX RX RX RX RX MK MK MK MK MK MK MK MK MK MK ES ES ES RX ES LD RX RX DK

WFERRY

GPU

ENET

SMC

WFERRY

M70AUDIO

POWER

DSIMON-WF

POWER

GPU

POWER

ENET

DSIMON-WF

SMC

GPU

GRAPHIC

EUGENE

WFERRY

Date

06/01/2006

07/17/2006

06/21/2006

11/10/2005

08/23/2005

04/26/2006

03/12/2007

07/13/2005

05/31/2006

07/13/2005

06/29/2006

07/13/2005

12/06/2005

06/12/2006

08/19/2005

06/23/2006

06/06/2005

05/21/05

06/08/2006

06/12/2006

06/08/2006

06/12/2006

K36A EE DRIS: DK-DINESH KUMAR

A

Schematic / PCB #’s

PART NUMBER

051-7559 820-2279

QTY

1 1

8

DESCRIPTION

SCHEM,MLB,K36A

PCBF,MLB,K36

REFERENCE DES

SCH PCB

CRITICAL

CRITICAL CRITICAL

BOM OPTION

7 6

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

ANGLES

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

5

4

3

DRAFTER

ENG APPD

QA APPD

RELEASE

METRIC

MATERIAL/FINISH

NOTED AS

APPLICABLE

DESIGN CK

MFG APPD

DESIGNER

SCALE

NONE

SIZE

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TITLE

SCHEM,MLB,K36A

DRAWING NUMBER

D

APPLE INC.

051-7559

A

REV.

SHT

H

OF

106

1

8 7

U1000

D

U9200

TMDS

PG 68

J9401

DVI-I

PG 69

J9001

GPIO

MUX

Int Disp

Conn

C

PG 67

J4501

SATA Conn

PG 40

J4401

UATA Conn

PG 39

SDVO

64-Bit

800/1066? MHz

PCI-E

Pg 14

Out

TV

RGB

LVDS

Pg 14

SATA-0

Pg 22

SATA-1 SATA-2

Pg 22

Ln1 Ln2 Ln3 Ln4 Ln5 Ln6

UATA

6

CPU

2.? GHz

Core ~1.2V

Pg 10

Pg 9

FSB

Pg 13

U1400

NB-GMCH

Core

1.05 - 1.25V

Pg 17,18,19

DMI

Pg 15

x4 DMI

2.5 GHz

DMI SPI

Pg 23

U2300

SATA

SB-ICH8

Misc

Pg 15

CLnk 0

Pg 15

CLnk 0

Pg 24

Core 1.05V

J1302

ITP CONN

DDR2 - Dual Channel

Pg 15/16

Main Memory

533/667/800? MHz

Pg 23

PG 12

1.8V - 64 Bits

U6100/50

SPI

Boot ROM

PG 54

GPIOs

USB

Pg 22

Pg 24

Pg 23

5

8 7 9 651 2 3 4

U2900

CK 505

Clocks

Pg 28

J3101 J3201

DIMM

Pg30,31

U4800

IR

CONTROLLER

PG 44

CAMERA

TERMS Pg 29

Parallel

Term

Pg 32

J4850

3G

CONNECTOR

PG 43 PG 42 PG 43 PG 41

A

U4900

4

J6900/50

DC/Batt

ADC

BSBBSAB,0

SMC

PG 44

J4700

Geyser

Trackpad/Keyboard

Conn

PG 57

Temp Sense

CPU

HEAT-PIPE/FIN

U5920 SUDDEN MOTION DETECT PG 51

POWER SENSE PG 48

J5601

FAN CONN PG 50

Ser

Fan

Prt

J4810

Bluetooth

Power

Supply

PG 57-67

3

U5520

PG 49

U5500

PG 49

J5100

LPC Conn

PG 46

J4600

USB

Connectors

J4601

2 1

D

C

PCI-E

B

Pg 23

Core

Pg 25

E-NET

Pg 22

CLnk 1

Pg 24

33 MHz 32-Bit

U4000

PCI

Pg 23

FW32306

Pg 37

A

J3400

Mini PCI-E

AirPort

Pg 33

8

7 6

U3700

NINEVEH

J3900

E-NET

Pg 34

Conn

Pg 36

J4300

FireWire

Conn

PG 38

SMB LPC

AZALIA

Pg 22

Pg 24

DIMM’s

Clk Gen

U2900

J3101

UC500

J3201

U6200

Audio Codec

Pg 53

JACK

TRANSLATORS

PG 56

J6701 INTERNAL MIC J6702/03 INTERNAL SPEAKER J6750/00 LINE IN/OUT

5

4

U6600/10/20

Audio Conns

PG 55

Speaker

Amps

PG 54

APPLE INC.

3

2

System Block Diagram

SYNC_MASTER=WFERRY-WF

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

051-7559

SCALE

NONE

SYNC_DATE=05/11/2006

SHT

OF

2

106

1

REV.

B

A

H

8 7

6

5

4

3

2 1

K36 POWER SYSTEM ARCHITECTURE

D6901

ENRGYSTR LDO

VIN

MAX8719

D

SMC_ENRGYSTR_LDO_EN

01

AC

ADAPTER

DCIN

6A FUSE

U7970

A

U7950

SHGN*

(PAGE 66)

ENABLES

VIN

CHGR_EN

(S5)

IN

VOUT

D7950

VOUT

PPVBAT_G3H_CHGR_REG

U7975

SMC_BATT_ISENSE

7A FUSE

PPDCIN_G3H

PPBUS_G3H

17 17

PBUSB_VSENSE

1V05S0_RUNSS

(S0)

1V5S0_RUNSS

(S0)

PBUS CONVERTER/

SMC_DCIN_ISENSE

BATTERY CHARGER

A

ISL6257HRZ

U7900

(PAGE 66)

BATTERY

3S2P

BATT_POS_F

C

01

02

IMVP_VR_ON

23

CPUVCORE

VIN

ISL9504

VR_ON

U7100

(PAGE 59)

VOUT

CLKEN#

PGOOD

PPBUS_G3H

12

RC

ICH

PM_S4_STATE_L

PM_SLP_S3_L

PM_SLP_S4_L

11

Q7860

B

14

Q3801

PP3V3ENET_SS

Q3802

PM_ENET_EN_L

15

A

RUNSS_GATE_D

Q7006

Q7007

Q7006

SOFT START

P5VS3_EN_L

DELAY

(S3)

RC

P3V3S3_EN_L

DELAY

(S3)

15

WOL_EN

SMC_ADAPTER_EN

U7870

1V5S0_RUNSS (S0)

1V05S0_RUNSS (S0)

1V25S0_RUNSS (S0)

12

04-1

17

GFX_VR_EN

20

SMC

U4900

(PAGE 45)

1V8S3_RUNSS

PM_SLP_S3_L

02

GPU_VCORE

VIN

ISL6263

U7200

ENA

(PAGE 60)

P25

SMC_PM_G2_EN

P60

(S5)

12

14

VOUT

CHGR_EN

LOGIC

06

Q7004

Q7860

17-1

PM_ENET_EN_L

P1V8S0_EN

P1V8_S0_FET

15

02

PP1V5_S0_REG

VIN

S5 S3

PPVCORE_S0_NB_GFX_IMVP

(7.7A MAX CURRENT)

VLDOIN

1.8V

VOUT1

0.9V

VOUT2

TPS51116

U7500

(PAGE 62)

Q7859

07

5VS5_RUNSS

(S5)

3V3S5_RUNSS

(S5)

07

Q7859

1.2V YUKON

VIN

U3830

MAX8516

VOUT

(PAGE 35)

ENA

16

PP1V8_S3_REG

(10.75A MAX CURRENT)

PP0V9_S0_REG

VIN

ENA

13

MCH DPLL

TPS731125

(PAGE 21)

21

VIN

ENA1

3.3V

ENA2

TPS51120

U7600

(PAGE 63)

PGOOD1,2

RSMRST_PWRGD

PP1V2_ENET_REG

U2265

P1V25_S0_NB_DPLL

VOUT

R7502

18

02

VOUT1

5V

VOUT2

VREG3

PP1V8_S3_REG_R

02

Q5350

V

1.05V

ENA1

1.5V

ENA2

TPS51124 (PAGE 61)

PGOOD1

PGOOD_1V05S0

U5300

A

VR_PWRGD_CK505_L

VR_PWRGOOD_DELAY

PP5V_S5_REG

(7.5A MAX CURRENT) PP3V3_S5_REG

(5A MAX

V

SMC_CPU_ISENSE

08

CURRENT)

09

18

ENABLE

3.425V G3HOT LT3470

U7790

(PAGE 64)

02

VIN

VOUT1

VOUT2

U7300

PGOOD2

PGOOD_1V5S0

SMC_CPU_VSENSE

PPVCORE_CPU_S0

Q7000

P5VS0_EN

Q7865

P5VS3_EN_L

08

Q7866

P3V3S3_EN_L

Q7001

P3V3S0_EN

Q3810

PM3V3ENET_SS

PGOOD_1V8S3 PP5V_S0_FET PP3V3_S0_FET PP1V8_S0_FET

PM_SLP_S3_L

14

PP3V42_G3H_REG

PP1V05_S0_REG (8A MAX CURRENT) PP1V5_S0_REG (4A MAX CURRENT)

19 19

(36A MAX CURRENT)

PP5V_S0_FET

15

13

PP5V_S3

12

PP5V_S5

PP3V3_S5

12

PP3V3_S0_FET

15

P3V3_ENET_FET

15

PGOOD_SEQUENCER

RST*

UVLO_A UVLO_B UVLO_C UVLO_D

ENA*

ISL6130IRZA

U7000

(PAGE 58)

03

24

16

4.5V AUDIO TPS79501

VIN

U6201

ENA

(PAGE 53)

17

1V25S0_RUNSS

PP3V3_S3

PP3V3_ENET_FET

16

P5VS0_EN

GATE A

P3V3S0_EN

GATE B

P1V8S0_EN

GATE C

GATE D

RUNSS_GATE_D

SMC PWRGD

RN5VD30A-F

U5000

(PAGE 45)

R7302

26

PP4V5_AUDIO_ANALOG

VOUT

1.25V S0 TPS62510

ENA

U7720

VIN

(PAGE 64)

13

1.9V S3

TPS79501DRB

VIN

U3820

ENA

(PAGE 35)

PP1V25_S0_FET

16

19

SMC_RESET_L

PP1V05_S0_REG_R

18

25

VR_PWRGOOD_DELAY

PP1V25_S0_REG

VOUT

PP1V9_ENET_REG

VOUT

TPS3808-1.25V

U7200

MR*

RESET*

SENSE

(PAGE 58)

PGOOD_1V5S0 PGOOD_1V05S0

15 15 15 15

17-1

04

18

U2803

CLK_PWRGD

VR_PWRGD_CK505

PM_SB_PWROK

U2801

18

17

ALL_SYS_PWRGD

09

RSMRST_PWRGD

SMC_ONOFF_L

BATTERY ONLY:

ADAPTER IN :

22

SLP_S5_L SLP_S4_L SLP_S3_L

PWRGD

CK_PWRGD

VRMPWRGD

27

PWROK

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

05

10-1

SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93)

SYNC_MASTER=POWER

APPLE INC.

CLOCK

SLG8LP537V

U2900

(PAGE 28)

ICH8M

PWRBTN*

PLTRST* RSMRST*

CPUPWRGD(GPIO49)

U2300

(PAGE 22)

06-1

PLT_RST_L

CPU_PWRGD

28

CPU

PWRGOOD

RESET*

U1000

(PAGE 9)

CRESTLINE

HCPURST*

U1400

(PAGE 13)

SMC

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

PLT_RST*

P17(BTN_OUT)

RST*

U4900

(PAGE 44)

30

FSB_CPURST_L

10

PM_RSMRST_L

IMVP_VR_ON

PM_PWRBTN_L SMC_RESET_L

Power Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

051-7559

SCALE

NONE

SHT

29

23

SYNC_DATE=06/30/2005

REV.

OF

3

106

D

C

B

A

H

8

7 6

5

4

3

2

1

PAGE_BORDER=TRUE

8 7

6

5

Page Notes

Power aliases required by this page: (NONE)

Signal aliases required by this page: (NONE)

BOM options provided by this page: (NONE)

D

BOARD STACK-UP AND CONSTRUCTION

Top

2 3 4 5

C

6 7 8

9 10 11

BOTTOM

PART#

337S3592

337S3576

337S3586

337S3587

B

337S3561

PART NUMBER

337S3600 337S3576 THERMTRIP SCREENED

337S3604 337S3561

PART#

338S0516 IC,CRESTLINE,GM965,667

338S0434

516-0162

PART#

A

341S2273

341S2060

341S2093

LOCKED BOOTROM PN 341S2274 FOR K36A

PART#

826-4393

DESCRIPTION

QTY

IC,PDC,SLAPS,PRQ,M0/3M,2.1/0.8G,479FCBGA

1 1

IC,PDC,SLAPR,PRQ,M0/3M,2.4/0.8G,479FCGBA

IC,PDC,SLAPR,PRQ,M0/3M,2.4/0.8G,479FCBGA

1

IC,PDC,Q7ZF,QS,C0,2.1/0.8G,3M,479FCBGA

1

IC,PDC,Q7ZF,QS,NON-DTS,M0,2.1/0.8G,3M,479FCBGA

1

IC,PDC,Q7ZF,QS,C0,2.4/0.8G,3M,479FCBGA

1

IC,PDC,Q7ZF,QS,C0,2.4/0.8G,3M,479FCBGA

ALTERNATE FOR PART NUMBER

337S3592

337S3586

DESCRIPTION

QTY

1

IC,ICH8,BGA

1 2

IN-LINE SODIMM CONNECTOR

DESCRIPTION

QTY

1

IC,16MBIT 8PIN SPI FLASH ROM,FOR K36A

IC,EEPROM,SERIAL IIC,8KBIT,SO8

1 1

IC,SMC,HS8/2116 FOR K36A341S2275

1

IC,CYPRESS,CY7C63833,ENCORE_II,USB_CONTR

DESCRIPTION

QTY

LBL,P/N LABEL,PCB,28MMX6MM

1

LBL,P/N LABEL,PCB,28MMX6MM

1

SIGNAL GROUND SIGNAL(High Speed) SIGNAL(High Speed)

GROUND

POWER POWER

GROUND SIGNAL(High Speed)

SIGNAL(High Speed) GROUND SIGNAL

REFERENCE DESIGNATOR(S)

BOM OPTION

?

REF DES

U1000

U1000 U1000 U1000 U1000 U1000 U1000 U1000

COMMENTS:

THERMTRIP SCREENED337S3598

THERMTRIP SCREENED337S3599

THERMTRIP SCREENED

REFERENCE DESIGNATOR(S)

U1400 U2300

J3101,J3201

REFERENCE DESIGNATOR(S)

U6100 U3780 U4900 U4800

REFERENCE DESIGNATOR(S)

EEE:0PH EEE:0PJ EEE:0PK

CRITICAL BOM OPTION

CRITICAL CRITICAL

CRITICAL CRITICAL CRITICAL CRITICAL1BEST_FUSED

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL BOM OPTION

CRITICAL GOOD CRITICAL1BETTER

GOOD BETTER BESTCRITICAL GOOD_FUSED GOOD_NON_DTS BETTER_FUSED

CRITICAL BOM OPTION

CRITICAL CRITICAL CRITICAL

CRITICAL BOM OPTION

CRITICAL CRITICAL CRITICAL CRITICAL

K36 K36 K36

P

K36_PGM K36_PGM K36_PGM K36_PGM

BESTCRITICAL

CONFORMAL_COAT L1 SIGNAL(TOP)

L1-L2

L2 GROUND

L2-L3

L3 SIGNAL

L3-L4

L4 SIGNAL

L4-L5

L5 GND

L5-L6

L6 POWER

TABLE_5_HEAD

TABLE_5_ITEM

L6-L7

L7 POWER

L7-L8

L8 GROUND

L8-L9

L9 SIGNAL

L9-L10

L10 SIGNAL

L10-L11

L11 GROUND

L11-L12

L12 SIGNAL(BOTTOM) CONFORMAL_COAT

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

re

TOTAL

MLB STACKUP

LAYER

THICKNESS

0.018

0.047

0.07

0.014

0.076

0.014

0.156

0.014

0.076

0.014

0.07

0.031

0.076

0.031

0.07

0.014

0.076

0.014

0.156

0.014

0.076

0.014

0.07

0.047

0.018

1.276

(MM)

l

TRACE WIDTH

(MM)

0.1

---

0.079

---

m

i

0.1

---

4

BOM OPTION

BOMOPTION

COMMON ALTERNATE ARB_ONLY K36 LPCPLUS INVERTER_BUF INVERTER_UNBUF ITP NO_REBOOT_MODE NBCFG_DMI_REVERSE NBCFG_DMI_X2 NBCFG_DYN_ODT_DISABLE NBCFG_PEG_REVERSE NBCFG_SDVO_AND_PCIE GOOD BETTER BEST K36_PGM YUKON_EC YUKON_ULTRA NORMAL FANCY STANDOFF ODD_PWR_CORE ODD_PWR_RESUME

ISL6126

i

ISL6130

n

BOM TABLE FOR HF POSCAPS

PART#

128S0147

128S0164

128S0148

128S0169

128S0160

128S0150

128S0157

DESCRIPTION

QTY

HF VERSION OF 128S0057

4

HF VERSION OF 128S0073

3 1

HF VERSION OF 128S0085

3

HF VERSION OF 128S0111

2 K36

HF VERSION OF 128S0113

HF VERSION OF 128S0115

6

HF VERSION OF 128S0122

1

HF VERSION OF 128S0123128S0162

1 K36 2

HF VERSION OF 128S0129128S0135

K36 GOOD

PVT

> >

>

BOM OPTION REMOVED

a

>

>>>> >

BOM OPTION REMOVED

3

PVT PVT

> >

>

BOM OPTION REMOVED

>

>>> >

>

BOM OPTION REMOVED

REFERENCE DESIGNATOR(S)

C4610,C4611,C6830,C6831

C2130,C2716,C7543

C6605

C7220,C7352,C7542

C2173,C2700

C6204,C6205,C7651,C7652,C7691,C7692

C2220

C2140

C6601,C6603

2 1

K36 K36 K36 K36

K36 K36

K36

M70 GOOD 630-7935

CONCEPT

> >

> > > >

> >> >

>

>>

TABLE_5_HEAD

TABLE_5_ITEM

SYNC_MASTER=SMC

APPLE INC.

CONFIGURATION OPTIONS

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

K36 BESTK36 BETTER

630-9106630-9105630-9104

> >

>

BOM OPTION REMOVED

ry

> >> >

>

BOM OPTION REMOVED

CRITICAL BOM OPTION

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

SYNC_DATE=07/18/2005

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

DRAWING NUMBER

SIZE

D

051-7559

SCALE

NONE

SHT

OF

D

C

B

A

REV.

H

1064

8

7 6

5

4

3

2

1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CSA PAGE 8: CSA PAGE 34:

- ALL 128S0129 BECOME 128S0135.

- REMOVE ALIASES FOR GND_CHASSIS_AUDIO_SPKRCONN,GND_CHASSIS_AUDIO_SHIELD1,GND_CHASSIS_AUDIO_SHIELD2,GND_CHASSIS_AUDIO_SHIELD3,MIC_SHIELD_LVDS_R,MIC_SHLD_CONN.

CSA PAGE 76:

- DELETE XW7620.

- PP3V3_S5_REG_P BECOMES =PP3V3_S5_REG.

- CHANGE U1400 FROM 343S0448 TO 338S0516(NB667, PRQ).

9/3/2007

- NOSTUFF R5931 AND STUFF R5930.

- NOSTUFF U5930,C5931,C5932.

CSA PAGE 59:

- STUFF R4670 AND R4671.

CSA PAGE 46:

CSA PAGE 30:

- ADD OMIT TO L9405, L9406 AND L9407.

CSA PAGE 94:

- CHANGE C7208 FROM 0.0018UF(132S400) TO 0.001UF(132S0045).

CSA PAGE 22:

- STUFF R2242 AND NOSTUFF R2247. CSA PAGE 92:

- CHANGE R9201 AND R9202 FROM 5.23K TO 2.94K.

- CHANGE R9211 AND R9212 FROM 16.5K TO 9.09K.

CSA PAGE 4:

8/9/2007

8/10/2007

- ALL 128S0115 BECOME 128S0150.

- UPDATE BOM OPTION TABLE FOR J4300.

- NORMAL CHANGES FROM 514-0359 TO 514-0456, FANCY CHANGES FROM 514-0316 TO 514-0476.

- CHANGE J4600 AND J4601 FROM 514-0288 TO 514-0457 (DIFFERENT JEDEC, SAME LANDPATTERN).

- NORMAL CHANGES FROM 514-0288 TO 514-0457, FANCY CHANGES FROM 514-0315 TO 514-0477.

- ADD PAGE_TITLE AUDIO: CODEC.

- UPDATE BOM OPTION TABLE FOR J4600 AND J4601.

- CHANGE J4300 FROM 514-0289 TO 514-0456 (SAME JEDEC).

CSA PAGE 62:

CSA PAGE 4:

7/24/2007

CSA PAGE 79: CSA PAGE 94:

- UPDATE BOM OPTION TABLE FOR J9401.

7/12/2007 CSA PAGE 43:

CSA PAGE 59:

7/17/2007

- UPDATE BOM OPTION TABLE FOR J6700.

- 4954357 ADD =PP3V3_S3_AIRPORT_AUX BACK TO PP3V3_S3 ALIAS.

- CHANGE Z0901 AND Z0906 FROM 998-1178 TO 998-1186 (NON-PLATED).

- UPDATE PN FOR FANCY RJ45 CONNECTOR, 514-0475.

- ADD R5930, 10K PU ON SMC_SMS_INT.

- ADD R5931 (WAS R5077 BEFORE), 10K PD ON SMC_SMS_INIT.

- REMOVE R5077 (BECOMES R5931).

- STUFF C3210 AND C3211.

- STUFF U5930 (DIGITAL ACCELEROMETER) CIRCUIT.

- THE PULL-UP RESISTORS SHOULD BE CONNECTED BETWEEN SMB_MGMT_CLK AND SMB_MGMT_DATA TO =I2C_SMS_SCL AND =I2C_SMS_SDA OF THE NEW ACCELEROMETER.

-ADD 2ND SMS (U5930).

- CHANGED C6210 FROM A CASE-R 10UF TANT. CAP. TO A SMA-LF 3.3UF TANT. CAP.

- MADE NO_TEST ATTRIBUTE VISIBLE FOR NET NC_VRP CONNECTED TO PIN 37 OF U6200.

- REMOVED NO STUFF RESISTORS R6730, R6731, AND R6732. ALSO REMOVED L6774.

- MADE DZ6702, DZ6703, DZ6704, DZ6705, DZ6752, DZ6753, DZ6754, DZ6755, DZ6770, DZ6771´CRITICAL.

- CHANGE R7208 FROM 8.66K TO 15.8K.

7/11/2007

CSA PAGE 67:

CSA PAGE 62:

CSA PAGE 50:

CSA PAGE 39:

CSA PAGE 67:

CSA PAGE 46:

CSA PAGE 59:

- CHANGE U4675 FROM APN 353S1505 TO APN 353S1742. (SMALL PACKAGE)

- ADD R4670 & R4671. (USB BYPASS ROUTING).

- REMOVE ALIAS FOR =SMC_SMS_INT TO SMC_PG1 - SIGNAL SHOULD JUST BE CALLED SMC_SMS_INT.

- CHANGE R5077 FROM PULL-UP TO A PULL-DOWN RESISTOR AND NAME IT SMC_SMS_INT.

- ICH8-M ME SMBUS:

CSA PAGE 59:

- ADD TWO NEW 10K PULL-UP RESISTOR (R5232 & R5233) TO =PP3V3_S3_SMBUS_SMC_MGMT.´

- THE 10K PULL-UP RESISTORS (R5230 AND R5231), AND STILL REMAIN CONNECTED TO PP3V3_S5_SMBUS_SB_ME AND STAY ON THE SB SIDE.

- SMB_ME_CLK AND SMB_ME_DATA ON SOUTHBRIDGE DISCONNECTED FROM SMB_MGMT_CLK AND SMB_MGMT_DATA FROM SMC.´

- BOOTROM PART NUMBER CHANGES FROM 341S2085 TO 341S2196.

7/10/2007

- SMC MANAGEMENT SMBUS CONNECTION:

CSA PAGE 50:

CSA PAGE 72:

- NO STUFFED R6854

CSA PAGE 68:

- STUFFED R6740.

CSA PAGE 52:

CSA PAGE 49:

CSA PAGE 46:

- ADD CRITICAL TO U4401.

CSA PAGE 44:

- ADD CRITICAL TO U2900.

CSA PAGE 8:

CSA PAGE 4:

- WAKE-ON-WIRELESS SUPPORT - RADAR: 4954357

Revision History

- 4999533 SWAP PIN 2 AND PIN 3 OF MIC CONNECTOR, BACK TO M42 PIN OUT.

- 5029811 CHANGE Q7940 FROM 376S0326 TO 376S0558.

MICROPHONE THROUGH LVDS CABLE

CSA PAGE 94:

- SYNC FROM AUDIO TEAM.

CSA PAGE 62,66,67,68:

CSA PAGE 25:

3/8/2007

CSA PAGE 25:

CSA PAGE 67:

CSA PAGE 62,66,67,68:

- NO STUFF 3G CONNECTOR CIRCUITRY

CSA PAGE 22:

- UPDATE SYMBOL FOR J4501.

CSA PAGE 79:

CSA PAGE 94:

CSA PAGE 47:

3/14/2007

CSA PAGE 77:

- ADD TEXT NOTE TO CHANGE L9404 FROM 155S0303 TO 155S0348 WHEN SYMBOL IS READY.

- DELETE LVDS_VREFH AND LVDS_VREFL TO GROUND TO FIX LVDS GLITCH.

- ADD TEXT NOTE TO UPDATE J6900 FROM 518S0287 TO 518S0526 WHEN SYMBOL IS READY.

- 4986074 CHANGE R9469 FOR CRT_TVO_IREF FROM 1.3K TO 1.21K.

- ADD TEXT NOTE TO UPDATE J4700 FROM 516S0251 TO 516S0588 WHEN SYMBOL IS READY. CSA PAGE 69:

- 4986074 CHANGE L2205 TO R2205(100OHM,5%,1/10W,0603).

- 4924443 CHANGE R2514 FROM 100K PULL-DOWN TO 10K PULL-UP TO 3.3V_S5.

CSA PAGE 45:

- 4924443 CHANGE R2514 FROM 100K PULL-UP TO 47K PULL-UP.

3/12/2007

AND REVERT REFERENCE DESIGNATORS. (CHANGE FROM TPS62510 TO LTC3412A)

C7723 FROM 2.2NF TO 10000PF, C7724 FROM 22PF TO 100PF, C7728 FROM 2.2NF TO 10000PF,

- 5048817 SYNC 1P25V REGULATOR CIRCUIT FROM M82, CHANGE R AND C TO 0402, CHANGE =PP3V3_S5_P1V25S0 TO =PP3V3_S5_1V25S0,

3/5/2007

CSA PAGE 49:

CSA PAGE 4:

- CHANGE GOOD CPU FROM 337S3471(1.8G) TO 337S3463(2.0G).

- CHANGE BETTER CPU FROM 337S3456(2.0G) TO 337S3464(2.2G).

- CHANGE BEST CPU FROM 337S3457(2.2G) TO 337S3465(2.4G).

- CHANGE NB FROM 338S0426(500M) TO 343S0448(667M). CSA PAGE 16:

- DISCONNECT GFX_VID<0> TO GND.

- CONNECT GFX_VID<0:3> TO GFX_VID0:3 ON NB.

- ADD R1600 (0OHM, 0402) TO CONNECT GFX_VID<4> TO GND. CSA PAGE 22:

- 5282756 ADD C2207 (0.1UF, 0402).

- SIZING DOWN R2205 FROM 0603 TO 0402 FOR PLACEMENT.

- CHANGE GFX_VID<1:4> TO GFX_VID<0:3>.

- CHANGE STRAPPING FROM 0010 ON GFX_VID<1:4> TO 0001 ON GFX_VID<0:3>. CSA PAGE 39:

- EDIT BOM OPTION TABLE. CSA PAGE 46:

- CHANGE U4600 FROM 353S1245 TO 353S1728.

- REMOVE MIN_NECK_WIDTH=0.3MM FROM PP5V_S3_USB2_EXTA/B.

- ADD NOSTUFF R4660 AND R4661. CSA PAGE 47:

- CHANGE J4700 FROM 516S0251 TO 516S0588. CSA PAGE 69:

- CHANGE J6900 FROM 518S0287 TO 518S0526.

- REPLACE BATTERY INTERFACE CIRCUIT WITH THE ONE ON M42B ESTAR. CSA PAGE 94:

- 5040728 CHANGE L9404 FROM 155S0303 TO 155S0348.

CSA PAGE 4:

- REPLACE ALL M70 WITH K36 (TEXT, BOM OPTIONS, 630 NUMBERS). CSA PAGE 21:

- CHANGE C2173 FROM 128S0051 TO 128S0113 PER CE. CSA PAGE 27:

CSA PAGE 28:

- CHANGE J2800 FROM 518S0487 TO 518S0519. CSA PAGE 46:

- REMOVE R4660 AND R4601 (U4675 BYPASS RESISTORS).

M70 DVT TO K36 CHANGES

6/29/2007

CSA PAGE 48: CSA PAGE 55:

- J5550 CHANGES FROM 2PIN TO 4PIN. CSA PAGE 56:

- CHANGE J5601 FROM 518S0369 TO 518S0521. CSA PAGE 67:

- CHANGE J6702 FROM 518S0487 TO 518S0519.

- CHANGE J6703 FROM 518S0369 TO 518S0521. CSA PAGE 90:

- CHANGE J9000 FROM 518S0369 TO 518S0521.

CSA PAGE 8:

- REMOVE NO_TEST=TRUE FOR CK505_PCI4_CLK_SPN, CK505_SRC1_N/P_SPN, CK505_SRC3_N/P_SPN, CK505_SRC7_N/P_SPN, CK505_SRC_CLKREQ1/3_L?SPN.

- ADD FUNC_TEST=TRUE FOR PP1V05_S0_R. CSA PAGE 9:

- REMOVE ALIAS FOR =FWPWR_PWRON.

- ADD SPN ALIASES FOR TP_CK505_SRC7_N/P.

- ADD SPN ALIASES FOR CK505_PCI2/4_CLK. CSA PAGE 12:

- REMOVE R1290 TO R1296 ON CPU_VID<0:6>. CSA PAGE 13:

- DELETE TEXT NOTE AND WITH RESET BUTTON. CSA PAGE 15:

- RENAME LVDS_VREFH/L TO TP_LVDS_VREFH/L. CSA PAGE 25:

- ADD R2597 AND R2596 FOR 10K PU ON GPIO6 AND GPIO17(EXTGPU_RST_L).

- CHANGE L2902 AND L2903 FROM 155S0302 TO 0OHM R2906 AND R2907.

- NOSTUFF C2907, C2910, C2916, C2911, C2914.

- CHANGE R2900, R2901 FROM 2.2OHM TO 0OHM.

- CHANGE R2902 FROM 1OHM TO 0OHM. CSA PAGE 44:

- REMOVE TEXT NOTE WILL CHANGE TO 606P. CSA PAGE 53:

- RE-DRAW CPU VOLTAGE SENSE RC FILTERING. CSA PAGE 62:

- ADDED A NO STUFF PULL-UP TO CODEC_DVDD AT GPIO1.

- ADDED SMALL 15PF COMPENSATION CAP. TO U6201 FEEDBACK NETWORK (C6224). CSA PAGE 67:

- CHANGED ALL TRANSIENT SUPPRESSORS TO 6.8V/100PF DEVICES (WERE ORIGINALLY 8V/100PF DEVICES).

- ADDED L6771 AND L6773 TO MIC INPUT EMI FILTER.

- REMOVED DZ6772.

- ADDED R6740 NO STUFF. CSA PAGE 68:

- CONNECTED MIC_SHLD_CONN TO GND_CHASSIS_AUDIO_MIC THROUGH R6854.

- ADDED R6856 NO STUFF. CSA PAGE 71:

- RENAME CPU_VID_R<6:0> TO CPU_VID<6:0>.

CSA PAGE 29:

- CHANGE R2514 TO 100K.

7/5/2006

- CHANGE C2700 FROM 128S0051 TO 128S0113 PER CE.

- CHANGE J4810 FROM 518S0369 TO 518S0521.

- CHANGE U5500 FROM M70 EMC1033 CIRCUIT TO M71 EMC1043 CIRCUIT.

7/6/2006

- ADD FUNC_TEST=TRUE FOR THRM_FINSTACK_P/N.

- REMOVE NO_TEST=TRUE FOR 1V8S3_COMP, 1V8S3_FSET, 3V3S5_COMP, 3V3S5_FSET, 1V05S0_COMP, 1V05S0_FSET, IMVP6_RBIAS, IMVP6_COMP, 5VS5_RUNSS, 1V5S0_RUNSS.

- CHANGE J3900 FROM 514S0143 TO 514-0443.

- CHANGE SB FROM 338S0427 TO 338S0434.

CSA PAGE 90:

CSA PAGE 9: CSA PAGE 31:

- STUFF C3110 AND C3111. CSA PAGE 32:

- UPDATE EEE CODES, Z55 FOR GOOD, Z56 FOR BETTER, Z57 FOR BEST.

- ADD ALIAS =PP3V3_S3_SMBUS_SMC_MGMT TO PP3V3_S3. CSA PAGE 29:

- SMC PART NUMBER CHANGES FROM 341S2088 TO 341S2198.

- CHANGE L7900 FROM 152S0302 TO 152S0670 FOR CORRECT AVL.

- NORMAL CHANGES FROM 514-0375 TO 514-0480, FANCY CHANGES FROM 514-0376 TO 514-0481.

- CHANGE J6700 FROM 514-0409 TO 514-0459 (DIFFERENT JEDEC, SAME LANDPATTERN).

- NORMAL CHANGES FROM 514-0408 TO 514-0458, FANCY CHANGES FROM 514-0410 TO 514-0478.

- UPDATE BOM OPTION TABLE FOR J6750.

- CHANGE J6750 FROM 514-0408 TO 514-0458 (DIFFERENT JEDEC, SAME LANDPATTERN).

- NORMAL CHANGES FROM 514-0409 TO 514-0459, FANCY CHANGES FROM 514-0411 TO 514-0479.

M70 PROTO TO EVT CHANGES

- ALL 128S0085 BECOME 128S0148.

- ALL 128S0113 BECOME 128S0160.

- CHANGE BOM STUFFING TO ENABLE ON-BOARD MICROPHONE CONNECTOR (M42/M42A SOLUTION) INSTEAD OF ROUTING

- CHANGE BOM STUFFING TO SPEED UP PORT POWER SHUT-OFF RESPONSE TIME DURING ACTIVE LATE-VG EVENT (RADAR: 4985252)

- HIGH-PRECISION 0.1% RESISTORS TO INCREASE OUTPUT VOLTAGE REGULATION (5V, 3.3V, PBUS_LDO) ACCURACY - RADAR:4972500

M70 EVT TO DVT CHANGES

- MODIFY FIREWIRE CONNECTOR SYMBOL TO SUPPORT MINI-DVI CONNECTOR WITH TAB

- MOVE SMC RESET BUTTON PAD TO TOP SIDE OF MLB - RADAR: 4920913

- CHANGE 10UF, 16V CPU VCORE CAPS TO 10UF, 6.3V CAPS - RADAR: 4952553

- FIX MOJO-CARD SMC TX, RX REVERSAL - RADAR: 4910888

- FIX LINDA CARD POWER ALIAS (NEED TO CONNECT TO PP3V42_G3HOT INSTEAD OF PP3V3_S5) - RADAR: 4927858

CSA PAGE 12: CSA PAGE 79:

8/30/2007

PER CE, ALL SANYO POSCAPS HAVE NEW HF PART NUMBERS.

- ALL 128S0057 BECOME 128S0147.

K36 EVT TO DVT1 CHANGES

CSA PAGE 34:

8/13/2007

CSA PAGE 9:

CSA PAGE 72:

CSA PAGE 46:

CSA PAGE 4:

CSA PAGE 43:

- ALL 128S0122 BECOME 128S0157.

- ALL 128S0111 BECOME 128S0169.

- ALL 128S0073 BECOME 128S0164.

- SYNC FROM AUDIO TEAM.

PROPERLY DISCHARGE ODD POWER WHEN IT’S TURNED OFF - RADAR: 4923903

- LOWER RDS(ON) MOSFET (FDC606P - APN: 376S0552) FOR ODD AND LCD POWER - RADAR: TBD

- ADD 270K PULL-DOWN RESISTOR ON HTPLG - RADAR: 4888755

- ADD ISOLATION BUFFER FOR ODD_RESET_L SIGNAL, ADD 100K PULL-DOWN TO ODD_PWR_EN_L, ADD ’DRAG’ CIRCUIT TO

- RE-CONNECTED /SHDN INPUT OF U6801 SO THAT IT’S CONTROLLED BY U6200 PORTA VREF. - DISCONNECTED GPIO1 AND TERMINATED IT WITH A 10K PULL DOWN.

9/3/2007 CSA PAGE 73:

- DELETE XW7320.

- CHANGE 2.2GHZ CPU FROM 337S3500 TO 337S3502 (2.2GHZ CPU, PRQ).

- PP5V_S5_REG_P BECOMES =PP5V_S5_REG. 9/7/2007

- UNCHECK BOM OPTIONS ITP AND LPCPLUS IN TABLE.

- ADD BOMOPTION ITP TO R3004 AND R3005.

- NOSTUFF U4675,C4675.

- DELETE XW7660.

- PP1V5_S0_REG_P BECOMES =PP1V5_S0_REG.

- ALL 128S0123 BECOME 128S0162.

- ADD BOM OPTION TABLE FOR ALL SANYO POSCAP TO USE HF PARTS.

- CHANGE BETTER AND BEST CPU TO G0 STEPPING PARTS (FROM 337S3464 TO 337S3500).

- UPDATE SYMBOL FOR U5930, VENDOR PART NUMBER CHANGES FROM SMB380 TO BMA150.

- CHANGE BEST CPU FROM 337S3465(2.4GHZ) TO 337S3464(2.2GHZ). CSA PAGE 38:

- CHANGE C3831 AND C3832 FROM 138S0582 TO 138S0554 (DON’T NEED LOW-PROFILE PARTS).

CSA PAGE 4:

7/13/2007

- NOSTUFF C0930.

- 5040728 STUFF C9421 FOR EMI.

- 4954357 MOVE C3409 AND C3410 FROM PP3V3_S3_AP_AUX RAIL TO =PP3V3_S3_AIRPORT_AUX RAIL.

- 4954357 BREAK OUT =PP3V3_S3_AIRPORT_AUX(J3400,PIN 24) FROM PP3V3_S3_AP_AUX AGAIN.

- TEST POINT MOVEMENTS REQUESTED BY ICT AND MAC-1 GROUPS - RADAR: 4924481

- CHANGE LOAD CAP STUFFING OPTION FOR RTC AND ETHERNET CRYSTALS TO MEET 5XESR (-R) REQUIREMENT

K36 DVT2 TO PVT CHANGES

- ADD ALTERNATE TABLE TO MAKE 155S0370 ALTERNATE OF 155S0348.

- ADD BOM TABLE TO CHANGE L9405, L9406 AND L9407 FROM 155S0303 TO 155S0371.

- CHANGE J3400 FROM 516S0406 TO 516S0635 TO ADD ACON AS 2ND SOURCE.

- C1235 SYMBOL CORRECTED TO REFLECT 20% TOLERANCE.

- CHANGE R7920 FROM 107S0077(EOL) TO 107S0110.

- CHANGE R7952 FROM 103S0189 TO 103S0200 FOR HF.

- ADD OMIT TO ALL ABOVE PARTS SO THE HF PARTS IN BOM TABLE TAKE OVER.

- CHANGE C7210 FROM 150PF(131S111) TO 220PF(131S2225).

- ADD ALTERNATE TABLE TO MAKE 155S0310 ALTERNATE OF 155S0322.

- ADD ALTERNATE TABLE TO MAKE 155S0369 ALTERNATE OF 155S0326.

(C2205,C4800,C4804,C7305,C7500,C7605,C7902,C7911,C7912)

CHANGE ALL 138S0578 TO 138S0614 FOR ADDITIONAL VENDORS.

K36 DVT1 TO DVT2 CHANGES

- CHANGE L7320 AND L7360 FROM 152S0432 TO 152S0685 TO ADD TDK.

- IN BOM TABLE, CHANGE PART NUMBER OF Z0903,Z0904,Z0905 AND Z0921 FROM 860-0876 TO 860-0964.

- CHANGE R7210 FROM 2.94K TO 499 OHM 1%.

- CHANGE R7208 FROM 15.8K TO 4.99K 1%.

CSA PAGE 72:

CSA PAGE 22:

- UNSTUFF R2242 AND STUFF R2247.

- CHANGE L7520 FROM 152S0432 TO 152S0685 TO ADD TDK.

CSA PAGE 75:

CSA PAGE 73:

- NOSTUFF C9401 FOR EMC (RDAR:5475926).

- CHANGE R5280 AND R5281 TO 1K (RDAR:5188703). CSA PAGE 94:

CSA PAGE 52:

10/1/2007

9/27/2007

CSA PAGE 9:

9/25/2007

9/13/2007

SYNC_DATE=N/A

SYNC_MASTER=N/A

H

106

5

H

051-7559

Preliminary

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LVDS NO_TESTS

FIREWARE NO_TESTS

NO_TEST

CLOCK NO_TESTS

NO_TEST

Power Supply NO_TESTs

Power Supply FUNC_TEST

THERMAL FUNC_TEST

SPEAKER FUNC_TEST

LPC+ Debug Connector

FUNC_TEST

Functional Test Points

Audio FUNC_TEST

NO_TEST

FUNC_TEST

NO_TEST

Battery Digital Connector

SLEEP LED FUNC_TEST

Fan Connectors

Other Func Test Points

SMBus FUNC_TEST

FIREWIRE FUNC_TEST

SMC FUNC_TEST

Battery FUNC_TEST

USB FUNC_TEST

MIC FUNC_TEST

DC-JACK FUNC_TEST

Battery charger FUNC_TEST

INVERTER CONNECTOR FUNC_TEST

FUNC_TEST

I1

I10

I11

I111 I112 I113

I114

I115

I116 I117 I118 I119

I12

I120

I122

I125

I15

I151

I152

I153 I154

I155

I156

I157 I158 I159

I16

I160 I161

I162 I163 I164

I166 I167 I168

I169

I17

I171 I172 I173

I174

I175 I176

I177

I178

I18

I180

I181

I182

I183

I186 I187 I188 I189

I19

I190 I191

I194 I195

I199

I20

I200 I201 I202 I203 I204 I205 I206 I207 I208

I209

I21

I210 I211 I212 I213 I214 I215

I219

I22

I220

I221

I222

I223

I224 I225

I226

I227

I228

I229

I23

I230

I231

I232 I233 I234 I235

I236

I237

I238

I239

I24

I240

I241

I242

I243

I244

I25

I29

I3

I31

I32

I33 I36 I38

I4

I44

I45

I46

I47

I48

I57

I58

I59

I60

I61 I63

I71 I72 I73 I74 I75 I76 I77 I78 I79 I80 I81 I82 I83 I84 I85 I86 I87 I88 I89

I9

I90

I91

I92

I93 I94

I95 I96

FUNC TEST 1 OF 2

7

H

106

051-7559

IMVP6_RBIAS

CK505_CPU1_N

TRUE

CK505_DOT96_27M_N CK505_DOT96_27M_P

TRUE

CK505_CPU2_ITP_SRC10_N

TRUE

CK505_CPU1_P

TRUE TRUE

CK505_CPU2_ITP_SRC10_P

CK505_CPU0_P

TRUE

CK505_CPU0_N

TRUE

SMC_TMS

TRUE TRUE

DEBUG_RESET_L

TRUE

SMC_TRST_L

LPC_AD<1>

TRUE

=PP5V_S0_LPCPLUS

TRUE

LPC_AD<0>

TRUE

ACZ_BITCLK

TRUE

ACZ_SDATAOUT

TRUE

MIC_HI

TRUE TRUE

MIC_LO

TRUE

MIC_SHIELD

TRUE

MIC_HI_CONN

INV_BKLIGHT_PWM_L

TRUE

PP5V_INV_F

TRUE

PPVBAT_G3H_CHGR_OUT

ACIN_ENABLE_GATE

TRUE

PPBUS_ALL_INV_CONN

USB2_3G_F_N

TRUE

USB2_BT_F_N

TRUE

USB2_BT_F_P

TRUE

TP_USB_EXTC_N

TRUE

TP_USB_EXTC_P

TRUE

TP_USB_EXCARD_N

TRUE

TP_USB_EXCARD_P

TRUE

ACZ_RST_L

USB2_3G_F_P

TRUE

INV_GND

TRUE

SYS_ONEWIRE

TRUE

LPC_AD<3>

TRUE

SMC_TCK

LVDS_B_DATA_P1_SPN

TRUE

FW_C_TPA_P_SPN

TRUE

FW_B_TPBIAS_SPN

TRUE

PP3V3_S5

TRUE

PP1V8_S3

TRUE

SMC_LID

TRUE

SPKRCONN_R_P_OUT

TRUE

SPKRCONN_L_N_OUT

TRUE

SPKRCONN_L_P_OUT

PPFW_SWITCH

TRUE

SYS_LED_ANODE

TRUE

SMBUS_SMC_B_S0_SDA

TRUE

SMBUS_SMC_B_S0_SCL

TRUE

LINDACARD_GPIO

TRUE

SMC_TDI

SMC_MD1

TRUE

SMC_TX_L

TRUE

FWH_INIT_L

TRUE TRUE

PCI_CLK33M_LPCPLUS

TRUE

LPC_AD<2>

TRUE

INT_SERIRQ

TRUE

PM_SUS_STAT_L

TRUE

SMC_RESET_L

SMC_TDO

TRUE

BOOT_LPC_SPI_L

TRUE

=PP5V_S0_FAN_RT

TRUE

FAN_RT_PWM

TRUE

FAN_RT_TACH SMC_FAN_1_CTL

TRUE

SMC_ADAPTER_EN

TRUE

SMC_BC_ACOK

TRUE

GND_BT_F

PP0V9_S0

TRUE

BATT_POS

TRUE

SMBUS_BATT_SCL_F

TRUE

SMBUS_BATT_SDA_F

BATT_NEG

TRUE

SMC_FAN_3_TACH

TRUE

LVDS_B_DATA_P2_SPN

LVDS_B_DATA_N0_SPN

TRUE

FW_C_TPB_P_SPN

TRUE

=PP3V3_S0_FAN_RT

TRUE

FW_C_TPB_N_SPN

TRUE

LVDS_B_CLK_N_SPN

TRUE

LVDS_B_DATA_N1_SPN

FW_C_TPA_N_SPN

TRUE

FW_B_TPB_P_SPN

TRUE

FW_C_TPBIAS_SPN

TRUE

LVDS_B_CLK_P_SPN

TRUE

FW_B_TPB_N_SPN

TRUE

FW_B_TPA_N_SPN

TRUE

=PP5V_S0_AUDIO

TRUE

GND_AUDIO_AMP GND_AUDIO_CODEC

TRUE

=PP5V_S0_AUDIO_AMP

SMC_BS_ALRT_L

TRUE

LVDS_B_DATA_N2_SPN

TRUE

SMC_BATT_CHG_EN

SMC_BATT_TRICKLE_EN_L

TRUE

ACZ_SYNC

TRUE

ACZ_SDATAIN<0>

TRUE

SMC_BATT_ISET

TRUE

SMC_NMI

TRUE

SMC_RX_L

=PP1V05_S0_REG

TRUE

PP18V5_G3H

=PP3V42_G3H_LPCPLUS

TRUE

SMC_FAN_1_TACH

TRUE

PM_CLKRUN_L

LPC_FRAME_L

TRUE

CK505_SRC8_N

TRUE

CK505_LVDS_P

TRUE

CK505_SRC2_P

TRUE

CK505_SRC2_N

TRUE

CK505_SRC4_N

TRUE

CK505_SRC4_P

TRUE

CK505_SRC5_N

TRUE TRUE

CK505_SRC5_P

CK505_SRC8_P

TRUE

CK505_SRC6_N

TRUE TRUE

CK505_SRC6_P

THRM_DIMM_DX_F_N

TRUE

SPKRCONN_SUB_P_OUT

TRUE

SPKRCONN_SUB_N_OUT

TRUE

MIC_SHLD_CONN

TRUE

MIC_LO_CONN

TRUE

THRM_HEATPIPE_P

TRUE

THRM_HEATPIPE_N

TRUE

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PP3V3_S3_BT_F

THRM_FINSTACK_P

TRUE

THRM_DIMM_DX_F_P

TRUE

PP5V_S3

TRUE

PP3V3_S3

TRUE

SMC_MANUAL_RST_L

SMC_CPU_VSENSE

TRUE

SPKRCONN_R_N_OUT

PP3V42_G3H

TRUE

PP1V2_ENET_S0

TRUE

PP5V_S0

TRUE

PP3V3_S0

ALL_SYS_PWRGD

TRUE

PP1V5_S0

TRUE

PP1V8_S0

TRUE

PP1V05_S0

TRUE

PPVCORE_S0_CPU PP1V05_S0_R

TRUE

THRM_FINSTACK_N

TRUE

IMVP6_COMP 5VS5_RUNSS

1V5S0_RUNSS

TRUE

CK505_LVDS_N

CK505_PCIF1_CLK

TRUE

FW_B_TPA_P_SPN

TRUE

57C4

46B6

45B3

66A6

46B4

57A8

45D5

44D5

57C7

54D8

45D5

46B6

75D3

46B6

46C6

57C8

46C4

46B4

45C5

46B4

44C5

75C3

46C4

46B4

46B6

38C6

57C3

56C4

54C8

57A2

66A4

66A3

44C5

46B6

75C3

75D3

75C3

56A6

58A3

75C3

75D3

59B7

29D6

29B6

29D6

45C5

46B6

44C8

46C6

44C8

53C7

56A6

55D3

66C2

66A6

53B7

45D5

44C8

45C5

44B5

55C2

45A3

76C3

24D5

45C5

46B6

44B8

46C4

44C8

44C5

45D7

45C5

46B6

50C4

50B4

35C7

45B6

44A8

50C4

53A7

54B8

45C5

45B6

53C7

66A8

46B4

44B8

61B8

46C6

50C4

37A5

44C8

29B6

29C6

29B6

29C6

55C2

55D3

48B1

55C2

45D1

44D8

45D2

59B7

65C5

61B5

29C6

29B6

59A4

28C4

28A4

28C4

44B5

27D1

44C1

22D4

7A7

22D4

8A5

55B3

55B1

67D2

67D3

66B5

57C3

67D3

43A4

43C2

8B2

8A5

43A4

67D2

44B8

22D4

44B5

8D5

8D1

7D1

7B4

42C3

54D1

54C1

38D3

40C5

47C5

24A7

44B5

44D1

41A8

46C5

29B3

22D4

24C8

24D5

44C3

44B5

23B5

7A7

50B3

50C3

44A8

33C7

44C5

43C2

7D7

57B5

57A5

44A4

8D5

8D1

7C4

8D1

8D5

8D1

8D5

8D1

7A7

8A4

8B4

7A7

44C5

8D5

44C8

8A5

44B5

44C1

41A8

7D8

7B1

44A8

24C8

22D4

28A4

28B4

28A4

28B4

49B6

54B1

55A1

55B1

49D6

7C1

7B1

43D2

49C6

49B6

7A4

45D8

44C5

54C1

7C1

7B5

7A7

7D4

27A5

7C7

7B7

7D7

49C6

59A4

63B5

58B1

28B4

28B6

8D1

Preliminary

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"S3" RAILS

(CPU VCOR PWRE)

(REGULATOR OUTPUT CPU VCORE PWR)

(DDR2 TERMINATION 0.9V PWR)

(REGULATOR OUTPUT CPU 0.90V PWR)

"S0,S0M" RAILS

"S5" RAILS

"G3H" RAILS

8

H

SYNC_MASTER=WFERRY

Power Aliases

SYNC_DATE=06/15/2006

106

051-7559

PP3V3_S3

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

=PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_ENET_P3V3ENETFET

=PPVCORE_S0_NB_GFX

=PP5V_S0_3G =PP5V_S0_LPCPLUS =PP5V_S0_ISENSECAL =PP5V_S0_FAN_RT =PP5V_S0_AUDIO =PP5V_S0_AUDIO_AMP

=PP5V_S0_CPU_IMVP

=PP5V_S0_SB

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S0

VOLTAGE=5V

=PP5V_S0_NB_GFX_IMVP

=PP5V_S0_LCD =PP5V_S0_TMDS =PP5V_S0_NB_TVDAC

=PP5V_S0_SATA

MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PPVCORE_S0_NB_GFX

VOLTAGE=1.25V

=PP1V8_S0_NB_DPLL

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4 mm

PP1V8_S0

MAKE_BASE=TRUE

=PP1V5_S0_NB_FOLLOW

=PP1V5_S0_AIRPORT

=PP1V5_S0_SB_VCCUSBPLL

=PP1V5_S0_SB_VCC1_5_A

=PP1V5_S0_SB_VCC1_5_A_ARX

=PP1V5_S0_SB

=PP1V5_S0_NB_TVDAC

=PP1V5_S0_CPU

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V5_S0

VOLTAGE=1.5V

=PP1V25_S0_FET

=PP1V25_S0_NB_VCCA

=PP1V25_S0_NB_VCC

=PP1V25_S0_NB_PLL

=PP1V25_S0_NB_VCCAXF

=PP1V25_S0_NB_VCCDMI

=PP1V25_S0_NB_PLL

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 mm

PP1V25_S0

MAKE_BASE=TRUE

=PP1V05_S0M_NB_VCCAXM

=PP1V25R1V05_S0_NB_VTT

=PP1V25R1V05_S0_FSB_NB

=PPVCORE_S0_NB

=PP1V05_S0_NB_PCIE

PP1V05_S0_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE

=PPVCORE_S0_SB

PP1V05_S0

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

=PP0V9_S3M_MEM_TERM

=PP3V3_S0_SB_VCC3_3_IDE =PP3V3_S0_SB_VCC3_3_VCCPCORE

PP3V3_S5

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

=PP3V3_S5_FET

=PP3V3_S5_SB

=PP3V3_S5_SB_GPIO

=PP3V3_S5_SB_USB

=PP3V3_S5_SB_PM

=PP3V3_S5_SB_VCCSUS3_3_USB =PP3V3_S5_SB_VCCSUS3_3 =PP3V3_S5_SB_3V3_VCCSUSHDA =PP3V3_S5_FWLATEVG

=PP3V3_S5_SMBUS_SB_ME =PP3V3_S5_ROM =PP3V3_S5_LCD

=PP3V3_S5_1V25S0 =PP3V3_S5_AIRPORT_AUX

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S5

VOLTAGE=5V

=PP5V_S5_SB

=PP5V_S5_USB

=PP5V_S5_PWRCTL =PP5V_S5_FET

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=3.42V

=PP3V42_G3H_SMC

=PP3V42_G3H_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_ACIN =PP3V42_G3H_LIDSWITCH =PP3V42_G3H_PWRCTL =PP3V42_G3H_SB_RTC =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_LPCPLUS

PP18V5_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM

MAKE_BASE=TRUE

VOLTAGE=18.5V

=PP18V5_G3H_CHGR

MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V MAKE_BASE=TRUE

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 mm

=PPVIN_G3H_P3V42G3H

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

=PPDCIN_G3H

=PPBUSA_G3H

=PP5V_S5_PATA

=PP5V_S5_1V8S30V9S0

=PP3V3_S0_AIRPORT

=PP3V3_S0_SB

=PP3V3_S5_REG

=PP3V3_S0_THRM_SNR

=PP18V5_G3H_INRUSH

=PP3V3_S5_SB_CLINK1

=PP3V3_S0_NB

=PP3V3_S0MWOL_SB_CLINK0

=PPSPD_S0_MEM

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.2V

MAKE_BASE=TRUE

PP1V2_ENET_S0

MIN_NECK_WIDTH=0.2 mm

=PP1V2_ENET_PHY

=PP1V5_S0_SB_VCC1_5_A_ATX

=PP3V3_S0_PBATTISENS

=PPBUS_S5_FWPWRSW

=PP5V_S5_1V51V05S0

=PP3V3_S0_NB_FOLLOW =PP3V3_S0_SB_GPIO

=PP3V3_S0_SB_VCC3_3_PCI

=PP3V3_S0_SB_PM =PP3V3_S0_RSTBUF

=PP3V3_S0_SMC_LS

=PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SB

=PP3V3_S0_LCD

=PPVIN_S5_IMVP

=PPVIN_S5_1V5S0 =PPVIN_S5_1V05S0

=PPVIN_S5_5VS5 =PPVIN_S5_3V3S5

=PPVIN_S5_1V8S30V9S0

=PPBUS_S5_INV

=PP3V3_S0_PATA

=PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_FW

=PP3V3_S0_SB_VCC3_3_DMI

MIN_NECK_WIDTH=0.3 MM

MIN_LINE_WIDTH=0.3 mm

MAKE_BASE=TRUE

VOLTAGE=0.9V

PPVCORE_S0_CPU

=PPVORE_S0_CPU_REG

=PP0V9_S0_REG

=PPVCORE_S0_CPU

=PPVIN_S5_NB_GFX_IMVP

=PPVIN_S5_CPU_IMVP

=PPVCORE_S0_NB_GFX_IMVP

=PP1V8_S0_TMDS

=PP1V8_S0_FET

=PP1V5_S0_REG

=PP5V_S3_IR

=PP5V_S3_GEYSER

=PP5V_S3_SYSLED

=PP3V42_G3H_REG

=PP5V_S5_REG

=PP5V_S3_CAMERA

=PP1V25_S0_REG

=PP5V_S0_FET

=PP1V05_S0_REG

=PP1V05_S0_REG_R

=PP3V3_S0_SB_VCCGLAN3_3

=PP3V3_S0_PDCISENS

=PP3V3_S0_CPUPOWER

VOLTAGE=2.5V

MIN_LINE_WIDTH=0.6 mm

PP1V9_ENET_S0

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

=PPBUSB_G3H

=PP3V3_S0MWOL_SB_VCCLAN3_3

=PPVIN_S0_NB_DPLL

=PP3V3_S0MWOL_SB_VCCCL3_3

=PP3V3_S0_FET

=PP3V3_S0_NB_VCCHV

=PP3V3_S0_SB_VCC3_3_SATA

=PP5V_S3_FET

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

=PP3V3_S0_SB_PCI

=PP3V3_S0_TMDS

=PP3V3_S0_AUDIO

=PP3V3_S0_FAN_RT =PP3V3_S0_ENET

=PP3V3_S0_IMVP

=PP3V3_S0_NB_GFX_IMVP

=PP1V8_S0_YUKON

=PP1V8R2V5_ENET_PHY

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_ENET_FET

=PP1V8_S0_NB_LVDS

=PP5V_S0_IDE_RESET

=PP3V3R1V5_S0_SB_VCCHDA

=PP3V3_S0_NB_VCCA_PEG_BG

=PP3V3_S0_CK505 =PP3V3_S0_NB_VCCSYNC

=PP3V3_S0_TMDS

=PP1V9_ENET_REG

=PP1V8_S3_MEMVREF

=PP1V8_S3_FET

=PP1V8_S3_MEM

=PP1V8_S3M_MEM_NB

=PP1V8_S3_REG

=PP1V8_S3_NB_VCC

=PP3V3_S3_PDCISENS

=PP3V3_S3_SMBUS_SMC_A_S3

PP1V8_S3_MEM_NB

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=1.8V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

PP5V_S3

=PP3V3_S3_ENETPWRCTL

=PP3V3_S3_FET

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

PP0V9_S0

VOLTAGE=0.9V

=PP1V05_S0_SB_CPU_IO

=PP1V05_S0_CPU

=PP1V25_S0_SB_DMI

=PP1V2_ENET_REG

=PP3V3_ENET_PHY

=PP1V8_S3_REG_R

=PP3V3_S3_AIRPORT_AUX =PP3V3_S3_FW =PP3V3_S3_PCI =PP3V3_S3_BT =PP3V3_S3_SMS

=PP1V8_ENET_P1V8ENETFET

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V8_S3

69C8

69C2

12C5

69B7

12B3

58D3

68D8

31D6

11A3

51B8

48B5

58C4

21B7

68C8

29D2

68C8

31D4

31D2

10C7

48B3

54D8

20D8

35C7

65B5

45D8

66B8

24D8

48B3

59D8

58C3

20A8

68B7

56B5

29B2

68B7

31B2

30D2

9D5

21C5

56C4

54C8

26D6

20D3

20D8

29C6

20B4

26C6

65C4

26D8

26D2

33D7

58D5

45D4

66A8

31A7

24B3

67C6

11D7

59D4

66C3

58B8

18B3

68B2

55D8

28D8

68B2

30D6

20C8

26C4

9C5

51B6

17D5

46C6

50C4

53A7

54B8

26B6

26C2

26D5

26C8

11B3

20B4

20A8

20B4

17C1

20C8

29B6

17D7

26D2

45D2

26B4

26A6

65A5

24A8

26D2

26B6

26B2

38A8

33D6

58C6

45C1

66A5

46C6

39C8

49D2

31A3

26C6

22D7

26B4

27B8

67B7

63B6

26A8

10D7

59C2

58C4

62C5

45A4

58D4

61B8

61C5

26D3

26B2

58B3

15C7

26B8

26C2

45D1

68B1

53D7

50C4

26C4

20A6

28D3

21B5

68B1

35D1

20A6

30D4

17D7

62C2

65C3

25C3

9B6

26A6

6A2

47C3

35D3

17B7

43B5

6D2

48B8

6D2

6D1

59D8

26D8

6A2

60D2

67D7

69D7

21D6

40C6

21A7

6B2

21D5

33D2

25A6

25B6

26A8

21D8

10B7

6B2

58A3

20B8

20A8

7C7

20D4

18C3

7C7

17B3

18D3

13B7

17D3

20D5

6B2

25D3

6B2

32D4

25C3

6A2

58C5

24A3

24D8

23C8

27C5

25A3

25B3

38A6

47A7

52C6

67C7

64B6

33C7

6A2

26D8

41C8

65B6

58B3

6A2

44D4

45C8

47C3

57C4

57A8

65C7

27D7

41A6

6D2

6A2

66D8

64C6

6A2

57D3

66C2

39D6

62C5

33C6

26D8

63B1

49C2

57D1

24B1

69C8

24C1

30A7

6A2

34D6

25B6

66B3

38D5

61C4

20B2

22D2

25B3

27B6

27D4

45D4

46C4

47D8

67B5

45A6

61B3

61B5

63A6

63B3

62B3

67D4

39C2

47D5

47C5

38C6

25C3

6B2

59D1

62B8

10B5

60C2

48D7

60C2

68D6

58B8

61B1

43D8

42D6

40B6

64C4

63B8

67A5

64B2

58C8

6B2

61C7

25A6

60C2

48D2

66C2

25A3

25A6

58A3

15B7

25C3

65B4

25B6

6A2

23A3

7C4

53A7

6D2

8A4

59D8

60C7

36D8

34C7

35D4

21C5

39B7

25B3

18C6

28C8

18D6

7C4

35B2

20A5

58C5

30B2

15D2

62B2

20A4

62A2

47D3

6A2

35D7

65A4

6A2

22D2

9B5

25C3

35C1

34D6

62C4

33C2

37D5

37C5

43D3

51C7

35C3

6A2

Preliminary

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

AIRPORT CARD STANDOFF SCREW HOLE

FOR LAYOUT PLACEMENT BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL

CPU HEATSINK STANDOFF SCREW HOLE

Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL

NB CFG ALIASES

DCIN CONNECTOR CHASSIS GND

NO-CONNECT UNUSED LVDS INTERFACE PORTS

(EMI PAD FOR INVERTER GONNECTOR)

DIP DIMM CONNECTOR CHASSIS GND

USB PORT [0] = External USB2.0 Port A

USB PORT [1] = PCI-E Mini Card

USB PORT [2] = 3G USB

USB PORT [3] = CAMERA

USB PORT [4] = IR CONTROLLER

USB PORT [5] = Trackpad(Geyser)

USB PORT [6] = BLUETOOTH

NO-CONNECT UNUSED FIREWIRE INTERFACE PORTS

ANALOG SWITCH GPIO

NB ALIASES

USB PORT [9] = Unused

USB PORT [8] = Unused

USB PORT [7] = External USB2.0 Port B

SO-DIMM ALIASES

PCI_EXP ALIASES

SATA ALIASES

NO-CONNECT UNUSED SATA INTERFACE PORTS

NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS

NO-CONNECT UNUSED SDVO INTERFACE PORTS

NO-CONNECT UNUSED ADDRESS INTERFACE PORTS

FIREWIRE ALIASES

DIP DIMM CONNECTOR CHASSIS GND

NC NC

I/O CONNECTOR CHASSIS GND

PCI_EXPRESS GRAPHICS ALIASES

Ethernet ALIASES

SATA,LVDS CONNECTOR CHASSIS GND

LVDS ALIASES

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

CLOCK ALIASES

NO-CONNECT UNUSED CLOCK INTERFACE PORTS

SB ALIASES

BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND

CHASSIS GND

Z0906

OMIT

5R2P3-7SQBNP

1

OMIT

7X7R2P3-5B

1

Z0902

402

CERM

16V

10%

0.01UF

2

1

C0908

0.1UF

402

10% 16V X5R

2

1

C0907

Z0901

OMIT

5R2P3-7SQBNP

1

OMIT

5R2P3-7SQB

1

Z0909

5R2P3-7B

OMIT

1

Z0911

5R2P3-7SQB

OMIT

1

Z0910

402

MF-LF

1/16W

0

5%

2

1

R0912

STDOFF-4.2OD3.95H-5.52R3.37-6B

OMIT

1

Z0913

STDOFF-4.2OD2.15H-1.2-3.2-TH

OMIT

1

Z0912

5P0R2P3-7BLB

OMIT

1

Z0908

CLIP-SM-M42

EMI-SPRING

1

ZS0920

STDOFF-4.2OD3.95H-5.52R3.37-7SQB

OMIT

1

Z0904

STDOFF-4.5OD3.95H-1.1-3.2-TH

OMIT

1

Z0921

6P5R2P6-7SQB

OMIT

1

Z0907

STDOFF-4.2OD3.95H-5.52R3.37-6B

OMIT

1

Z0903

NOSTUFF

402

16V

10% X5R

0.1UF

2

1

C0930

0.1UF

10% 402

X5R

16V

2

1

C0910

0.01UF

10% 16V CERM 402

2

1

C0911

X5R

0.1UF

10% 16V

402

2

1

C0916

CERM 402

16V

10%

0.01UF

2

1

C0917

X5R

0.1UF

402

10% 16V

2

1

C0914

CERM

16V

0.01UF

402

10%

2

1

C0915

402

16V

10%

0.1UF

X5R

2

1

C0912

16V CERM

0.01UF

10% 402

2

1

C0913

0.1UF

16V X5R

10% 402

2

1

C0918

402

CERM

16V

10%

0.01UF

2

1

C0919

0

402

1/16W

5% MF-LF

2

1

R0910

0

5% 402

MF-LF

1/16W

2

1

R0921

STDOFF-4.5OD3.95H-1.1-3.2-TH

OMIT

1

Z0905

402

MF-LF

5%

0

1/16W

2

1

R0911

SM

21

XW0802

SM

21

XW0801

SYNC_MASTER=GPU

SIGNAL ALIAS /RESET

9

H

106

SYNC_DATE=07/17/2006

051-7559

STANDOFF W/THRU HOLES,WIRELESS

Z0913

STANDOFF

1

860-0749

STANDOFF WIRELESS

Z0912

STANDOFF

1

860-0723

THERMAL STANDOFF

STANDOFF

4

Z0903,Z0904,Z0905,Z0921

860-0964

=GND_CHASSIS_DIPDIMM_RIGHT

=ENET_CLKREQ_L

ENET_CLKREQ_L

MAKE_BASE=TRUE

TP_PCIE_B_R2D_C_N TP_PCIE_B_R2D_C_P TP_PCIE_EXCARD_D2R_N

PEG_D2R_N11_SPN

MAKE_BASE=TRUE

PEG_D2R_N12_SPN

MAKE_BASE=TRUE

PEG_D2R_P3_SPN

MAKE_BASE=TRUE

TP_CK505_SRC3_P

MAKE_BASE=TRUE

CK505_SRC3_P_SPN

TP_CK505_SRC7_N

CK505_PCI4_CLK

TP_CK505_SRC7_P CK505_PCI2_CLK

CK505_SRC7_N_SPN

MAKE_BASE=TRUE

CK505_PCI2_CLK_SPN

MAKE_BASE=TRUE

CK505_SRC7_P_SPN

MAKE_BASE=TRUE

CK505_PCI4_CLK_SPN

MAKE_BASE=TRUE

CK505_SRC1_P_SPN

MAKE_BASE=TRUE

CK505_SRC3_N_SPN

CK505_SRC1_N_SPN

MAKE_BASE=TRUE

TP_CK505_SRC3_N

TP_CK505_SRC1_P

TP_CK505_SRC1_N

EXTGPU_RST_L TP_SB_GPIO17

MAKE_BASE=TRUE

SB_SATA_CLKREQ_L

SB_CLK100M_SATA_OE_L

MAKE_BASE=TRUE

VR_PWRGD_CLKEN VR_PWRGD_CK505

MAKE_BASE=TRUE

=SB_CLINK_MPWROK CLINK_MPWROK

MAKE_BASE=TRUE

PCIE_B_D2R_P_SPN

MAKE_BASE=TRUE

PCIE_B_R2D_C_N_SPN

MAKE_BASE=TRUE

PCIE_C_R2D_C_N_SPN

MAKE_BASE=TRUE

TP_PCIE_FW_D2R_N

TP_PCIE_FW_R2D_C_N

PEG_D2R_N10_SPN

MAKE_BASE=TRUE

PEG_D2R_N9_SPN

MAKE_BASE=TRUE

PEG_D2R_N13_SPN

TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_EXCARD_R2D_C_N

TP_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

PCIE_C_R2D_C_P_SPN PCIE_D_D2R_N_SPN

MAKE_BASE=TRUE

PCIE_D_D2R_P_SPN

MAKE_BASE=TRUE

PEG_D2R_P15_SPN

MAKE_BASE=TRUE

PEG_D2R_P7_SPN

MAKE_BASE=TRUE

MEM_B_A<15>

GND_AUDIO_CODEC

MAKE_BASE=TRUE

GND_AUDIO_AMP

MAKE_BASE=TRUE

=ENET_VMAIN_AVLBL

TP_MEM_CLKP2

TP_MEM_CLKN2

VOLTAGE=0V

INVT_CHGND

MAKE_BASE=TRUE

PEG_D2R_N<2> PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5>

MAKE_BASE=TRUE

PEG_D2R_N5_SPN

MAKE_BASE=TRUE

PEG_D2R_N4_SPN

LVDS_A_DATA_P3_SPN

MAKE_BASE=TRUE

LVDS_B_DATA_P2_SPN

MAKE_BASE=TRUE

LVDS_B_DATA_P3_SPN

MAKE_BASE=TRUE

=NB_TDB_SENSE

USB_EXTB_P

FW_B_TPB_P_SPN

MAKE_BASE=TRUE

CPU_THERMAL_SCREW_RIGHT

TP_LVDS_A_DATAN3

TP_MEM_CLKP5

MEM_A_A<15>

=GND_AUDIO_CODEC

ACZ_SDATAOUT

MAKE_BASE=TRUE

ACZ_SDATAIN<0>

MAKE_BASE=TRUE

ACZ_RST_L

MAKE_BASE=TRUE

PEG_D2R_N7_SPN

MAKE_BASE=TRUE

GND_CHASSIS_IO1

VOLTAGE=0V

GND_CHASSIS_SATA

VOLTAGE=0V MAKE_BASE=TRUE

LVDS_B_DATA_P<2>

TP_NB_CFG<8>

MAKE_BASE=TRUE

TP_NB_CFG<7>

MAKE_BASE=TRUE

TP_NB_CFG<6>

MAKE_BASE=TRUE

TP_NB_CFG<4>

MAKE_BASE=TRUE

PEG_R2D_C_P15_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P14_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P13_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P12_SPN

TP_USB_EXTC_P

MAKE_BASE=TRUE

HDA_BIT_CLK HDA_SYNC

TP_HDA_SDIN1

TP_PCIE_FW_D2R_P

SATA_C_R2D_C_N SATA_C_R2D_C_P

MAKE_BASE=TRUE

PCIE_A_D2R_P_SPN PCIE_A_R2D_C_N_SPN

MAKE_BASE=TRUE

PCIE_A_R2D_C_P_SPN

MAKE_BASE=TRUE

PCIE_B_D2R_N_SPN

SATA_C_D2R_N

MAKE_BASE=TRUE

PEG_D2R_N3_SPN

PEG_D2R_N6_SPN

MAKE_BASE=TRUE

PEG_D2R_P2_SPN

MAKE_BASE=TRUE

PEG_D2R_P9_SPN

PEG_R2D_C_N12_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N11_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N10_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P10_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P11_SPN

PEG_R2D_C_P<14>

PEG_R2D_C_P<13>

PEG_R2D_C_P<12>

PEG_R2D_C_P<11>

PEG_R2D_C_P<10>

PEG_R2D_C_P<9>

PEG_R2D_C_P<8>

PEG_R2D_C_P<6>

PEG_R2D_C_P<5>

PEG_R2D_C_P<4>

PEG_R2D_C_N<15>

PEG_R2D_C_N<14>

PEG_R2D_C_N<13>

PEG_R2D_C_N<9>

PEG_R2D_C_N<5>

PEG_R2D_C_N<4>

PEG_D2R_P<14>

PEG_D2R_P<13>

PEG_D2R_P<12>

PEG_D2R_P<11>

PEG_D2R_P<10>

PEG_D2R_P<3>

PEG_D2R_P<2>

PEG_D2R_N<14>

PEG_D2R_N<12>

PEG_D2R_N<11>

PEG_D2R_N<10>

PEG_D2R_N<9>

PEG_D2R_N<8>

PEG_D2R_N<7>

LVDS_B_DATA_P<1>

LVDS_B_DATA_P<0>

TP_LVDS_B_DATAN3

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

MAKE_BASE=TRUE

LVDS_B_DATA_N1_SPN

LVDS_B_DATA_P1_SPN

MAKE_BASE=TRUE

LVDS_B_CLK_P LVDS_B_DATA_N<0>

LVDS_B_DATA_N3_SPN

MAKE_BASE=TRUE

LVDS_B_CLK_N_SPN

LVDS_B_CLK_N

MAKE_BASE=TRUE

PEG_D2R_N8_SPN

MAKE_BASE=TRUE

PEG_D2R_P6_SPN

TP_LVDS_A_DATAP3

=USB2_GEYSER_N

=USB2_CAMERA_N

VOLTAGE=0V

GND_CHASSIS_IO

MAKE_BASE=TRUE

PEG_D2R_P8_SPN

USB_EXCARD_N

=USB2_IR_N

USB_EXTB_N=USB2_EXTB_N

PEG_D2R_N<0>

VOLTAGE=0V MAKE_BASE=TRUE

GND_CHASSIS_CENTER

CPU_THERMAL_SCREW_DOWN

PEG_R2D_C_N14_SPN

MAKE_BASE=TRUE

NB_RIGHT_DOWN_SCREW

TP_PCIE_A_D2R_P

=USB2_GEYSER_P

=USB2_BT_P

=USB2_EXTB_P

=EXTBUSB_OC_L

GND_CHASSIS_RIGHT

VOLTAGE=0V MAKE_BASE=TRUE

=USB2_CAMERA_P

USB_CAMERA_N

USB_CAMERA_P

=USB2_3G_N

MAKE_BASE=TRUE

USB2_3G_N

USB_EXTD_P

USB_EXTD_N

=USB2_AIRPORT_N

=USB2_AIRPORT_P

USB2_AIRPORT_P

MAKE_BASE=TRUE

USB_MINI_N

USB_MINI_P

=EXTAUSB_OC_L

=USB2_EXTA_P

USB2_EXTA_P

MAKE_BASE=TRUE

USB2_EXTA_N

MAKE_BASE=TRUE

USB_EXTA_OC_L

USB_EXTB_OC_L

USB_EXCARD_P

USB_BT_N

USB_BT_P

USB_IR_N

USB_IR_P

USB_TPAD_N

USB_TPAD_P

=GND_DCIN_CHGND

GND_CHASSIS_FANSCREW

=GND_CHASSIS_DIPDIMM_CENTER

PEG_D2R_P<15>

MAKE_BASE=TRUE

PEG_D2R_P0_SPN

FW_B_TPA_N

FW_B_TPBIAS

FW_B_TPB_P

FW_C_TPBIAS

FW_B_TPB_N

FW_B_TPA_N_SPN

MAKE_BASE=TRUE

FW_C_TPBIAS_SPN

MAKE_BASE=TRUE

FW_C_TPA_P_SPN

MAKE_BASE=TRUE

FW_C_TPA_N_SPN

MAKE_BASE=TRUE

FW_C_TPB_P_SPN FW_C_TPB_N_SPN

MAKE_BASE=TRUE

GND_CHASSIS_CPU

FW_C_TPB_P

FW_C_TPA_N

FW_C_TPA_P

FW_B_TPB_N_SPN

MAKE_BASE=TRUE

FW_B_TPA_P_SPN

MAKE_BASE=TRUE

FW_B_TPBIAS_SPN

PEG_D2R_N15_SPN

MAKE_BASE=TRUE

PEG_D2R_P<6>

MAKE_BASE=TRUE

PEG_D2R_P4_SPN

FW_C_TPB_N

LVDS_B_DATA_P0_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P<7>

MAKE_BASE=TRUE

PEG_D2R_N2_SPN

PEG_D2R_N0_SPN

MAKE_BASE=TRUE

SATA_B_D2R_N

SATA_B_D2R_P_SPN

MAKE_BASE=TRUE

SATA_B_D2R_P

MAKE_BASE=TRUE

SATA_B_R2D_C_P_SPN

SATA_B_R2D_C_P

MAKE_BASE=TRUE

SATA_B_R2D_C_N_SPN

MAKE_BASE=TRUE

SATA_C_D2R_P_SPN

TP_PCIE_A_R2D_C_N

PCIE_C_D2R_N_SPN

MAKE_BASE=TRUE

PCIE_B_R2D_C_P_SPN

MAKE_BASE=TRUE

TP_PCIE_B_D2R_N

PCIE_C_D2R_P_SPN

MAKE_BASE=TRUE

PCIE_D_R2D_C_N_SPN

MAKE_BASE=TRUE

PCIE_D_R2D_C_P_SPN

MAKE_BASE=TRUE

PEG_D2R_N14_SPN

MAKE_BASE=TRUE

PEG_D2R_P5_SPN

MAKE_BASE=TRUE

TP_PCIE_FW_R2D_C_P

TP_PCIE_B_D2R_P

TP_PCIE_A_R2D_C_P

MAKE_BASE=TRUE

PEG_D2R_P11_SPN

MAKE_BASE=TRUE

PEG_D2R_P12_SPN PEG_D2R_P13_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N7_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N9_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P6_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P5_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N13_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N<12>

PEG_R2D_C_N<11>

PEG_R2D_C_N<10>

PEG_R2D_C_N<8>

PEG_R2D_C_N<7>

PEG_R2D_C_N<6>

MAKE_BASE=TRUE

PEG_R2D_C_N5_SPN

MAKE_BASE=TRUE

PEG_D2R_P14_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N4_SPN

PEG_R2D_C_N6_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N8_SPN

MAKE_BASE=TRUE

PEG_R2D_C_N15_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P4_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P9_SPN

PEG_R2D_C_P8_SPN

MAKE_BASE=TRUE

PEG_R2D_C_P7_SPN

MAKE_BASE=TRUE

HDA_SDIN0

HDA_RST_L

PEG_R2D_C_P<15>

HDA_SDOUT

USB_EXTC_N

USB_EXTC_P

MAKE_BASE=TRUE

MEM_CLK_P_2_SPN

=GND_AUDIO_AMP

MAKE_BASE=TRUE

LVDS_B_DATA_N2_SPN

LVDS_A_DATA_N3_SPN

MAKE_BASE=TRUE

DIMM_OVERTEMPB_L

DIMM_OVERTEMPA_L

=NB_CLINK_MPWROK

TP_PCIE_A_D2R_N

PCIE_A_D2R_N_SPN

MAKE_BASE=TRUE

SATA_C_R2D_C_N_SPN

SATA_B_D2R_N_SPN

MAKE_BASE=TRUE

=USB2_BT_N

MAKE_BASE=TRUE

USB2_EXTB_P

MAKE_BASE=TRUE

USB2_EXTB_N

MAKE_BASE=TRUE

EXTBUSB_OC_L

TP_USB_EXCARD_N

MAKE_BASE=TRUE

TP_USB_EXCARD_P

MAKE_BASE=TRUE

SATA_C_D2R_P

SATA_B_R2D_C_N

MAKE_BASE=TRUE

MEM_B_A15_SPN

MAKE_BASE=TRUE

MEM_CLK_N_2_SPN

MAKE_BASE=TRUE

PM_EXTTS_L<0>

MAKE_BASE=TRUE

GFX_VR_EN

MAKE_BASE=TRUE

CLINK_MPWROK

MAKE_BASE=TRUE

NB_CLK96M_DOT_P NB_CLK96M_DOT_N

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_P

MAKE_BASE=TRUE

NB_CLK100M_DPLLSS_N

MAKE_BASE=TRUE

=NB_CLK96M_DOT_N

=NB_TDE_FORCE

=NB_CLK100M_DPLLSS_N

=NB_CLK100M_DPLLSS_P

TP_LVDS_B_DATAP3

PEG_D2R_N<6>

PEG_D2R_N<13>

PEG_D2R_N<15> PEG_D2R_P<0>

PEG_D2R_P<4> PEG_D2R_P<5>

PEG_D2R_P<7> PEG_D2R_P<8> PEG_D2R_P<9>

PEG_D2R_P10_SPN

MAKE_BASE=TRUE

MEM_CLK_N_5_SPN

TP_MEM_CLKN5

=USB2_EXTA_N

TP_USB_EXTC_N

MAKE_BASE=TRUE

PM_EXTTS_L<1>

MAKE_BASE=TRUE

=GFX_VR_EN

=NB_CLK96M_DOT_P

=NB_TDE_SENSE

=NB_TDB_FORCE

MAKE_BASE=TRUE

MEM_A_A15_SPN

MAKE_BASE=TRUE

ACZ_BITCLK ACZ_SYNC

MAKE_BASE=TRUE

TP_NB_CFG<3>

MAKE_BASE=TRUE

=GND_CHASSIS_FW_UPPER

=GND_CHASSIS_TMDS_DOWN

NB_CFG<8>

NB_CFG<7>

NB_CFG<6>

NB_CFG<4>

NB_CFG<3>

TP_HDA_SDIN3

HDN_SDIN1_SPN

MAKE_BASE=TRUE

HDN_SPIN2_SPN

MAKE_BASE=TRUE

HDN_SPIN3_SPN

MAKE_BASE=TRUE

=YUKON_EC_PP2V5_ENET

MAKE_BASE=TRUE

MEM_CLK_P_5_SPN

=USB2_IR_P

MAKE_BASE=TRUE

USB_BT_N

MAKE_BASE=TRUE

USB_BT_P

USB2_GEYSER_N

MAKE_BASE=TRUE

USB2_GEYSER_P

MAKE_BASE=TRUE

USB_IR_N

MAKE_BASE=TRUE

USB_IR_P

MAKE_BASE=TRUE

USB2_CAMERA_N

MAKE_BASE=TRUE

USB2_CAMERA_P

MAKE_BASE=TRUE

USB2_AIRPORT_N

EXTAUSB_OC_L

MAKE_BASE=TRUE

=USB2_3G_P

USB2_3G_P

MAKE_BASE=TRUE

USB_EXTA_N

USB_EXTA_P

=GND_CHASSIS_USB

=GND_CHASSIS_FW_DOWN

MAKE_BASE=TRUE

LVDS_B_DATA_N0_SPN

LVDS_B_CLK_P_SPN

MAKE_BASE=TRUE

=GND_CHASSIS_3GPOWER

=GND_CHASSIS_LVDS

VOLTAGE=0V MAKE_BASE=TRUE

GND_CHASSIS_DCIN

=GND_CHASSIS_RJ45 =GND_CHASSIS_TMDS_UPPER

CPU_THERMAL_SCREW_UP

TP_HDA_SDIN2

FW_B_TPA_P

MAKE_BASE=TRUE

SATA_C_D2R_N_SPN

MAKE_BASE=TRUE

SATA_C_R2D_C_P_SPN

GND_CHASSIS_IO

=GND_BATT_CHGND =GND_CHASSIS_AUDIO_JACK

=GND_CHASSIS_AUDIO_MIC

=GND_CHASSIS_DIPDIMM_LEFT

=PP3V3_S0_ENET

56C4 56B8 56B5

56B4 56B1 56A8 56A4 55B3

54C8 54B8 54A8

54C8

73B3

41C4

67B2

53D3

73B3

54B8

23C2

41C2

67A6

34B8

75D3

24C5

27A6

73B3

53B7

53C7

53B7

73C3

73B3

23C2

73B3

31A5

73C3

73B3

54A8

44B8

27A6

75B3

75B3 75B3

44B8

53C7

8C1

73B3

41A4

43B5

67A4

69C4

31D4

28A4

23D5

28B4

28B6

28B4

28B6

28B4

24B5

24C5 28B4

24C5 27A8

24C3

8B1

23D5

31C4

6D1

34C2

15C6

67C2

14D3

6A7

19C2

23C2

6B7

15C6

30C4

53A7

6D1

6C1

40C8

14C5

6C1

22C8

23D5

22B6

14A3

14B3

14C3

14D3

14C5

15C6

14C5

6A7

14C5

6A7

14C5

15C6

42C7

67A4

8D7

23C2

43C4

23C2 41B5

14D3

23D5

42C7

43C3

41B5

41C8

67B4

23C2

43A4

23C2

33B3

23C2

41C8

41A8

23C8

23C2

8B2

8C2

23C2

57C8

30D5

14C3

37B3

6B7

37B3

6B7

14C3

37B3

14B3

22B6

23D5

14B3

22C8

14A3

22B8

23C2

54A5

6A7

31C4

30C4

15A3

23D5

43C3

6C1

22B6

15B7

60C6

8B3

29B3

29C3 29C3

15C3

19C2

15C3

15C6

14D3

14C3

15C6

41A8

6C1

15B7

15B3

15C3

19D2

19C2

6C1

38B1

69A3

15B6

22C8

34C7

43C4

43A4

23C2

41A2

38B1

6A7

43A5

67A2

36B2

69A4

22C8

37B3

57A6

55C3

56A4

30A5

7C4

Preliminary

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD9

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

NC

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

RESERVED

ADDR GROUP0ADDR GROUP1

ICH

DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

DATBP1*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PIN. MAKE SURE CPU_TEST4 IS

PLACE C1000 CLOSE TO CPU_TEST4

REFERENCED TO GND

0.5" MAX LENGTH FOR CPU_GTLREF

FSB_IERR_L WITH A GND

PLACE TESTPOINT ON

0.1" AWAY

GMCH WITHOUT T (NO STUB)

SHOULD CONNECT TO ICH AND

PM_THRMTRIP#

COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5".

LAYOUT NOTE:

NC

402

MF-LF

54.9

1/16W

1%

2

1

R1002

MF-LF 402

1/16W

5%

68

2

1

R1004

402

1K

MF-LF

1%

1/16W

2

1

R1005

402

1/16W

2.0K

MF-LF

1%

2

1

R1006

402

54.9

1/16W MF-LF

1%

R1019

402

1%

MF-LF

1/16W

27.4

R1018

402

54.9

1/16W MF-LF

1%

R1017

402

27.4

1/16W MF-LF

1%

R1016

13C5 70C3

13B5 70C3

13B3 70C3

13A3 70C3

13B3 70C3

13B5 70C3

13B3 70C3

13A3 70C3

13B3 70C3

15B6 22C4 59C7 70B3

22C4 70B3

13B3 70D3

13A5 70B3

27B3

12B1 22C4 70C3

13D5 70D3

13C5 70D3

13B3 70D3

13C5 70C3

13B3 70C3

29B6 70B3

29A6 70B3

29C6 70B3

13D3 70C3

13C3 70C3

13A3 70C3

13C3 70C3

13C3 70D3

13B3 70D3

12B2 70A3

12B3 70A3

12B2 70A3

9A7

12B5 70B3

12B4 27C6

45B5 45C3 59C8 70C3

49B7

15A6 22C2 45B3 70B3

22C4 46B2 70B3

12B5 13A5 70D3

13A3 70D3

13B3 70D3

9A7

12B2 12B3 70B3

9B7

12B3 70B3

9B7

12B2 70B3

9A7

12B3 70A3

49C7

29D3 75C3

22C4 70C3

22C4 70B3

22C4 70C3

22C4 70B3

22C2 70C3

402

NOSTUFF

5%

MF-LF

1/16W

0

R1030

402

NOSTUFF

1K

MF-LF

5% 1/16W

2

1

R1007

402

54.9

MF-LF

1%

1/16W

2

1

R1003

402

54.9

1/16W MF-LF

1%

R1020

402

1%

MF-LF

1/16W

54.9

R1021

402

1%

MF-LF

1/16W

54.9

R1022

13C3 70C3

402

1%

MF-LF

1/16W

649

R1023

402

MF-LF

NOSTUFF

1K

5%

1/16W

2

1

R1012

402

16V

10%

0.1uF

NOSTUFF

X5R

2

1

C1000

FCBGA

MEROM

OMIT

AB6

G2

AB5

C7

B25

A24

AB3

AA6

AC5

D5

A3

F6

D3

D22

D2

C3

B2

V3

T2

N5

M4

G3

F4

F3

C1

L1

J3

K2

H2

K3

D21

AC1

AC2

B1

H4

B4

C6

B3

C4

D20

E4

G6

A5

F21

H5

E1

C20

F1

G5

AC4

AD1

AD3

AD4

E2

A21

A22

V1

M1

H1

J1

N2

M3

K5

L4

L5

AA3

AB2

AA4

W3

V4

U2

J4

Y4

W5

W2

T3

T5

R4

U1

Y5

U4

A6

W6

R3

U5

Y2

R1

P1

P4

L2

P2

P5

N3

U1000

FCBGA

MEROM

OMIT

A26

AF1

AF26

C24

D25

C23

D7

D6

AE6

AD26

AF24

AA26

H26

AE25

Y26

L26

J26

D24

B5

E5

AC20

U22

N24

H25

M26

G24

K24

E23

AC23

AF22

AD23

AC22

E25

AD21

AE21

AC25

AF23

AE22

AD20

AC26

AB21

AB22

AA21

G25

AD24

AE24

AB25

AA24

AA23

W25

W24

Y23

W22

Y25

F23

U23

U25

T22

V23

V26

V24

AB24

Y22

N25

T25

G22

L25

R24

T24

P22

P23

P25

M23

L22

M24

L23

E26

R23

P26

K25

N22

H23

K22

F26

H22

J23

J24

F24

E22

Y1

AA1

U26

R26

C21

B23

B22

U1000

402

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

54.9

1/16W MF-LF

1%

R1024

CPU FSB

10

H

051-7559

106

SYNC_MASTER=T9_MLB_NOME

SYNC_DATE=11/12/2006

TP_CPU_TEST5

FSB_DINV_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<25>

FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14>

FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<19>

FSB_D_L<18>

FSB_DSTB_L_P<1>

FSB_D_L<0>

FSB_D_L<32> FSB_D_L<1> FSB_D_L<2>

FSB_D_L<5>

FSB_D_L<16>

FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24>

FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29>

FSB_DSTB_L_N<1>

CPU_GTLREF CPU_TEST1

CPU_TEST2 TP_CPU_TEST3 CPU_TEST4

TP_CPU_TEST6

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_DSTB_L_N<2> FSB_DSTB_L_P<2> FSB_DINV_L<2>

FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_DSTB_L_N<3> FSB_DSTB_L_P<3> FSB_DINV_L<3>

CPU_COMP<0> CPU_COMP<1> CPU_COMP<2> CPU_COMP<3>

CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L

FSB_D_L<17>

FSB_D_L<4>

FSB_D_L<3>

FSB_DSTB_L_N<0>

FSB_D_L<15>

FSB_D_L<10>

FSB_LOCK_L

CPU_INIT_L

CPU_A20M_L

FSB_A_L<6>

FSB_A_L<3> FSB_A_L<4>

FSB_A_L<14>

FSB_A_L<16>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD9

TP_CPU_RSVD8

TP_CPU_RSVD7

TP_CPU_RSVD6

TP_CPU_RSVD5

TP_CPU_RSVD4

TP_CPU_RSVD3

TP_CPU_RSVD2

TP_CPU_RSVD1

TP_CPU_RSVD0

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_STPCLK_L

CPU_FERR_L

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_A_L<26> FSB_A_L<27>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

FSB_A_L<25>

CPU_IGNNE_L

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

XDP_TCK

XDP_TDO

XDP_TMS

XDP_TDI

XDP_TRST_L

=PP1V05_S0_CPU

CPU_THERMD_N

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<2>

12C5

12B3

11A3

10C7

70B3

9D5

9C5

12B3

70B3

70A3

9C5

9B6

9C5

9B6

12B2

12B5

12B2

12B3

9B5

9B6

9B5

70B3 70B3

70B3

70C3

9C6

7C7

Preliminary

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VSSSENSE

VCCSENSE

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VCCA

VCCP

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TBD A (Deep Sleep LFM)

TBD A (Sleep LFM)

TBD A (Auto-Halt/Stop-Grant LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (LFM)

TBD A (HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Sleep HFM)

TBD A (Deep Sleep HFM)

TBD A (Deeper Sleep)

TBD A (Enhanced Deeper Sleep)TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep SuperLFM)

TBD A (Deep Sleep HFM)

TBD A (Sleep SuperLFM)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (SuperLFM)

18.7 A (LFM)

21.0 A (HFM)

23.0 A (Design Target) 17.0 A (Design Target)

Ultra Low Voltage:

Low Voltage:

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

Standard Voltage:

44.0 A (Design Target)

41.0 A (HFM)

16.8 A (Sleep SuperLFM)

16.0 A (Deep Sleep SuperLFM)

4500 mA (before VCC stable) 2500 mA (after VCC stable)

9.4 A (Enhanced Deeper Sleep)

25.5 A (SuperLFM)

30.4 A (LFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Sleep HFM)

25.0 A (Deep Sleep HFM)

11.5 A (Deeper Sleep)

59C7 70A3

R1101

1

2

1/16W

1%

100

402

MF-LF

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

59C7 70A3

59A4 59A5 70A3

OMIT

U1000

A7 A9

B9

B10 B12

B14 B15

B17

B18 B20

C9

C10

A10

C12

C13

C15 C17

C18

D9

D10

D12 D14

D15

A12

D17 D18

E7

E9 E10

E12 E13

E15

E17 E18

A13

E20

F7

F9

F10

F12 F14

F15 F17

F18

F20

A15

AA7

AA9

AA10 AA12

AA13

AA15 AA17

AA18 AA20

AB9

A17

AC10 AB10

AB12

AB14 AB15

AB17

AB18

AB20 AB7

AC7

A18

AC9

AC12

AC13 AC15

AC17

AC18 AD7

AD9

AD10 AD12

A20

AD14 AD15

AD17

AD18 AE9

AE10

AE12 AE13

AE15

AE17

B7

AE18

AE20 AF9

AF10

AF12 AF14

AF15

AF17 AF18

AF20

B26

C26

G21

V6

R21 R6

T21 T6

V21

W21

J6

K6

M6 J21

K21

M21 N21

N6

AF7

AD6

AF5 AE5

AF4 AE3

AF3

AE2

AE7

MEROM

FCBGA

U1000

A4

A8

B11

W1 W4

W23 W26

Y3

Y6 Y21

Y24

AA2 AA5

B13

AA8

AA11 AA14

AA16 AA19

AA22

AA25 AB1

AB4

AB8

B16

AB11

AB13

AB16 AB19

AB23 AB26

AC3

AC6 AC8

AC11

B19

AC14 AC16

AC19

AC21 AC24

AD2 AD5

AD8

AD11 AD13

B21

AD16

AD19 AD22

AD25

AE1 AE4

AE8 AE11

AE14

AE16

B24

AE19

AE23

AE26 A2

AF6

AF8 AF11

AF13 AF16

AF19

C5

AF21 A25

AF25

C8

C11

C14

A11

C16

C19

C2

C22

C25

D1

D4

D8 D11

D13

A14

D16 D19

D23 D26

E3

E6

E8

E11

E14 E16

A16

E19

E21 E24

F5

F8

F11

F13 F16

F19

F2

A19

F22

F25

G4

G1

G23 G26

H3

H6 H21

H24

A23

J2

J5

J22

J25

K1

K4 K23

K26

L3

L6

AF2

L21

L24

M2

M5

M22 M25

N1

N4

N23

N26

B6

P3

P6

P21

P24 R2

R5

R22 R25

T1

T4

B8

T23

T26 U3

U6

U21 U24

V2

V5 V22

V25

OMIT

MEROM

FCBGA

R1100

1

2

100

1% 1/16W

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

402

MF-LF

106

11

H

051-7559

CPU Power & Ground

SYNC_MASTER=T9_MLB_NOME

SYNC_DATE=11/12/2006

=PPVCORE_S0_CPU

CPU_VID<2> CPU_VID<3>

CPU_VID<5>

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<0> CPU_VID<1>

CPU_VID<6>

CPU_VID<4>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

12C5 12B3 11A3

48B5

9D5

48B3

9C5

11D7

9B6

10B5

10D7

11B3

9B5

7D7

7C7

Preliminary

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

CPU VCORE HF AND BULK DECOUPLING

C1250, C1251, C1252 AND C1253 NEED TO USE 6mOHM CAPS.

PLACE ON BOTTOMSIDE

PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)

PLACE ON BOTTOMSIDE

LAYOUT NOTE:

LAYOUT NOTE: PLACE C1235 CLOSE TO CPU

PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)

4x 330uF. 20x 10uF 0805

VCCP (CPU I/O) DECOUPLING

VCCA (CPU AVdd) DECOUPLING

PLACE C1281 NEAR PIN B26 OF U1000

LAYOUT NOTE:

1x 10uF, 1x 0.01uF

1X 330UF, 6X 0.1UF

330UF

20%

C1235

1

2 3

CRITICAL

2.5V TANT

D2T

402

0.1UF

CERM

10V

20%

2

1

C1237

402

20% 10V CERM

0.1UF

2

1

C1238

402

0.1UF

CERM

10V

20%

2

1

C1239

402

20% 10V CERM

0.1UF

2

1

C1240

402

20% 10V CERM

0.1UF

2

1

C1241

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1210

10UF

10%

CRITICAL

X5R

6.3V 805-2

2

1

C1216

10%

10UF

CRITICAL

X5R

6.3V 805-2

2

1

C1201

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1202

10%

10UF

CRITICAL

X5R

6.3V 805-2

2

1

C1203

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1204

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1205

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1206

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1207

10%

10UF

CRITICAL

X5R

6.3V 805-2

2

1

C1208

10%

10UF

CRITICAL

X5R

6.3V 805-2

2

1

C1209

10UF

10%

CRITICAL

X5R

6.3V 805-2

2

1

C1214

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1213

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1212

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1211

10%

10UF

CRITICAL

X5R

6.3V 805-2

2

1

C1219

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1200

20% 10V CERM

0.1UF

402

2

1

C1236

CRITICAL

10%

10UF

X5R

6.3V 805-2

2

1

C1215

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1217

10%

CRITICAL

10UF

X5R

6.3V 805-2

2

1

C1218

10%

402

CERM

16V

0.01UF

2

1

C1281

603

X5R

6.3V

20%

10uF

2

1

C1280

TANT

CRITICAL

10%

330UF

2.0V D2T

3 2

1

C1250

CRITICAL

10% TANT

330UF

2.0V D2T

3 2

1

C1251

D2T

10% TANT

CRITICAL

330UF

2.0V

3 2

1

C1252

CRITICAL

10% TANT

330UF

2.0V D2T

3 2

1

C1253

051-7559

12

SYNC_MASTER=MSARWAR

SYNC_DATE=04/26/2006

H

106

CPU Decoupling & VID

=PP1V5_S0_CPU

=PP1V05_S0_CPU

=PPVCORE_S0_CPU

12C5 12B3 10C7

9D5

48B5

9C5

48B3

9B6

10D7

10B7

9B5

10B5

7C7

7D7

Preliminary

OUT

IN IN

OUT

IO

IN

OUT

IN

IO

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(TCK)

CPU ITP700FLEX DEBUG SUPPORT

(FBO)

(DEBUG PORT RESET)

(DBR#)

(DEBUG PORT ACTIVE)

(DBA#)

TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX CONNECTOR’S FBO PIN.

ITP TCK SIGNAL LAYOUT NOTE:

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S

TO ICH8M SYS_RST*, AND WITH SYSTEM RESET LOGIC

INDICATE THAT ITP IS USING TAP I/F, NC IN 965GM CHIPSET SYSTEM.

516S0394

(FROM CK505 HOST 133/167MHZ)

402

16V

ITP

10% X5R

0.1UF

2

1

C1300

402

MF-LF

1/16W

1%

22.6

ITP

21

R1302

1% 1/16W

402

MF-LF

54.9

NOSTUFF

2

1

R1301

22.6

1%

1/16W

402

MF-LF

ITP

21

R1300

QT500306-L021-9F

CRITICAL

M-ST-SM

ITP

9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J1302

051-7559

SYNC_MASTER=MASTER

CPU ITP700FLEX DEBUG

SYNC_DATE=5/23/05

106

13

H

=PP1V05_S0_CPU

XDP_TDO

XDP_TRST_L

XDP_BPM_L<2>

CPU_PWRGD

XDP_BPM_L<1>

FSB_CPURST_L

XDP_BPM_L<4>

=PP1V05_S0_CPU

ITPRESET_L

ITP_TDO

XDP_TMS LVDS_CTRL_DATA LVDS_CTRL_CLK

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_BPM_L<3>

CPU_XDP_CLK_P

CPU_XDP_CLK_N

XDP_TCK

XDP_TDI

12B3

12C5

11A3

10C7

9D5

9C5

70B3

9B6

70B3

70A3

70C3

70D3

9B6

70B3

12B3

12B2

70B3

9B5

9C6

70A3

22C4

70A3

13A5 70A3

9B5

9C6

67A7

9C6

70A3

27C6

70A3

9C6

7C7

9A7

9C6

9B2

9C6

9D6 9C6

7C7

9B7

14D5

9A7

9C5

9C6

29D3

9A7

9B7

Preliminary

BI

BI BI

OUT

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI

BI BI BI BI

BI BI

OUT

BI

OUT

BI BI BI BI BI

BI BI

H_D0*

H_D3*

H_D2*

H_D33* H_D34* H_D35*

H_D1*

H_D4*

H_D10*

H_A4* H_A5* H_A6* H_A7* H_A8*

H_A9* H_A10* H_A11* H_A12* H_A13* H_A14* H_A15* H_A16* H_A17* H_A18* H_A19* H_A20* H_A21* H_A22* H_A23* H_A24* H_A25* H_A26* H_A27* H_A28* H_A29* H_A30* H_A31* H_A32* H_A33* H_A34* H_A35*

H_ADS*

H_ADSTB0* H_ADSTB1*

H_A3*

H_D7* H_D8* H_D9*

H_D11* H_D12* H_D13* H_D14* H_D15* H_D16* H_D17* H_D18* H_D19* H_D20* H_D21* H_D22* H_D23*

H_D25* H_D26* H_D27* H_D28* H_D29* H_D30*

H_D32*

H_D36* H_D37* H_BNR* H_D38*

H_BPRI* H_D39* H_D40*

H_DEFER*

H_D41*

H_DBSY* H_D42* H_D43* H_D44*

H_DPWR* H_D45*

H_DRDY* H_D46* H_HIT* H_D47*

H_HITM* H_D48*

H_LOCK*

H_TRDY*

H_D51* H_D52* H_D53*

H_DINV0*

H_D54*

H_DINV1*

H_D55*

H_DINV2*

H_D56*

H_DINV3*

H_D57* H_D58*

H_DSTBN0*

H_D59*

H_DSTBN1*

H_D60*

H_DSTBN2*

H_D61*

H_DSTBN3*

H_D62* H_D63*

H_DSTBP0* H_DSTBP1*

H_DSTBP2* H_SWING H_RCOMP

H_REQ0* H_SCOMP H_REQ1* H_SCOMP*

H_REQ2*

H_REQ3* H_CPURST*

H_REQ4* H_CPUSLP*

H_RS0* H_RS1*

H_AVREF

H_RS2*

H_DVREF

H_D5* H_D6*

H_D31*

H_BREQ*

H_D24*

H_D49* H_D50*

H_DSTBP3*

HPLL_CLK

HPLL_CLK*

HOST

(1 OF 10)

BI BI BI BI

BI

IN

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

9D8

70C3

9D8

70C3

9C8

70C3

9D6

70D3

9D6

70D3

9D6

70D3

9D6

70D3

9D6

70D3

9B2

70D3

9D6

70D3

9D8

70C3

X5R

0.1uF

10% 16V

402

2

1

C1425

2.0K

MF-LF

1%

1/16W

402

2

1

R1426

1K

MF-LF

1%

1/16W

402

2

1

R1425

9C4

70D3

9B4

70C3

9C2

70C3

9B2

70C3

9C4

70D3

9B4

70C3

9D8

70C3

9C2

70C3

9B2

70C3

9C4

70D3

9B4

70C3

9C2

70C3

9B2

70C3

9C6

70D3

9C6

70D3

9D6

70D3

9D8

70C3

9D6

70D3

9D6

70D3

9D6

70D3

9D8

70C3

9D8

70C3

9D8

70C3

9D8

70C3

9C8

70C3

9D8

70C3

54.9

MF-LF

1% 1/16W

402

2

1

R1420

24.9

MF-LF

1%

1/16W

402

2

1

R1415

221

MF-LF

1%

1/16W

402

2

1

R1410

100

MF-LF

1%

1/16W

402

2

1

R1411

X5R

0.1uF

10% 16V

402

2

1

C1410

9D8

70C3

OMIT

CRESTLINE

FCBGA

AM7

AM5

B7

B3

W2

W1

D8

D7

E12

B12

H13

A11

E13

M14

C2

G10

C6

E4

A9

AJ10

AC2

K2

L7

AH11

AD2

K3

M7

K7

H8

AE13

AD13

L2

K5

D6

C10

H2

N8

F3

AH13

AH2

AJ3

AE5

G4

AJ2

AJ7

AE7

AJ6

AH5

AJ5

AH12

AE11

AE9

AJ14

H3

AH8

AJ9

AG3

AC5

AE2

AC6

Y3

AB1

AD7

AB2

H7

AC11

AD11

AC14

AC7

AC9

AD9

AE3

AD12

N1

W3

M6

P4

Y9

Y7

N2

W9

W6

N3

N5

J1

M3

G7

V4

Y8

W10

M2

K9

P13

H5

N9

N12

M10

G2

E2

E5

B6

F12

E8

C8

B9

G20

H17

G12

L13

F16

C15

M11

C11

B11

N19

B19

A19

C18

E17

B15

J13

B17

E19

B18

J19

N16

M17

D17

L19

H20

B16

R17

P15

K19

B14

J17

L16

B13

K16

C14

G17

U1400

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

54.9

MF-LF

1%

1/16W

402

2

1

R1421

9D6

70D3

29D3 75C3

9D6

12B5 70D3

9A2

70B3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C8

70C3

9C4

70D3

9D8

70C3

9D8

70C3

9D8

70C3

9D8

70C3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70D3

9C4

70C3

9B4

70C3

9C4

70C3

9C4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9D8

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9B4

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9D8

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9D8

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9C2

70C3

9B2

70C3

9C2

70C3

9C2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9D8

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9B2

70C3

9D6

70D3

SYNC_DATE=10/30/2006

NB CPU Interface

051-7559

H

106

14

SYNC_MASTER=T9_MLB

=PP1V25R1V05_S0_FSB_NB

FSB_D_L<47>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<33> FSB_D_L<34> FSB_D_L<35>

FSB_D_L<1>

FSB_D_L<10>

FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>

FSB_D_L<11>

FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23>

FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30>

FSB_D_L<32>

FSB_D_L<36> FSB_D_L<37>

FSB_D_L<39> FSB_D_L<40>

FSB_D_L<42>

FSB_D_L<44> FSB_D_L<45> FSB_D_L<46>

FSB_D_L<48>

FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58>

FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

NB_FSB_SCOMP NB_FSB_SCOMP_L

FSB_CPURST_L FSB_CPUSLP_L

FSB_D_L<6>

FSB_D_L<31>

FSB_D_L<24>

FSB_D_L<49> FSB_D_L<50>

FSB_D_L<12>

FSB_D_L<43>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<0>

FSB_D_L<38>

FSB_D_L<41>

FSB_D_L<59>

NB_FSB_SWING NB_FSB_RCOMP

NB_FSB_VREF

FSB_A_L<3>

FSB_A_L<6>

FSB_A_L<4> FSB_A_L<5>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29>

FSB_A_L<32>

FSB_A_L<30> FSB_A_L<31>

FSB_A_L<33> FSB_A_L<34> FSB_A_L<35>

FSB_ADS_L FSB_ADSTB_L<0> FSB_ADSTB_L<1>

FSB_BPRI_L

FSB_BNR_L

FSB_BREQ0_L FSB_DEFER_L FSB_DBSY_L

FSB_DPWR_L

FSB_CLK_NB_P FSB_CLK_NB_N

FSB_DRDY_L FSB_HIT_L FSB_HITM_L

FSB_TRDY_L

FSB_LOCK_L

FSB_DINV_L<0> FSB_DINV_L<1> FSB_DINV_L<2> FSB_DINV_L<3>

FSB_DSTB_L_N<0> FSB_DSTB_L_N<1> FSB_DSTB_L_N<2> FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0> FSB_DSTB_L_P<1> FSB_DSTB_L_P<2> FSB_DSTB_L_P<3>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_RS_L<2>

29C6 29B6

7C7

Preliminary

IN

OUT

IN

OUT OUT OUT

IN IN

OUT OUT OUT

OUT

IN

OUT

BI

L_BKLT_CTRL

L_VDD_EN

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX14

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX15

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_COMPI PEG_COMPO

CRT_DDC_DATA

L_CTRL_DATA

LVDSB_DATA1 LVDSB_DATA2

LVDSB_DATA0

LVDSB_DATA2*

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA2

LVDSA_DATA0 LVDSA_DATA1

LVDSB_CLK*

LVDS_VREFL

LVDS_IBG

TVC_RTN

TVA_RTN TVB_RTN

TVC_DAC

TVB_DAC

TVA_DAC

CRT_RED*

CRT_RED

CRT_GREEN*

CRT_GREEN

CRT_BLUE*

CRT_BLUE

CRT_VSYNC

CRT_TVO_IREF

CRT_HSYNC

CRT_DDC_CLK

L_BKLT_EN

L_DDC_CLK

TV_DCONSEL0 TV_DCONSEL1

LVDSA_DATA2*

L_DDC_DATA

LVDSA_DATA1*

LVDSA_DATA0*

LVDSB_CLK

LVDSA_CLK

LVDSA_CLK*

LVDS_VREFH

L_CTRL_CLK

LVDS_VBG

VGA

TV

LVDS

(3 OF 10)

PCI-EXPRESS GRAPHICS

BI

OUT

IN

IN IN

IN

IN IN IN IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

BI BI

OUT OUT OUT OUT

OUT OUT

IN

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT OUT

OUT

BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN# SDVO_INT#

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_CLKP

SDVOC_BLUE

SDVOC_GREEN

SDVOC_RED

If SDVO is used, VCCD_LVDS must remain powered with proper

LVDS Disable

Tie VCC_TX_LVDS and VCCA_LVDS to GND.

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can

should connect to GND through 75-ohm resistors.

Component: DACA, DACB & DACC

Composite: DACA only

TV-Out Signal Usage:

Can tie the following rails to GND:

VSYNC and CRT_TVO_IREF to GND.

CRT Disable / TV-Out Enable

TV-Out Disable / CRT Enable

Tie TVx_DAC and TVx_RTN to GND. Must power all

Leave GFX_VID<3..0> and GFX_VR_EN as NC.

Tie VCC_AXG and VCC_AXG_NCTF to GND.

Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).

Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.

Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and TV_DCONSELx to GND.

Follow instructions for LVDS and CRT & TV-Out Disable above.

Internal Graphics Disable

and filtered at all times!

NOTE: Must keep VDDC_TVDAC powered

VCCD_CRT, VCCD_QDAC and VCC_SYNC.

VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,

omit filtering components. Unused DAC outputs

All CRT/TVDAC rails must be powered. All

CRT & TV-Out Disable

Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.

share filtering with VCCA_CRT_DAC.

Unused DAC outputs must remain powered, but can

S-Video: DACB & DACC only

Can leave all signals NC if LVDS is not implemented.

decoupling. Otherwise, tie VCCD_LVDS to GND also.

Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).

rails must be filtered except for VCCA_CRT.

8C6

24.9

1% 1/16W MF-LF 402

2

1

R1510

67B8

8C6

69B8

69A8

69D7

69D8

69D7

69A8

8C6

69B8

69A8

67A8 71C3

FCBGA

CRESTLINE

OMIT

L27

K27

J27

G27

F27

E27

P33

M35

AD39

AC38

W38

Y39

W46

Y47

Y43

W42

T42

U43

R50

R51

N51

N50

U47

T46

AH44

AH43

AE49

AE50

AH39

AG39

AC42

AD43

AC49

AC50

AC46

AD47

U39

T38

N45

M45

W49

Y48

AB51

AB50

Y40

W41

Y44

W45

U40

T41

T50

T49

T45

U44

N47

M47

AG41

AG42

AG45

AH45

AH49

AG49

AG46

AH47

AD40

AC41

AD44

AC45

L51

L50

J51

J50

M43

N43

B45

A45

B47

A47

G44

E44

D44 E42

F49

F48

E51

E50

G51

G50

D46

C45

N40

N41

L43

L41

K40

D35

C37

E40

E39

H39

J40

E33

C32

E29

F29

F33

J29

K29

G35

K33

G32

H32

U1400

12B1 67A7

69C8

8C6

8D6

68B6 71D3

8C6

68B6 71D3

8C6

8B6

68C6 71D3

8B6

8A6

8B6

8C6

8B6

8C6

8B6

8C6

68B6 71D3

68C6 71D3

67C6

67D8

8C6

67B6

67B3 71D3

8D6

67B2 71D3

8C6

67B2 71D3

8D6

67B2 71D3

8D6

8C6

69D8

69D7

69B8

SYNC_MASTER=T9_MLB

NB PEG / Video Interfaces

051-7559

H

106

15

SYNC_DATE=10/30/2006

=TV_B_RTN

=TV_B_DAC

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

LVDS_CTRL_DATA

LVDS_CTRL_CLK

TP_LVDS_VBG

PEG_D2R_P<9>

PEG_D2R_P<11>

PEG_D2R_P<10>

PP1V05_S0_NB_VCCPEG

PEG_D2R_N<1>

PEG_D2R_N<6>

TP_LVDS_VREFH

LVDS_A_CLK_N LVDS_A_CLK_P

LVDS_B_CLK_P

LVDS_A_DATA_N<0> LVDS_A_DATA_N<1> LVDS_A_DATA_N<2>

TV_DCONSEL<1>

TV_DCONSEL<0>

LVDS_BKLT_EN

CRT_DDC_CLK

=CRT_HSYNC_R =CRT_TVO_IREF =CRT_VSYNC_R

=CRT_BLUE =CRT_BLUE_L =CRT_GREEN =CRT_GREEN_L =CRT_RED =CRT_RED_L

=TV_A_DAC

=TV_C_DAC

=TV_A_RTN

=TV_C_RTN

LVDS_IBG

TP_LVDS_VREFL

LVDS_B_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<0>

LVDS_A_DATA_P<2>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

CRT_DDC_DATA

PEG_COMP

PEG_D2R_N<0>

PEG_D2R_N<2> PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5>

PEG_D2R_N<7> PEG_D2R_N<8> PEG_D2R_N<9> PEG_D2R_N<10>

PEG_D2R_P<0> PEG_D2R_P<1> PEG_D2R_P<2> PEG_D2R_P<3> PEG_D2R_P<4> PEG_D2R_P<5> PEG_D2R_P<6> PEG_D2R_P<7> PEG_D2R_P<8>

PEG_D2R_P<12> PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_D2R_N<11> PEG_D2R_N<12> PEG_D2R_N<13> PEG_D2R_N<14> PEG_D2R_N<15>

PEG_D2R_P<14>

PEG_R2D_C_P<0> PEG_R2D_C_P<1> PEG_R2D_C_P<2> PEG_R2D_C_P<3> PEG_R2D_C_P<4> PEG_R2D_C_P<5> PEG_R2D_C_P<6> PEG_R2D_C_P<7> PEG_R2D_C_P<8> PEG_R2D_C_P<9> PEG_R2D_C_P<10> PEG_R2D_C_P<11> PEG_R2D_C_P<12> PEG_R2D_C_P<13> PEG_R2D_C_P<14> PEG_R2D_C_P<15>

PEG_R2D_C_N<0> PEG_R2D_C_N<1> PEG_R2D_C_N<2> PEG_R2D_C_N<3> PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6> PEG_R2D_C_N<7> PEG_R2D_C_N<8> PEG_R2D_C_N<9> PEG_R2D_C_N<10> PEG_R2D_C_N<11> PEG_R2D_C_N<12> PEG_R2D_C_N<13> PEG_R2D_C_N<14> PEG_R2D_C_N<15>

LVDS_BKLT_CTL

LVDS_DDC_CLK LVDS_DDC_DATA LVDS_VDD_EN

20D3 18B3

Preliminary

IN

CLKREQ*

NC1

NC8

CL_CLK

CL_PWROK

CL_RST*

RSVD6

THERMTRIP*

PM_BM_BUSY*

RSVD4

RSVD3

RSVD7

SM_CKE1

SM_CK0*

SM_CKE0

SM_ODT0

SM_ODT2

SM_RCOMP

SM_RCOMP*

SM_VREF0 SM_VREF1

SM_RCOMP_VOL

SM_CS1*

SM_CS0*

RSVD14

RSVD11

RSVD10

RSVD9

RSVD5

RSVD8

RSVD2

DPLL_REF_CLK*

DPLL_REF_SSCLK

PEG_CLK

DMI_RXN1

DMI_RXN0

DMI_RXN3

DMI_RXN2

DMI_RXP0 DMI_RXP1 DMI_RXP2

DMI_TXN0

DMI_RXP3

DMI_TXN2

DMI_TXN1

DMI_TXP0

DMI_TXN3

DMI_TXP1 DMI_TXP2 DMI_TXP3

PEG_CLK*

RSVD12

CL_DATA

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

ICH_SYNC*

TEST1 TEST2

GFX_VID0 GFX_VID1 GFX_VID2

GFX_VR_EN

GFX_VID3

RSVD20 RSVD21

RSVD24 RSVD25

RSVD27

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39

RSVD41 RSVD42

RSVD40

RSVD43 RSVD44 RSVD45

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13

CFG16

CFG15

CFG14

CFG17 CFG18 CFG19 CFG20

PM_DPRSTP* PM_EXT_TS0*

PWROK

PM_EXT_TS1*

RSTIN*

DPRSLPVR

NC2

NC4

NC3

NC5

NC7

NC6

NC10

NC9

NC12

NC11

NC13 NC14 NC15 NC16

DPLL_REF_CLK

SM_RCOMP_VOH

SM_ODT3

SM_ODT1

RSVD13

SM_CS2* SM_CS3*

SM_CK3 SM_CK4

SM_CK4*

SM_CKE3

RSVD1

SM_CKE4

DPLL_REF_SSCLK*

SM_CK3*

SM_CK1*

SM_CK1

SM_CK0

SA_MA14

RSVD22 RSVD23

RSVD26

SB_MA14

SM_CK2 SM_CK2* SM_CK5 SM_CK5*

(2 OF 10)

RSVD

DDR MUXING

CLK

CFG

DMI

PM

GRAPHICS VID

ME

MISC

NC

OUT OUT OUT OUT OUT

BI BI

IN

OUT

BI

BI OUT OUT

IN

OUT

OUT OUT

IN IN IN OUT

OUT OUT OUT

BI

OUT

BI

OUT

IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT

IN

IN IN

IN

IN IN IN IN

IN IN

IN

OUT

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Clk used for PEG and DMI

NB_CFG<3>

High = DMIx4

NB CFG<8:0> used for debug access

IPU

NB_CFG<4>

NB_CFG<5>

DMI x2 Select

NOTE: GMCH CL_PWROK input must be PWRGD signal for PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

If ME/AMT is not used, short CL_PWROK to PWROK.

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.

NB_CFG<18>

NB_CFG<15>

FSB Dynamic ODT

NB_CFG<17>

NB_CFG<14>

NB_CFG<16>

NB_CFG<11>

NB_CFG<12>

NB_CFG<13>

DMI Lane Reversal

SDVO/PCIe x1

Concurrent

NB_CFG<20>

NB_CFG<19>

00 = RESERVED

or PCIe x16

11 = Normal Operation

High = Reversed

Low = Only SDVO

NB_CFG<13:12>

High = Both active

Low = Normal

01 = XOR Mode Enabled 10 = All-Z Mode Enabled

High = Enabled

Low = Disabled

See Below

RESERVED

Lane Reversal

PCIe Graphics

NB_CFG<9>

NB_CFG<10>

Low = Reversed

High = Normal

RESERVED

NB_CFG<7>

NB_CFG<6>

RESERVED

IPU

IPD IPD

IPD

IPU

NB_CFG<8>

Low = DMIx2

RESERVED

IPU

NB CFG<13:12> require ICT access

IPU

27D1

20A4

10V

0.1uF

20%

CERM 402

2

1

C1616

10V

0.1uF

20%

CERM

402

2

1

C1615

OMIT

FCBGA

CRESTLINE

N20

R32

A37

AW4

AR49

BL31

BK31

BK14

BL15

BE16

BJ14

BJ15

BH18

BE13

BG16

BK16

BG20

BG37

BD39

AY32

BE29

BD24

BC23

AW23

AV23

AW25

BA25

BG23

BF23

BA23

BB23

AW30

AV29

K36

H35

BE24

BJ29

J12

AN13

AM12

AR13

AR12

C34

B34

B36

B37

A35

C44

N35

B44

D47

C48

BK20

AW20

BH39

R35

BJ18

BK18

BH20

BF19

BK22

BJ20

B51

H10

P37

D20

AM37

AL36

AM36

AR37

P36

AV20

AW49

J36

L36

L39

G41

K45

K44

BJ1

BK1

BL2

BL3

BL49

BL50

BK50

BK51

BK2

A49

A50

B50

C51

A5

E1

BJ51

G40

E36

B39

C38

A39

E35

G36

H47

H48

C42

B42

AM43

AM39

AJ42

AJ47

AM44

AM40

AJ41

AJ46

AN45

AN41

AJ39

AM47

AN46

AN42

AJ38

AN47

G39

AM50

AN49

AT43

AK50

AM49

C20

J20

G23

N23

F23

C23

C21

L35

N24

N33

L32

M24

M20

K23

E20

E23

J23

L23

R24

N27

P27

U1400

21B6 60C6

8B2

24C3 74A3

8B2

24C3 74A3

68A6

28B4

24B5

5% 1/16W MF-LF

20K

402

2

1

R1691

5% 1/16W MF-LF

0

402

2

1

R1690

24C3 59D8 70B3

8B2

44B8

1/16W

5%

MF-LF

10K

402

2

1

R1631

402

CERM

16V

10%

0.01UF

2

1

C1625

20%

CERM1

6.3V

2.2UF

603

2

1

C1624

402

1/16W

1%

MF-LF

1K

2

1

R1624

3.01K

MF-LF

1/16W

1%

402

2

1

R1622

20%

2.2UF

CERM1

6.3V

603

2

1

C1622

402

CERM

16V

10%

0.01UF

2

1

C1623

MF-LF

1% 1/16W

402

1K

2

1

R1620

1% 1/16W MF-LF

392

402

2

1

R1641

1%

1K

1/16W MF-LF 402

2

1

R1640

0.1uF

CERM

10V

20%

402

2

1

C1640

NBCFG_DMI_X2

1/16W MF-LF

3.9K

5%

402

2

1

R1655

NBCFG_PEG_REVERSE

3.9K

MF-LF

1/16W

5%

402

2

1

R1659

MF-LF

5% 1/16W

3.9K

NBCFG_DYN_ODT_DISABLE

402

2

1

R1666

NBCFG_DMI_REVERSE

5% 1/16W MF-LF

3.9K

402

2

1

R1669

NBCFG_SDVO_AND_PCIE

3.9K

MF-LF

1/16W

5%

402

2

1

R1670

60C6

30C4 32C6 72D3

31C4 32A5 72B3

29C8 70B3

29B8 70B3

8A6

15D7

24D5

8A6

402

MF-LF

1/16W

5%

0

21

R1600

9C6

22C2 45B3 70B3

8B2

44B8

9B2

22C4 59C7 70B3

27B5 59C7

30D4 72D3

31A4 72B3

31D4 72B3

30A4 72D3

30D4 72D3

31A4 72B3

31D4 72B3

30A4 72D3

30C6 32D6 72D3

30C4 32D6 72D3

31C6 32D6 72B3

30B4 32D6 72D3

31C4 32D5 72B3

30B6 32D6 72D3

31B4 32D6 72B3

31B6 32D6 72B3

30B4 32D6 72D3

30B6 32D6 72D3

31B4 32D6 72B3

31B6 32D6 72B3

402

20

1% 1/16W MF-LF

2

1

R1610

402

20

MF-LF

1% 1/16W

2

1

R1611

20A5

29C3 75B3

8B2

23D2 71D3

10K

5% 1/16W MF-LF

402

2

1

R1630

NB Misc Interfaces

SYNC_DATE=10/30/2006

SYNC_MASTER=T9_MLB

16

106

H

051-7559

GFX_VID<4>

DMI_N2S_P<0>

DMI_N2S_P<2>

CLINK_NB_CLK CLINK_NB_DATA =NB_CLINK_MPWROK CLINK_NB_RESET_L

SDVO_CTRLCLK

TP_NB_RSVD<42>

TP_NB_RSVD<41>

TP_NB_RSVD<43>

NB_BSEL<1>

NB_CFG<3>

NB_CFG<9>

TP_NB_CFG<12>

TP_NB_CFG<15> NB_CFG<16>

DMI_N2S_N<3>

DMI_N2S_P<1>

DMI_N2S_P<3>

GFX_VID<1>

=GFX_VR_EN

GFX_VID<3>

TP_LVDS_A_DATAP3

TP_NB_RSVD<34>

MEM_B_A<14>

TP_NB_RSVD<27>

TP_NB_RSVD<26>

TP_NB_RSVD<25>

NB_BSEL<0>

NB_CFG<5>

MEM_CKE<4>

TP_NB_RSVD<1>

MEM_CLK_P<0>

MEM_CLK_N<4>

MEM_CLK_N<3>

MEM_CLK_P<4>

MEM_CLK_P<3>

TP_NB_RSVD<13>

TP_NB_NC<16>

TP_NB_NC<15>

TP_NB_NC<14>

TP_NB_NC<13>

TP_NB_NC<11> TP_NB_NC<12>

TP_NB_NC<9> TP_NB_NC<10>

TP_NB_NC<6> TP_NB_NC<7>

TP_NB_NC<5>

TP_NB_NC<3>

TP_NB_NC<2>

PM_EXTTS_L<0>

NB_CFG<20>

NB_CFG<19>

TP_NB_CFG<18>

TP_NB_CFG<14>

TP_NB_CFG<10>

TP_NB_RSVD<23>

TP_NB_RSVD<22>

TP_NB_RSVD<21>

TP_NB_RSVD<20>

NB_TEST2

NB_TEST1

TP_NB_RSVD<2>

TP_NB_RSVD<8> TP_NB_RSVD<9> TP_NB_RSVD<10> TP_NB_RSVD<11>

MEM_CS_L<0> MEM_CS_L<1>

MEM_CKE<0>

MEM_CLK_N<1>

MEM_CLK_P<1>

MEM_CLK_N<0>

TP_NB_RSVD<7>

TP_NB_RSVD<3> TP_NB_RSVD<4>

TP_NB_NC<8>

TP_NB_NC<1>

NB_CLK100M_PCIE_P

DMI_S2N_P<0>

DMI_N2S_N<0>

SDVO_CTRLDATA NB_CLKREQ_L NB_SB_SYNC_L

TP_MEM_CLKN2 TP_MEM_CLKP5 TP_MEM_CLKN5

PM_BMBUSY_L CPU_DPRSTP_L

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

MEM_CS_L<2>

MEM_ODT<2> MEM_ODT<3>

MEM_CS_L<3>

MEM_ODT<0> MEM_ODT<1>

TP_NB_RSVD<6>

TP_NB_RSVD<12>

TP_NB_NC<4>

DMI_S2N_P<3>

=PP0V9_S3M_MEM_NBVREFB

TP_NB_RSVD<5>

TP_NB_RSVD<24>

TP_MEM_CLKP2

TP_LVDS_A_DATAN3

TP_LVDS_B_DATAP3

MEM_A_A<14>

TP_NB_RSVD<35> TP_NB_RSVD<36>

TP_LVDS_B_DATAN3

TP_NB_RSVD<45>

TP_NB_RSVD<14>

PM_DPRSLPVR

NB_RESET_L

PM_EXTTS_L<1>

NB_CFG<16>

=PP3V3_S0_NB_VCCHV

NB_CFG<19>

NB_CFG<20>

=PP3V3_S0_NB_VCCHV

TP_NB_CFG<11>

TP_NB_CFG<13>

=PP3V3_S0_NB_VCCHV

TP_NB_CFG<17>

PP1V25_S0M_NB_VCCAXD

NB_CLINK_VREF

NB_BSEL<2>

NB_CFG<6> NB_CFG<7> NB_CFG<8>

NB_CFG<5>

MEM_RCOMP_L

TP_NB_RSVD<44>

NB_CFG<4>

MEM_CKE<1> MEM_CKE<3>

=PP0V9_S3M_MEM_NBVREFA

MEM_RCOMP_VOL

MEM_RCOMP

=PP1V8_S3M_MEM_NB

MEM_RCOMP_VOH

NB_CFG<9>

GFX_VID<0>

=NB_CLK96M_DOT_P =NB_CLK96M_DOT_N =NB_CLK100M_DPLLSS_P =NB_CLK100M_DPLLSS_N

NB_CLK100M_PCIE_N

DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>

DMI_S2N_P<1> DMI_S2N_P<2>

DMI_N2S_N<1> DMI_N2S_N<2>

GFX_VID<2>

21B7

20A8

21B7

31D2

18B3

20A8

30D2

15C7

18B3

20C8

15B7

15C7

20A6

17D7

15D7

8D6

15B6

15C7

8B4

8D6

15B6

7D4

15B6

7D4

18C3

74A3

7A4

15B6

Preliminary

BI

BI BI BI BI BI

OUT

BI

OUT

BI BI BI

BI

BI BI BI BI

BI BI

BI BI BI BI BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI

BI

BI BI BI BI BI

BI BI

BI

OUT

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

BI

OUT

BI

BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

OUT

BI

OUT OUT

OUT

BI

OUT

SA_DQ0 SA_DQ1 SA_DQ2

SA_DQ4

SA_DQ6

SA_DQ14

SA_CAS*

SA_BS2

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ34 SA_DQ35

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ30

SA_DQ28 SA_DQ29

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ20

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ13

SA_DQ11 SA_DQ12

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ3

SA_BS1

SA_BS0

SA_DQ45

SA_DM0 SA_DM1

SA_DM3

SA_DM2

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_DQS1*

SA_DQS0*

SA_DQS2*

SA_DQS4*

SA_DQS3*

SA_DQS5* SA_DQS6* SA_DQS7*

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7

SA_MA9

SA_MA8

SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_RAS*

SA_RCVEN*

SA_WE*

DDR SYSTEM MEMORY A

(4 OF 10)

SB_DQ2

SB_DQ1

SB_DQ5

SB_DM0

SB_DQ0

SB_DQ4

SB_DQ6 SB_DQ7

SB_CAS*

SB_BS2

SB_BS0 SB_BS1

SB_DQ63

SB_DQ62

SB_DQ59

SB_DQ58

SB_DQ56

SB_DQ55

SB_DQ54

SB_DQ53

SB_DQ52

SB_DQ51

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ45 SB_DQ46

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ34 SB_DQ35

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ28 SB_DQ29

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQ24

SB_DQ23

SB_DQ22

SB_DQ21

SB_DQ20

SB_DQ19

SB_DQ18

SB_DQ17

SB_DQ16

SB_DQ15

SB_DQ14

SB_DQ13

SB_DQ11 SB_DQ12

SB_DQ10

SB_DQ9

SB_DQ8

SB_DQ3

SB_DQ57

SB_DQ61

SB_DQ60

SB_WE*

SB_RCVEN*

SB_RAS*

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA8 SB_MA9

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA2

SB_MA1

SB_MA0

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS3* SB_DQS4*

SB_DQS2*

SB_DQS0* SB_DQS1*

SB_DQS7

SB_DQS6

SB_DQS5

SB_DQS4

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS0

SB_DM6 SB_DM7

SB_DM4 SB_DM5

SB_DM2 SB_DM3

SB_DM1

(5 OF 10)

DDR SYSTEM MEMORY B

BI

OUT OUT OUT

BI

OUT

BI

OUT

BI

BI BI BI BI BI BI BI BI BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

30A6 72D3

30C6 72C3

30B6 72C3

30B4 72C3

30A4 72C3

30A6 72C3

30A4 72C3

30A6 72C3

30B6 72C3

30B4 72C3

30C4 72C3

30A6 72D3

30C6 72C3

30D4 72C3

31A6 72B3

31A4 72B3

31A6 72B3

31A4 72B3

31A6 72B3

31A4 72B3

30A6 72D3 31A6 72B3

31A6 72B3

31A4 72B3

31A6 72B3

31A4 72B3

31B6 72B3

31A6 72B3

31A4 72B3

30A4 72D3

31B6 72B3

31A6 72B3

31B4 72B3

31A4 72B3

31A6 72B3

31B6 72B3

31B4 72B3

30A4 72D3

31B6 72B3

31C6 72B3

31B6 72B3

31B4 72B3

31C4 72B3

31C6 72B3

31C4 72B3

31C6 72B3

30A6 72D3

31C4 72B3

31C6 72B3

31C4 72B3

31C6 72B3

31C4 72B3

31C6 72B3

31C4 72B3

30A6 72D3

31D4 72B3

31D6 72B3

31D4 72B3

31D6 72B3

30A4 72D3

31D4 72B3

31D6 72B3

31D4 72B3

31D6 72B3

31D4 72B3

31D6 72B3

31B6 32A6 72B3

31B4 32A6 72B3

31B4 32A5 72B3

30A6 72D3

31C6 32A5 72B3

31B6 32B5 72B3

31C4 32A5 72B3

31C6 32B5 72B3

31C4 32B5 72B3

31B6 32B5 72B3

31C4 32B5 72B3

31B4 32B5 72B3

31B6 32B5 72B3

30A4 72D3

31B4 32B5 72B3

31B6 32B5 72B3

31B4 32B5 72B3

31A4 72A3

31A6 72A3

31C4 72A3

31B6 72A3

31B4 72A3

31C6 72A3

31D6 72A3

30A4 72D3

31A6 72A3

31A4 72A3

31D6 72A3

31B6 72A3

31A4 72A3

31C4 72A3

31D6 72A3

31C6 72A3

31A6 72A3

31D6 72A3

30A6 72D3

31A6 72B3

31A4 72A3

31C6 72B3

31B4 72B3

31C4 72B3

31D4 72B3

31B6 32A6 72B3

31C6 32A6 72B3

31B6 32A6 72B3

30A4 72D3

31B4 32A6 72B3

FCBGA

CRESTLINE

OMIT

BA19

AY20

BE18

BA28

BL28

BJ25

BJ27

BK28

BL24

BH28

BK27

BJ16

BG30

BE28

BC19

BD20

BJ19

AP2

AP3

BC1

BB2

BH7

BH6

BA16

BB16

BA37

BC37

BC41

BB43

BD47

BE48

AT47

AT46

BF48

BB45

AW47

AN11

AM9

AN9

AT9

AT42

AN10

AM8

AN3

AR9

AR8

AR5

BB7

AY6

AT7

AT5

AR45

AY7

BB5

BB9

BD7

AW9

BG10

AY9

BD8

BD10

BE10

AR41

BA11

BA13

AT11

AU15

AV11

AW11

AT13

AV13

AT38

AV38

AY46

AY41

AW41

AW36

AT39

AW40

AR40

BF40

BG40

BH45

BF44

BA45

BE40

BG42

BE44

AW43

BE45

BH49

BG50

BB47

BJ45

BG47

AW44

AR43

AN6

AY5

BG8

AW13

AW38

BD42

BD44

AT45

BL17

BF29

BK19

BB19

U1400

FCBGA

CRESTLINE

OMIT

BC17

AY18

AV16

BD37

AY28

BC28

BA29

BE25

BF25

AW17

BG25

BG13

BA39

BE37

BG17

BG28

BC18

AV3

AV2

BF2

BE2

BK7

BL7

BK12

BJ12

BK38

BK39

BL45

BK46

BC50

BD50

AU50

AT50

BB50

BA50

AV49

AT2

AU2

AY3

AY2

AV50

AT3

AR1

BB3

BA3

BJ2

BD3

BE4

BK3

BC2

BG1

AN50

BH5

BF4

BJ6

BJ8

BK10

BK9

BL5

BK5

BL9

BJ10

AN51

BG12

BC12

BE12

BC13

BC11

BK11

BE11

BK13

BK37

BL35

AW51

BJ40

BK41

BJ36

BJ37

BL41

BJ41

BK42

BK43

BK49

BK47

AW50

BL43

BJ43

BJ44

BJ50

BF49

BF50

AY49

BA51

BE50

BA49

AR51

AP49

AW2

BF3

BJ7

BH12

BL39

BK45

BD49

AR50

BE17

BG36

BG18

AY17

U1400

30B4 72D3

30A6 72D3

30B6 72D3

30B4 72D3

30B6 72D3

30D4 72D3

30B4 72D3

30B6 72D3

30B4 72D3

30B6 72D3

30B4 72D3

30C6 72D3

30C4 72D3

30D4 72D3

30C4 72D3

30A6 72D3

30C6 72D3

30C4 72D3

30C6 72D3

30D6 72D3

30C6 72D3

30C4 72D3

30C6 72D3

30C4 72D3

30C6 72D3

30A4 72D3

30C4 72D3

30D4 72D3

30D6 72D3

30D4 72D3

30D6 72D3

30A4 72D3

30D6 72D3

30D4 72D3

30D6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30C6 32C6 72D3

30A4 72D3

30B6 32B6 72D3

30D4 72C3

30B4 32C6 72D3

30B4 32B6 72D3

30B6 32B6 72D3

30C6 32C6 72D3

30C4 32C6 72D3

30B6 32C6 72D3

30C6 32C6 72D3

30A6 72D3

30C6 32C6 72D3

30C4 32C6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30B6 32C6 72D3

30B4 32C6 72D3

30D6 72C3

30A4 72D3

30D6 72C3

30C4 72C3

30C6 72C3

30B6 72C3

30B4 72C3

30A4 72C3

30A6 72C3

30D6 72C3

30C4 72C3

SYNC_DATE=10/30/2006

SYNC_MASTER=T9_MLB

NB DDR2 Interfaces

051-7559

H

106

17

MEM_A_DQ<35>

TP_MEM_A_RCVEN_L TP_MEM_B_RCVEN_L

MEM_B_DQ<39>

MEM_B_BS<0> MEM_B_BS<1> MEM_B_BS<2>

MEM_B_DM<0>

MEM_B_CAS_L

MEM_B_DM<1> MEM_B_DM<2>

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8>

MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<1>

MEM_B_DQS_P<7> MEM_B_DQS_N<0>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12>

MEM_B_RAS_L

MEM_B_A<13>

MEM_B_WE_L

MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38>

MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_CAS_L

MEM_A_BS<2>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_DM<0> MEM_A_DM<1>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34>

MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

Preliminary

VCC_SM20

VCC_AXG_NCTF42

VCC_SM9 VCC_SM10

VCC_SM17

VCC_SM16

VCC3

VCC_SM5

VCC_SM8

VCC_AXG_NCTF1 VCC_AXG_NCTF2 VCC_AXG_NCTF3 VCC_AXG_NCTF4 VCC_AXG_NCTF5 VCC_AXG_NCTF6

VCC_AXG_NCTF8

VCC_AXG_NCTF7

VCC_AXG_NCTF10

VCC_AXG_NCTF9

VCC_AXG_NCTF11 VCC_AXG_NCTF12 VCC_AXG_NCTF13 VCC_AXG_NCTF14 VCC_AXG_NCTF15 VCC_AXG_NCTF16

VCC_AXG_NCTF18

VCC_AXG_NCTF17

VCC_AXG_NCTF20

VCC_AXG_NCTF19

VCC_AXG_NCTF21 VCC_AXG_NCTF22

VCC_AXG_NCTF25 VCC_AXG_NCTF26

VCC_AXG_NCTF28

VCC_AXG_NCTF27

VCC_AXG_NCTF29 VCC_AXG_NCTF20 VCC_AXG_NCTF31 VCC_AXG_NCTF32 VCC_AXG_NCTF33 VCC_AXG_NCTF34 VCC_AXG_NCTF35 VCC_AXG_NCTF36

VCC_AXG_NCTF38

VCC_AXG_NCTF37

VCC_AXG_NCTF40

VCC_AXG_NCTF39

VCC_AXG_NCTF41

VCC_AXG_NCTF43 VCC_AXG_NCTF44 VCC_AXG_NCTF45 VCC_AXG_NCTF46

VCC_AXG_NCTF48

VCC_AXG_NCTF47

VCC_AXG_NCTF49 VCC_AXG_NCTF50 VCC_AXG_NCTF51

VCC_AXG_NCTF55

VCC_AXG_NCTF58

VCC_AXG_NCTF57

VCC_AXG_NCTF59

VCC_AXG_NCTF61

VCC_AXG_NCTF60

VCC_AXG_NCTF62 VCC_AXG_NCTF63 VCC_AXG_NCTF64

VCC_AXG_NCTF66

VCC_AXG_NCTF65

VCC_AXG_NCTF67 VCC_AXG_NCTF68 VCC_AXG_NCTF69

VCC_AXG_NCTF71

VCC_AXG_NCTF70

VCC_AXG_NCTF72 VCC_AXG_NCTF73 VCC_AXG_NCTF74

VCC_AXG_NCTF76

VCC_AXG_NCTF75

VCC_AXG_NCTF77 VCC_AXG_NCTF78 VCC_AXG_NCTF79

VCC_AXG_NCTF81

VCC_AXG_NCTF80

VCC_AXG_NCTF82 VCC_AXG_NCTF83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC_AXG_NCTF56

VCC_AXG_NCTF54

VCC_AXG_NCTF53

VCC_AXG_NCTF52

VCC_AXG1 VCC_AXG2 VCC_AXG3 VCC_AXG4 VCC_AXG5 VCC_AXG6 VCC_AXG7 VCC_AXG8 VCC_AXG9 VCC_AXG10 VCC_AXG11 VCC_AXG12 VCC_AXG13 VCC_AXG14 VCC_AXG15 VCC_AXG16 VCC_AXG17 VCC_AXG18 VCC_AXG19 VCC_AXG20 VCC_AXG21 VCC_AXG22 VCC_AXG23 VCC_AXG24 VCC_AXG25 VCC_AXG26 VCC_AXG27 VCC_AXG28 VCC_AXG29 VCC_AXG30 VCC_AXG31 VCC_AXG32 VCC_AXG33 VCC_AXG34

VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4

VCC_SM6 VCC_SM7

VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15

VCC_SM18 VCC_SM19

VCC_SM21 VCC_SM22 VCC_SM23

VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36

VCC_SM25

VCC_SM24

VCC1 VCC2

VCC7 VCC8 VCC9 VCC10 VCC11 VCC12

VCC13

VCC_AXG_NCTF24

VCC_AXG_NCTF23

VCC6

VCC5 VCC4

VCC GFX

VCC SM

VCC SM LF

(6 OF 10)

VCC CORE

POWER

VCC GFX NCTF

VCC_NCTF49

VCC_NCTF15

VCC_NCTF2

VCC_NCTF10

VCC_AXM7

VCC_AXM5

VCC_AXM4

VCC_AXM3

VCC_AXM2

VCC_AXM1

VSS_SCB6

VSS_SCB5

VSS_SCB4

VSS_SCB3

VSS_SCB2

VSS_SCB1

VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF12

VSS_NCTF11

VSS_NCTF13

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_NCTF22

VCC_NCTF27

VCC_NCTF50

VCC_NCTF47 VCC_NCTF48

VCC_NCTF44

VCC_NCTF43

VCC_NCTF39 VCC_NCTF40

VCC_NCTF38

VCC_NCTF37

VCC_NCTF34 VCC_NCTF35

VCC_NCTF33

VCC_NCTF32

VCC_NCTF31

VCC_NCTF29

VCC_NCTF28

VCC_NCTF26

VCC_NCTF24 VCC_NCTF25

VCC_NCTF23

VCC_NCTF21

VCC_NCTF18 VCC_NCTF19

VCC_NCTF16 VCC_NCTF17

VCC_NCTF3 VCC_NCTF4

VCC_NCTF41 VCC_NCTF42

VCC_NCTF45 VCC_NCTF46

VCC_AXM6

VCC_AXM_NCTF1 VCC_AXM_NCTF2 VCC_AXM_NCTF3 VCC_AXM_NCTF4 VCC_AXM_NCTF5 VCC_AXM_NCTF6 VCC_AXM_NCTF7 VCC_AXM_NCTF8 VCC_AXM_NCTF9 VCC_AXM_NCTF10 VCC_AXM_NCTF11 VCC_AXM_NCTF12 VCC_AXM_NCTF13 VCC_AXM_NCTF14 VCC_AXM_NCTF15 VCC_AXM_NCTF16 VCC_AXM_NCTF17 VCC_AXM_NCTF18 VCC_AXM_NCTF19

VCC_NCTF8

VCC_NCTF20

VCC_NCTF1

VCC_NCTF5 VCC_NCTF6 VCC_NCTF7

VCC_NCTF36

VCC_NCTF30

VCC_NCTF9

VCC AXM NCTF

VCC NCTF

VSS SCBVCC AXM

VSS NCTF

(7 OF 10)

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Current numbers from Crestline EDS, doc #21749.

NCTF balls are Not Critical To Function

These connections can break without

impacting part performance.

5 mA (standby)

7700 mA (Int Graphics)

1310 mA (Ext Graphics) 1573 mA (Int Graphics)

540 mA

3300 mA (2 ch, 667MHz) 2700 mA (2 ch, 533MHz) 1700 mA (1 ch, 667MHz) 1395 mA (1 ch, 533MHz)

CRESTLINE

FCBGA

OMIT

AT6

AW8

BD4

BD17

BE39

BC39

AW45

BA33

BA32

AY35

AW35

AW33

AV33

AU30

BL33

BK35

BK34

BK33

BK32

BJ34

AU35

BJ33

BJ32

BH35

BH34

BH32

BG35

BG33

BG32

BF34

BF33

AU33

BE35

BE33

BE32

BD35

BD32

BC35

BC33

BC32

BB33

BA35

AU32

U16

Y31

V29

V28

V26

U15

AR26

AR24

AR23

AR21

AR20

AP24

AP23

AP21

AP20

AP19

T25

AP17

AP16

AP15

AM23

AM21

AM20

AM19

AM16

AM15

AL23

T23

AL21

AL20

AL19

AL17

AL16

AK19

AK16

AJ19

AJ17

AJ16

T22

AH19

AH17

AH16

AH15

AF19

AF16

AD17

AD16

AD15

AC19

T21

AC17

AC16

AB19

AB16

AA17

AA16

Y29

Y28

Y26

Y24

T19

Y23

Y21

Y20

Y19

Y17

Y16

Y15

V24

V23

V21

T18

V20

V19

V17

V16

U26

U23

U21

U20

U19

U17

T17

AA28

AA26

AA23

AA20

Y12

W14

AN14

AJ20

AD31

AH26

AH24

W13

AH23

AH21

AH20

AA31

AF26

AF21

AD28

AD24

AD23

AD20

T14

AC29

AC28

AC26

AC24

AC23

AC21

AC20

AB29

AB24

AB21

R20

AH32

AJ28

AJ31

AK32

AC32 AC31

AH28

AT34

R30

AF32

AH29

AH31

AT35

U1400

FCBGA

CRESTLINE

OMIT

A51

BL51

BL1

C1

B2

A3

AB35

AB17

AA19

V35

V31

U28

U24

AR28

AR19

T37

AR15

AP28

AP26

AM24

AM17

AK17

AF35

AF17

AD37

AD19

T27

AF33

AD36

AD35

AC36

V37

AC35

V36

V33

V32

U36

U35

U33

U32

U31

U29

T35

AC33

T34

T30

Y37

Y36

Y35

Y33

Y32

AR36

AR35

AP36

AB37

AP35

AA36

AA35

AA33

AL35

AL33

AM35

AJ36

AD33

AK37

AB36

AK36

AK35

AK33

AJ35

AJ33

AH37

AH36

AH35

AH33

AF36

AB33

AM33

AM32

AM31

AM29

AM28

AM26

AL28

AL26

AR33

AR32

AR31

AL32

AL31

AL29

AP33

AP32

AP31

AP29

AL24

AJ23

AJ26

AK23

AK24

AK29

AT31

AT33

U1400

20%

CERM

10V

0.1uF

402

2

1

C1806

20%

CERM

10V

0.1uF

402

2

1

C1807

20%

6.3V

0.22UF

X5R 402

2

1

C1804

20%

6.3V

0.22UF

X5R 402

2

1

C1805

6.3V

1uF

CERM

10%

402

2

1

C1802

CERM-X5R

6.3V

0.47UF

10%

402

2

1

C1803

6.3V

1uF

CERM

10%

402

2

1

C1801

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

NB Power 1

051-7559

H

106

18

=PPVCORE_S0_NB

=PP1V05_S0M_NB_VCCAXM

=PPVCORE_S0_NB_GFX

=PP1V8_S3M_MEM_NB

=PPVCORE_S0_NB

=PPVCORE_S0_NB_GFX

NB_VCCSM_LF6

NB_VCCSM_LF4

NB_VCCSM_LF3

NB_VCCSM_LF2

NB_VCCSM_LF1

NB_VCCSM_LF7

NB_VCCSM_LF5

=PP1V05_S0M_NB_VCCAXM

31D2

20D8

48B3

30D2

20D8

48B3

20B4

20D8

21C5

20C8

20B4

21C5

20D8

17D7

17C1

17B7

15D2

17D3

17D5

17B3

7C7

7B7

7A4

7C7

7B7

7C7

Preliminary

VCCA_CRT_DAC1

VTT7 VTT8

VCC_AXD_NCTF

VCCD_CRT

VCC_RXR_DMI1 VCC_RXR_DMI2

VTT1

VCCA_SM_CK2 VCC_TX_LVDS

VCC_HV2

VCC_PEG1 VCC_PEG2 VCC_PEG3

VCC_AXF2

VCC_AXD1 VCC_AXD2

VSSA_LVDS

VCCA_SM5

VCCA_PEG_PLL

VCCA_MPLL

VCCA_HPLL VTT16

VTT17

VTT15

VCCD_LVDS2

VCCD_LVDS1

VCCD_PEG_PLL

VCCD_HPLL

VCCD_QDAC

VCCD_TVDAC

VCCA_TVC_DAC1 VCCA_TVC_DAC2

VCCA_TVB_DAC2

VCCA_TVB_DAC1

VCCA_TVA_DAC2

VCCA_TVA_DAC1

VCCA_SM_CK1

VCCA_SM2

VCCA_SM1

VCCA_SM_NCTF2

VCCA_SM_NCTF1

VCCA_SM11

VCCA_SM10

VCCA_SM9

VCCA_SM8

VCCA_SM7

VCCA_SM4

VCCA_SM3

VSSA_PEG_BG

VCCA_PEG_BG

VCCA_LVDS

VCCA_DPLLB

VCCA_DPLLA

VSSA_DAC_BG

VCCA_DAC_BG

VCC_AXF3

VCC_HV1

VCC_PEG5

VTTLF1

VTTLF3

VTTLF2

VCC_PEG4

VCC_SM_CK3

VCC_SM_CK2

VCC_SM_CK1

VCC_SM_CK4

VCC_DMI

VCC_AXF1

VTT22

VCC_AXD6

VCC_AXD5

VCC_AXD4

VCC_AXD3

VTT19

VTT2

VTT6

VTT5

VTT11

VTT10

VTT9

VTT13

VTT12

VTT14

VTT18

VTT21

VTT20

VTT3 VTT4

VCCA_CRT_DAC2

VCC_SYNC

CRT

AXD

PEG

HV

AXF

VTTLF

VTT

SM CK

DMI

TV/CRT

D

LVDS

A SMA CK

CRT A LVDS

A PEG

PLL

(8 OF 10)

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

550 mA (533MHz DDR)

640 mA (667MHz DDR)

Current numbers from Crestline EDS, doc #21749.

515 mA

495 mA

850 mA @ 800MHz FSB (1.05V)

35 mA

100 mA

60 mA

30 mA

80 mA

0.4 mA

260 mA

1260 mA

770 mA @ 667MHz FSB (1.05V)

150 mA

TBD mA @ 1067MHz FSB (1.25V)

S0 or S3M is acceptable

5 mA

150 mA

250 mA

60 mA

40 mA

10 mA

100 mA

50 mA

5 mA

200 mA

100 mA

6.3V

402

CERM-X5R

10%

0.47UF

2

1

C1911

402

CERM-X5R

6.3V

10%

0.47UF

2

1

C1913

402

CERM-X5R

6.3V

10%

0.47UF

2

1

C1912

CRESTLINE

FCBGA

OMIT

AH1

F2

A7

U2

U3

U5

U7

U8

U9

U11

R1

R2

R3

U12

T2

T3

T5

T6

T7

T9

T10

T11

T13

U1

U13

K49

B41

B32

L29

N28

U48

H42

J41

AN2

M32

A28

B28

B27

C27

B25

C25

AR16

AR17

BB29

BC29

AT19

AT21

AT22

AU17

AU18

AU19

AV19

AT17

AT18

AW18

U51

K50

AM2

A41

AL2

H49

B49

A30

B33

A33

A43

J32

BJ23

BJ24

BK23

BK24

AH51

AH50

V50

V49

W51

W50

AD51

B40

C40

AJ50

A21

B21

B23

AR29

AT30

AT25

AT29

AU24

AU28

AT23

U1400

SYNC_MASTER=T9_MLB

SYNC_DATE=10/30/2006

NB Power 2

19

106

H

051-7559

NB_VTTLF_CAP2

=PP1V8_S0_NB_VCCD_LVDS

PP1V25_S0_NB_VCCA_DPLLA

PP1V25_S0M_NB_VCCA_HPLL

PP3V3_S0_NB_VCCA_TVDACA

=PP1V5_S0_NB_VCCD_CRT PP1V5_S0_NB_VCCD_TVDAC

PP1V5_S0_NB_VCCD_QDAC

=PP1V25_S0M_NB_VCCD_HPLL

=GND_NB_VSSA_LVDS

PP3V3_S0_NB_VCCA_DAC_BG

PP1V25_S0M_NB_VCCA_MPLL

NB_VTTLF_CAP1

NB_VTTLF_CAP3

=PP1V25_S0_NB_VCCDMI

=GND_NB_VSSA_DAC_BG

=GND_NB_VSSA_PEG_BG

PP1V8_S0_NB_VCCTXLVDS

PP1V05_S0_NB_VCCPEG

=PP3V3_S0_NB_VCCHV

PP1V05_S0_NB_VCCRXRDMI

PP1V25_S0_NB_VCCAXF

PP1V25_S0M_NB_VCCAXD

PP3V3_S0_NB_VCCA_TVDACC

PP1V25_S0_NB_VCCA_DPLLB

PP3V3_S0_NB_VCCA_TVDACB

=PP1V25R1V05_S0_NB_VTT

PP1V8_S0_NB_VCCTXLVDS

PP3V3_S0_NB_VCCA_CRTDAC

=PP3V3_S0_NB_VCCSYNC

PP1V25_S0M_NB_VCCA_SM_CK

PP1V25_S0_NB_PEGPLL

PP1V8_S3M_NB_VCCSMCK

PP1V25_S0M_NB_VCCA_SM

=PP3V3_S0_NB_VCCA_PEG_BG

21B7

20A8 15C7

20A8

21C3

20D3

15B7

20A6

20C8

21C3

21B5

20A6

21B3

21A3

20D1

21D1

21C7

21D6

21C5

20D1

21B3

21B1

20C1

7C7

21B1

20A6

18C6

14D2

7D4

20C3

20D5

15A2

21C1

21A3

21C1

7C7

18B3

21D1

7C4

20B5

20B2

20A2

20B5

7C4

Preliminary

VSS198VSS99

VSS197VSS98

VSS196VSS97

VSS195VSS96

VSS194VSS95

VSS193VSS94

VSS192VSS93

VSS191VSS92

VSS190VSS91

VSS189VSS90

VSS188VSS89

VSS187VSS88

VSS186VSS87

VSS185VSS86

VSS184VSS85

VSS183VSS84

VSS182VSS83

VSS181VSS82

VSS180VSS81

VSS179VSS80

VSS178VSS79

VSS177VSS78

VSS176VSS77

VSS175VSS76

VSS174VSS75

VSS173VSS74

VSS172VSS73

VSS171VSS72

VSS170VSS71

VSS169VSS70

VSS168VSS69

VSS167VSS68

VSS166VSS67

VSS165VSS66

VSS164VSS65

VSS163VSS64

VSS162VSS63

VSS161VSS62

VSS160VSS61

VSS159VSS60

VSS158VSS59

VSS157VSS58

VSS156VSS57

VSS155VSS56

VSS154VSS55

VSS153VSS54

VSS152VSS53

VSS151VSS52

VSS150VSS51

VSS149VSS50

VSS148VSS49

VSS147VSS48

VSS146VSS47

VSS145VSS46

VSS144VSS45

VSS143VSS44

VSS142VSS43

VSS141VSS42

VSS140VSS41

VSS139VSS40

VSS138VSS39

VSS137VSS38

VSS136VSS37

VSS135VSS36

VSS134VSS35

VSS133VSS34

VSS132VSS33

VSS131VSS32

VSS130VSS31

VSS129VSS30

VSS128VSS29

VSS127VSS28

VSS126VSS27

VSS125VSS26

VSS124VSS25

VSS123VSS24

VSS122VSS23

VSS121VSS22

VSS120VSS21

VSS119VSS20

VSS118VSS19

VSS117

VSS116VSS17

VSS115VSS16

VSS114VSS15

VSS113VSS14

VSS112VSS13

VSS111VSS12

VSS110VSS11

VSS109VSS10

VSS108

VSS9

VSS107VSS8

VSS106VSS7

VSS105VSS6

VSS104VSS5

VSS103VSS4

VSS102

VSS101

VSS100

VSS1

VSS18

VSS2 VSS3

VSS

(9 OF 10)

VSS202

VSS289 VSS290 VSS291 VSS292

VSS295

VSS199 VSS287 VSS200 VSS288 VSS201

VSS203 VSS204

VSS293 VSS294

VSS208 VSS296 VSS209 VSS297 VSS210 VSS298 VSS211 VSS299 VSS212 VSS300 VSS213 VSS301 VSS214 VSS215 VSS216 VSS302 VSS217 VSS218 VSS219 VSS303 VSS220 VSS221 VSS222 VSS304 VSS223 VSS224 VSS225 VSS305 VSS226 VSS227 VSS228 VSS229 VSS306 VSS230 VSS307 VSS231 VSS308 VSS232 VSS309 VSS233 VSS310 VSS234 VSS311 VSS235 VSS312 VSS236 VSS313 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243

VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286

VSS207

VSS206

VSS205

(10 OF 10)

VSS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NOTE: TDE = _P

Crestline Thermal Diode Pins

TDB_SENSE

NOTE: TDB = _N

Mainly for investigation. If not used, alias these nets directly to GND.

TDB_FORCE

TDE_FORCE

TDE_SENSE

CRESTLINE

OMIT

FCBGA

AW16

AW12

AW1

AV48

AV39

AU51

AU49

AU36

AU3

AU29

AB23

AU23

AU1

AT49

AT41

AT14

AT10

AR7

AR47

AR44

AR39

AB20

AR2

AR11

AP50

AP48

AP4

AN7

AN5

AN43

AN39

AN38

AA29

AN1

AM45

AM41

AM4

AM3

AM13

AM11

AL1

AK51

AK31

AA24

AK28

AK26

AK21

AK20

AJ49

AJ45

AJ43

AJ32

AJ29

AJ24

AA21

AJ21

AJ13

AJ11

AH9

AH7

AH41

AH40

AH3

AG50

AG47

A24

AG43

AG38

AG2

AF31

AF24

AF23

AF20

AE6

AE14

AE10

A17

AD8

AD50

AD5

AD49

AD45

AD41

AD3

AD29

AD26

AD21

A15

C41

C36

C33

C29

C28

C19

C16

C12

BL47

AD1

BL37

BL22

BL19

BL13

BL11

BK8

BK6

BK44

BK40

BK36

AC47

BK29

BK25

BK17

BK15

BJ46

BJ42

BJ4

BJ38

BJ13

BJ11

AC43

BH8

BH46

BH44

BH30

BH17

BG51

BG5

BG48

BG39

BG29

AC39

BG24

BG2

BG19

BF36

BF16

BF12

BE8

BE51

BE42

BE30

AC3

BE23

BE19

BE1

BD5

BD48

BD45

BD28

BD2

BD13

BC51

AC13

BC40

BC36

BC25

BC24

BC16

BB8

BB49

BB44

BB40

BB25

AC10

BB12

BA24

BA2

BA18

BA17

BA1

B8

B5

B46

B43

AB31

B38

B35

B30

B29

B24

B20

B10

AY50

AY47

AY45AB28

AY43

AY42

AY37

AY24

AY10

AW7

AW5

AW32

AW29

AW24

AB26

A13

U1400

CRESTLINE

OMIT

FCBGA

H50

AV25

AT27

AF29

AF28

AD32

AB32

AA32

R28

T33

T31

T29

P29

Y11

Y50

Y5

Y49

Y45

Y41

Y2

Y13

W7

W5

W47

W43

W39

W11

V3

V2

U50

U45

U41

T47

T43

T39

R49

P50

P3

P23

P2

P19

N7

N49

N44

N39

N36

N32

N29

N17

N14

N11

M9

M50

M5

M49

M46

M42

M28

L49

L33

L3

L28

L24

L20

L17

L1

K8

K47

K12

J39

J35

J33

J28

J24

J2

J16

J11

H45

H4

H28

H24

G8

G48

G45

G42

G33

G29

G28

G24

G19

G16

G13

G1

F50

F40

F4

F36

F19

E47

E32

E28

E24

E16

E10

D49

D45

D39

D32

D3

D24

D13

C7

C50

C46

U1400

SYNC_DATE=10/30/2006

SYNC_MASTER=T9_MLB

NB Grounds

20

106

H

051-7559

=NB_TDB_SENSE

=NB_TDB_FORCE

=NB_TDE_FORCE

=NB_TDE_SENSE

8A2

Preliminary

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Analog,I/O logic,and Term Voltage for PCI-E Graphics

10uF caps should

RX and I/O Logic for DMI

250 mA

Layout Note: 10uF caps should be close to MCH on opposite side.

NOTE: This follower is redundant if VCORE is always 1.05V.

WF: Should be 1.0, 1%

2400 mA

GMCH Memory I/O Rail

GMCH ME Core Power

close to MCH

Place L and C

WF: "Place where LVDS

??? mA

Layout Note:

1450 mA

350 mA

I/O voltage Supply

need to find "1uH,220mA,150mohm max"

Analog PLL Voltage for PCI-E GPU

on opposite side.

be close to MCH

Layout Note:

1200 mA

??? mA

100 mA

WF: Should be 1.0, 1%

Layout Note: Route to caps, then GND

Host PLL Digital Supply

250 mA

200 mA

Memory clock logic voltage.

100 mA 100 mA

200 mA

GMCH FSB I/O Rail

850 mA

150 mA

50 mA

Current numbers from Crestline EDS Addendum, doc #20127.

5 mA

200 mA

LAYOUT NOTE: PLACE THOSE COMPONENT CLOSE TO GMCH

200 mA

Host PLL Analog Supply

450 mA

100 mA

GMCH Core Power

MPLL Analog Supply

250mA,0.5ohm

These supplies are still needed even using external GPU

540 mA

??? mA

Memory voltage supply.

WF: 220-ohm

Memory I/O logic and DLL voltage.

and DDR2 taps." (C2125)

WF: Matanzas has 270uF

5.6nH,0.9A,45mohm max.no bigger than 0603

spec requires "3.9uH ferrite,1A,32mohm max".

this is "1 of 2" 1.8V bulk decoupling caps.

PLACEMENT_NOTE=Place close to U1400

402

6.3V

0.47UF

10%

CERM-X5R

2

1

C2124

20%

2.2uF

603

CERM1

6.3V

2

1

C2123

603

20%

CERM

6.3V

4.7uF

2

1

C2121

CRITICAL

D2T

TANT

2.5V

20%

470UF

32

1

C2100

0.22uF

20%

6.3V X5R 402

2

1

C2112

0.22uF

X5R

20%

6.3V 402

2

1

C2111

603

CERM

6.3V

4.7uF

20%

2

1

C2122

6.3V

20%

PLACEMENT_NOTE=Place close to U1400

22UF

CERM 805

2

1

C2131

PLACEMENT_NOTE=Place close to U1400

20%

6.3V

22UF

CERM 805

2

1

C2132

402

10V

0.1UF

20% CERM

2

1

C2135

0.51

1%

402

MF-LF

1/16W

2

1

R2183

1.1

402

1% 1/16W MF-LF

2

1

R2190

L2190

FERR-220-OHM-2.5A

0603

21

603

10uF

6.3V

20% X5R

2

1

C2190

OMIT

C2130

330UF

20%

2.5V POLY

CASE-C2

CRITICAL

2

1

603

X5R

6.3V

20%

10uF

2

1

C2174

OMIT

CRITICAL

CASE-B2

220UF

2.5V POLY

20%

2

1

C2173

CRITICAL

1210

91NH

21

L2173

1.1

1%

MF-LF

1/16W

402

2

1

R2195

0603

1.0UH-0.23A

21

L2195

603

X5R

10uF

20%

6.3V 2

1

C2195

6.3V

20%

805

22UF

CERM

2

1

C2196

CERM

6.3V

10%

1UF

402

2

1

C2171

603

X5R

6.3V

20%

10uF

2

1

C2170

2

6.3V

10% CERM

402

1UF

1

C2151

NOSTUFF

20%

603

X5R

6.3V

10uF

2

1

C2150

6.3V

20%

22UF

CERM 805

2

1

C2142

X5R-CERM

10%

6.3V 603

4.7UF

2

1

C2143

OMIT

C2140

1

2

CASE-B2

2.0V

330UF

POLY

20%

CRITICAL

402

10%

6.3V CERM

1UF

2

1

C2144

402

5%

0

1/16W MF-LF

21

R2141

20%

6.3V

22UF

CERM 805

2

1

C2145

402

MF-LF

1/16W

R2145

0

5%

21

CERM

6.3V

2.2UF

20%

NOSTUFF

402-LF

2

1

C2147

0.1UF

20% 10V CERM 402

2

1

C2148

10

1% 1/16W MF-LF

402

21

R2186

MF-LF

1K

402

1/16W

1%

2

1

R2112

R2113

1K

402

1%

MF-LF

1/16W

2

1

402

1K

1/16W MF-LF

1%

2

1

R2110

1K

402

1%

MF-LF

1/16W

2

1

R2111

120-OHM-0.3A-EMI

0402-LF

21

L2183

402

10V CERM

0.1UF

20%

2

1

C2113

402

0.1UF

20% 10V CERM

2

1

C2114

0.1UF

402

CERM

10V

20%

2

1

C2115

C2160

402

0.1UF

20% 10V CERM

2

1

0.1UF

CERM

10V

20%

402

2

1

C2161 C2165

0.1UF

1

20% 10V CERM 402

2

20% 10V CERM 402

0.1UF

2

1

C2197

402

0.1UF

20% 10V CERM

2

1

C2191

20%

402

CERM

10V

0.1UF

2

1

C2192

20% 10V CERM

0.1UF

402

2

1

C2182

20% 10V CERM 402

0.1UF

2

1

C2180

6.3V

20%

22UF

CERM 805

2

1

C2110

5%

1/16W

0

402

MF-LF

21

R2109

SOD-723

1SS418

2 1

D2186

0402-LF

120-OHM-0.3A-EMI

21

L2181

PLACEMENT_NOTE=Place in GMCH cavity

CERM

0.1UF

10V

20%

402

2

1

C2104

603

X5R

6.3V

20%

10uF

2

1

C2177

0.22uF

402

X5R

20%

6.3V

PLACEMENT_NOTE=Place in GMCH cavity

2

1

C2103

6.3V

0.22uF

20% X5R

PLACEMENT_NOTE=Place in GMCH cavity

402

2

1

C2102

20%

0.1UF

PLACEMENT_NOTE=Place C2184 by U1400.AM2

402

CERM

10V

2

1

C2184

805

20%

6.3V

22UF

CERM

2

1

C2181

6.3V

20%

805

CERM

22UF

2

1

C2183

20%

6.3V

PLACEMENT_NOTE=Place in GMCH cavity

22UF

CERM 805

2

1

C2101

051-7559

NB Standard Decoupling

SYNC_MASTER=WFERRY

SYNC_DATE=06/15/2006

21

H

106

=PP1V8_S3M_MEM_NB

=PP1V05_S0M_NB_VCCAXM

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCA_SM

PP3V3_S0_NBCORE_FOLLOW_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

=PPVCORE_S0_NB

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCAXD

=PP1V25_S0_NB_VCC

=PP0V9_S3M_MEM_NBVREFB

=PP3V3_S0_NB_VCCHV

=PP1V8_S3_NB_VCC

=PP3V3_S0_NB_FOLLOW

PP1V8_S3_NB_VCCSMCK_RC

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

=PP1V8_S3_MEMVREF

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0M_NB_VCCA_MPLL

=PP1V25_S0M_NB_VCCD_HPLL

PP0V9_S3M_MEM_NBVREFB

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=0.9V

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

=GND_NB_VSSA_PEG_BG

=PP1V25_S0_NB_VCCDMI

PP1V25_S0_NB_PEGPLL

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 MM

PP1V05_S0_NB_VCCRXRDMI

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

=PP1V25_S0_NB_PLL

PP1V25_S0_NB_VCCAXF

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

=PP1V25_S0_NB_VCCAXF

=PP1V05_S0_NB_PCIE

PP1V8_S3M_NB_VCCSMCK

MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_NB_VCCPEG

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

=PP1V25_S0_NB_PLL

MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0M_NB_VCCA_HPLL

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0M_NB_MPLL_RC

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCA_SM_CK

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

=PP3V3_S0_NB_VCCA_PEG_BG

=PPVCORE_S0_NB

=PP1V25R1V05_S0_NB_VTT

=PP1V25_S0_NB_VCCA

=PP0V9_S3M_MEM_NBVREFA

PP0V9_S3M_MEM_NBVREFA

VOLTAGE=0.9V

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

PP1V25_S0_NB_PEGPLL_RC

31D2

21B7

30D2

20D8

18B3

20B4

17D7

17C1

17D7

15C7

17D7

15D2

17B3

17D3

18C3

15B7

20A6

20A5

18C3

20B4

18B3

20D3

18C6

17D3

18D3

7A4

7C7

18C6

7C7

15A2

7C7

15C2

7D4

7A4

7D4

7B4

18D6

18A6

18C6

7C7

18C6

18B3

7C7

18C3

7C7

18B3

14D2

7C7

18D6

18B6

7C4

7C7

Preliminary

OUT

EN

NR/FB

IN

GND

THRML

NC

EN

IN

OUT

NR

PAD

GND

OUT OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

VID<3:0>=1001=1.05575V

WF: Matanzas has 2x 330uF

NEED TO FIND A "1£GH, 500MA, 78MOHM" INDUCTOR

WF: Should be 1uH, 30%

260 mA

Layout Note: Route to cap, then GND

WARNING VOLTAGE DROP

VCCD_TVDAC also powers internal thermal sensors.

0011=1.21025V

1000=1.08150V

65 mA

WF: Check part properties

10 mA

6 mA

5 mA

Vout = 1.204V * (Ra + Rb)/Rb

110 mA

Layout Note:

80 mA

WF: Is this the best part to use?

These 2 caps should be within 6.35 mm of NB edge

80 mA

125 mA

80 mA

Layout Note: These 8 caps should be

Layout Note: Route to caps, then GND

within 6.35 mm of NB edge

40 mA

5 mA

40 mA

80 mA

Layout Note:

Current numbers from Crestline EDS Addendum, doc #20127.

150 mA

60 mA

(1.7V - 5.5V)

NC

205 mA

Ra || Rb should be 19Kohms

7700 mA

WF: Check C2266 value, R2267 value

GMCH Graphics Core Power These 4 caps should be within 6.35 mm of NB edge

205 mA

NOTE: This filter is required even if using only external graphics.

16V

NFM18

22000pF-1000mA

CRITICAL

31

2

C2289

16V

10%

402

CERM

0.01UF

2

1

C2282

402

1/16W

100

5% MF-LF

2

1

R2205

20% 10V CERM

0.1UF

402

2

1

C2207

0

5% MF-LF

1/16W 402

2

1

R2281

10%

6.3V

402

CERM

NO STUFF

1UF

2

1

C2281

10%

1UF

6.3V CERM

402

2

1

C2280

16V

NFM18

22000pF-1000mA

CRITICAL

31

2

C2292

CERM

10V

20%

402

0.1UF

2

1

C2291

16V

NFM18

CRITICAL

22000pF-1000mA

31

2

C2294

0.1UF

CERM

10V

20%

402

2

1

C2293

0.1UF

CERM

10V

20%

402

2

1

C2288

16V

22000pF-1000mA

NFM18

CRITICAL

31

2

C2296

0.1UF

CERM

10V

20%

402

2

1

C2295

16V

NFM18

22000pF-1000mA

CRITICAL

31

2

C2298

0.1UF

CERM

10V

20%

402

2

1

C2297

6.3V

20% X5R

603

10uF

2

1

C2290

0402-LF

120-OHM-0.3A-EMI

21

L2290

402

0

MF-LF

5%

1/16W

21

R2261

20% 10V CERM 402

0.1UF

2

1

C2261

402

0

5%

MF-LF

1/16W

21

R2262

402

0.1UF

CERM

10V

20%

2

1

C2262

20% 50V

402

0.001uF

CERM

2

1

C2223

20% 50V CERM 402

0.001uF

2

1

C2221

NFM18

16V

CRITICAL

22000pF-1000mA

31

2

C2201

C2206

22000pF-1000mA

1

CRITICAL

16V

NFM18

3

2

0.1UF

CERM

10V

20%

402

2

1

C2200

1

2

402-1

C2205

X5R

10%

1UF

10V

1.0UH-0.5A-0.675A

1007

21

L2220

OMIT

2.5V

2

CRITICAL

POLY

20%

220UF

CASE-B2-SM

1

C2220

0.1UF

CERM

10V 402

20%

PLACEMENT_NOTE=Place in GMCH cavity

2

1

C2217

PLACEMENT_NOTE=Place in GMCH cavity

0.1UF

CERM

10V

20%

402

2

1

C2216

PLACEMENT_NOTE=Place in GMCH cavity

0.47UF

10%

6.3V CERM-X5R 402

2

1

C2215

PLACEMENT_NOTE=Place in GMCH cavity

10uF

20%

6.3V X5R 603

2

1

C2213

CERM

22UF

20%

PLACEMENT_NOTE=Place in GMCH cavity

805

6.3V

2

1

C2212

20%

470UF

TANT

D2T

2.5V

CRITICAL

32

1

C2210

CERM 402

6.3V

10%

1UF

2

1

C2226

10

402

1/16W MF-LF

1%

NO STUFF

21

R2285

0402-LF

120-OHM-0.3A-EMI

21

L2288

PLACEMENT_NOTE=Place in GMCH cavity

1UF

CERM

10%

6.3V 402

2

1

C2214

402

6.3V CERM

1UF

10%

2

1

C2265

1/10W

5%

0.300

FF 603

2

1

R2266

6.3V X5R

20%

10UF

603

2

1

C2266

0.1UF

20%

402

CERM

10V

2

1

C2230

6.3V X5R 603

10UF

20%

2

1

C2285

SOT23-5

TPS731125

CRITICAL

5 4

1

2

3

U2265

402

16V

0.01UF

CERM

10%

2

1

C2267

NO STUFF

SOD-723

1SS418

2 1

D2285

TPS79933

SON

CRITICAL

7

1

2

5

6

3

4

U2280

15B3 60C6

402

22K

5% MF-LF

1/16W

2

1

R2245

NO STUFF

1/16W

5%

22K

402

MF-LF

2

1

R2250

NO STUFF

402

22K

5% MF-LF

1/16W

2

1

R2244

NO STUFF

1/16W MF-LF

5%

22K

2

1

R2243

402

1

402

22K

5% 1/16W MF-LF

2

R2249

R2248

5%

22K

402

MF-LF

1/16W

2

1

5%

1

R2242

22K

402

1/16W MF-LF

2

NO STUFF

5% MF-LF

402

R2247

1/16W

2

22K

1

051-7559

22

SYNC_DATE=06/15/2006

SYNC_MASTER=WFERRY

106

H

NB Graphics Decoupling

=PP5V_S0_NB_TVDAC

=PP1V5_S0_NB_TVDAC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V5_S0_NB_VCCD_QDAC

VOLTAGE=1.5V

PP3V3_S0_NB_TVDAC

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0_NB_VCCTXLVDS

=PP3V3_S0_NB_VCCHV

=GND_NB_VSSA_DAC_BG

P3V3TVDAC_EN_RC

=PP1V8_S0_NB_DPLL

PP3V3_S0_NB_VCCA_CRTDAC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_S0_NB_VCCA_TVDACA

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_NB_VCCA_TVDACC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_NB_VCCA_DAC_BG

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_NB_TVDAC_F

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0_NB_VCCA_DPLLB

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

P3V3TVDAC_NOISE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_NB_TVDAC_FOLLOW

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0_NB_DPLL_RF

P1V25S0NBDPLL_FB

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V5_S0_NB_VCCD_CRT

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM VOLTAGE=1.5V

PP1V5_S0_NB_VCCD_TVDAC

MAKE_BASE=TRUE

PP1V5_S0_NB_VCCD_CRT

=PP1V5_S0_NB_VCCD_CRT

=GND_NB_VSSA_LVDS

=PP1V5_S0_NB_FOLLOW

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_VCCA_DPLLA

VOLTAGE=1.25V

=PPVCORE_S0_NB_GFX

PP3V3_S0_NB_CRTDAC_F

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

=PP1V8_S0_NB_VCCD_LVDS

PP1V25_S0_NB_DPLL

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

=PP3V3_S0_NB_VCCSYNC

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 MM

PP3V3_S0_NB_VCCA_TVDACB

=PP1V8_S0_NB_LVDS

PP1V5_S0_NB_QDAC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.5V

GFX_VID<2>

GFX_VID<1>

GFX_VID<0>

GFX_VID<3>

20A8 18B3

48B3

15C7

17D5

18C6

15B7

17B7

18D6

7A7

7B7

18B6

18B3

7D4

18D6

7B7

18D6

18B6

18D6

21C5

18B6

21D6

18B6

18C6

7B7

18D6

7B7

18A6

7C4

18B6

7B7

Preliminary

SATA0RXP

SATA0RXN

SATALED*

RTCRST*

HDA_BIT_CLK

DDREQ

RTCX1

RTCX2

DCS1* DCS3*

IDEIRQ

DDACK*

IORDY

DIOR* DIOW*

DD11 DD12

DD4

DD2

DD14

DD0

DD15

DD1

DD13

DD5

DD10

DD8

DD3

DD9

LDRQ0*

FWH2/LAD2 FWH3/LAD3

FWH1/LAD1

LDRQ1*/GPIO23

FWH0/LAD0

FWH4/LFRAME*

HDA_SDIN0

HDA_SYNC

SATA1TXN

SATA1TXP

HDA_SDIN1

HDA_SDIN2

RCIN*

SATA0TXP

SATA0TXN

CPUPWRGD/GPIO49

SMI*

A20M*

SATA1RXP

SATA1RXN

SATARBIAS

SATARBIAS*

IGNNE*

DPRSTP*

INTVRMEN

A20GATE

SATA2RXN

SATA2RXP

THRMTRIP*

DPSLP*

INIT*

HDA_RST*

HDA_SDOUT

HDA_DOCK_EN*/GPIO33

SATA2TXN

SATA2TXP

FERR*

NMI

HDA_SDIN3

INTR

SATA_CLKP

SATA_CLKN

DA2

DD6

STPCLK*

TP8

DA0 DA1

HDA_DOCK_RST*/GPIO34

INTRUDER*

LAN_TXD0

LAN100_SLP

LAN_RSTSYNC

LAN_RXD0

LAN_RXD1

LAN_RXD2

DD7

LAN_TXD2

LAN_TXD1

GLAN_DOCK*/GPIO13

GLAN_COMPI

GLAN_COMPO

GLAN_CLK

LAN/GLANIHDA

CPU

RTC

LPC

(1 OF 6)

SATA

IDE

OUT

IN

BI

BI BI

BI

OUT

IN

OUT

IN

IN OUT OUT

IN

OUT

IN

OUT OUT

IN

OUT

OUT OUT OUT

IN IN IN

BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

INT PU

INT PD

INT PD INT PD

INT PD

INT PU INT PD

INTEGRATED PD

INTEGRATED PDs

ACZ_SYNC

HDA_SDOUT

HDA_SDIN[0-2]

HDA_RST#

HDA_BIT_CLK

24.000MHZ CLOCK W/INTERNAL WEAK PD

HDA

INT PD

INT PU

ICH8M

BGA

OMIT

AA23

AE27

AA24

AG28

AG1 AG2

AF10

AC6

AB7

AE3

AE4

AF1

AF2

AJ3

AJ4

AG4

AG3

AH6

AH5

AF5

AF6

AF24

AG25

AF23

AH14

AD23

E6

G9

C20

E20

D21

C22

B21

C21

D22

AD21

Y1

AF25

AD22

AC20

AE24

AF27

Y3

AJ15

AE13

AD13

AH15

AH17

AJ17

AE14

AG14

AE10

AJ16

AH21

C25

D25

B24

C4

F6

G8

F5

E5

AD24

AE26

AF26

W3

W4

W5

Y2

R2

T3

T6

AB2

T5

V4

T1

V3

U6

V2

U1

V5

V6

T4

U2

V1

Y5

Y6

AB3

AA1

AA4

AG29

AG26

AF13

U2300

27C8

27D5

27C5

6D2

44C8 46C6

6C2

44C8 46C4

6C2

44C8 46C4

6D2

44C8 46C6

6C2

44C8 46B6

9C8

70C3

NO STUFF

2.2K

5% 1/16W MF-LF

402

2

1

R2304

1/16W MF-LF

24.9

1%

402

2

1

R2302

1/16W

402

MF-LF

332K

1%

2

1

R2301

40C4 73D3

40D4 73D3

8D4

29C3 75B3

40D2

9B2

15B6 59C7 70B3

9B2

70B3

9C8

70C3

9B2

12B1 70C3

39C3 73D3

39B5 73D3

39B3 73D3

39B5 73D3

39C3 73D3

39C5 73D3

39C3 73D3

39B5 73D3

39B3 73D3

9B8

70B3

9B8

70C3

9B8

70B3

9C8

70B3

9D6

46B2 70B3

9B8

70C3

1/16W

5%

402

MF-LF

10K

2

1

R2306

9C6

15A6 45B3 70B3

402

24.9

1/16W MF-LF

1%

PLACEMENT_NOTE=Place R2308 within 50mm of U2300

21

R2308

8A6

73C3

MF-LF

402

332K

1%

1/16W

2

1

R2300

402

MF-LF

1/16W

5%

8.2K

2

1

R2303

8A6

73C3

8A6

73C3

8A6

73B3

8A6

73C3

8.2K

5% 1/16W MF-LF

402

2

1

R2310

54.9

402

MF-LF

1/16W

1%

2

1

R2305

PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)

54.9

402

MF-LF

1/16W

1%

2

1

R2309

5%

1/16W MF-LF33402

21

R2313

402

33

MF-LF1/16W

5%

21

R2314

402

5%

MF-LF

33

1/16W

21

R2315

33

402

MF-LF1/16W

5%

21

R2316

5%

10K

MF-LF 402

1/16W

2

1

R2311

39B3 73D3

39B5 73D3

SB Enet, Disk, FSB, LPC

SYNC_DATE=10/30/2006

SYNC_MASTER=T9_MLB

051-7559

106

23

H

PP3V3_G3_SB_RTC

SB_RTC_X1 SB_RTC_X2

HDA_DOCK_EN_L

LAN_ENERGY_DET

=PP3V3_S0_SB_GPIO

PP1V5_S0_SB_VCC1_5_B

GLAN_COMP

SB_INTVRMEN SB_LAN100_SLP

SB_SM_INTRUDER_L

SB_RTC_RST_L

TP_LAN_R2D<2>

LPC_AD<2>

LPC_AD<0> LPC_AD<1>

LPC_AD<3>

LPC_FRAME_L

EXTGPU_PWR_EN

PM_THRMTRIP_L

CPU_THERMTRIP_R

CPU_A20M_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD

CPU_IGNNE_L

CPU_INIT_L CPU_INTR

CPU_NMI CPU_SMI_L

CPU_STPCLK_L

IDE_PDD<0>

IDE_PDD<2>

IDE_PDD<1>

IDE_PDD<3> IDE_PDD<4> IDE_PDD<5>

IDE_PDD<7>

IDE_PDD<6>

IDE_PDD<8>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<12>

IDE_PDD<11>

IDE_PDD<13>

IDE_PDD<15>

IDE_PDD<14>

IDE_PDA<0> IDE_PDA<1> IDE_PDA<2>

IDE_PDCS3_L

IDE_PDCS1_L

IDE_PDIOW_L

IDE_PDIOR_L

IDE_PDDACK_L IDE_IRQ14 IDE_PDIORDY IDE_PDDREQ

=PP1V05_S0_SB_CPU_IO

=PP3V3_S0_SB_GPIO

CPU_FERR_L

SB_A20GATE

TP_LPC_DRQ0_L

SB_RCIN_L

TP_SB_TP8

TP_LAN_D2R<2>

SATA_A_D2R_P

TP_SB_SATALED_L

SATA_A_R2D_C_P

SATA_A_R2D_C_N

SATA_B_D2R_P

SATA_B_D2R_N

TP_HDA_DOCK_RST_L

TP_LAN_R2D<0>

TP_LAN_RSTSYNC

TP_LAN_D2R<0>

TP_LAN_R2D<1>

SATA_B_R2D_C_N SATA_B_R2D_C_P

SATA_C_D2R_P

SATA_C_D2R_N

SATA_C_R2D_C_N SATA_C_R2D_C_P

SB_CLK100M_SATA_P

SB_CLK100M_SATA_N

SATA_RBIAS_P

SATA_RBIAS_N

HDA_BIT_CLK_R HDA_SYNC_R

HDA_RST_L_R

HDA_SDOUT_R

HDA_SYNC

HDA_BIT_CLK

HDA_RST_L

HDA_SDOUT

SATA_A_D2R_N

TP_HDA_SDIN1

TP_ENET_GLAN_CLK

TP_LAN_D2R<1>

HDA_SDIN0

TP_HDA_SDIN3

TP_HDA_SDIN2

24D8

26C6

24D8

27D4

24B3

26A4

26C4

24B3

26A5

22D2

25D6

25C3

22D7

25D6

7D4

23C2

74B3

7D7

7D4

73C3

73B3

8A6

Preliminary

SPI_CS1*

PETN1

PERP1

OC4*/GPIO43 OC5*/GPIO29 OC6*/GPIO30 OC7*/GPIO31 OC8* OC9*

SPI_MOSI

OC0* OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42

PERN5

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI_CLKN DMI_CLKP

PETP1

USBP9N USBP9P

PERN2

USBP7N USBP7P USBP8N USBP8P

PETN2

USBP6N USBP6P

PERP3

USBP4N USBP4P USBP5N USBP5P

PETN3

PETP3

USBP3N USBP3P

PERN4 PERP4

USBP1N USBP1P USBP2N USBP2P

PETN4 PETP4

USBP0N USBP0P

PERP5

SPI_MISO

USBRBIAS

USBRBIAS*

PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0*

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI_IRCOMP

DMI_ZCOMP

PERN1

PERP2

PETP2

PERN3

PETN5

PCI_EXPRESS

DIRECT MEDIA INTERFACE

SPI

USB

(2 OF 6)

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

IN OUT OUT

IN

IN OUT OUT

BI BI

BI

AD4 AD5

AD9

PIRQF*/GPIO3

PIRQE*/GPIO2

AD13

PME*

PCIRST*

GNT2*/GPIO53

C/BE2*

PIRQG*/GPIO4

SERR*

PIRQA*

AD1

REQ1*/GPIO50

C/BE3*

AD11

C/BE1*

AD25 AD26

AD0

AD2

DEVSEL*

AD18

AD21

PAR

GNT0*

AD7

GNT1*/GPIO51

C/BE0*

STOP*

AD20

AD16

GNT3*/GPIO55

TRDY*

IRDY*

AD22

PIRQC*

REQ2*/GPIO52

AD19

PCICLK

PLOCK*

AD15

PIRQB*

PIRQH*/GPIO5

PLTRST*

AD3

AD6

AD8

FRAME*

AD14

AD12

AD10

REQ3*/GPIO54

PIRQD*

AD17

PERR*

REQ0*

AD31

AD27 AD28

AD30

AD29

AD24

AD23

(3 OF 6)

INTERRUPT I/F

PCI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

IN

BI

BI BI

OUT

BI BI BI

BI

OUT

IN

BI BI

IN

IN IN IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

selects SPI ROM by default.

NOTE: USBP[0-9]P/N have internal 15K pull-downs.

IR

Bluetooth

External D / WWAN

External A

Geyser Trackpad/Keyboard

External B

ExpressCard

AirPort (PCIe Mini-Card)

Camera

External C

INT PD

EHCI0

INT PD

INT PU

EHCI1

INT PD

Spares

ExpressCard

FireWire

(AirPort)

Ethernet

(x2-capable, pull HDA_SYNC high for x2)

SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

SB BOOT BIOS SELECT

INT PU

1

GNT0#

0

NOTE:

LPC

I/F

SPI

FireWire INT*

INT PU

If used, ensure GNT2# is not low when PWROK

enabled only when PCIRST# = 0 and PWROK = 1

Yukon-PCIE Nineveh-GLCI

R2415 pull-down on GNT0#

Provide a pull-down on this GPIO if not used.

NOTE: GNT[0-3]# have internal 20K pull-ups

rises, or PCIe ports 5 & 6 will be disabled.

PCIe Mini Card

MF-LF

1/16W

402

10K

5%

2

1

R2408

5%

10K

402

MF-LF

1/16W

2

1

R2407

MF-LF

1/16W

5%

402

10K

2

1

R2400

10K

5%

MF-LF 402

1/16W

2

1

R2409

1/16W

10K

5%

402

MF-LF

2

1

R2401

10K

MF-LF

1/16W

5%

402

2

1

R2402

5%

10K

MF-LF

1/16W

402

2

1

R2404

5% 1/16W

402

MF-LF

10K

2

1

R2403

OMIT

ICH8M

BGA

F2

F3

N2

N3

M1

M2

M4

M5

L2

L3

K1

K2

K4

K5

J2

J3

H1

H2

H4

H5

G2

G3

D23 F21

E22

B23

C23

C28

E28

G28

J28

L28

N28

C29

E29

G29

J29

L29

N29

D26

F26

H26

K26

M26

P26

D27

F27

H27

K27

M27

P27

AH18

AD14

AJ18

AD12

AG17

AF15

AE15

AG15

AG16

AJ19

Y23 Y24

T25

T26

AC28

AC29

AD26

AD27

AA28

AA29

AB25

AB26

W28

W29

Y26

Y27

U28

U29

V26

V27

U2300

15B3 71D3

15C3 71D3

15B3 71D3

15C3 71D3

15B3 71D3

29C3 75B3

24.9

1/16W MF-LF

402

1%

21

R2413

8C1

73B3

8C1

73B3

8C1

73B3

8C1

73B3

8C1

73B3

8C1

73B3

8C1 8C2

73B3

8C1 8C2

73B3

8C1

73B3

8C1

73B3

8B1 8B2

73B3

8C1 8C2

73B3

8B1

73B3

8B1

73B3

8B1

73B3

8B1

73B3

8B1

73B3

8B1

73B3

1/16W

1%

402

MF-LF

22.6

21

R2414

33B6

34C8

52C7 73A3

52C3 73A3

ICH8M

BGA

OMIT

C9

C16

F10

A11

B19

E18

A4

G7

AG24

B7

B3

F12

G11

F8

A10

C5

B5

F9

A7

G6

B10

D9

C8

C10

F18

C18

D7

A17

D16

E17

F16

E15

C17B16

A18

C19

A19

A21

D17

A3

D6

A20

E8

A6

D8

E12

E13

E11

F13

C7

D10

C12

D19

B12

D11

A9

C11

B6

A15

G16

A14

E16

A12

E19

D20

U2300

37C5 74D3

37B5 74D3

37B6 74D3

37B5 74D3

23A4 74C3

23A4 37A5 74C3

23A4 74D3

23A4 37A5 74D3

23A4 74D3

37B5 74D3

23A4 37A5 74D3

37B5 74D3

37A6

23A4 37A5 74D3

23A4 74D3

23A4 37A5 74D3

27D4 67C6

29A5 29B3 75B3

23A4 74C3

10K

1/16W MF-LF 402

5%

2

1

R2405

NOSTUFF

402

100K

MF-LF

5%

1/16W

2

1

R2406

402

5% 1/16W

1K

MF-LF

2

1

R2415

8.2K

21

R2423

8.2K

21

R2424

8.2K

21

R2425

8.2K

21

R2426

8.2K

21

R2427

8.2K

21

R2428

8.2K

21

R2430

8.2K

21

R2429

8.2K

21

R2432

8.2K

21

R2431

8.2K

21

R2433

8.2K

21

R2437

8.2K

21

R2439

8.2K

21

R2438

8.2K

21

R2436

8.2K

21

R2440

23A4 74C3

8.2K

21

R2441

8C1

8B1

23A4 39C8

68A4 68B8

37A5 74D3

39A8 73D3

6C2

46B6

8.2K

21

R2442

39B8

33B6

SB PCI, PCIe, DMI, USB

SYNC_MASTER=T9_MLB

H

24

106

051-7559

SYNC_DATE=10/30/2006

SB_GPIO42

=PP3V3_S5_SB_USB

EXTGPU_LVDS_EN

PCI_FW_GNT_L

MAKE_BASE=TRUE

TP_SB_GPIO55

TP_SB_GPIO51

ODD_RST_5VTOL_L

SB_GPIO30

USB_EXTA_OC_L

USB_EXTB_OC_L EXCARD_OC_L

SB_GPIO40 USB_EXTD_OC_L

USB_EXTC_OC_L

ODD_PWR_EN_L

INT_PIRQF_L

INT_PIRQE_L

PCI_FRAME_L

PCI_TRDY_L

PCI_STOP_L

PCI_LOCK_L

PCI_PERR_L

PCI_RST_L

PCI_PAR

PCI_FW_REQ_L

TP_SB_GPIO53

PCI_C_BE_L<0>

PCI_C_BE_L<2>

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

TP_SPI_CE_R_L<1>

PCI_DEVSEL_L

PM_LATRIGGER_L

TP_PCIE_A_R2D_C_P

PCI_AD<14>

PCI_AD<4> PCI_AD<5>

PCI_AD<9>

PCI_AD<13>

INT_PIRQA_L

PCI_AD<1>

PCI_AD<11>

PCI_AD<25> PCI_AD<26>

PCI_AD<0>

PCI_AD<2>

PCI_AD<18>

PCI_AD<21>

PCI_AD<7>

PCI_AD<20>

PCI_AD<16>

PCI_AD<22>

INT_PIRQC_L

PCI_AD<19>

PCI_AD<15>

INT_PIRQB_L

PCI_AD<3>

PCI_AD<6>

PCI_AD<8>

PCI_AD<12>

PCI_AD<10>

INT_PIRQD_L

PCI_AD<17>

PCI_AD<31>

PCI_AD<27> PCI_AD<28>

PCI_AD<30>

PCI_AD<29>

PCI_AD<24>

PCI_AD<23>

BOOT_LPC_SPI_L

PCI_REQ1_L

PCI_C_BE_L<3>

PCI_SERR_L

PCI_REQ1_L

PCI_TRDY_L

INT_PIRQE_L

INT_PIRQD_L

INT_PIRQB_L

INT_PIRQA_L

PCI_REQ2_L

PCI_STOP_L

PCI_IRDY_L

PCI_FRAME_L

PCI_FW_REQ_L

PCI_LOCK_L

INT_PIRQF_L

INT_PIRQC_L

ODD_PWR_EN_L

PCI_SERR_L PCI_DEVSEL_L PCI_PERR_L

=PP3V3_S0_SB_PCI

PP1V5_S0_SB_VCC1_5_B

USB_RBIAS

DMI_IRCOMP_R

TP_PCIE_A_R2D_C_N

TP_PCIE_A_D2R_P

SPI_SI_R

PCIE_MINI_D2R_N

TP_PCIE_B_D2R_N

TP_PCIE_B_R2D_C_N

TP_PCIE_EXCARD_D2R_P TP_PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_FW_D2R_N TP_PCIE_FW_D2R_P TP_PCIE_FW_R2D_C_N TP_PCIE_FW_R2D_C_P

PCIE_MINI_D2R_P

PCIE_ENET_D2R_N

SPI_SCLK_R SPI_CE_R_L<0>

TP_PCIE_A_D2R_N

TP_PCIE_B_D2R_P

TP_PCIE_B_R2D_C_P

TP_PCIE_EXCARD_D2R_N

USB_EXTC_P

USB_EXCARD_P USB_EXTC_N

USB_EXCARD_N

USB_EXTB_P

USB_EXTB_N

USB_BT_P

USB_TPAD_P USB_BT_N

USB_TPAD_N

USB_IR_P

USB_IR_N

USB_CAMERA_N USB_CAMERA_P

USB_EXTD_P

USB_EXTD_N

USB_MINI_P

USB_MINI_N

USB_EXTA_P

USB_EXTA_N

SB_CLK100M_DMI_P

SB_CLK100M_DMI_N

DMI_S2N_P<3>

DMI_S2N_N<3>

DMI_N2S_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>

DMI_S2N_N<2>

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_S2N_P<1>

DMI_S2N_N<1>

DMI_N2S_P<1>

DMI_N2S_N<1>

DMI_S2N_P<0>

DMI_S2N_N<0>

DMI_N2S_P<0>

DMI_N2S_N<0>

PCI_IRDY_L

PCIE_ENET_R2D_C_N

SPI_SO

PCI_C_BE_L<1>

PLT_RST_L

PCI_REQ2_L

PCI_CLK33M_SB TP_PCI_PME_L

DVI_HOTPLUG_DET

26C6

74D3

74C3

74D3

26A4

74D3

37A5

74C3

37A5

74C3

74D3

37A5

74D3

74C3

39C8

37A5

25D6

7D1

8D4

23B6

23A6

23A8

23B6

23A6

23B6

23A6

23A8

23A6

7C4

22D7

73B3

8D4

8C4

8D4

8C4

Preliminary