Apple A1151 Schematic Rev06

ANGLES

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DATE

APPD

ENG

DATE

APPD

CK

ECN

ZONE

REV

DO NOT SCALE DRAWING

X.XXX

X.XX

XX

DIMENSIONS ARE IN MILLIMETERS

THIRD ANGLE PROJECTION

D

SIZE

APPLICABLE

NOTED AS

MATERIAL/FINISH

NONE

SCALE

DESIGNER

MFG APPD

DESIGN CK

RELEASE

QA APPD

ENG APPD

DRAFTER

METRIC

OF

SHT

DRAWING NUMBER

TITLE

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

Apple Computer Inc.

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

DESCRIPTION OF CHANGE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

(6.0.0)

DVT

3/3/2006

Schematic / PCB #’s

M9 MLB

Sully

ALIASES RESOLVED

FireWire Port Power

45

(M1_MLB)

43

(11/03/2005)

FW PHY Power Supply

44

(MASTER)

42

(MASTER)

Yukon Power Control

43

M1_MLB

41

02/10/2006

Ethernet Connector

42

M1_MLB

40

02/10/2006

ETHERNET CONTROLLER

41

M1_MLB

39

02/10/2006

FireWire PHY (TSB83AA22)

40

(MASTER)

38

(MASTER)

FireWire Link (TSB83AA22)

39

(MASTER)

37

(MASTER)

PATA Connector

38

M1_MLB

36

02/10/2006

Mobile Clocking

37

M1_MLB

35

02/10/2006

Clock Termination

34

M1_MLB

34

02/10/2006

CLOCKS

33

M1_MLB

33

02/10/2006

DDR2 VRef

32

M1_MLB

32

12/19/2005

Memory Vtt Supply

31

M1_MLB

31

02/10/2006

Memory Active Termination

30

(M1_MLB)

30

(11/07/2006)

DDR2 SO-DIMM Connector B

29

M1_MLB

29

02/10/2006

DDR2 SO-DIMM Connector A

28

M1_MLB

28

02/10/2006

M1 SMBus Connections

27

M1_MLB

27

01/04/2006

SB Misc

26

M1_MLB

26

02/10/2006

SB Decoupling

25

M1_MLB

25

02/10/2006

SB: 4 OF 4

24

M1_MLB

24

02/10/2006

SB: 3 OF 4

23

M1_MLB

23

02/10/2006

SB: 2 of 4

22

M1_MLB

22

02/10/2006

SB: 1 OF 4

21

M1_MLB

21

02/10/2006

NB Config Straps

20

M1_MLB

20

02/10/2006

NB (GM) Decoupling

19

M1_MLB

19

02/08/2006

NB Grounds

18

M1_MLB

18

02/10/2006

NB Power 2

17

M1_MLB

17

02/10/2006

NB Power 1

16

M1_MLB

16

02/10/2006

NB DDR2 Interfaces

15

M1_MLB

15

02/10/2006

NB Misc Interfaces

14

M1_MLB

14

02/10/2006

NB PEG / Video Interfaces

13

M1_MLB

13

02/10/2006

NB CPU Interface

12

M1_MLB

12

02/10/2006

CPU ITP700FLEX DEBUG

11

M1_MLB

11

02/10/2006

CPU MISC1-TEMP SENSOR

10

M1_MLB

10

02/10/2006

CPU Decoupling & VID

9

M1_MLB

9

02/08/2006

CPU 2 OF 2-PWR/GND

8

M1_MLB

8

02/10/2006

CPU 1 OF 2-FSB

7

M1_MLB

7

02/10/2006

Signal Aliases

6

(M1_MLB)

6

(11/11/2005)

Functional / ICT Test

5

(MASTER)

5

(MASTER)

BOM Configuration

4

(MASTER)

4

(MASTER)

Power Block Diagram

3

(MASTER)

3

(MASTER)

System Block Diagram

2

(MASTER)

2

(MASTER)

86

104

M1_MLB

02/10/2006

M1 Net Properties

85

103

M1_MLB

02/10/2006

M1 Spacing & Physical Constraints

84

102

M1_MLB

02/10/2006

More System Constraints

83

101

M1_MLB

02/10/2006

Napa Platform Constraints

82

100

(MASTER)

Revision History

81

99

M1_MLB

12/19/2005

LVDS Interface Pull-downs

80

98

(MASTER)

M9 Specific Connectors

79

97

M1_MLB

11/18/2005

External Display Connector

78

94

M1_MLB

01/09/2006

Internal Display Connectors

77

93

M1_MLB

02/10/2006

ATI M56 Video Interfaces

76

91

M1_MLB

02/10/2006

ATI M56 GPIO/DVO/Misc

75

90

M1_MLB

02/10/2006

GDDR3 Frame Buffer B

74

89

M1_MLB

02/10/2006

GDDR3 Frame Buffer A

73

88

M1_MLB

02/10/2006

GPU Straps

72

87

M1_MLB

02/10/2006

ATI M56 Frame Buffer I/F

71

86

M1_MLB

02/10/2006

ATI M56 Core Power

70

85

M1_MLB

02/10/2006

GPU (M56) Core Supplies

69

84

M1_MLB

02/10/2006

ATI M56 PCI-E

68

83

M1_LIO

12/19/2005

PBus Supply & Batt. Charger

67

82

(MASTER)

DC-In & Battery Connectors

66

81

M1_MLB

12/19/2005

Power Aliases

65

80

M1_MLB

02/10/2006

3.3V G3Hot Supply & Power Control

64

79

M1_MLB

02/10/2006

3.3V / 1.05V Power Supplies

63

78

M1_MLB

02/10/2006

1.8V Supply

62

77

M1_MLB

02/10/2006

2.5V & 1.2V Regulators

61

76

M1_MLB

02/10/2006

5V / 1.5V Power Supply

60

75

M1_MLB

02/08/2006

IMVP6 CPU VCore Regulator

59

67

M1_MLB

02/10/2006

TPM

58

66

M1_MLB

02/10/2006

Sudden Motion Sensor (SMS)

57

65

M1_MLB

02/10/2006

Fan Connectors

56

64

M1_MLB

02/10/2006

ALS Support

55

63

M1_MLB

02/10/2006

SPI BOOTROM

54

62

M1_MLB

01/05/2006

Current & Voltage Sensing

53

61

M1_MLB

02/10/2006

Thermal Sensors

52

60

M1_MLB

02/10/2006

LPC+ Debug Connector

51

59

M1_MLB

02/10/2006

SMC Support

50

58

M1_MLB

02/10/2006

SMC

49

57

M1_MLB

02/10/2006

PCI-E Connections

48

56

(MASTER)

Current & Thermal Sensors

47

55

(MASTER)

Left I/O Board Connector

46

52

M1_MLB

02/10/2006

External USB Connector

45

49

M1_MLB

02/10/2006

Internal USB Connections

Page Contents

(.csa)

Date

Sync

Table of Contents

1

N/A

1

N/A

Contents

Date

(.csa)

SyncPage

44

46

(MASTER)

FireWire Ports

TITLE=SULLY

ABBREV=DRAWING

LAST_MODIFIED=Fri Mar 3 17:59:45 2006

PCBF,SULLY,FINAL,M9

820-2023 CRITICAL

PCB

1

CRITICAL

SCH

1

051-7023

SCHEM,SULLY,M9

?

? ??

?

86

1

051-7023

SCHEM,SULLY,M9

06

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

P.82

Connector

Temperature

Sensors

P.48,53

P.39

P.41

P.37-38

Controller

TSB83AA22 FireWire

P.44

Connectors

HDD/BT/IR

P.80

USB x2

w/TV-Out Support

SENSOR

& REGULATOR

DDR2 VTT

Upper Connector

Lower Connector

DDR2 SO-DIMM A

J2800

J2900

Connector

Audio Board

Left I/O &

DDR2 VREF

BUFFER

Azalia (HD-Audio)

PCIe x1

Connector

ITP700FLEX

CPU Debug

479 BGA

CH.A

CH.B

FSB

NB

1466UFCBGA

945GM

Core Duo

(Yonah)

CPU

THERMAL

ATI M56P

GDDR3

S-Video/Composite

Dual-Channel LVDS

Dual-Channel TMDS

PWM

USB

609 BGA

Debug

LPC

Connector

Sensors

SMC

SPI

BootROM

SMBus

USB

SATA

USB

SB SMBus

PATA

66MHZ 16BITS

CK410 Clock

Controller

TP Connector

Geyser KB /

Connector

ODD

Connector

LCD Panel

CONNECTOR

INVERTER

Yukon PowerYukon Gig-E

PCI

Controller

FW

SMS

Fan

Connectors

PWM/Tach

SMC SMBus

DDR2 SO-DIMM B

Battery SMBus

Analog

SMBus x5

H8S/2116

Connector

Right USB 2.0

GPU

128MB/256MB

Frame Buffer

ENET

DVI-I/DL Connector

P.78

P.78,81

P.79

P.69-73,76-77

P.74-75

P.10

P.7-9

P.11

P.12-20

P.47

P.30-31

P.29

P.28

P.32

P.46

P.45

P.36

P.33-34

P.27

PCIe x1

Connectors

P.50-51

P.52

P.55

P.56

P.57

P.58

P.59

Power

RT ALS

Camera

USB x2

P.40

Connector

RJ45 (Ethernet)

Supplies

P.43

Port Power

1394a/b (FireWire)

P.42

PHY Power

TPM

LPC 33MHZ

P.21-26

SB

ICH7-M

P.54

P.68

PBUS Supply

Batt Chgr/

PCIe x1

DMI x4

PCIe x16

P.60-67,70

051-7023

86

2

06

System Block Diagram

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PPBUS_G3H_B

12.6V - 9V

PPBUS_G3H_A

18.5V - 9V

PP1V8_S3

1.8V

Q7615

U8000

ENABLE

(LT3470)

SMC_PM_G2_ENABLE

U7900

3.3V

PPVCORE_S0_GPU

PP2V5_S3

S3

PGOOD

IMVP_PWRGD_IN

PPDCIN_G3H

J5500

U7530

(ISL6262)

PP3V3_S5

PP1V05_S0

1.05V

PM_SLP_S3_L

PP3V42_G3H

Q7845

ENABLES

PPVCORE_S0_CPU

NC

U7750

Q7770

Q7720

"IMVP6"

PGOOD

RSMRST_PWRGD

3.3V

PP3V3_S3

Q7610

LIO Power

J5500

Inverter

Connector

PM_SLP_S3_LS5V

PPBUS_S5_FWPORT

12.6V - 9V

FWPWR_EN

5V/1.5V

U8500

PP3V3_S0

NC

1.5V

PGOOD

(ISL6269)

S5

3.3V

ENABLE

?V

PGOOD

1.05V

U7950

1.2V - 1.0V

S0

(ISL6269)

GPU VCore

ENABLE

3.3V

NC

(LTC3412)

S3

PGOOD

1.2V

ENABLE

1.2V

PP1V2_S3

2.5V

PP2V5_S0

2.5V

(LTC3411)

2.5V

PGOOD

ENABLE

U7700

PP5V_S0

5.0V

PP5V_S3

PP1V5_S0

5.0V

PP5V_S5

NC

(LTC3728)

S5/S0

PGOOD

ENABLES

U7600

5V

1.5V

SMC_PM_G2_ENABLE

VR_PWRGOOD_DELAY

S0

CPU VCore

IMVP_VR_ON

(ISL6269)

S0

PM_SLP_S3_L

PM_SLP_S4_LS5V

PM_SLP_S3_LS5V

PM_SLP_S3_LS5V_L

ENABLE

NC

1.8V

U7800

S3

ENABLE

(ISL6269)

PGOOD

PM_SLP_S3_L

U3100

0.9V (Vtt) S0

(BD3533FVM)

PP0V9_S0

0.9V

Q4565

PP1V2_S0

1.2V

PM_SLP_S3_LS5V_L

PP1V8_S0

1.8V

5.0V

3.425V

G3Hot

3.425

J8200

LIO Flex

Connector

12.6V - 9V

Connector

PM_SLP_S4_L

IMVP_PWRGD_IN/ALL_SYS_PWRGD

PM_SLP_S3_L

PM_SLP_S4_LS5V

Q7945

Q7947

3 86

06

051-7023

Power Block Diagram

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

TABLE_ALT_ITEM

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

Module Parts

Bar Code Labels / EEE #’s

M9 Specific Aliases

IS

GPU_MEM_256M,VRAM_256_SAMSUNG

VRAM_256SAM

VRAM_256HY

GPU_MEM_HYNIX,GPU_MEM_256M,VRAM_256_HYNIX

SMC_BLANK

338S0274

1

CRITICAL

IC,SMC,HS8/2116

U5800

SMC_FINAL

IC,SMC,PRGRM,M9

341S1876

U5800

CRITICAL

1

338S0270 CRITICAL

U4101

1

IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

BOOTROM_BLANK

335S0384 CRITICAL

1

IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

U6301

ITP,ITPCONN,LPCPLUS

M9_DEBUG

LIO_TEMP,BOOTROM_DEVEL,SMC_DEVEL

M9_COMMON4

LVDS_PD,M56_REV_B24_LP,FW_B_BILINGUAL,FW_A_DS_ONLY,FW_PORT_FAULT_PU,FW_PLTRST_UNGATED

M9_COMMON3

ENET_LOM_DISABLE,ENETPWR_S3AC,GPUTHM_A_GPU,GPU_BB_CTL,HSTHMSNS_HAS,INVERTER_BUF,ONEWIRE_PU

M9_COMMON1

ALTERNATE,COMMON,M9_COMMON1,M9_COMMON2,M9_COMMON3,M9_COMMON4,M9_DEBUG

M9_COMMON

VRAM_128_SAMSUNG

VRAM_128SAM

1

343S0385

IC,SB,652BGA

CRITICAL

U2100

338S0269

IC,945GM,SOUTHBRIDGE

U1200

CRITICAL

1

CPU_2_16GHZ

U0700

1

CRITICAL

IC,CPU,479 BGA

337S3268

CPU_2_0GHZ

337S3267

IC,CPU,479 BGA

CRITICAL

1

U0700

337S3282

CPU_1_83GHZ

U0700

1

CRITICAL

IC,CPU,479 BGA

U6700

CRITICAL

1

IC, TPM, 28-PIN TSSOP

341S1789

IC,CY28445-5,CLOCK GEN,68PIN QFN

U3301

1

CRITICAL359S0101

1

IC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE

CRITICAL

U7530

353S1235

BOOTROM_FINAL

IC,EFI,BOOTROM FINAL,M9

341S1829 CRITICAL

1

U6301

BOOTROM_DEVEL

IC,EFI,BOOTROM DEVELOPMENT,M9

341S1828

U6301

1

CRITICAL

341S1797

U4102

IC,EEPROM,SERIAL IIC,8KBIT,SO8

1

CRITICAL

SMC_DEVEL

IC,SMC,PRGRM,M9

341S1876

1

CRITICAL

U5800

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

VRAM_256_HYNIX

CRITICAL

U8900,U8950,U9000,U9050

4

333S0351

VRAM_128_SAMSUNG

CRITICAL

U8900,U8950,U9000,U9050

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

4

333S0354

KBDLED_HAS,MEMVREF_S3,MEMVTT_EN_PU,RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PU

M9_COMMON2

GPU_MEM_HYNIX,VRAM_128_HYNIX

VRAM_128HY

VRAM_256SAM,M9_COMMON,CPU_2_16GHZ,EEE_UP1

630-7406

PCBA,SULLY,2.16GHz,M9

VRAM_256SAM,M9_COMMON,CPU_2_0GHZ,EEE_UNZPCBA,SULLY,2.0GHz,M9

630-7404

IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA

VRAM_128_HYNIX

CRITICAL

U8900,U8950,U9000,U9050

333S0358

4

333S0350

4

VRAM_256_SAMSUNG

U8900,U8950,U9000,U9050

CRITICAL

IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

M56_REV_B24_LL

U8400

338S0266

LP is alt to LL

338S0309

1.86 max alt to 1.9 max

128S0083 128S0073

C2516

376S0445376S0448

Vishay 2nd source

ALL

U8400

338S0266 338S0309

M56_REV_B24_LP

LL is alt to LP

B26_LP is alt to B24_LP

338S0315

U8400

338S0309

M56_REV_B24_LP

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL826-4393

1

EEE_UNZ

[EEE:UNZ]

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL

EEE_UP0

[EEE:UP0]

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

[EEE:UP1]

826-4393

EEE_UP1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

[EEE:UYU]

EEE_UYU

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:UP2]

CRITICAL826-4393

EEE_UP2

1

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

CRITICAL338S0302

M56_REV_B24_HL

U8400

1

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

1

CRITICAL338S0266

M56_REV_B24_LL

CRITICAL

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

338S0309

M56_REV_B24_LP

1

CRITICAL

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

1

338S0315

M56_REV_B26_LP

M56_REV_B26_P

338S0316 CRITICAL

IC,ATI,M56P,GRPHSCTRL,880BGA,LF

U8400

1

128S0093 128S0092

ALL

Kemet is alt to Sanyo

BOM Configuration

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

4 86

06

051-7023

C2 package is alt to C3

128S0061128S0081

ALL

Sanyo is alt to Panasonic

128S0094128S0060

ALL

128S0094128S0095

330uF,2V,6MOHM,D2

PP3V3_FWPHY

PPFW_PORTA_VP_UF

SMC_RSTGATE_L

MAKE_BASE=TRUE

PPFW_PORTB_VP_UF

PP3V3_FWPHY

PP3V3_S0

PP1V8_S3

PP1V95_FWPHY

PCI_REQ3_L

PCI_GNT3_L

MAKE_BASE=TRUE

LT2USB_OC_L

PP1V95_FWPHY

PPBUS_S5_FW_FET

MAKE_BASE=TRUE

PCI_AD<19>

MAKE_BASE=TRUE

LT2USB_OC_L

SMBUS_SMC_B_S0_SCL

PP1V95_FWPHY

MAKE_BASE=TRUE

VOLTAGE=1.95V

PP1V95_FWPHY

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

PP1V8_S3

PP5V_S0

MAKE_BASE=TRUE

SMC_RSTGATE_L

PP3V3_FWPHY

PPBUS_S5_FW_FET

PCI_GNT3_L

MIN_LINE_WIDTH=0.38 mm

VOLTAGE=3.3V

PP3V3_FWPHY

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PPBUS_S5_FW_FET

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

PCI_REQ3_L

PP3V3_FWPHY

PPBUS_S5_FW_FET

SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA

PPDCIN_G3H

PPBUS_G3H

PP3V3_S0

=FW_PCI_IDSEL PP5V_S0

PP3V3_S0

PPFW_PORTB_VP_UF

MAKE_BASE=TRUE

PPFW_PORTA_VP_UF

PPDCIN_G3H

PPBUS_G3H

79

78

70

66

65

64

60

59

57

56

53

51

48

43

37

80

37

80

37

36

79

36

79

36

34

78

34

78

34

33

70

33

70

33

29

67

29

67

29

28

66

28

66

28

27

65

78

27

65

27

78

26

66

61

70

26

61

26

70

25

63

60

68

25

60

25

68

24

54

57

66

24

57

24

66

23

37

56

64

23

56

23

64

22

32

54

63

22

54

22

63

21

31

52

61

21

52

21

61

20

29

47

44

60

20

47

20

60

44

19

28

42

44 43

44

54

19

42

19

54

43

17

19

66

50

42

19

36

43

66

42

66

50

43

66

50

68

47

17

36

17

68

47

42

14

16

42

37

47

42

43

47

48

42

38

16

31

42

43

38

43

48

37

42

43

48

67

43

14

31

14

67

43

38

44

50

44

38

10

14

38

26

37

22

38

42

22

27

38

5

14

25

50

38

42

37

5

42

27

26

38

42

27

66

41

10

25

10

44

66

41

5

43

37

43

5

22

5

38

37

5

10

5

4

5

37

5

38

22

4

38

10

22

5

38

10

65

5

43

65

5

4

22

4

37

4

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Request for at least 2 GND TPs per resistor

Camera Connector

FUNC_TEST

Resistor Calibration

(=PP3V3_S0_CK410)

FUNC_TEST

Left I/O Data Connector

FUNC_TEST

Functional Test Points

CPU FSB NO_TESTs

NO_TEST

EXPOSED_VIA

Battery Connector

FUNC_TEST

Fan Connectors

FUNC_TEST

Left I/O Power Connector

FUNC_TEST

SMC TPs

Power Nets

Request for at least 10 GND TPs

LPC+ Debug Connector

Request for at least 10 GND test points

Thermal Sensors

Misc EXPOSED_VIA Nets

opening for use as engineering probe point.

should have a via with 10-mil soldermask

EXPOSED_VIA property indicates that the net

FUNC_TEST

MAC-1 TPs

Characterization TPs

FUNC_TEST

Power Supply NO_TESTs

(=PP1V2_S3_ENET) (=PP3V3_S3_ENET) (=PP2V5_S3_ENET)

I134 I135

I138

I139

I140

I141

I142

I143

I164

I165 I166

I167

I168

I169

I170

I171

I172

I173

I174

I175

I176

I177

I178

I179

I182

I183 I184

I185

I186 I187

I188 I189

I190

I191 I192

I193

I194 I195

I197

I198

I199

I200

I201

I202 I203

I204

I205 I206

I207 I208

I209

I210 I211

I212

I213

I214

I215

I216 I217

I218

I219

I220

I221

I222

I223

I224 I225

I226I227

I228

I229 I230

I231

I232 I233

I234

I235

I236

I237 I238

I239

I240 I241

I242

I243 I244

I245 I246

I247

I248

I249

I250

I251

I252

I253

I254

I255

I256

I257

I258

I259 I260

I261

I262

I263

I264

Functional / ICT Test

5 86

06

051-7023

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

TRUE

PP2V5_S3

TRUE

PP2V5_S3_ENET_AVDD

TRUE

PM_SLP_S5_L

TRUE

P1V5P1V05S0_PGOOD

PP3V3_S0_CK410_VDDA

TRUE

PP3V3_S5

TRUE

PP5V_S3

IMVP_VR_ON

TRUE

PM_SLP_S3_L

TRUE

PM_SLP_S3BATT

P1V8S3_FSET

TRUE

PP3V3_S0_CK410_VDD_CPU_SRC

TRUE

PP3V3_S0_CK410_VDD_PCI

TRUE

PP3V3_S0_CK410_VDD48

TRUE

PP3V3_S0_CK410_VDD_REF

TRUE

PP3V3_S0

PP2V5_S0_GPU_LVDDR

TRUE

PP2V5_S0_GPU_LPVDD

TRUE

PP2V5_S0_GPU_A2VDD

TRUE

PP2V5_S0_GPU_AVDD

TRUE

PP2V5_S0_GPU_TXVDDR

TRUE

PP2V5_S0_GPU_TPVDD

TRUE

CPU_PWRGD

TRUE

NB_SB_SYNC_L

TRUE

FSB_DPWR_L

TRUE

FSB_SLPCPU_L

TRUE

FSB_CPURST_L

TRUE

VR_PWRGOOD_DELAY

TRUE

VR_PWRGD_CK410

TRUE

PM_STPPCI_L

TRUE

PM_STPCPU_L

TRUE

SB_RTC_RST_L

TRUE

PM_RSMRST_L

TRUE

PM_SB_PWROK

TRUE

PCI_RST_L

TRUE

PM_LAN_ENABLE

TRUE

CPU_DPSLP_L

TRUE

PM_DPRSLPVR

TRUE

TP_CPU_CPUSLP_L

TRUE

FSB_ADSTB_L<1..0>

TRUE

FSB_BREQ0_L

TP_SB_SUS_CLK

TRUE

CPU_THERMTRIP_R

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

NB_CLK100M_GCLKIN_N

TRUE

NB_CLK100M_GCLKIN_P

TRUE

CLK_NB_OE_L

TRUE

FSB_CLK_NB_N

TRUE

FSB_CLK_NB_P

TRUE

CPU_STPCLK_L

TPM_LRESET_L

TRUE

SMC_LRESET_L

TRUE

PEG_RESET_L

TRUE

PLT_RST_L

TRUE

PLT_RST_L

TRUE

FSB_CLK_CPU_N

IMVP6_VID<6..0>

TRUE

CPU_DPRSTP_L

TRUE

PM_SLP_S4_L

TRUE

IMVP_DPRSLPVR

DMI_N2S_P<1..0>

TRUE

DMI_N2S_N<1..0>

TRUE

SB_CLK100M_SATA_N

TRUE

SV_SET_UP

TRUE

PCI_CLK_PORT80_LPC

TRUE

LPC_AD<2>

TRUE

LPC_AD<3>

TRUE

FWH_INIT_L

TRUE

SMC_TX_L

TRUE

SMC_MD1

SMC_TRST_L

TRUE

DEBUG_RST_L

TRUE

BOOT_LPC_SPI_L

TRUE

PM_CLKRUN_L

TRUE

LPC_FRAME_L

TRUE

FAN_RT_PWM

TRUE

LPC_AD<0>

TRUE

LPC_AD<1>

SMC_TMS

TRUE

SMC_TDO

TRUE

INT_SERIRQ

TRUE

PM_SUS_STAT_L

TRUE TRUE

SMC_TDI SMC_TCK

TRUE

SMC_NMI

TRUE

SMC_RX_L

TRUE

ISENSE_CAL_EN

TRUE

USB2_CAMERA_N

TRUE

USB2_CAMERA_P

TRUE

HSTHMSNS_DX_P

TRUE

PP3V3_S3

TRUE

PP3V3_S0

TRUE

PP1V8_S3

TRUE

PP1V5_S0

PP0V9_S0

TRUE

PP1V05_S0

TRUE

SMC_BC_ACOK

TRUE

PCIE_WAKE_L

TRUE

PP18V5_DCIN

TRUE

PP5V_S5

TRUE

PP5V_S0_AUDIO_PWR GND_AUDIO_PWR

TRUE

PP1V8_S0

TRUE

PP2V5_S0

TRUE

PP5V_S0

TRUE

PP5V_S5

TRUE

GND

TRUE

PP2V5_S3

TRUE

PPBUS_G3H

PP1V05_S0

TRUE

PPVCORE_S0_GPU

TRUE

GND

TRUE

RSFSTHMSNS_D_P

TRUE

P2V5S3_MODE

TRUE

FSB_DSTBN_L<3..0>

TRUE TRUE

PP5V_S0

TRUE

PP5V_S0

TRUE

PP5V_S3

RSFSTHMSNS_D_N

TRUE

P1V5S0_RUNSS

TRUE

PP1V2_S0 PP1V2_S3

TRUE

GPUBBP_ADJ

TRUE

P1V05S0_COMP

TRUE

IMVP6_RBIAS

TRUE

P1V2S3_RUNSS

PP3V42_G3H

TRUE

PM_SYSRST_L

TRUE

SMC_ONOFF_L

TRUE

HSTHMSNS_DX_N

GND_AUDIO

TRUE

PP5V_S0_AUDIO

TRUE

PP3V42_G3H

PPBUS_G3H

TRUE

P1V8S3_COMP

SMBUS_SMC_BSA_SDA

TRUE

SMC_BS_ALRT_L

P2V5S3_SHDNRT

TRUE

P5VS5_RUNSS

TRUE

SB_CLK100M_SATA_P

TRUE

TRUE TRUE

FSB_DSTBP_L<3..0>

TRUE

FSB_HITM_L FSB_LOCK_L

TRUE TRUE

FSB_REQ_L<4..0>

FSB_BNR_L

TRUE

FSB_D_L<63..0>

FSB_ADS_L

TRUE

FSB_A_L<31..3>

TRUE

PP5V_S0

TRUE

FAN_LT_TACH

TRUE

FAN_RT_TACH

P3V3S5_FSET

TRUE

P3V3S5_COMP

TRUE

P1V2S3_RT

TRUE

FSB_DBSY_L

TRUE

FSB_HIT_L

TRUE

FSB_DRDY_L

TRUE

TRUE TRUE

FSB_DINV_L<3..0>

TRUE

GPUVCORE_FSET

SMBUS_SMC_BSA_SCL

TRUE

BATT_POS

TRUE

BATT_NEG

TRUE

PP1V5_S0

TRUE

FAN_LT_PWM

TRUE

ALS_GAIN

TRUE

LTALS_OUT

TRUE

ACZ_SDATAIN<0>

TRUE

ACZ_SDATAOUT

TRUE

ACZ_BITCLK

TRUE

ACZ_RST_L

TRUE

EXCARD_OC_L

TRUE

LTUSB_OC_L

TRUE

LT2USB_OC_L

PM_SLP_S4_L

TRUE

PM_SLP_S3_LS5V

TRUE

SYS_ONEWIRE

TRUE

SMC_EXCARD_CP

TRUE

MINI_CLKREQ_L

TRUE

SMC_EXCARD_PWR_EN

TRUE

EXCARD_CLKREQ_L

TRUE

LIO_PLT_RESET_L

TRUE

ACZ_SYNC

TRUE

USB2_LT_N

TRUE

USB2_LT_P

TRUE

USB2_EXCARD_N

TRUE

USB2_EXCARD_P

PCIE_EXCARD_R2D_C_P

TRUE

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

TRUE

PCIE_EXCARD_D2R_N

TRUE

PCIE_CLK100M_EXCARD_P

TRUE

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

TRUE

PCIE_MINI_D2R_N

TRUE

PCIE_MINI_D2R_P

TRUE

PCIE_CLK100M_MINI_P

SMBUS_SB_SCL

TRUE

PCIE_CLK100M_MINI_N

SMBUS_SB_SDA

TRUE

GND

TRUE

USB2_LT2_P

TRUE

PCIE_CLK100M_EXCARD_N

TRUE

USB2_LT2_N

TRUE

PP3V3_S3AC

TRUE

PP1V2_S3

TRUE

PP1V95_FWPHY_PLLVDD

TRUE

PP1V95_FWPHY

PP3V3_FWPHY_PLLVDD

TRUE

PP3V3_FWPHY_AVDD

TRUE

PP3V3_FWPHY

PP1V8_S3

TRUE

PPVCORE_S0_CPU

TRUE

SMBUS_SMC_0_S0_SCL

TRUE

SMBUS_SMC_0_S0_SDA

SMC_RST_L

TRUETRUE

FSB_CLK_CPU_P

TRUE

GPUVCORE_COMP

TRUE

P3V42G3H_FB

P1V05S0_FSET

TRUE

79

78

70

66

65

64

60

59

57

56

53

51

48

43

37

80 80

80

36

79 79

79

34

78 78

78

33

66

70

66

70

29

64

67

64

67

28

54

66

54

66

27

80

27

34

65

78

34

65

78

65

26

66

26

66

25

61

70

25

61

68

70

61

78

25

64

25

63

66

24

60

68

24

60

67

68

60

66

24

63

24

54

65

21

70

57

70

66

21

57

66

57

65

23

62

23

37

47

19

67

56

67

64

19

56

65

64

56

47

64

22

59

22

32

25

17

66

54

66

63

17

54

63

54

25

62

65

21

65

58

21

31

24

16

65

52

65

61

16

52

61

52

24

65

55

64

20

63

56

20

29

19

13

64

77

47

64

60

13

47

51

60

47

19

63

47

26

80

54

19

50

51

19

28

17

12

63

76

42

63

54

12

42

80

50

54

42

17

50

45

25

66

50

17

47

59

45

17

19

16

11

68

61

66

36

61

47

11

76

36

66

76

45

47

36

16

47

33

44

66

24

61

43

14

86

26

46 59

59

52

59

52

41

14

16

13

66

9

67

51

65

31

51

66

43

9

71

31

61

69

66

35

54

35

43

31

13

51

46

29

66

43

60

53

62

51

65

23

51

39

10

86

12

60

86

60

86

22

60

41 52

52

51

52

51

52

45

37

10

14

9

65

8

51

47

46

66

62

25

46

62

41

8

70

86

25

51

66

62

27

50

51

27

41

67

86

25

86

67

9

50

86

47

41

65

51

47

86

47

49

28

47

66

62

42

54

53

50

52

39

40

50

64

22

45

60

32

5

21

22

12

11

26

33

26

50

26

37

50

21

23

12

23

34

33

34

21

59

50

69

14

34

60

21

23

86

22

34

52

50

51

52

50

51

50

51

52

51

54

22

32

5

8

31

7

50

39

25

65

19

5

25

39

5

7

66

12

5

45

65

39

62

26

50

26

5

50

51

65

34

12

5

12

50

68

8

47

56

47

22

23

61

50

34

50

34

47

22

49

47

49

47

27

47

27

22

47

22

41

39

38

9

50

45

51 34

5

39

23

60

33

11

5

50

23

41

63

33

4

77

7

14

7

14

23

21

23

22

23

7

14

21

7

6

21

14

12

7

26

5

7

9

7

5

60

14

21

23

34

21

50

26

22

23

21

57

21

50

23

50

6

53

27

4

5

30

5

47

23

67

5

67

63

17

4

5

4

5

54

53

62

7

4

5

53

61

62

5

70

64

60

41

5

23

45

53

47

5

4

63

27

50

62

61

21

7

4

57

64

62

7

70

27

67

5

57

6

47

21

6

4

5

47

33

47

33

26

21

6

47

22

34

47

22

34

23

34

23

6

34

6

39

5

38

4

38

4

8

27

50

7

70

65

64

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

USB Port "D" = Camera

USB Port "F" = IR Receiver

USB Port "C" = Left USB 2.0 Port

USB Port "G" = Bluetooth (M13P)

USB Port "A" (Debug Port) = Right USB 2.0 Port

USB Port "E" = ExpressCard

USB Port "B" = Trackpad (Geyser)

USB Port "H" = 2nd Left USB 2.0 Port

Chassis connection to be made at the mounting hole southwest of the USB connector

NOTE: NB_CFG<13..12> require test access

Ethernet Powr Management Support

"ENET_LOM_DISABLE" are mutually-exclusive.

NOTE: BOM options "USB_G_OC_PU" and

Chassis connection to be made on FW shell

Chassis connection to be made at the mounting hole northwest of the DVI connector

Chassis connection to be made at the fan cutout near the right ALS

Chassis connection to be made at the mounting hole east of the LVDS connector

ZT0600

1

HOLE-VIA-P5RP25

ZT0603

1

HOLE-VIA-P5RP25

ZT0602

1

HOLE-VIA-P5RP25

SH0600

1

2

3

OG-503040

SHLD-SM-LF

ZT0601

1

HOLE-VIA-P5RP25

R0600

1 2

0

5% 1/16W MF-LF

402

R0690

1 2

ENET_LOM_DISABLE

0

5%

402

MF-LF

1/16W

R0601

1 2

5%

1/16W

0

402

MF-LF

SH0601

1

EMI-SPRING

0G-502620R

6 86

06

051-7023

Signal Aliases

SYNC_MASTER=(M1_MLB)

SYNC_DATE=(11/11/2005)

NC_CPU_A35_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_APM0_LNC_CPU_APM0_L

MAKE_BASE=TRUE NO_TEST=TRUE

NC_CPU_SPARE0

NC_CPU_SPARE4

NC_CPU_A37_L

NC_CPU_A34_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A33_L

MAKE_BASE=TRUE NO_TEST=TRUE

NC_CPU_A32_LNC_CPU_A32_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A33_L

MIN_LINE_WIDTH=0.5 mm VOLTAGE=0V

MAKE_BASE=TRUE

GND_CHASSIS_DVI_TOP

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_INVERTER

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

ENET_LOM_DIS_L

SB_GPIO30

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_ENET_CTRL25 NC_ENET_CTRL25

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_ENET_CTRL12 NC_ENET_CTRL12

RTALS_GAIN

MAKE_BASE=TRUE

ALS_GAIN

RTALS_GAIN

TP_SB_SUS_CLK

MAKE_BASE=TRUE

TP_NB_CFG<13..12>

NB_CFG<13..12>

MAKE_BASE=TRUE

TP_NB_CFG<17>

NB_CFG<17>

MAKE_BASE=TRUE

TP_NB_CFG<15..14>

NB_CFG<15..14>

MAKE_BASE=TRUE

TP_NB_CFG<11..10>

NB_CFG<11..10>

MAKE_BASE=TRUE

TP_NB_CFG<8>

NB_CFG<8>

MAKE_BASE=TRUE

TP_NB_CFG<6>

NB_CFG<6>

MAKE_BASE=TRUE

TP_NB_CFG<4..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_A_A<15..14>

NC_CPU_A36_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A39_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A36_L

GND

GND_CHASSIS_DVI_TOP

GND_CHASSIS_USB

GND_CHASSIS_DVI_BOT

GND_CHASSIS_DVI_BOT GND_CHASSIS_DVI_BOT

GND_CHASSIS_DVI_BOT

GND_CHASSIS_USB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=0V

MAKE_BASE=TRUE

GND_CHASSIS_DVI_BOT

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

MAKE_BASE=TRUE

USB2_LT2_N

MAKE_BASE=TRUE

USB2_LT2_P

USB2_LT2_N

USB2_LT2_P

VOLTAGE=0V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

GND_CHASSIS_LVDS

MIN_NECK_WIDTH=0.25 mm

GND_CHASSIS_LVDS

NC_CPU_HFPLL

NC_CPU_EXTBREF

NO_TEST=TRUE

MAKE_BASE=TRUE

USB2_LT_N

USB2_LT_P

MAKE_BASE=TRUE

USB_TRACKPAD_P

USB2_CAMERA_P

USB_IR_N

MAKE_BASE=TRUE

USB_IR_P

MAKE_BASE=TRUE

USB_IR_N

USB_BT_P USB_BT_N

USB_IR_N

MAKE_BASE=TRUE

UNUSED_USB_D_OC_L

NC_CPU_SPARE1

NC_CPU_SPARE2

NC_CPU_APM1_L

NC_CPU_A39_L

NC_CPU_A38_L

NC_CPU_A35_L

NC_CPU_A34_L

NC_CPU_SPARE4

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_SPARE2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_HFPLL

MAKE_BASE=TRUE NO_TEST=TRUE

NC_CPU_A38_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_A37_L

NO_TEST=TRUE

MAKE_BASE=TRUE

GND_CHASSIS_LVDS GND_CHASSIS_LVDS

GND_CHASSIS_LVDS

MAKE_BASE=TRUE

USB2_RT_N

USB2_RT_P

MAKE_BASE=TRUE

USB2_RT_P USB2_RT_N

USB2_RT_P USB2_RT_N RTUSB_OC_L

USB_TRACKPAD_P USB_TRACKPAD_N UNUSED_USB_B_OC_L

MAKE_BASE=TRUE

UNUSED_USB_B_OC_L

USB2_LT_P

LTUSB_OC_L

USB2_LT_N

RTUSB_OC_L

MAKE_BASE=TRUE

RTUSB_OC_L

MAKE_BASE=TRUE

USB_TRACKPAD_P

MAKE_BASE=TRUE

USB_TRACKPAD_NUSB_TRACKPAD_N

USB2_LT_P

USB2_CAMERA_N UNUSED_USB_D_OC_L

EXCARD_OC_L

MAKE_BASE=TRUE

EXCARD_OC_L

USB2_EXCARD_N

USB_BT_N

USB_BT_P

MAKE_BASE=TRUE

USB2_CAMERA_PUSB2_CAMERA_P USB2_CAMERA_N

MAKE_BASE=TRUE

USB2_CAMERA_N

USB2_EXCARD_P

MAKE_BASE=TRUE

USB2_EXCARD_N

USB_BT_P

MAKE_BASE=TRUE

USB_BT_N

USB2_EXCARD_N

USB2_EXCARD_P USB2_EXCARD_P

USB2_LT_N

USB_IR_PUSB_IR_P

USB2_LT2_N

USB2_LT2_P

MAKE_BASE=TRUE

LTUSB_OC_L

GND_CHASSIS_FANFRAME

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=0V

NB_CFG<4..3>

MEM_B_A<15..14>

MEM_A_A<15..14>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_B_A<15..14>

MAKE_BASE=TRUE

TP_SB_SUS_CLK

NC_CPU_SPARE0

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_EXTBREF

NC_CPU_APM1_L

NO_TEST=TRUE

MAKE_BASE=TRUE

47

51 51

45

47

79

22

47

22

45

80

46

47

46

45

47

45

47 47

47

22

45

22

45

22

80

47

47 47

47

50

23

46

44

46

44

6

22

6

45

22

80

22

46

45

22

46

22

45

22

22 22

22

80

6

22

6

22

6

22

22 22

22

80 80

22

23

7

7 7

7

7 7

7

79

78

39 39

47 56

6

7

79

44

40

44

40

5

6

78

7

5

22

6

22

7

78

6

22

6

22

6

22

6

22

6 6

6

22

5

6

5

6

5

6

6 6

6

22 22

6

7

6

6 6

6

6 6

6

39 22

6 6

5 6

5

14

28

6

5

6

5

6

5

6

5

6

5 5

5

6

5

5 5

5

6 6

5

14

29

5

6

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN IN

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

A7*

RSVD14 RSVD15

BCLK1

BCLK0

RSVD20

RSVD17 RSVD18 RSVD19

RSVD16

RSVD13

RSVD12

THERMTRIP*

THERMDC

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM1* BPM2*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

LOCK*

INIT*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BPRI*

BNR*

ADS*

RSVD11

RSVD6 RSVD7 RSVD8

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5

RSVD9 RSVD10

SMI*

LINT0 LINT1

STPCLK*

IGNNE*

FERR*

A20M*

ADSTB1*

A30* A31*

A27* A28* A29*

A26*

A25*

A24*

A22* A23*

A21*

A20*

A19*

A18*

A17*

REQ4*

REQ3*

REQ1*

REQ0*

REQ2*

ADSTB0*

A14* A15* A16*

A13*

A12*

A11*

A10*

A9*

A8*

A6*

A5*

A4*

A3*

(1 OF 4)

THERM

HCLK

RESERVED

ADDR GROUP1 ADDR GROUP0

CONTROL

XDP/ITP SIGNALS

PSI*

SLP*

PWRGOOD

DPRSTP*

DPSLP*

DPWR*

COMP2 COMP3

COMP1

COMP0

DSTBP3*

DSTBN3*

DINV3*

D63*

D62*

D61*

D60*

D59*

D58*

D57*

D56*

D55*

D54*

D52* D53*

D51*

D50*

D49*

D48*

DINV2*

DSTBN2*

D47*

DSTBP2*

D45* D46*

D44*

D43*

D42*

D41*

D40*

D39*

D38*

D37*

D36*

D35*

D34*

D33*

D32*

BSEL2

DSTBN1*

BSEL0 BSEL1

TEST2

TEST1

DINV1*

DSTBP1*

D31*

D30*

D29*

D26* D27* D28*

D24* D25*

D23*

D21* D22*

D20*

D19*

D18*

D16* D17*

DINV0*

DSTBP0*

DSTBN0*

D15*

D14*

D13*

D12*

D11*

D10*

D9*

D8*

D7*

D6*

D5*

D4*

D3*

D2*

D1*

D0*

GTLREF NC

(2 OF 4)

MISC

DATA GRP0

DATA GRP2

DATA GRP1

DATA GRP3

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU IS HOT

AND CPU VR TO INFORM

WITHOUT T-ING (NO

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50 SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

PLACE GND VIA W/IN 1000 MILS

FSB_IERR_L WITH A GND

PLACE TESTPOINT ON

LAYOUT NOTE: 0.5" MAX LENGTH

ICH7-M AND GMCH

TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE

LAYOUT NOTE:

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

CPU_PROCHOT_L TO SMC

SHOULD CONNECT TO

PM_THRMTRIP#

STUB)

SPARE[7-0],HFPLL: ROUTE TO TP VIA AND

0.1" AWAY

R0702

1

2

1%

54.9

MF-LF 402

1/16W

R0704

1

2

68

1/16W

5% 402

MF-LF

R0705

1

2

1K

MF-LF 402

1% 1/16W

R0706

1

2

2.0K

MF-LF 402

1% 1/16W

R0719

1 2

1%

402

54.9

R0718

1 2

27.4

R0717

1 2

1%

402

54.9

R0716

1 2

27.4

402

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

21 60

5

21 86

5

12 86

5

12

60

5

21 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

34

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12 86

5

12

86 5

12

86

11 86

11

11 26

10

14 21 51

21 86

5

11 12 86

12 86

7

11

7

11

7

11

10

5

34

5

34

21 86

5

21 86

21

R0730

1 2

NOSTUFF

402

0

R0707

1

2

1/16W

5% 402

MF-LF

1K

NOSTUFF

R0712

1

2

51

1/16W

5% 402

MF-LF

R0703

1

2

402

MF-LF

1/16W

1%

54.9

R0720

1 2

1%

402

54.9

R0721

1 2

54.9

402

1%

R0722

1 2

1%

402

54.9

U0700

N3 P5 P2 L1 P4 P1 R1

Y2 U5 R3 W6

A6

U4 Y5 U2 R4 T5 T3 W3 W5 Y4

J4

W2 Y1

L4 M3 K5 M1 N2 J1

H1

L2

V4

A22 A21

E2

AD4 AD3 AD1 AC4

G5

F1

C20

E1

H5 F21

A5

G6 E4

D20

C4

B3

C6 B4

H4

AC2 AC1

D21

K3 H2 K2 J3 L5

B1 F3 F4 G3

AA1

C3

B25

T22

D2 F6 D3 C1 AF1 D22 C23

AA4

C24

AB2 AA3

M4 N5 T2 V3 B2

A3

D5

AC5 AA6 AB3

A24 A25

C7

AB5

G2

AB6

OMIT

CPU

YONAH

BGA

U0700

B22 B23 C21

R26 U26 U1 V1

E22 F24

J24 J23 H26 F26 K22 H25

N22 K25 P26 R23

E26

L25 L22 L23 M23 P25 P22 P23 T24 R24 L26

H22

T25 N24

AA23 AB24 V24 V26 W25 U23 U25 U22

F23

AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24

AC22 AC23

G25

AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21

E25

AE25 AF25 AF22 AF26

E23 K24 G24

J26

M26

V23

AC20

E5 B5 D24

H23

M24

W24

AD23

G22

N25

Y25

AE24

AD26

A2

AE6

D6 D7

C26 D25

OMIT

BGA

YONAH

CPU

CPU 1 OF 2-FSB

SYNC_MASTER=M1_MLB

7

06

051-7023

86

SYNC_DATE=02/10/2006

FSB_BPRI_L

FSB_BNR_L

FSB_ADS_L

CPU_PSI_L

FSB_SLPCPU_L

CPU_PWRGD

CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L

CPU_COMP<2> CPU_COMP<3>

CPU_COMP<1>

CPU_COMP<0>

FSB_DSTBP_L<3>

FSB_DSTBN_L<3> FSB_DINV_L<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<52> FSB_D_L<53>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTBN_L<2>

FSB_D_L<47> FSB_DSTBP_L<2>

FSB_D_L<45> FSB_D_L<46>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

CPU_BSEL<2>

FSB_DSTBN_L<1>

CPU_BSEL<0> CPU_BSEL<1>

CPU_TEST2

CPU_TEST1

FSB_DINV_L<1>

FSB_DSTBP_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<26> FSB_D_L<27> FSB_D_L<28>

FSB_D_L<24> FSB_D_L<25>

FSB_D_L<23>

FSB_D_L<21> FSB_D_L<22>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<16> FSB_D_L<17>

FSB_DINV_L<0>

FSB_DSTBP_L<0>

FSB_DSTBN_L<0>

FSB_D_L<15>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

CPU_GTLREF

FSB_A_L<7>

NC_CPU_SPARE1 NC_CPU_SPARE2

FSB_CLK_CPU_N

FSB_CLK_CPU_P

TP_CPU_SPARE7

NC_CPU_SPARE4 TP_CPU_SPARE5 TP_CPU_SPARE6

TP_CPU_SPARE3

NC_CPU_SPARE0

NC_CPU_EXTBREF

PM_THRMTRIP_L

CPU_THERMD_N

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<0>

FSB_CPURST_L

FSB_LOCK_L

CPU_INIT_L

FSB_IERR_L

FSB_BREQ0_L

FSB_DRDY_L

FSB_DEFER_L

NC_CPU_HFPLL

NC_CPU_A37_L NC_CPU_A38_L NC_CPU_A39_L

NC_CPU_A32_L NC_CPU_A33_L NC_CPU_A34_L NC_CPU_A35_L NC_CPU_A36_L

NC_CPU_APM0_L NC_CPU_APM1_L

CPU_SMI_L

CPU_INTR CPU_NMI

CPU_STPCLK_L

CPU_IGNNE_L

CPU_FERR_L

CPU_A20M_L

FSB_ADSTB_L<1>

FSB_A_L<30> FSB_A_L<31>

FSB_A_L<27> FSB_A_L<28> FSB_A_L<29>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<22> FSB_A_L<23>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<1>

FSB_REQ_L<0> FSB_REQ_L<2>

FSB_ADSTB_L<0>

FSB_A_L<14> FSB_A_L<15> FSB_A_L<16>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

XDP_TCK

XDP_TDI

XDP_TMS

PP1V05_S0

FSB_DBSY_L

XDP_BPM_L<1>

PP1V05_S0

FSB_TRDY_L

FSB_RS_L<2> FSB_HIT_L

FSB_HITM_L

XDP_BPM_L<5>

FSB_RS_L<1>

FSB_RS_L<0>

66

64

54

34

25

24

21

19

17

16

13

12

11

9

8

11

7

86

86 86

6

86

6

7

5

OUT OUT OUT OUT OUT OUT OUT

OUT

VSS_82 VSS_83 VSS_84 VSS_85

VSS_87

VSS_86

VSS_88 VSS_89 VSS_90

VSS_92

VSS_91

VSS_93 VSS_94 VSS_95

VSS_97

VSS_96

VSS_100

VSS_98 VSS_99

VSS_102

VSS_101

VSS_105

VSS_103 VSS_104

VSS_106 VSS_107

VSS_110

VSS_109

VSS_108

VSS_111 VSS_112

VSS_115

VSS_114

VSS_113

VSS_116 VSS_117 VSS_118

VSS_120

VSS_119

VSS_123

VSS_121 VSS_122

VSS_124 VSS_125

VSS_128

VSS_126 VSS_127

VSS_129 VSS_130

VSS_133

VSS_131 VSS_132

VSS_134 VSS_135

VSS_138

VSS_136 VSS_137

VSS_139 VSS_140 VSS_141

VSS_143

VSS_142

VSS_146

VSS_144 VSS_145

VSS_147 VSS_148

VSS_151

VSS_150

VSS_149

VSS_152 VSS_153

VSS_156

VSS_155

VSS_154

VSS_157 VSS_158 VSS_159

VSS_161

VSS_160

VSS_162

VSS_1 VSS_2 VSS_3

VSS_5

VSS_4

VSS_6 VSS_7 VSS_8

VSS_10

VSS_9

VSS_11 VSS_12

VSS_15

VSS_13 VSS_14

VSS_16 VSS_17 VSS_18 VSS_19 VSS_20

VSS_23

VSS_22

VSS_21

VSS_24 VSS_25

VSS_28

VSS_27

VSS_26

VSS_29 VSS_30

VSS_33

VSS_32

VSS_31

VSS_34 VSS_35

VSS_38

VSS_37

VSS_36

VSS_39 VSS_40 VSS_41 VSS_42 VSS_43

VSS_46

VSS_44 VSS_45

VSS_47 VSS_48

VSS_51

VSS_49 VSS_50

VSS_52 VSS_53

VSS_56

VSS_54 VSS_55

VSS_57 VSS_58 VSS_59 VSS_60 VSS_61

VSS_63

VSS_62

VSS_64 VSS_65 VSS_66

VSS_69

VSS_68

VSS_67

VSS_70 VSS_71

VSS_74

VSS_73

VSS_72

VSS_75 VSS_76

VSS_79

VSS_78

VSS_77

VSS_80 VSS_81

(4 OF 4)

VCC_67

VCC_64

VCC_66

VCC_65

VCC_63

VCC_62

VCC_61

VCC_59 VCC_60

VCC_58

VCC_57

VCC_56

VCC_54 VCC_55

VCC_53

VCC_51 VCC_52

VCC_49 VCC_50

VCC_48

VCC_47

VCC_46

VCC_44 VCC_45

VCC_43

VCC_41 VCC_42

VCC_40

VCC_39

VCC_38

VCC_36 VCC_37

VCC_33

VCC_35

VCC_34

VCC_31 VCC_32

VCC_29 VCC_30

VCC_28

VCC_26 VCC_27

VCC_23

VCC_25

VCC_24

VCC_22

VCC_21

VCC_20

VCC_18 VCC_19

VCC_17

VCC_16

VCC_15

VCC_13 VCC_14

VCC_12

VCC_10 VCC_11

VCC_8 VCC_9

VCC_7

VCC_6

VCC_5

VCC_3 VCC_4

VCC_2

VCC_1 VCC_68

VCC_69

VCC_71

VCC_70

VCC_72

VCC_74

VCC_76

VCC_75

VCC_78

VCC_77

VCC_79

VCC_81

VCC_80

VCC_84

VCC_82 VCC_83

VCC_86

VCC_85

VCC_87

VCC_89

VCC_88

VCC_90 VCC_91 VCC_92

VCC_94

VCC_93

VCC_95 VCC_96 VCC_97

VCC_99

VCC_98

VCC_100

VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7

VCCP_9

VCCP_8

VCCP_11

VCCP_10

VCCP_12 VCCP_13 VCCP_14

VCCP_16

VCCP_15

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VSSSENSE

VCCSENSE

VCC_73

(3 OF 4)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

CPU_VCCSENSE_P/CPU_VCCSENSE_N USE ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.

(CPU INTERNAL PLL POWER 1.5V)

TO TP_VSSSENSE WITH NO

LAYOUT NOTE:

PROVIDE A TEST POINT (WITH NO STUB) TO CONNECT A DIFFERENCTIAL PROBE BETWEEN VCCSENSE AND VSSSENSE AT THE LOCATION WHERE THE TWO 54.9 OHM

SHOULD BE OF EQUAL LENGTH

VCCSENSE AND VSSSENSE LINES

LAYOUT NOTE:

STUB.

(CPU IO POWER 1.05V)

(CPU CORE POWER)

LAYOUT NOTE:

RESISTORS TERMINATE THE 55 OHM TRANSMISSION LINE

VID FOR CPU POWER SUPPLY IF NO USE, NEED PULL-UP OR PULL-DOWN

LAYOUT NOTE: CONNECT R0803

VCCA=1.5 ONLY

9

86

9

86

9

86

9

86

9

86

9

86

R0803

1

2

1/16W

1% 402

MF-LF

100

9

86

60 86

R0802

1

2

100

MF-LF 402

1% 1/16W

U0700

A4

B8

V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2

B11

AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4

B13

AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8

B16

AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11

B19

AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14

B21

AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16

B24

AF19 AF21 AF24

C5 C8

C11

A8

C14 C16 C19

C2 C22 C25

D1

D4

D8 D11

A11

D13 D16 D19 D23 D26

E3

E6

E8 E11 E14

A14

E16 E19 E21 E24

F5

F8 F11 F13 F16 F19

A16

F2 F22 F25

G4

G1 G23 G26

H3

H6 H21

A19

H24

J2

J5 J22 J25

K1

K4 K23 K26

L3

A23

L6 L21 L24

M2

M5 M22 M25

N1

N4 N23

A26

N26

P3

P6 P21 P24 R2 R5 R22 R25 T1

B6 T4

T23 T26 U3 U6 U21 U24 V2 V5 V22

OMIT

BGA

YONAH

CPU

U0700

A7

B7

AF20

B9 B10 B12 B14 B15 B17 B18 B20

C9

A9

C10 C12 C13 C15 C17 C18

D9 D10 D12 D14

A10

D15 D17 D18

E7

E9 E10 E12 E13 E15 E17

A12

E18 E20

F7

F9 F10 F12 F14 F15 F17 F18

A13

F20 AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

A15

AB9

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7

A17

AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10

A18

AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15

A20

AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18

B26

V6

N6 R21 R6 T21 T6 V21 W21

G21 J6 K6 M6 J21 K21 M21 N21

AF7

AD6 AF5 AE5 AF4 AE3 AF2 AE2

AE7

OMIT

BGA

YONAH

CPU

CPU 2 OF 2-PWR/GND

SYNC_MASTER=M1_MLB

051-7023

06

8 86

SYNC_DATE=02/10/2006

PPVCORE_S0_CPU

PP1V05_S0

PP1V5_S0 CPU_VID<0>

CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>

CPU_VCCSENSE_N

CPU_VCCSENSE_P

PPVCORE_S0_CPU

66 64 54 34 25

24 21 19 17 16

66

13

66

60

12

60

54

11

54

9

8

7

8

5

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: This cap is shared

CPU VCORE HF AND BULK DECOUPLING

VCCP (CPU I/O) Decoupling

Will probably be removed before production

Resistors to allow for override of CPU VID

CPU VCORE VID Connections

4x 470uF. 20x 22uF 0805

1x 10uF, 1x 0.01uF

between CPU and NB

1x 470uF, 6x 0.1uF 0402

VCCA (CPU AVdd) Decoupling

C0906

1

2

6.3V

20% CERM

805

22UF

C0904

1

2

6.3V

20% CERM

22UF

805

C0916

1

2

6.3V

20% CERM

22UF

805

C0914

1

2

6.3V

20% CERM

22UF

805

C0908

1

2

6.3V

20% CERM

22UF

805

C0903

1

2

6.3V

20% CERM

22UF

805

C0907

1

2

6.3V

20% CERM

22UF

805

C0902

1

2

6.3V

20% CERM

22UF

805

C0901

1

2

6.3V

20% CERM

805

22UF

C0913

1

2

6.3V

20% CERM

805

22UF

C0912

1

2

6.3V

20% CERM

22UF

805

C0911

1

2

805

6.3V

20% CERM

22UF

C0919

1

2

6.3V

20% CERM

22UF

805

C0900

1

2

6.3V

20% CERM

22UF

805

C0910

1

2

22UF

6.3V

20% CERM

805

C0936

1

2

0.1UF

CERM 402

20% 10V

C0935

1

2 3

D2TS

POLY

470uF-9MOHM

20%

2.5V

CRITICAL

C0905

1

2

6.3V

20% CERM

22UF

805

C0909

1

2

6.3V

20% CERM

22UF

805

C0915

1

2

20% CERM

22UF

6.3V 805

C0917

1

2

6.3V

20% CERM

22UF

805

C0937

1

2

0.1UF

CERM 402

20% 10V

C0938

1

2

0.1UF

CERM 402

20% 10V

C0939

1

2

0.1UF

CERM 402

20% 10V

C0940

1

2

0.1UF

CERM 402

20% 10V

C0941

1

2

0.1UF

CERM 402

20% 10V

C0918

1

2

22UF

CERM

20%

6.3V 805

C0950

1

23

D2TS

CRITICAL

470uF-8MOHM

POLY

20%

2.5V

C0952

1

23

D2TS

CRITICAL

470uF-8MOHM

POLY

20%

2.5V

C0953

1

23

D2TS

CRITICAL 470uF-8MOHM

POLY

20%

2.5V

C0954

1

23

D2TS

CRITICAL

470uF-8MOHM

POLY

20%

2.5V

C0981

1

2

16V

0.01UF

CERM 402

20%

C0980

1

2

X5R

10uF

20%

6.3V 603

R0996

1 2

0

5% 1/16W MF-LF

402

R0995

1 2

0

5% 1/16W MF-LF

402

R0993

1 2

402

MF-LF

1/16W

5%

0

R0994

1 2

402

1/16W

5%

0

MF-LF

R0991

1 2

402

MF-LF

1/16W

5%

0

R0992

1 2

402

MF-LF

1/16W

5%

0

R0990

1 2

402

MF-LF

1/16W

5%

0

CPU Decoupling & VID

051-7023

SYNC_DATE=02/08/2006

SYNC_MASTER=M1_MLB

06

9 86

PP1V5_S0

PP1V05_S0

IMVP6_VID<1>

CPU_VID<6>

IMVP6_VID<4>

CPU_VID<4>

IMVP6_VID<2>

CPU_VID<2>

IMVP6_VID<0>

CPU_VID<0>

IMVP6_VID<5>

CPU_VID<5>

IMVP6_VID<3>

CPU_VID<3>

CPU_VID<1>

IMVP6_VID<6>

PPVCORE_S0_CPU

66 64 54 34 25

66

24

65

21

47

19

25

17

24

16

19

13

17

12

66

16

11

60

13

8

54

8

7

60

86

60 86

86

60

8

5

8

5 8

8

5

D+ D-

ALERT*/

THM*

SCLK

SDATA

VDD

GND

THM2*

BI BI

IN

OUT

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

PLACE U1001 NEAR THE U1200

ADD GND GUARD TRACE

CPU_THERMD_N ON SAMEFOR CPU_THERMD_P AND

10 MIL SPACING

LAYER. 10 MIL TRACE

ROUTE CPU_THERMD_P AND

CPU ZONE THERMAL SENSOR

LAYOUT NOTE:

CPU_THERMD_N

(TO CPU INTERNAL THERMAL DIODE)

LAYOUT NOTE:

PLACEHOLDER ADT7461A

U1001

6

2 3

5

8 7

4

1

CRITICAL

MSOP

ADT7461

R1001

1 2

MF-LF

499

1/16W

402

1%

C1001

1

2

CERM

50V

0.001uF

10%

402

4

27 48 50

4

27 48 50

C1002

1

2

X5R

0.1UF

16V

10%

402

7

R1002

1 2

499

1%

MF-LF

402

1/16W

R1005

1

2

1/16W

5%

402

10K

MF-LF

R1006

1

2

10K

1/16W 402

MF-LF

5%

051-7023

06

10 86

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

CPU MISC1-TEMP SENSOR

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

THRM_ALERT

THRM_ALERT_L

PP3V3_S0

CPU_THERMD_N

CPU_THERMD_P

THRM_CPU_DX_N

THRM_CPU_DX_P

79 78 70 66 65 64 60 59 57 56 53 51 48 43 37 36 34 33 29 28 27 26 25 24 23 22 21 20 19 17 14

5 4

53

OUT OUT OUT

OUT

IN

IN IN

BI

OUT

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

ITP TCK SIGNAL LAYOUT NOTE:

CONNECTOR’S FBO PIN.

518S0320

(TCK)

(FBO)

CPU ITP700FLEX DEBUG SUPPORT

(DEBUG PORT ACTIVE) (DBR#)

(DBA#)

NC

TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC

(AND WITH RESET BUTTON)

(DEBUG PORT RESET)

(FROM CK410M HOST 133/167MHZ)

INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.

TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX

ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S

R1100

1 2

MF-LF

22.6

1%

1/16W

402

ITP

R1102

1 2

ITP

402

1%

22.6

1/16W MF-LF

R1103

1

2

54.9

1/16W

1% 402

MF-LF

ITP

C1100

1

2

402

X5R

16V

10%

0.1UF

R1104

1

2

1/16W

240

402

MF-LF

5%

J1101

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28

29

3

30

4 5 6 7 8 9

F-RT-SM

52435-2872

CRITICAL

ITPCONN

R1101

1

2

1/16W 402

54.9

1% MF-LF

R1106

1

2

680

402

5% 1/16W MF-LF

7

11

7

11

7

34 86

7

86

7

86

7

86

7

86

7

86

7

86

5 7

12 86

CPU ITP700FLEX DEBUG

SYNC_DATE=02/10/2006

051-7023

06

11 86

SYNC_MASTER=M1_MLB

ITPRESET_L

XDP_DBRESET_L

ITP_TDO

CPU_XDP_CLK_P

XDP_TCK

XDP_BPM_L<5> XDP_BPM_L<4> XDP_BPM_L<3> XDP_BPM_L<2> XDP_BPM_L<1>

XDP_TRST_L

CPU_XDP_CLK_N

XDP_TMS

PP1V05_S0

PP3V3_S5

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<0>

FSB_CPURST_L

PP1V05_S0

66

64

54

34

25

24

78

24

21

66

21

19

65

19

17

64

17

16

62

16

13

55

13

12

26

12

11

25

11

9

24

9

8

23

8

7

22

7

86

5

BI

BI BI

OUT

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI

BI BI BI BI

BI BI

OUT

BI

OUT

BI BI BI BI BI

IN

BI

IN

BI

HD4*

HD6*

HD16*

HTRDY*

HSLPCPU*

HRS1*

HRS0*

HHITM* HLOCK*

HHIT*

HDSTBP2* HDTSBP3*

HDSTBP1*

HDSTBP0*

HDSTBN3*

HDSTBN1* HDSTBN2*

HDSTBN0*

HDINV2* HDINV3*

HDINV1*

HDINV0*

HDVREF

HDRDY*

HDPWR*

HDEFER*

HDBSY*

HCPURST*

HBREQ0*

HBPRI*

HBNR*

HAVREF

HCLKIN*

HCLKIN

HYSWING

HYRCOMP HYSCOMP

HXSWING

HXSCOMP

HXRCOMP

HA13*

HADS*

HADSTB0*

HD3*

HD2*

HD1*

HD0*

HD63*

HD62*

HD61*

HD60*

HD59*

HD58*

HD57*

HD56*

HD55*

HD54*

HD53*

HD52*

HD51*

HD50*

HD49*

HD48*

HD47*

HD46*

HD45*

HD44*

HD43*

HD42*

HD41*

HD40*

HD39*

HD38*

HD37*

HD36*

HD35*

HD34*

HD33*

HD32*

HD31*

HD29*

HD28*

HD27*

HD26*

HD25*

HD24*

HD23*

HD22*

HD21*

HD20*

HD19*

HD18*

HD17*

HD15*

HD10* HD11* HD12* HD13* HD14*

HD5*

HD7* HD8* HD9*

HA30*

HA29*

HA28*

HA27*

HA26*

HA25*

HA24*

HA23*

HA31*

HA20*

HA19*

HA18*

HA16*

HA15*

HA14*

HA21* HA22*

HA17*

HA9*

HA8*

HA7*

HA6*

HA5*

HA4*

HA3*

HA10* HA11* HA12*

HADSTB1*

HREQ0* HREQ1* HREQ2* HREQ3*

HD30*

HREQ4*

HRS2*

(1 OF 10)

HOST

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

5 7

86

5 7

86

5 7

86

5 7

11 86

7

86

7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

C1211

1

2

402

X5R

16V

10%

0.1uF

R1211

1

2

200

1% 1/16W MF-LF 402

R1210

1

2

100

1% 1/16W MF-LF 402

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

7

86

5 7

86

5 7

7

86

7

86

7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5

34

5 7

86

5

34

R1220

1

2

54.9

1% 1/16W MF-LF

402

R1221

1

2

402

MF-LF

1/16W

1%

24.9

R1225

1

2

221

1% 1/16W MF-LF 402

R1226

1

2

1% 1/16W MF-LF 402

100

C1226

1

2

0.1uF

402

X5R

16V

10%

C1236

1

2

402

X5R

16V

10%

0.1uF

R1235

1

2

221

1% 1/16W MF-LF 402

R1230

1

2

54.9

1% 1/16W MF-LF

402

5 7

86

R1236

1

2

1% 1/16W MF-LF 402

100

R1231

1

2

402

MF-LF

1/16W

1%

24.9

5 7

86

U1200

H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14

H9

C14 D14

C9 E11 G11 F11 G12 F9

E8 B9 C13 J13 C6 F6 C7

AG2 AG1

B7

F1 J1

K7 J8 H4 J3

K11

G4 T10 W11

T3

U7

H1

U9 U11 T11

W9

T1

T8

T4

W7

U5

T9

J6

W6

T5 AB7 AA9

W4

W3

Y3

Y7

W5 Y10

H3

AB8

W2 AA4 AA7 AA2 AA6

AA10

Y8 AA1 AB4

K2

AC9

AB11 AC11

AB3 AC2 AD1 AD9 AC1 AD7 AC6

G1

AB5

AD10

AD4 AC8

G2

K9

K1

A7 C3

J7 W8 U3 AB10

J9 H8

K4 T7 Y5 AC4

K3 T6 AA5 AC5

K13

D3 D4 B3

D8 G8 B8 F8 A8

B4 E6 D6

E3 E7

E1

E2

E4

Y1

U1

W1

BGA

NB

945GM

OMIT

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

5 7

86

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NB CPU Interface

06

12 86

051-7023

NB_FSB_XRCOMP

PP1V05_S0

FSB_RS_L<2>

FSB_REQ_L<4>

FSB_D_L<30>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_ADSTB_L<1>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<17>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<14> FSB_A_L<15> FSB_A_L<16>

FSB_A_L<18> FSB_A_L<19> FSB_A_L<20>

FSB_A_L<31>

FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<15>

FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29>

FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

FSB_ADSTB_L<0>

FSB_ADS_L

FSB_A_L<13>

NB_FSB_XSCOMP NB_FSB_XSWING

NB_FSB_YSCOMP

NB_FSB_YRCOMP

NB_FSB_YSWING FSB_CLK_NB_P

FSB_CLK_NB_N

FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_CPURST_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L

FSB_DINV_L<3>

FSB_DSTBN_L<1>

FSB_DSTBP_L<0>

FSB_HIT_L

FSB_LOCK_L

FSB_HITM_L

FSB_RS_L<0> FSB_RS_L<1>

FSB_SLPCPU_L FSB_TRDY_L

FSB_D_L<16>

FSB_D_L<0>

FSB_D_L<3>

FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<2>

FSB_D_L<1>

NB_FSB_VREF

FSB_DINV_L<2>

FSB_DINV_L<1>

FSB_DSTBN_L<0>

FSB_DINV_L<0>

FSB_DSTBP_L<3>

FSB_DSTBP_L<2>

FSB_DSTBP_L<1>

FSB_DSTBN_L<3>

FSB_DSTBN_L<2>

FSB_D_L<17>

66

64

54

34

25

24

21

19

17

16

13

12

11

9

8

7

5

CRT_BLUE*

CRT_BLUE

CRT_GREEN*

CRT_GREEN

CRT_RED

CRT_DDC_CLK

CRT_RED*

HSYNC

CRT_DDC_DATA

CRT_VSYNC

CRT_IREF

TV_IRTNC

TV_IRTNB

TV_IREF TV_IRTNA

TV_DACB_OUT TV_DACC_OUT

TV_DACA_OUT

LB_DATA2

LB_DATA1

LB_DATA0

LB_DATA2*

LB_DATA1*

LB_DATA0*

LA_DATA2

LA_DATA1

LA_DATA0

LA_DATA2*

LA_DATA1*

LA_DATA0*

LB_CLK

LB_CLK*

LA_CLK

LA_CLK*

L_VDDEN

L_VREFL

L_VREFH

L_VBG

L_IBG

L_DDC_CLK L_DDC_DATA

EXP_A_COMPI EXP_A_COMPO

EXP_A_RXN0 EXP_A_RXN1 EXP_A_RXN2 EXP_A_RXN3 EXP_A_RXN4 EXP_A_RXN5 EXP_A_RXN6 EXP_A_RXN7 EXP_A_RXN8

EXP_A_RXN9 EXP_A_RXN10 EXP_A_RXN11 EXP_A_RXN12 EXP_A_RXN13

EXP_A_RXN15

EXP_A_RXN14

EXP_A_RXP0

EXP_A_RXP1

EXP_A_RXP2

EXP_A_RXP4

EXP_A_RXP3

EXP_A_RXP5

EXP_A_RXP6

EXP_A_RXP7

EXP_A_RXP10

EXP_A_RXP9

EXP_A_RXP8

EXP_A_RXP11 EXP_A_RXP12

EXP_A_RXP14

EXP_A_RXP13

EXP_A_RXP15

EXP_A_TXN1

EXP_A_TXN0

EXP_A_TXN3

EXP_A_TXN2

EXP_A_TXN6

EXP_A_TXN5

EXP_A_TXN4

EXP_A_TXN7

EXP_A_TXN8

EXP_A_TXN9 EXP_A_TXN10 EXP_A_TXN11 EXP_A_TXN12

EXP_A_TXN14

EXP_A_TXN13

EXP_A_TXN15

EXP_A_TXP0

EXP_A_TXP2

EXP_A_TXP1

EXP_A_TXP3

EXP_A_TXP4

EXP_A_TXP5

EXP_A_TXP7

EXP_A_TXP6

EXP_A_TXP8

EXP_A_TXP9 EXP_A_TXP10

EXP_A_TXP12

EXP_A_TXP11

EXP_A_TXP13 EXP_A_TXP14 EXP_A_TXP15

L_CLKCTLB

L_BKLTEN L_CLKCTLA

L_BKLTCTL

(3 OF 10)

LVDS

TV

VGA

PCI-EXPRESS GRAPHICS

IN

OUT

IN

OUT OUT OUT OUT

IN IN

OUT OUT OUT

OUT

IN

OUT

BI

IN

IN IN

IN

IN IN IN IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT OUT OUT

IN

BI BI

OUT OUT OUT OUT

OUT OUT

IN

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT OUT

OUT

BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used

Can leave all signals NC if LVDS is not implemented

CRT Disable

TV-Out Disable

Composite: DACA only

TV-Out Signal Usage:

HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core

Unused DAC outputs must remain powered, but can omit

S-Video: DACB & DACC only

connect to GND through 75-ohm resistors.

Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and

Component: DACA, DACB & DACC

rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.

filtering components. Unused DAC outputs should

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie

VCCD_LVDS must remain powered with proper decoupling.

LVDS Disable

Otherwise, tie VCCD_LVDS to GND also.

SDVOC_CLKP

SDVOC_BLUE

SDVOC_GREEN

SDVOC_RED

SDVOB_BLUE SDVOB_CLKP

SDVOB_RED# SDVOB_GREEN# SDVOB_BLUE# SDVOB_CLKN SDVOC_RED# SDVOC_GREEN# SDVOC_BLUE# SDVOC_CLKN

SDVOB_RED SDVOB_GREEN

SDVO_FLDSTALL

SDVO_INT

SDVO_TVCLKIN

SDVO_INT#

SDVO_TVCLKIN#

SDVO Alternate Function

SDVO_FLDSTALL#

U1200

E23 D23

C26 C25

C22 B22

J22

A21 B21

H23

D40 D38

F34 G38

V34 W38 Y34 AA38 AB34 AC38

H34 J38 L34 M38 N34 P38 R34 T38

D34 F38

T34 V38 W34 Y38 AA34 AB38

G34 H38 J34 L38 M34 N38 P34 R38

F36 G40

V36 W40 Y36 AA40 AB36 AC40

H36 J40 L36 M40 N36 P40 R36 T40

D36 F40

T36 V40 W36 Y40 AA36 AB40

G36 H40 J36 L40 M36 N40 P36 R40

G23

D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32

A32

A33

B37

C37

B34

B35

A36

A37

E26

E27

F30

G30

D29

D30

F28

F29

A16 C18 A19

J20 B16 B18 B19

OMIT

945GM

NB

BGA

69

R1310

1

2

24.9

1% 1/16W MF-LF 402

19

69

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

19

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

69

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

19

69

19

69

19

69

19

69

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

19

NB PEG / Video Interfaces

SYNC_DATE=02/10/2006

SYNC_MASTER=M1_MLB

13 86

06

051-7023

GND

TP_LVDS_CLKCTLB

PP1V5_S0

TP_LVDS_BKLTCTL

TP_LVDS_CLKCTLA

TP_LVDS_BKLTEN

PEG_R2D_C_P<15>

PEG_R2D_C_P<14>

PEG_R2D_C_P<13>

PEG_R2D_C_P<11> PEG_R2D_C_P<12>

PEG_R2D_C_P<10>

PEG_R2D_C_P<9>

PEG_R2D_C_P<8>

PEG_R2D_C_P<6> PEG_R2D_C_P<7>

PEG_R2D_C_P<5>

PEG_R2D_C_P<4>

PEG_R2D_C_P<3>

PEG_R2D_C_P<1> PEG_R2D_C_P<2>

PEG_R2D_C_P<0>

PEG_R2D_C_N<15>

PEG_R2D_C_N<13> PEG_R2D_C_N<14>

PEG_R2D_C_N<12>

PEG_R2D_C_N<11>

PEG_R2D_C_N<10>

PEG_R2D_C_N<9>

PEG_R2D_C_N<8>

PEG_R2D_C_N<7>

PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6>

PEG_R2D_C_N<2> PEG_R2D_C_N<3>

PEG_R2D_C_N<0> PEG_R2D_C_N<1>

PEG_D2R_P<15>

PEG_D2R_P<13> PEG_D2R_P<14>

PEG_D2R_P<12>

PEG_D2R_P<11>

PEG_D2R_P<8> PEG_D2R_P<9> PEG_D2R_P<10>

PEG_D2R_P<7>

PEG_D2R_P<6>

PEG_D2R_P<5>

PEG_D2R_P<3> PEG_D2R_P<4>

PEG_D2R_P<2>

PEG_D2R_P<1>

PEG_D2R_P<0>

PEG_D2R_N<14>

PEG_D2R_N<13>

PEG_D2R_N<12>

PEG_D2R_N<11>

PEG_D2R_N<10>

PEG_D2R_N<8>

PEG_D2R_N<6>

PEG_D2R_N<5>

PEG_D2R_N<4>

PEG_D2R_N<3>

PEG_D2R_N<2>

PEG_D2R_N<1>

PEG_D2R_N<0>

PEG_COMP

TP_LVDS_DDC_DATA

TP_LVDS_DDC_CLK

NC_LVDS_IBG TP_LVDS_VBG

NC_LVDS_VREFH TP_LVDS_VREFL

TP_LVDS_VDDEN

NC_LVDS_A_CLKN NC_LVDS_A_CLKP NC_LVDS_B_CLKN NC_LVDS_B_CLKP

NC_LVDS_A_DATAN<0> NC_LVDS_A_DATAN<1> NC_LVDS_A_DATAN<2>

NC_LVDS_A_DATAP<0> NC_LVDS_A_DATAP<1> NC_LVDS_A_DATAP<2>

NC_LVDS_B_DATAN<0> NC_LVDS_B_DATAN<1> NC_LVDS_B_DATAN<2>

NC_LVDS_B_DATAP<0> NC_LVDS_B_DATAP<1> NC_LVDS_B_DATAP<2>

PP1V05_S0

TP_CRT_DDC_DATA

PP1V05_S0 TP_CRT_DDC_CLK

PP1V05_S0

PP1V05_S0 PP1V05_S0

PEG_D2R_N<15>

PEG_D2R_N<9>

PEG_D2R_N<7>

PP1V5_S0

66

65 47 25 24 19 17 16 13

9 8 5

SM_CS0*

RSVD15

RSVD14

SM_CKE2

RSVD2 RSVD3

RSVD6

RSVD4 RSVD5

RSVD8

RSVD7

RSVD9

RSVD1

RSVD10 RSVD11 RSVD12 RSVD13

CFG1

CFG0

CFG2 CFG3 CFG4

CFG6

CFG5

CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14

CFG17

CFG16

CFG15

CFG18 CFG19 CFG20

PM_BM_BUSY* PM_EXTTS0* PM_EXTTS1* PW_THRMTRIP* PWROK RSTIN*

SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC* CLK_REQ*

NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9

NC0 NC1

NC13

NC12

NC11

NC10

NC18

NC17

NC16

NC15

NC14

SM_CK0 SM_CK1 SM_CK2

SM_CK0*

SM_CK3

SM_CK1* SM_CK2* SM_CK3*

SM_CKE0 SM_CKE1

SM_CKE3

SM_CS1* SM_CS2* SM_CS3*

SMOCDCOMP0 SMOCDCOMP1

SM_ODT1

SM_ODT0

SM_ODT2

SMRCOMP*

SM_ODT3

SMRCOMP

SMVREF0 SMVREF1

G_CLKIN*

G_CLKIN

D_REFCLKIN*

D_REFCLKIN

D_REFSSCLKIN*

D_REFSSCLKIN

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0

DMI_TXP2

DMI_TXP1

DMI_TXP3

DDR MUXING

CFG

NC PM

CLKDMI

MISC

(2 OF 10)

RSVD

IN

OUT

IN IN

IN

BI BI OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT

IN

IN IN IN IN IN IN

IN IN IN IN

IN IN

IN

OUT

OUT OUT

OUT

IN IN IN

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC

IPU

NC NC

IPU IPU IPU IPU

IPU IPU IPU

IPU

IPD

IPU

NC

NC NC

NC

(D_PLLMON1#)

(VSS_MCHDETECT)

(H_PCREQ#)

(H_PLLMON1#)

(H_PLLMON1)

(TV_DCONSEL1)

(TV_DCONSEL0)

(TESTIN#)

(H_PROCHOT#)

(D_PLLMON1)

(H_EDRDY#)

(LB_DATAP3)

(LB_DATAN3)

(LA_DATAP3)

(LA_DATAN3)

IPD

NC

U1200

K16 K18

E16 D15 G15 K15 C15 H16 G18 H15 J25 K27

J18

J26

F18 E15 F15 E18 D19 D16 G16

H32

A26

A27

D41

C40

AE35 AF39 AG35 AH39

AC35 AE39 AF35 AG39

AE37 AF41 AG37 AH41

AC37 AE41 AF37 AG41

AG33

AF33

K28

D1

C41

B2

AY41

AY1

AW41

AW1 A40

A4

A39

A3

C1 BA41 BA40 BA39

BA3 BA2 BA1 B41

G28 F25 H26

G6 AH33 AH34

T32

J29 A41 A35 A34 D28 D27

R32

F3

F7 AG11 AF11

H7

J19 K30

H28 H27

AY35

AW35

AR1

AT1

AW7

AY7

AW40

AY40

AU20 AT20 BA29 AY29

AW13 AW12 AY21 AW21

BA13 BA12 AY20 AU21

AL20 AF10

AT9

AV9

AK1 AK41

BGA

NB

945GM

OMIT

6

20

R1430

1 2

402

MF-LF

1/16W

5%

100

5

22 26

R1441

1

2

10K

402

5% MF-LF

1/16W

R1440

1

2

10K

402

5% 1/16W MF-LF

14 28 29 32

C1416

1

2

0.1uF

402

CERM

10V

20%

C1415

1

2

0.1uF

402

CERM

10V

20%

23

7

21 51

28 29 50 51

5

23 60 86

5

26 60

19

5

22

5

33

28

29

28

29

28

28 30

29 30

28 30

29 30

28 30

29 30

28 30

29 30

R1410

1

2

1/16W

1%

402

MF-LF

80.6

R1411

1

2

1/16W

1%

402

MF-LF

80.6

14 28 29 32

5

34

5

34

22

5

22

5

22

5

22

5

22

R1420

1

2

1/16W

5%

402

MF-LF

10K

34

20

6

20

6

20

6

20

6

20

NB Misc Interfaces

SYNC_DATE=02/10/2006

SYNC_MASTER=M1_MLB

051-7023

06

8614

PM_EXTTS_L

NB_RST_IN_L_R

CLK_NB_OE_L

GND GND GND GND

PP3V3_S0

NB_TV_DCONSEL1

NB_TV_DCONSEL0

NC_NB_XOR_LVDS_A35

TP_NB_TESTIN_L

PM_DPRSLPVR

PP3V3_S0

NB_CFG<18>

NB_CFG<13>

NB_CFG<11>

NB_CFG<8>

PLT_RST_L

DMI_N2S_P<3>

DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_S2N_N<1>

DMI_S2N_N<0>

NB_CLK100M_GCLKIN_P

NB_CLK100M_GCLKIN_N

MEM_ODT<3>

MEM_ODT<0>

MEM_CKE<3>

MEM_CKE<1>

MEM_CKE<0>

MEM_CLK_N<3>

MEM_CLK_N<2>

MEM_CLK_N<1>

MEM_CLK_P<3> MEM_CLK_N<0>

MEM_CLK_P<2>

MEM_CLK_P<1>

MEM_CLK_P<0>

NB_SB_SYNC_L

TP_SDVO_CTRLDATA

TP_SDVO_CTRLCLK

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

PM_BMBUSY_L

NB_CFG<20>

NB_CFG<19>

TP_NB_CFG<15> NB_CFG<16> NB_CFG<17>

TP_NB_CFG<14>

NB_CFG<10>

NB_CFG<9>

NB_CFG<7>

NB_CFG<5> NB_CFG<6>

NB_CFG<4>

NB_CFG<3>

NB_BSEL<2>

NB_BSEL<0> NB_BSEL<1>

MEM_CS_L<0>

NB_CFG<12>

MEM_ODT<2>

MEM_ODT<1>

MEM_CS_L<3>

MEM_CS_L<2>

MEM_CS_L<1>

MEM_CKE<2>

PP1V8_S3

MEM_RCOMP_L MEM_RCOMP

MEMORY_VREF MEMORY_VREF

NC_NB_XOR_LVDS_A34 NC_NB_XOR_LVDS_D28 NC_NB_XOR_LVDS_D27

TP_NB_XOR_FSB2_H7

79

78

70

66

65

64

60

59

57

56

53

51

48

43

37

36

34

33

29

28

27

26

25

66

24

63

23

54

22

37

21

32

20

31

19

29

17

28

14

19

10

16

5

4

19

4

19

SA_DQ1

SA_DQ0

SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10

SA_DQ12

SA_DQ11

SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27

SA_DQ29

SA_DQ28

SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33

SA_DQ35

SA_DQ34

SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44

SA_DQ46

SA_DQ45

SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS1

SA_BS0

SA_BS2

SA_CAS*

SA_DM0 SA_DM1 SA_DM2 SA_DM3

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0

SA_DQS2

SA_DQS1

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6 SA_DQS7

SA_DQS3*

SA_DQS2*

SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7*

SA_MA1

SA_MA0

SA_MA2 SA_MA3

SA_MA5

SA_MA4

SA_MA6 SA_MA7

SA_MA9

SA_MA8

SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_RAS*

SA_RCVENIN*

SA_RCVENOUT*

SA_WE*

SA_DQS1*

SA_DQS0*

(4 OF 10)

DDR SYSTEM MEMORY A

BI

BI BI BI BI BI

OUT

BI

OUT

BI BI BI

BI

BI BI BI BI

BI BI

BI BI BI BI BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI

BI

SB_DQ1

SB_DQ0

SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10

SB_DQ12

SB_DQ11

SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27

SB_DQ29

SB_DQ28

SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33

SB_DQ35

SB_DQ34

SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44

SB_DQ46

SB_DQ45

SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS1

SB_BS0

SB_BS2

SB_CAS*

SB_DM0 SB_DM1 SB_DM2 SB_DM3

SB_DM5

SB_DM4

SB_DM7

SB_DM6

SB_DQS0

SB_DQS2

SB_DQS1

SB_DQS3

SB_DQS5

SB_DQS4

SB_DQS6 SB_DQS7

SB_DQS3*

SB_DQS2*

SB_DQS4* SB_DQS5* SB_DQS6* SB_DQS7*

SB_MA1

SB_MA0

SB_MA2 SB_MA3

SB_MA5

SB_MA4

SB_MA6 SB_MA7

SB_MA9

SB_MA8

SB_MA10 SB_MA11 SB_MA12 SB_MA13

SB_RAS*

SB_RCVENIN*

SB_RCVENOUT*

SB_WE*

SB_DQS1*

SB_DQS0*

(5 OF 10)

DDR SYSTEM MEMORY B

BI BI BI BI BI

BI BI

BI

OUT

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

BI

OUT

BI

BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

OUT

BI

OUT OUT

OUT

BI

OUT

BI

OUT OUT OUT

BI

OUT OUT

OUT

BI

OUT

BI

BI BI BI BI BI BI BI BI BI BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NC NC

U1200

AU12 AV14 BA20

AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4

AJ35 AJ34

AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24

AM31

AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24

AM33

AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12

AJ36

AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2

AK35

AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6

AJ32

AG9 AH6 AF4 AF8

AH31 AN35 AP33

AK33

AK32

AT33

AU33

AN28

AN27

AM22

AM21

AN12

AM12

AN8

AL8

AP3

AN3

AG5

AH5

AY16 AU14

AU13 AT17 AV20 AV12

AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16

AW14 AK23 AK24 AY14

OMIT

NB

945GM

BGA

28

29

28 29

29

28

29

28

29

28

29

28

29

U1200

AT24 AV23 AY28

AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4

AK39 AJ37

AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36

AP39

BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31

AR41

AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15

AJ38

AJ11 AH10

AJ9 AN10 AK13 AH11 AK10

AJ8 BA10 AW10

AK38

BA4

AW4 AY10

AY9

AW5

AY5

AV4

AR5

AK4

AK3

AN41

AT4

AK5

AJ5

AJ3

AP41 AT40 AV41

AM39

AM40

AT39

AU39

AU35

AT35

AR29

AP29

AR16

AP16

AR10

AT10

AR7

AT7

AN5

AP5

AY23 AW24

AV24 BA27 AY27 AR23

AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27

AU23 AK16 AK18 AR27

OMIT

NB

945GM

BGA

29

28

29

29 30

28

29 30

28

29 30

29

28

29

28

29

29 30

28

29 30

28

28 30

28

28 30

28

28 30

28

28 30

28

15 86

06

051-7023

NB DDR2 Interfaces

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

MEM_A_DQ<5>

MEM_A_DQS_N<0> MEM_A_DQS_N<1>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<8> MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<4> MEM_A_A<5>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0> MEM_A_A<1>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<2> MEM_A_DQS_N<3>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<4> MEM_A_DQS_P<5>

MEM_A_DQS_P<3>

MEM_A_DQS_P<1> MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

MEM_A_DM<6> MEM_A_DM<7>

MEM_A_DM<4> MEM_A_DM<5>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<1>

MEM_A_DM<0>

MEM_A_CAS_L

MEM_A_BS<2>

MEM_A_BS<0> MEM_A_BS<1>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<45> MEM_A_DQ<46>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<28> MEM_A_DQ<29>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<11> MEM_A_DQ<12>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<0> MEM_A_DQ<1>

MEM_B_DQS_N<0> MEM_B_DQS_N<1>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<8> MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<4> MEM_B_A<5>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<0> MEM_B_A<1>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<2> MEM_B_DQS_N<3>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<4> MEM_B_DQS_P<5>

MEM_B_DQS_P<3>

MEM_B_DQS_P<1> MEM_B_DQS_P<2>

MEM_B_DQS_P<0>

MEM_B_DM<6> MEM_B_DM<7>

MEM_B_DM<4> MEM_B_DM<5>

MEM_B_DM<3>

MEM_B_DM<2>

MEM_B_DM<1>

MEM_B_DM<0>

MEM_B_CAS_L

MEM_B_BS<2>

MEM_B_BS<0> MEM_B_BS<1>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<45> MEM_B_DQ<46>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<34> MEM_B_DQ<35>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<28> MEM_B_DQ<29>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<11> MEM_B_DQ<12>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<0> MEM_B_DQ<1>

VCC_SM19

VCC_SM107

VCC_SM105

VCC_SM106

VCC_SM102

VCC_SM104

VCC_SM103

VCC_SM100

VCC_SM101

VCC_SM98

VCC_SM99

VCC_SM97

VCC_SM95

VCC_SM96

VCC_SM93

VCC_SM94

VCC_SM92

VCC_SM91

VCC_SM90

VCC_SM89

VCC_SM88

VCC_SM86

VCC_SM87

VCC_SM85

VCC_SM84

VCC_SM83

VCC_SM81

VCC_SM80

VCC_SM82

VCC_SM79

VCC_SM78

VCC_SM77

VCC_SM74

VCC_SM75

VCC_SM76

VCC_SM73

VCC_SM72

VCC_SM70

VCC_SM71

VCC_SM68

VCC_SM67

VCC_SM69

VCC_SM65

VCC_SM66

VCC_SM64

VCC_SM63

VCC_SM62

VCC_SM61

VCC_SM60

VCC_SM59

VCC_SM58

VCC_SM56

VCC_SM57

VCC_SM55

VCC_SM53

VCC_SM54

VCC_SM52

VCC_SM50

VCC_SM51

VCC_SM49

VCC_SM48

VCC_SM46

VCC_SM47

VCC_SM44

VCC_SM45

VCC_SM43

VCC_SM41

VCC_SM42

VCC_SM40

VCC_SM39

VCC_SM37

VCC_SM38

VCC_SM36

VCC_SM34

VCC_SM35

VCC_SM32

VCC_SM33

VCC_SM30

VCC_SM31

VCC_SM28

VCC_SM29

VCC_SM27

VCC_SM26

VCC_SM25

VCC_SM23

VCC_SM24

VCC_SM22

VCC_SM21

VCC_SM20

VCC_SM18

VCC_SM16

VCC_SM17

VCC_SM15

VCC_SM13

VCC_SM14

VCC_SM11

VCC_SM12

VCC_SM10

VCC_SM9

VCC_SM8

VCC_SM7

VCC_SM6

VCC_SM5

VCC_SM4

VCC_SM3

VCC_SM0

VCC_SM1

VCC_SM2

VCC_110

VCC_109

VCC_108

VCC_105

VCC_106

VCC_107

VCC_104

VCC_103

VCC_101

VCC_100

VCC_102

VCC_98

VCC_99

VCC_96

VCC_97

VCC_95

VCC_94

VCC_93

VCC_92

VCC_91

VCC_90

VCC_88

VCC_89

VCC_87

VCC_86

VCC_85

VCC_83

VCC_84

VCC_82

VCC_80

VCC_81

VCC_79

VCC_78

VCC_76

VCC_77

VCC_74

VCC_73

VCC_75

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_65

VCC_64

VCC_62

VCC_63

VCC_61

VCC_60

VCC_59

VCC_57

VCC_58

VCC_55

VCC_56

VCC_53

VCC_54

VCC_52

VCC_50

VCC_51

VCC_49

VCC_46

VCC_47

VCC_48

VCC_44

VCC_45

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_34

VCC_35

VCC_33

VCC_32

VCC_31

VCC_30

VCC_28

VCC_29

VCC_25

VCC_26

VCC_27

VCC_24

VCC_23

VCC_21

VCC_20

VCC_22

VCC_13

VCC_14

VCC_12

VCC_16

VCC_15

VCC_17

VCC_18

VCC_19

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_4

VCC_5

VCC_6

VCC_2

VCC_3

VCC_0

VCC_1

(6 OF 10)

VCC

VCCAUX_NCTF57

VCCAUX_NCTF56

VCCAUX_NCTF55

VCCAUX_NCTF54

VCCAUX_NCTF53

VCCAUX_NCTF52

VCCAUX_NCTF51

VCCAUX_NCTF50

VCCAUX_NCTF49

VCCAUX_NCTF47 VCCAUX_NCTF48

VCCAUX_NCTF45

VCCAUX_NCTF44

VCCAUX_NCTF46

VCCAUX_NCTF40

VCCAUX_NCTF39

VCCAUX_NCTF37 VCCAUX_NCTF38

VCCAUX_NCTF36

VCCAUX_NCTF34 VCCAUX_NCTF35

VCCAUX_NCTF32 VCCAUX_NCTF33

VCCAUX_NCTF31

VCCAUX_NCTF30

VCCAUX_NCTF29

VCCAUX_NCTF27 VCCAUX_NCTF28

VCCAUX_NCTF26

VCCAUX_NCTF24 VCCAUX_NCTF25

VCCAUX_NCTF22

VCCAUX_NCTF21

VCCAUX_NCTF23

VCCAUX_NCTF42 VCCAUX_NCTF43

VCCAUX_NCTF41

VCCAUX_NCTF19 VCCAUX_NCTF20

VCCAUX_NCTF18

VCCAUX_NCTF17

VCCAUX_NCTF16

VCCAUX_NCTF14 VCCAUX_NCTF15

VCCAUX_NCTF13

VCCAUX_NCTF12

VCCAUX_NCTF11

VCCAUX_NCTF9

VCCAUX_NCTF10

VCCAUX_NCTF8

VCCAUX_NCTF7

VCCAUX_NCTF6

VCCAUX_NCTF5

VCCAUX_NCTF4

VCCAUX_NCTF3

VCCAUX_NCTF1

VCCAUX_NCTF0

VCCAUX_NCTF2

VSS_NCTF12

VSS_NCTF11

VSS_NCTF10

VSS_NCTF9

VSS_NCTF7 VSS_NCTF8

VSS_NCTF5 VSS_NCTF6

VSS_NCTF4

VSS_NCTF2 VSS_NCTF3

VSS_NCTF0 VSS_NCTF1

VCC_NCTF72

VCC_NCTF71

VCC_NCTF70

VCC_NCTF69

VCC_NCTF68

VCC_NCTF67

VCC_NCTF66

VCC_NCTF65

VCC_NCTF64

VCC_NCTF61 VCC_NCTF62 VCC_NCTF63

VCC_NCTF60

VCC_NCTF57 VCC_NCTF58 VCC_NCTF59

VCC_NCTF56

VCC_NCTF55

VCC_NCTF53 VCC_NCTF54

VCC_NCTF52

VCC_NCTF50 VCC_NCTF51

VCC_NCTF49

VCC_NCTF48

VCC_NCTF46 VCC_NCTF47

VCC_NCTF45

VCC_NCTF44

VCC_NCTF43

VCC_NCTF41

VCC_NCTF40

VCC_NCTF42

VCC_NCTF38 VCC_NCTF39

VCC_NCTF36 VCC_NCTF37

VCC_NCTF34 VCC_NCTF35

VCC_NCTF33

VCC_NCTF31 VCC_NCTF32

VCC_NCTF30

VCC_NCTF29

VCC_NCTF28

VCC_NCTF27

VCC_NCTF26

VCC_NCTF25

VCC_NCTF24

VCC_NCTF23

VCC_NCTF22

VCC_NCTF21

VCC_NCTF20

VCC_NCTF18 VCC_NCTF19

VCC_NCTF17

VCC_NCTF16

VCC_NCTF15

VCC_NCTF13 VCC_NCTF14

VCC_NCTF11 VCC_NCTF12

VCC_NCTF10

VCC_NCTF8 VCC_NCTF9

VCC_NCTF7

VCC_NCTF6

VCC_NCTF5

VCC_NCTF4

VCC_NCTF3

VCC_NCTF2

VCC_NCTF0 VCC_NCTF1

(7 OF 10)

NCTF

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1.8V Max Current Speed 1 Channel 2 Channel 400MTs 1300mA 2400mA 533MTs 1500mA 2800mA 667MTs 1700mA 3200mA

1.05V, Internal Graphics: 3500mA Max

1.5V, Internal Graphics: 5500mA Max

1.05V, External Graphics: 1500mA Max

1.05V or 1.5V

Place in cavity

Layout Note:

Layout Note: Place near pin BA15

Place near pin BA23

Layout Note:

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

U1200

AA33

W33

P32

M19

L19

N18

M18

L18

P17

N17

M17

N16

M16

N32

L16

M32

L32

J32

AA31

W31

V31

T31

R31

P33

P31

N31

M31

AA30

Y30

W30

V30

U30

T30

R30

N33

P30

N30

M30

L30

AA29

Y29

W29

V29

U29

R29

L33

P29

M29

L29

AB28

AA28

Y28

V28

U28

T28

R28

J33

P28

N28

M28

L28

P27

N27

M27

L27

P26

N26

AA32

L26

N25

M25

L25

P24

N24

M24

AB23

AA23

Y23

Y32

P23

N23

M23

L23

AC22

AB22

Y22

W22

P22

N22

W32

M22

L22

AC21

AA21

W21

N21

M21

L21

AC20

AB20

V32

Y20

W20

P20

N20

M20

L20

AB19

AA19

Y19

N19

AU41

AT41

AR34

AR6

AP6

AN6

AL6

AK6

AJ6

AV1

AJ1

BA30

AY30

AW30

AV30

AU30

AT30

AR30

AP30

AN30

AM41

AM30

AM29

AL29

AK29

AJ29

AH29

AJ28

AH28

AJ27

AH27

AU40

BA26

AY26

AW26

AV26

AU26

AT26

AR26

AJ26

AH26

AJ25

BA34

AH25

AJ24

AH24

BA23

AJ23

BA22

AY22

AW22

AV22

AU22

AY34

AT22

AR22

AP22

AK22

AJ22

AK21

AK20

BA19

AY19

AW19

AW34

AV19

AU19

AT19

AR19

AP19

AK19

AJ19

AJ18

AJ17

AH17

AV34

AJ16

AH16

BA15

AY15

AW15

AV15

AU15

AT15

AR15

AJ15

AU34

AJ14

AJ13

AH13

AK12

AJ12

AH12

AG12

AK11

BA8

AY8

AT34

AW8

AV8

AT8

AR8

AP8

BA6

AY6

AW6

AV6

AT6

BGA

NB

945GM

OMIT

C1610

1

2

402

6.3V CERM-X5R

0.47uF

20%

C1621

1

2

603

20% X5R

6.3V

10uF

C1620

1

2

10uF

6.3V X5R

20%

603

U1200

AD27 AC27

AD26 AC26 AB26 AA26

Y26 W26 V26 U26 T26 R26

AB27

AD25 AC25 AB25 AA25

Y25 W25 V25 U25 T25 R25

AA27

AD24 AC24 AB24 AA24

Y24 W24 V24 U24 T24 R24

Y27

AD23

V23 U23 T23 R23

AD22

V22 U22 T22 R22

W27

AD21

V21 U21 T21 R21

AD20

V20 U20 T20 R20

V27

AD19

V19 U19

T19 AD18 AC18 AB18 AA18

Y18

W18

U27

V18

U18

T18

T27

R27

AG27 AF27

AG22 AF22 AG21 AF21 AG20 AF20 AG19 AF19 R19 AG18

AG26

AF18 R18 AG17 AF17 AE17 AD17 AB17 AA17 W17 V17

AF26

T17 R17 AG16 AF16 AE16 AD16 AC16 AB16 AA16 Y16

AG25

W16 V16 U16 T16 R16 AG15 AF15 AE15 AD15 AC15

AF25

AB15 AA15 Y15 W15 V15 U15 T15 R15

AG24 AF24 AG23 AF23

AE27 AE26

AC17 Y17 U17

AE25 AE24 AE23 AE22 AE21 AE20 AE19 AE18

945GM

NB

BGA

OMIT

C1611

1

2

402

6.3V CERM-X5R

0.47uF

20%

C1612

1

2

402

6.3V

CERM-X5R

0.47uF

20%

C1613

1

2

402

6.3V CERM-X5R

20%

0.47uF

C1614

1

2

402

6.3V

CERM-X5R

20%

0.47uF

C1615

1

2

402

6.3V CERM-X5R

20%

0.47uF

NB Power 1

SYNC_DATE=02/10/2006

SYNC_MASTER=M1_MLB

051-7023

06

8616

PP1V5_S0

PP1V05_S0

NB_VCCSM_LF4 NB_VCCSM_LF5

NB_VCCSM_LF2 NB_VCCSM_LF1

PP1V8_S3

66

64

54

34

25

24

66

21

63

65

19

54

47

17

37

25

16

32

24

13

31

19

12

29

17

11

28

13

9

19

9

8

14

8

7

5

4

VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8

VTT9 VTT10 VTT11 VTT12 VTT13

VTT15

VTT14

VTT16

VTT18

VTT17

VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25

VTT27

VTT26

VTT28 VTT29

VTT31

VTT30

VTT32

VTT34

VTT33

VTT35 VTT36 VTT37

VTT39

VTT38

VTT40 VTT41 VTT42 VTT43 VTT44 VTT45

VTT48

VTT46 VTT47

VTT49 VTT50

VTT52

VTT51

VTT53

VTT55

VTT54

VTT57

VTT56

VTT58 VTT59 VTT60 VTT61 VTT62

VTT64

VTT63

VTT65 VTT66 VTT67

VTT69

VTT68

VTT70 VTT71

VTT73

VTT72

VTT74

VTT76

VTT75

VCCSYNC

VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2

VCC3G0 VCC3G1

VCC3G3

VCC3G2

VCC3G4

VCC3G6

VCC3G5

VCCA_3GPLL VCCA_3GBG VSSA_3GBG

VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC

VCCA_DPLLB

VCCA_DPLLA

VCCA_HPLL

VSSA_LVDS

VCCA_LVDS

VCCA_MPLL

VCCA_TVBG VSSA_TVBG

VCCA_TVDACC0 VCCA_TVDACC1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACA0 VCCA_TVDACA1

VCCD_HMPLL0 VCCD_HMPLL1

VCCD_LVDS2

VCCD_LVDS0 VCCD_LVDS1

VCCD_TVDAC

VCC_HV1 VCC_HV2

VCC_HV0

VCCD_QTVDAC

VCCAUX19

VCCAUX18

VCCAUX17

VCCAUX16

VCCAUX14 VCCAUX15

VCCAUX13

VCCAUX12

VCCAUX11

VCCAUX10

VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4

VCCAUX6

VCCAUX5

VCCAUX9

VCCAUX8

VCCAUX7

VCCAUX21

VCCAUX20

VCCAUX23 VCCAUX24

VCCAUX22

VCCAUX25 VCCAUX26

VCCAUX29

VCCAUX28

VCCAUX27

VCCAUX30 VCCAUX31

VCCAUX33

VCCAUX32

VCCAUX34 VCCAUX35 VCCAUX36

VCCAUX38

VCCAUX37

VCCAUX39 VCCAUX40

POWER

(8 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

1500mA Max VCC3G/3GPLL

800mA Max

2mA Max

60mA Max

70mA Max VCCA_CRTDAC/VCCSYNC

20mA Max

24mA Max

10mA Max

50mA Max 50mA Max

45mA Max

120mA Max

150mA Max

See VCCSYNC

40mA Max

1900mA Max

U1200

AJ41 AB41

Y41 V41 R41 N41 L41

A23 B23 B25

C30 B30 A30

G41

AC33

F21 E21

B26 C39 AF1

A38

AF2

H20

E19 F19

C20 D20

E20 F20

AK31 AF31

AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28

AE31

AE28 AH22 AJ21 AH21 AJ20 AH20 AH19

P19 P16

AH15

AC31

P15 AH14 AG14 AF14 AE14

Y14 AF13 AE13 AF12 AE12

AL30

AD12

AK30 AJ30 AH30 AG30 AF30

AH1 AH2

A28 B28 C28

H19

D21

H22

H41

G21

B39

G20

AC14 AB14

AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13

W14

N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12

V14

R12 P12 N12 M12 L12 R11 P11 N11 M11 R10

T14

P10 N10 M10 P9 N9 M9 R8 P8 N8 M8

R14

P7 N7 M7 R6 P6 M6 A6 R5 P5 N5

P14

M5 P4 N4 M4 R3 P3 N3 M3 R2 P2

N14

M2 D2 AB1 R1 P1 N1 M1

M14 L14

OMIT

BGA

NB

945GM

C1711

1

2

402

CERM-X5R

6.3V

0.47uF

20%

C1712

1

2

20%

0.22uF

6.3V 402

X5R

C1713

1

2

402

6.3V

CERM-X5R

20%

0.47uF

SYNC_DATE=02/10/2006

SYNC_MASTER=M1_MLB

NB Power 2

051-7023

06

8617

GND

PP1V5_S0

PP1V05_S0

NB_VTTLF_CAP3

NB_VTTLF_CAP2 NB_VTTLF_CAP1

GND GND

PP1V5_S0_NB_VCC3G

PP1V5_S0_NB_VCCA_3GPLL PP2V5_S0 GND

GND

TP_NB_VCCA_DPLLB

TP_NB_VCCA_DPLLA

PP1V5_S0_NB_VCCA_HPLL

NC_GND_NB_VSSA_LVDS

GND

PP1V5_S0_NB_VCCA_MPLL PP1V5_S0

GND PP1V5_S0

PP1V5_S0

PP3V3_S0

PP1V5_S0 PP1V5_S0

PP1V05_S0

79 78 70

66 65 64 60 59 57 56 53 51 48 43 37 36

66

34

66

64

33

64

54

29

54

34

28

34

25

27

25

66

24

66

26

66

24

65

21

65

25

65

21

47

19

47

24

47

19

25

17

25

23

25

17

24

16

24

22

24

16

19

13

77

19

21

19

13

17

12

76

17

20

17

12

16

11

66

16

19

16

11

13

9

65

13

14

13

9

8

62

9

10

9

8

7

19

8

5

8

7

5

19

5

19

5

4

5

VSS_1

VSS_0

VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7

VSS_9

VSS_8

VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17

VSS_19

VSS_18

VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26

VSS_28

VSS_27

VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35

VSS_37

VSS_36

VSS_39

VSS_38

VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47

VSS_49

VSS_48

VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

VSS_57

VSS_56

VSS_59

VSS_58

VSS_61

VSS_60

VSS_64

VSS_63

VSS_62

VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71

VSS_73

VSS_72

VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79

VSS_82

VSS_80 VSS_81

VSS_84

VSS_83

VSS_85

VSS_87

VSS_86

VSS_89

VSS_88

VSS_91

VSS_90

VSS_92 VSS_93 VSS_94

VSS_96

VSS_95

VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112

VSS_114

VSS_113

VSS_115

VSS_117

VSS_116

VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125

VSS_127

VSS_126

VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135

VSS_137

VSS_136

VSS_138 VSS_139 VSS_140 VSS_141

VSS_143

VSS_142

VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156

VSS_158

VSS_157

VSS_159 VSS_160 VSS_161 VSS_162

VSS_164

VSS_163

VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170

VSS_172

VSS_171

VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179

VSS

(9 OF 10)

VSS_272

VSS_271

VSS_269 VSS_270

VSS_268

VSS_266 VSS_267

VSS_265

VSS_264

VSS_263

VSS_261 VSS_262

VSS_260

VSS_259

VSS_258

VSS_256 VSS_257

VSS_255

VSS_254

VSS_253

VSS_251 VSS_252

VSS_250

VSS_248 VSS_249

VSS_247

VSS_246

VSS_245

VSS_243 VSS_244

VSS_242

VSS_241

VSS_240

VSS_238 VSS_239

VSS_237

VSS_236

VSS_235

VSS_233 VSS_234

VSS_232

VSS_231

VSS_230

VSS_228 VSS_229

VSS_227

VSS_225 VSS_226

VSS_224

VSS_223

VSS_222

VSS_220 VSS_221

VSS_219

VSS_218

VSS_217

VSS_215 VSS_216

VSS_214

VSS_213

VSS_212

VSS_210 VSS_211

VSS_209

VSS_207 VSS_208

VSS_205 VSS_206

VSS_204

VSS_202 VSS_203

VSS_201

VSS_200

VSS_199

VSS_197 VSS_198

VSS_196

VSS_195

VSS_194

VSS_192 VSS_193

VSS_191

VSS_190

VSS_189

VSS_187 VSS_188

VSS_186

VSS_184 VSS_185

VSS_183

VSS_182

VSS_180 VSS_181

VSS_273 VSS_274

VSS_276

VSS_275

VSS_277

VSS_279

VSS_278

VSS_281

VSS_280

VSS_282 VSS_283 VSS_284

VSS_286

VSS_285

VSS_287 VSS_288 VSS_289

VSS_291

VSS_290

VSS_293

VSS_292

VSS_294

VSS_296

VSS_295

VSS_297

VSS_299

VSS_298

VSS_301 VSS_302

VSS_300

VSS_304

VSS_303

VSS_305 VSS_306 VSS_307

VSS_309

VSS_308

VSS_311

VSS_310

VSS_312 VSS_313 VSS_314 VSS_315

VSS_317

VSS_316

VSS_318 VSS_319 VSS_320

VSS_322

VSS_321

VSS_323 VSS_324 VSS_325

VSS_327

VSS_326

VSS_328 VSS_329 VSS_330

VSS_332

VSS_331

VSS_334

VSS_333

VSS_335

VSS_337

VSS_336

VSS_338 VSS_339 VSS_340

VSS_342 VSS_343

VSS_341

VSS_345

VSS_344

VSS_346 VSS_347 VSS_348

VSS_350

VSS_349

VSS_352

VSS_351

VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360

VSS

(10 OF 10)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

U1200

AC41 AA41

AN40

AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33

AK40

T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32

AJ40

AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31

AH40

AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29

AG40

K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28

AF40

AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27

AE40

G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25

B40

P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23

AY39 AW39

W41

AV39 AR39 AN39 AJ39 AC39 AB39 AA39

Y39 W39 V39

T41

T39 R39 P39 N39 M39 L39 J39 H39 G39 F39

P41

D39 AT38 AM38 AH38 AG38 AF38 AE38

C38 AK37 AH37

M41

AB37 AA37

Y37

W37

V37

T37

R37

P37

N37

M37

J41

L37

J37

H37

G37

F37

D37 AY36 AW36 AN36 AH36

F41

AG36 AF36 AE36 AC36

C36

B36 BA35 AV35 AR35 AH35

AV40

AB35 AA35

Y35

W35

V35

T35

R35

P35

N35

M35

AP40

L35

J35

H35

G35

F35

D35 AN34

AK34 AG34 AF34

NB

945GM

BGA

OMIT

U1200

AT23 AN23 AM23 AH23 AC23

W23 K23 J23 F23 C23

AA22

K22 G22 F22 E22 D22

A22 BA21 AV21 AR21 AN21 AL21 AB21

Y21

P21

K21

J21

H21

C21 AW20 AR20 AM20 AA20

K20

B20

A20 AN19 AC19

W19

K19

G19

C19 AH18

P18

H18

D18

A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16

J16

F16

C16 AN15 AM15 AK15

N15

M15

L15

B15

A15 BA14 AT14 AK14 AD14 AA14

U14

K14

H14

E14 AV13 AR13 AN13 AM13 AL13 AG13

P13

F13

D13

B13 AY12 AC12

K12

H12

E12 AD11 AA11

Y11

J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1

NB

945GM

BGA

OMIT

SYNC_DATE=02/10/2006

SYNC_MASTER=M1_MLB

NB Grounds

051-7023

06

8618

IN

IN IN IN

IN

IN IN IN

IN

IN IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Rail Totals: 2310mA Max?

3674mA Max

40mA Max?

Power Interface

These are the power signals that leave the NB "block"

(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)

GMCH CORE PWR 1.05V BYPASS

1500mA Max

1500mA Max 10mA Max?

?mA Max

60mA Max

70mA Max

3200mA Max

24mA Max

100mA Max

?mA Max

800mA Max

?mA Max 40mA Max

1500mA Max

2mA Max

1900mA Max

150mA Max

132mA Max

3200mA Max

(MCH TVDAC DEDICATED PWR 1.5V)

(MCH TVDAC DIGITAL QUIET 1.5V PWR)

(MCH TV OUT CHANNEL A 3.3V PWR)

(MCH TV OUT CHANNEL B 3.3V PWR)

(MCH TV DAC BAND GAP 3.3V PWR)

(MCH TV OUT CHANNEL C 3.3V PWR)

(MCH LVDS DATA/CLK TX 2.5V PWR)

(MCH LVDS DIGITAL 1.5V PWR)

(MCH LVDS ANALOG 2.5V PWR)

(MCH CRTDAC ANALOG 2.5V PWR)

(MCH H/V SYNC 2.5V PWR)

(MCH DISPLAY A PLL 1.5V PWR)

(MCH DISPLAY B PLL 1.5V PWR)

1500mA Max

be close to MCH on opposite side.

GMCH VCCA_3GPLL FILTER

(PCI-E/DMI ANALOG 1.5V PWR)

10uF caps should

Layout Note: Route to caps, then GND

(3GIO PLL 1.5V PWR)

GMCH VCC3G FILTER

Layout Note:

be placed in cavity

3GPLL 10uF cap should

Layout Note:

Place L and C close to MCH

Layout Note:

1500mA Max

GMCH VCCA_HPLL FILTER

45mA Max

(HOST PLL 1.5V PWR)

(MCH MEMORY PLL 1.5V PWR)

GMCH VCCA_MPLL FILTER

45mA Max

100mA Max

GMCH VCCAUX FILTER

1900mA Max

(MCH PCIE/DMI BAND GAP 2.5V PWR)

MCH VCCA_3GBG BYPASS

2mA Max

MCH VCC_HV BYPASS (MCH HV BUFFER 3.3V PWR)

40mA Max

Place on the edge

Layout Note:

(SHARE C0940 470UF)

MCH VTT BYPASS (MCH FSB 1.05V PWR)

Layout Note: Place in cavity

800mA Max

C1907

1

2

402

20%

6.3V X5R

0.22uF

C1972

1

2

10uF

6.3V

20%

603

X5R

C1970

1

2

220UF

20%

2.5V SMB2

POLY

C1967

1

2

0.22uF

X5R 402

20%

6.3V

C1966

1

2

CERM1

20%

2.2uF

603

6.3V

C1965

1

2

4.7uF

CERM 603

20%

6.3V

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

5

17 19 62 65 66 76 77

5 7 8 9

11 12 13 16 17 19 21

24 25 34 54 64 66

4 5

10 14 17 19 20 21 22 23

24 25 26 27 28 29 33 34 36

37

43 48 51 53 56 57 59 60 64

65

66 70 78 79

C1900

1

23

D2TS

CRITICAL

2.5V

20%

470uF-9MOHM

POLY

5 8 9

13 16 17 19 24 25 47 65

66

5 8 9

13 16 17 19 24 25 47 65

66

L1970

1 2

1210

91nH

C1916

1

2

CERM

10V

20% 402

0.1uF

C1906

1

2

402

0.22uF

X5R

20%

6.3V

C1915

1

2

0.1uF

CERM 402

20% 10V

C1914

1

2

10uF

X5R 603

20%

6.3V

C1905

1

2

0.22uF

X5R

20% 402

6.3V

C1935

1

2

0.1uF

CERM 402

10V

20%

L1934

1 2

0603

FERR-120-OHM-0.2A

C1937

1

2

402

10V

20% CERM

0.1uF

C1904

1

2

10% CERM

1uF

6.3V 402

L1936

1 2

0603

FERR-120-OHM-0.2A

C1934

1

2

6.3V

20% 805

CERM

22UF

C1936

1

2

6.3V

20% 805

CERM

22UF

C1903

1

2

10uF

603

20% X5R

6.3V

C1902

1

2

10uF

X5R 603

20%

6.3V

C1918

1

2

CERM

402

20% 10V

0.1uF

C1976

1

2

0.1uF

CERM 402

20% 10V

L1975

1 2

0805

1.0UH-220MA-0.12-OHM

C1975

1

2

10uF

X5R 603

20%

6.3V

R1975

1 2

1%

1/16W

0.51

402

MF-LF

C1971

1

2

6.3V

20%

603

X5R

10uF

19 86

06

051-7023

SYNC_MASTER=M1_MLB

SYNC_DATE=02/08/2006

NB (GM) Decoupling

PP1V05_S0

PP3V3_S0

PP2V5_S0 PP1V5_S0

PP1V5_S0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_MPLL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_HPLL

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.5V

PP1V5_S0_NB_3GPLL_F

GND

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=1.5V

PP1V5_S0_NB_VCCA_3GPLL

PP1V5_S0

GND GND

MAKE_BASE=TRUE

TP_NB_VCCA_DPLLB TP_NB_VCCA_DPLLB

TP_NB_VCCA_DPLLA

MAKE_BASE=TRUE

TP_NB_VCCA_DPLLA

GND

PP1V5_S0

PP1V05_S0 GND

MAKE_BASE=TRUE

NC_GND_NB_VSSA_LVDS

NO_TEST=TRUE

NC_GND_NB_VSSA_LVDS

GND

PP1V5_S0

PP1V05_S0

PP1V5_S0

PP1V05_S0

PP3V3_S0 PP3V3_S0

PP2V5_S0

PP1V5_S0 PP1V5_S0

PP1V5_S0

PP1V05_S0

MAKE_BASE=TRUE

TP_CRT_DDC_CLK

TP_CRT_DDC_DATA

MAKE_BASE=TRUE

TP_CRT_DDC_DATA

TP_CRT_DDC_CLK

PP1V05_S0

PP1V5_S0 PP1V5_S0

PP1V5_S0

TP_LVDS_BKLTEN

MAKE_BASE=TRUE

TP_LVDS_BKLTEN

TP_LVDS_BKLTCTL

MAKE_BASE=TRUE

TP_LVDS_BKLTCTL

TP_LVDS_CLKCTLA

MAKE_BASE=TRUE

TP_LVDS_CLKCTLA

TP_LVDS_CLKCTLB

MAKE_BASE=TRUE

TP_LVDS_CLKCTLB

TP_LVDS_DDC_CLK

MAKE_BASE=TRUE

TP_LVDS_DDC_CLK

NC_LVDS_IBG

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IBG

TP_LVDS_DDC_DATA

MAKE_BASE=TRUE

TP_LVDS_DDC_DATA

TP_LVDS_VREFL

MAKE_BASE=TRUE

TP_LVDS_VREFL

TP_LVDS_VDDEN

MAKE_BASE=TRUE

TP_LVDS_VDDEN

NC_LVDS_VREFH

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_VREFH

NC_LVDS_A_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_CLKP

NC_LVDS_A_CLKN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_CLKN

LVDS_A_DATA_P<2..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_DATAP<2..0>

LVDS_A_DATA_N<2..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_DATAN<2..0>

NC_LVDS_B_CLKN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_B_CLKN

LVDS_B_DATA_P<2..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_B_DATAP<2..0>

NC_LVDS_B_CLKP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_B_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_NB_XOR_LVDS_A35

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_NB_XOR_LVDS_D27

NC_NB_XOR_LVDS_D28

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_NB_XOR_LVDS_D28

NC_NB_XOR_LVDS_A35

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_NB_XOR_LVDS_A34

TP_SDVO_CTRLDATA

MAKE_BASE=TRUE

TP_SDVO_CTRLDATA

TP_SDVO_CTRLCLK

MAKE_BASE=TRUE

TP_SDVO_CTRLCLK

NC_NB_XOR_LVDS_A34

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_DATAN<2..0>

PP1V5_S0

GND

LVDS_B_DATA_N<2..0>

NC_NB_XOR_LVDS_D27

GND

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP1V5_S0_NB_VCC3G

VOLTAGE=1.5V

PP1V5_S0

PP1V8_S3

GND

79 78 70 66 65 64

60 59 57 56

53 51 48 43 37 36 34 66 33

66

64 29

64

54 28

54

34

27

34

25 26

25

24 25

66

24

66

24

66

21 24

65

21

65

21

65

19

23

47

19

47

19

47

17

22

25

17

25

17

25

16

21

77 24

24

16

24

16

24

13 20

76 19

19

13

19

13

19

12 19

66 17

17

12

17

12

17

11 17

65 16

16

11

16

11

16

9

14

62 13

13

9

13

9

13

8

10

19

9

8

9

8

9

7 5

17

8

19 19

8

7

19 19

8

7

19

19 19

19

7

8

19 19

19

19 19

19

19 19

19

8

19

5 4

5 5

5

17

5

17 17

5

17 17

5

13

13 13

13

5

13 13

13

13 13

13

13 13

14

14 14

14

14 14

14

13

5

14

17

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

Internal pull-ups

Internal pull-up

RESERVED

NB_CFG<11>

NB_CFG<10>

High = Mobile CPU

NB_CFG<7>

RESERVED

Internal pull-up

DMI x2 Select

PROBABLY NOT NEEDED

Lane Reversal

NB_CFG<4>

NB_CFG<3>

RESERVED

NB_CFG<13:12>

NB_CFG<14>

NB_CFG<5>

NB_CFG<15>

NB_CFG<16>

NB_CFG<6>

NB_CFG<17>

NB_CFG<18>

NB_CFG<8>

NB_CFG<9>

NB_CFG<19>

NB_CFG<20>

Low = DMIx2

High = DMIx4

Low = RESERVED

High = Normal

PCIE Graphics

RESERVED

CPU Strap

RESERVED

Low = Reversed

Internal pull-up

11 = Normal Operation

10 = All-Z Mode Enabled

01 = XOR Mode Enabled

00 = Partial Clock Gating Disable

RESERVED

Internal pull-up

RESERVED

High = Enabled Low = Disabled

RESERVED

FSB Dynamic ODT

or PCIe x1

Low = Only SDVO

High = Both active

945 External Design Spec says reserved

Internal pull-down

Low = 1.05V

High = 1.5V

Low = Normal

High = Reversed DMI Lane Reversal

VCC Select

Interop. Mode

PCIe Backward

R2075

1

2

402

5%

2.2K

1/16W MF-LF

NBCFG_DMI_X2

R2085

1

2

5%

2.2K

1/16W MF-LF 402

NBCFG_DYN_ODT_DISABLE

R2058

1

2

402

1/16W

5%

2.2K

NBCFG_VCC_1V5

MF-LF

R2059

1

2

402

MF-LF

1/16W

5%

2.2K

NBCFG_DMI_REVERSE

R2060

1

2

NBCFG_SDVO_AND_PCIE

402

MF-LF

1/16W

5%

2.2K

R2077

1

2

NO STUFF

2.2K

5% 1/16W MF-LF 402

R2079

1

2

402

MF-LF

1/16W

5%

2.2K

NBCFG_PEG_REVERSE

20 86

06

051-7023

NB Config Straps

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

PP3V3_S0

NB_CFG<18>

NB_CFG<19>

NB_CFG<20>

NB_CFG<16>

NB_CFG<5>

NB_CFG<9>

NB_CFG<7>

79

78

70

66

65

64

60

59

57

56

53

51

48

43

37

36

34

33

29

28

27

26

25

24

23

22

21

20

19

17

14

10

5

4

14

BI

IN

OUT

IN

OUT

IN

IN IN

BI BI BI BI

IN

BI

DDACK*

SATARBIASN SATARBIASP

SATA_CLKN SATA_CLKP

SATA_2TXP

SATA_2TXN

SATA_2RXN SATA_2RXP

SATA_0TXP

SATA_0TXN

SATA_0RXP

SATA_0RXN

SATALED*

ACZ_SDOUT

ACZ_SDIN1 ACZ_SDIN2

ACZ_SDIN0

ACZ_SYNC

ACZ_BIT_CLK

LAN_TXD2

LAN_TXD0 LAN_TXD1

LAN_RXD1 LAN_RXD2

LAN_RSTSYNC

LAN_RXD0

LAN_CLK

EE_SHCLK

EE_CS

INTVRMEN

INTRUDER*

RTCRST*

RTCX2

RTCX1

THRMTRIP*

STPCLK*

NMI

SMI*

RCIN*

INTR

INIT*

INIT3_3V*

IGNNE*

GPIO49/CPUPWRGD

FERR*

TP1/DPRSTP*

TP2/DPSLP*

A20M*

CPUSPL*

A20GATE

LFRAME*

LDRQ1*/GPIO23

LDRQ0*

LAD3

LAD2

LAD0 LAD1

EE_DOUT EE_DIN

ACZ_RST*

DIOR*

IDEIRQ

DIOW*

IORDY DDREQ

DD0 DD1

DD3

DD2

DD5

DD4

DD6 DD7 DD8

DD11

DD9

DD10

DD12 DD13 DD14 DD15

DA0 DA1 DA2

DCS3*

DCS1*

AC-97/

AZALIA

RTC

LPC

LAN

CPU

IDE

SATA

(1 OF 6)

OUT OUT

OUT

IN

OUT

IN IN

OUT OUT

IN IN

OUT OUT OUT

IN IN IN

OUT

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

(INT PU) (INT PU)

(WEAK INT PD)

NOTE: R2108=56 IN CV.

BOM CONSOLIDATION

CHANGED TO 54.9 FOR

NOTE: R2110=56 IN CV.

NOTE: PULLED UP PER INTEL

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU

INTEL CONFIRMS OK TO LEAVE PINS AS NC

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

INTO RESET STATE TO SAVE PWR.

NOTE: POR IS SMC WILL PUT LAN INT’F

NOTE: KEYBOARD CONTROLLER RESET CPU

NOTE: RISING-EDGE TRIGGERED AT CPU

BOM CONSOLIDATION

< 2 IN OF SB

LAYOUT NOTE: R2107 TO BE

CHANGED TO 54.9 FOR

LAYOUT NOTE: R2108 TO BE < 2 IN OF R2107 W/O STUB

(DSTROBE)

20K PD

(STOP)

(HSTROBE)

NOTE: DD<7> HAS INTERNAL 11.5K PD

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

INTERNAL 20K PD ONLY ENABLED IN S3COLD

INTERNAL 20K PD

NONE

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

INTERNAL 20K PD ENABLED WHEN

INTERNAL 20K PD

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

AC ’07

INTERNAL 20K PD

INTERNAL 20K PD ENABLED WHEN

ACZ_SDIN[0-2]

ACZ_RST#

ACZ_BIT_CLK

ACZ_SYNC

ACZ_SDOUT

INTEL HIGH DEFINITION AUDIO

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

NOTE: DDREQ HAS INTERNAL 11.5K PD

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

(WEAK INT PU)

36

7

14 51

5 7

86

7

86

7

86

7

86

5

50 51 52

7

86

5 7

86

7

5 7

86

5 7

60

5

50 52 59

7

86

26

5

26

21 36

5

50 52 59

5

50 52 59

5

50 52 59

R2100

1 2

NOSTUFF

1/16W

MF-LF

0

5%

402

50

R2101

1 2

NOSTUFF

402

2.2K

5% 1/16W MF-LF

R2195

1 2

MF-LF

5%

39

402

1/16W

R2198

1 2

39

R2197

1 2

39

R2196

1 2

39

R2199

1

2

402

10K

5% 1/16W MF-LF

U2100

AE22 AH28

U1

R5 T2 T3 T1

T4

R6

AG27

AH17 AE17 AF17

AE16 AD16

AB15 AE14

AB13 AC14 AF14 AH13 AH14 AC15

AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12

AF16

AE15

AF15 AH15

W1

W3

Y2

Y1

AG26 AG24

AH16

AG22

AF22

AG21

AF25

Y5 W4

AG16

AA6 AB5 AC4 Y6

V3 U3 U5

V4 T5

U7 V6 V7

AC3 AA5

AB3

AH24

AG23

AA3

AB1 AB2

AF3 AE3 AG2 AH2

AF7 AE7 AG6 AH6

AF1 AE1

AF18

AH10 AG10

AF23 AH22 AF26

AF24 AH25

BGA

SB

ICH7-M

OMIT

R2194

1

2

402

10K

5% 1/16W MF-LF

R2105

1

2

332K

402

1%

1/16W

MF-LF

R2107

1 2

24.9

MF-LF 1/16W

1%

402

R2108

1

2

402

MF-LF 1/16W

1%

54.9

R2110

1 2

MF-LF 1/16W

402

54.9

1%

5

47 86

5

47 86

5

47 86

5

47 86

5

47 86

36

80

36

80

5

34

5

34

36

06

21 86

051-7023

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

SB: 1 OF 4

IDE_PDD<3>

IDE_PDD<2>

TP_SB_XOR_V3

TP_SB_XOR_W3

TP_SB_XOR_T5

TP_SB_XOR_V4

TP_SB_XOR_U5

TP_SB_XOR_U3

PP3V3_G3C_SB_RTC_D

ACZ_RST_L

ACZ_BITCLK

SB_RTC_RST_L

SB_RTC_X2

LPC_FRAME_L

TP_SB_GPIO23

TP_SB_DRQ0_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

PP3V3_S0

IDE_PDD<6>

ACZ_SDATAOUT

PM_THRMTRIP_L

PP1V05_S0

SMC_RCIN_L

ACZ_SYNC

IDE_PDCS1_L IDE_PDCS3_L

IDE_PDA<2>

IDE_PDA<1>

IDE_PDA<0>

IDE_PDD<15>

IDE_PDD<14>

IDE_PDD<13>

IDE_PDD<12>

IDE_PDD<10>

IDE_PDD<9>

IDE_PDD<11>

IDE_PDD<8>

IDE_PDD<7>

IDE_PDD<4> IDE_PDD<5>

IDE_PDD<1>

IDE_PDD<0>

IDE_PDDREQ

IDE_PDIORDY

IDE_PDIOW_L

IDE_IRQ14

IDE_PDIOR_L

SB_ACZ_RST_L

TP_CPU_CPUSLP_L

CPU_A20M_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_PWRGD

CPU_IGNNE_L

FWH_INIT_L CPU_INIT_L

CPU_INTR

CPU_SMI_L

CPU_NMI

CPU_STPCLK_L

CPU_THERMTRIP_R

SB_RTC_X1

SB_SM_INTRUDER_L

SB_ACZ_BITCLK SB_ACZ_SYNC

ACZ_SDATAIN<0>

TP_SB_ACZ_SDIN2

TP_SB_ACZ_SDIN1

SB_ACZ_SDATAOUT

TP_SB_SATALED_L TP_SATA_A_D2RN

TP_SATA_A_D2RP TP_SATA_A_R2DN TP_SATA_A_R2DP

SATA_C_D2R_N

SATA_C_R2D_C_N SATA_C_R2D_C_P

SB_CLK100M_SATA_P

SB_CLK100M_SATA_N

SATA_RBIAS

IDE_PDDACK_L

SATA_C_D2R_P

CPU_RCIN_L

SB_A20GATE

CPU_FERR_L

PP1V05_S0

SB_INTVRMEN

TP_SB_XOR_W1 TP_SB_XOR_Y1 TP_SB_XOR_Y2

TP_SB_XOR_U7 TP_SB_XOR_V6 TP_SB_XOR_V7

79

78

70

66

65

64

60

59

57

56

53

51

48

43

37

36

34

33

33 66

66

29

29 64

64

28

28 54

54

27

27 34

34

26

26 25

25

24

24 21

21

23

23 19

19

22

22 17

17

21

21 16

16

20

20 13

13

19

19 12

12

17

17 11

11

14

9

26

10

8

25

5

5 7

7

24

4

4 5

86

5

86

5

IN

BI

IN

OUT

IN IN

OUT OUT

BI BI

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

OUT

IN

OUT

BI

DMI_ZCOMP

DMI_CLKP

DMI_IRCOMP

USBRBIAS*

USBRBIAS

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI2TXN DMI2TXP

DMI3RXN

DMI3TXP

DMI3TXN

DMI3RXP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P

USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P

USBP4N

OC0* OC1* OC2* OC3* OC4*

OC6*/GPIO30

OC5*/GPIO29

SPI_CLK SPI_CS*

SPI_MOSI SPI_MISO

SPI_ARB

DMI_CLKN

DMI2RXP

DMI2RXN

DMI1TXP

DMI1TXN

DMI1RXN DMI1RXP

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

OC7*/GPIO31

PCI-EXP

(3 OF 6)

DMI

SPI

USB

REQ4*/GPIO22

REQ0*

MCH_SYNC*

RSVD8

RSVD7

RSVD6

RSVD5

RSVD4

GPIO5/PIRQH*

GPIO4/PIRQG*

GPIO3/PIRQF*

GPIO2/PIRQE*

GPIO17/GNT5*

GPIO1/REQ5*

GNT4*/GPIO48

C/BE0* C/BE1*

DEVSEL*

PERR*

STOP*

PCIRST*

PME*

PLTRST*

TRDY*

FRAME*

IRDY*

PCICLK

PAR

PLOCK*

SERR*

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

C/BE2* C/BE3*

GNT0* REQ1* GNT1* REQ2* GNT2* REQ3* GNT3*

PIRQA* PIRQB* PIRQC* PIRQD*

RSVD0 RSVD1 RSVD2 RSVD3

MISC

INT I/F

PCI

(2 OF 6)

BI

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI

IN

BI

OUT

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NO STUFF - DEFAULT

GNT[0-3]# HAVE INT 20K PU

(INT 20K PU)

(AKA TP3, INTERNAL 20K PU)

SB: 2 OF 4

ENABLED ONLY WHEN PCIRST#=0

R2211

NOTE: FWH_WP_L NOT USED

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

(INT PD)

GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

PLACE R2204 < 1/2 IN FROM SB

LAYOUT NOTE:

PLACE R2203 < 1/2 IN FROM SB

LAYOUT NOTE:

NOTE:

LPC (DEFAULT) PCI SPI

UNSTUFF

STUFF

UNSTUFFUNSTUFF

UNSTUFF

STUFF

01

10

11

STRAP R2210

NOTE: CHANGE SYMBOL

TO RSVD[1-9]

GNT5# GNT4#

SB BOOT BIOS SELECT

TARGETING FWH BIOS SPACE)

IE SB INVERTS A16 FOR ALL CYCLES

(STRAPPED TO TOP-BLOCK SWAP MODE

STUFF - A16 SWAP OVERRIDE

NOTE:

EXTERNAL 0

EXTERNAL 1

EXTERNAL 2

AIRPORT (MINI-PCIE)

CAMERA

CF/SD

BT

IR

BOM NOTE FOR PD ON PCI_GNT3_L:

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L

AND PWROK=H

34

37

26 37

37

4

26 37

26

5

50 52

39

5

47 49

5

47 49

5

47 49

5

47 49

R2203

1 2

1/16W

402

24.9

MF-LF

1%

49

39

49

50 55

6

22 46

6

46

6

45

5 6

47

5 6

45

5 6

45

5 6

47

6

80

6

80

6

80

6

80

5 6

47

5 6

47

34

14

34

14

5

14

5

14

5

14

5

14

R2222

1

2

10K

1/16W MF-LF

5% 402

USB_G_OC_PU

R2204

1 2

402

22.6

1% 1/16W MF-LF

R2223

1

2

1/16W

5%

10K

MF-LF 402

R2225

1

2

10K

5% 1/16W MF-LF 402

R2226

1

2

402

MF-LF

1/16W

10K

5%

5

37

R2299

1

2

10K

5% 1/16W MF-LF 402

U2100

V26 V25 U28 U27

Y26 Y25 W28 W27

AB26 AB25 AA28 AA27

AD25 AD24 AC28 AC27

AE28 AE27

D25

C25

D3 C4 D5 D4 E5 C3 A2 B3

F26

H26

K26

M26

P26

T25

F25

H25

K25

M25

P25

T24

E28

G28

J28

L28

N28

R28

E27

G27

J27

L27

N27

R27

P1

R2 P6

P2

P5

F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3

D1

D2

OMIT

BGA

SB

ICH7-M

U2100

E18 C18

E14 D14 B12 C13 G15 G13 E12 C11 D11 A11

A16

A10 F11 F10

E9 D9 B9 A8 A6 C7 B6

F18

E6 D6

E16 A18 E17 A17 A15 C14

B15 C12 D12 C15

A12

F16

E7

D16

D17

F13

A14 C8 D8

G8 F7 F8 G7

A7

AH20

E10 A9

B18

C9

A3 B4 C5 B5

E11

C26

B19

D7

C16

C17

E13

A13

AE5 AD5 AG4 AH4 AD9

AE9 AG8 AH8 F21

B10 F15 F14

SB

BGA

ICH7-M

OMIT

50

R2200

1

2

MF-LF

1/16W

5%

10K

402

R2250

1

2

402

MF-LF

1/16W

5%

10K

USB_C_OC_PU

R2251

1

2

10K

5% 1/16W MF-LF 402

USB_E_OC_PU

R2255

1

2

USB_D_OC_PU

MF-LF

1/16W

5%

10K

402

R2298

1

2

MF-LF 402

1/16W

5%

10K

4

37

R2205

1

2

MF-LF

402

5%

10K

1/16W

R2206

1

2

402

10K

MF-LF

5%

1/16W

NOSTUFF

R2207

1

2

MF-LF 1/16W

10K

402

5%

VOLTAGE=0V

R2211

1

2

1/16W MF-LF

5%

1K

402

37

4

37

26 37

26

26 37

5

14

36

26

5

14 26

26 37

26

26 37

051-7023

8622

06

TP_PCI_GNT4_L

PCI_GNT3_L

TP_PCI_GNT2_L

TP_PCI_GNT0_L

TP_PCI_GNT1_L

PP3V3_S5

UNUSED_USB_D_OC_L

UNUSED_USB_B_OC_L

EXCARD_OC_L

RTUSB_OC_L

LT2USB_OC_L

NB_SB_SYNC_L

TP_SB_RSVD9

ODD_PWR_EN_L

SB_GPIO4

SB_GPIO3

SB_GPIO2

PCI_C_BE_L<0> PCI_C_BE_L<1>

PCI_DEVSEL_L

PCI_PERR_L

PCI_RST_L

TP_PCI_PME_L

PLT_RST_L

PCI_TRDY_L

PCI_FRAME_L

PCI_IRDY_L

PCI_CLK_SB

PCI_PAR

PCI_LOCK_L PCI_SERR_L

PCI_AD<0>

PCI_AD<2> PCI_AD<3> PCI_AD<4> PCI_AD<5>

PCI_AD<7> PCI_AD<8> PCI_AD<9> PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18> PCI_AD<19> PCI_AD<20> PCI_AD<21> PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29> PCI_AD<30> PCI_AD<31>

PCI_C_BE_L<3>

INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L

DMI_IRCOMP_R

SB_CLK100M_DMI_P

USB_RBIAS_PN

DMI_N2S_N<0> DMI_N2S_P<0> DMI_S2N_N<0> DMI_S2N_P<0>

DMI_S2N_N<2> DMI_S2N_P<2>

DMI_N2S_N<3>

DMI_S2N_P<3>

DMI_S2N_N<3>

DMI_N2S_P<3>

USB2_RT_N USB2_RT_P USB_TRACKPAD_N USB_TRACKPAD_P USB2_LT_N USB2_LT_P USB2_CAMERA_N USB2_CAMERA_P

USB2_EXCARD_P USB_IR_N USB_IR_P USB_BT_N USB_BT_P USB2_LT2_N

USB2_EXCARD_N

SB_GPIO30

SB_GPIO29

SB_CLK100M_DMI_N

DMI_N2S_P<2>

DMI_N2S_N<2>

DMI_S2N_P<1>

DMI_S2N_N<1>

DMI_N2S_N<1> DMI_N2S_P<1>

PCIE_A_D2R_N PCIE_A_D2R_P PCIE_A_R2D_C_N PCIE_A_R2D_C_P

PCIE_MINI_D2R_N PCIE_MINI_D2R_P PCIE_B_R2D_C_N PCIE_B_R2D_C_P

PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_C_R2D_C_N PCIE_C_R2D_C_P

TP_PCIE_D_D2RN TP_PCIE_D_D2RP TP_PCIE_D_R2DN TP_PCIE_D_R2DP

TP_PCIE_E_D2RN TP_PCIE_E_D2RP TP_PCIE_E_R2DN TP_PCIE_E_R2DP

TP_PCIE_F_D2RN TP_PCIE_F_D2RP TP_PCIE_F_R2DN TP_PCIE_F_R2DP

LT2USB_OC_L

PP1V5_S0_SB_VCC1_5_B

PP3V3_S5

LTUSB_OC_L

RTUSB_OC_L UNUSED_USB_B_OC_L

UNUSED_USB_D_OC_L

LTUSB_OC_L

SPI_ARB

SPI_SO

USB2_LT2_P

INT_PIRQD_L

TP_SB_XOR_AD5 TP_SB_XOR_AG4 TP_SB_XOR_AH4 TP_SB_XOR_AD9

TP_SB_XOR_AE5

TP_SB_XOR_AH8

SB_CRT_TVOUT_MUX

TP_SB_XOR_AG8

TP_SB_XOR_AE9

SB_GPIO29

EXCARD_OC_L

PCI_AD<6>

PCI_AD<1>

PCI_REQ0_L

PCI_REQ1_L

PCI_REQ3_L

PCI_STOP_L

SPI_SCLK

PCI_C_BE_L<2>

BOOT_LPC_SPI_L

PCI_REQ2_L

SB_GPIO30

SPI_CE_L

SPI_SI

PP3V3_S0

PCI_PME_FW_L

79 78

70 66 65 64 60 59 57 56 53 51 48 43 37 36 34 33 29 28

78

27

66

26

65

25

64

24

62

23

55

21

26

20

25

19

24

51

24

51

17

23

47

23

47

14

22

46

22

10

11

22

6

5

22

5

25

11

6

22

6

22

5

6

5

4

6

22

4

24

5

6

5

22

5

6

4

IN

OUT

OUT OUT OUT

OUT

IN

BI BI

OUT OUT

OUT

IN

BI

IN

BI

IN

IN IN

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

GPIO19/SATA1GP

GPIO21/SATA0GP

GPIO36/SATA2GP

CLK48

GPIO37/SATA3GP

CLK14

SUSCLK

SLP_S3* SLP_S4* SLP_S5*

PWROK

TP0/BATLOW*

GPIO16/DPRSLPVR

PWRBTN*

LAN_RST*

RSMRST*

GPIO10

GPIO9

GPIO12

GPIO14

GPIO13

GPIO24

GPIO15

GPIO25 GPIO35 GPIO38 GPIO39

SMBCLK SMBDATA LINKALERT*

SMLINK1

SMLINK0

RI*

SYS_RST*

SPKR SUS_STAT*

GPIO0/BM_BUSY*

GPIO18/STPPCI*

GPIO11/SMBALERT*

GPIO20/STPCPU*

GPIO26

GPIO28

GPIO27

GPIO32/CLKRUN*

GPIO33/AZ_DOCK_EN*

WAKE*

GPIO34/AZ_DOCK_RST*

SERIRQ THRM*

GPIO7

GPIO6

VRMPWRGD

GPIO8

(4 OF 6)

SMB

GPIO

PWR MNGT

SYS GPIO

CLKS

SATA GPIO

IN

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS

- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

AZALIA DOCKING INT’F

RESERVED FOR MOBILE

SYSTEM REBOOT FEATURE

STRAPPING @ PWROK RISING: SB WILL DISABLE TCO TIMER

NOTE FOR R2323 (DEF=NOSTUFF)

NOT USED

NOTE: RESERVED FOR FUTURE

(INT WEAK PD)

LAYOUT NOTE: PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

NOTE FOR GPIO25:

(INT 20K PU)

OD

DEF=GPI

IN RESET STATE TO SAVE PWR

SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F

NOTE:

NOTE: SV_SET_UP IS LINDACARD DETECT

LO = NOT PRESENT

HI = PRESENT

5

50

5

14 60 86

5

32 39 43 50 54 64 65

5

41 46 47 50 63 65

5

50 51

5 6

34

5

27 28 29 33 45 47

5

27 28 29 33 45 47

5

33

5

33

5

50 51 52 59

5

26 50

14

5

50 52 59

5

39 47

50

5

50 52 59

5

26

50

5

26

23

R2302

1 2

100

R2303

1 2

100

R2305

1 2

100

36

50 51

23

50

R2306

1

2

NOSTUFF

402 5%

MF-LF

1/16W

10K

R2307

1

2

10K

402 5%

MF-LF

1/16W

R2308

1

2

402

1/16W MF-LF

5%

10K

R2309

1

2

5%

MF-LF

1/16W

0

402

NOSTUFF

R2310

1

2

402 5%

MF-LF

1/16W

10K

R2311

1

2

1/16W MF-LF

5%

NOSTUFF

402

10K

R2313

1

2

10K

1/16W MF-LF

5%

402

R2314

1

2

402

NOSTUFF

0

1/16W MF-LF

5%

33

R2316

1

2

402

10K

1/16W MF-LF

5%

R2317

1

2

402

10K

1/16W MF-LF

5%

R2318

1

2

10K

402

1/16W MF-LF

5%

R2319

1

2

10K

1/16W MF-LF

5%

402

R2320

1

2

402 5%

MF-LF

1/16W

10K

RP2300

1 2 3 4

8 7 6 5

1/16W

5%

10K

SM-LF

R2399

1 2

5%

402

MF-LF

1/16W

100K

R2398

1

2

1/16W MF-LF

5%

402

1K

R2397

1

2

5%

MF-LF

1/16W

8.2K

402

R2396

1

2

MF-LF 5%

1/16W

10K

402

R2395

1

2

8.2K

1/16W MF-LF

402 5%

U2100

AC1 B2

AB18

A20

B23

F19 E19 R4 E22

AC22

AC20

AH18

AF21

AF19

R3 D20

A21 B21

E23 AG18 AC19

U2

AD21

AH19 AE19

AD20 AE20

AC21 AC18

E21

E20

C19

A26

C23

AA4

A28

Y4

AH21

B24 D23 F22

C22

B22

B25

A25

A19

A27

C20

A22

AF20

C21

AD22

F20

OMIT

BGA

SB

ICH7-M

R2390

1

2

402

10K

5% 1/16W MF-LF

R2388

1

2

402

1/16W MF-LF

5%

10K

R2323

1

2

MF-LF

402 5%

1K

1/16W

NO_REBOOT_MODE

R2326

1

2

NOSTUFF

10K

1/16W MF-LF 402 5%

R2327

1

2

NOSTUFF

5%

MF-LF

1/16W 402

10K

R2343

1

2

5% 402

8.2K

1/16W MF-LF

50

SB: 3 OF 4

SYNC_DATE=02/10/2006

SYNC_MASTER=M1_MLB

051-7023

8623

06

SV_SET_UP

PM_RSMRST_L

SMBUS_SB_SCL

SATA_C_DET_L

SB_GPIO19

SB_GPIO21

SB_CLK48M_USBCTLR

SB_GPIO37

SB_CLK14P3M_TIMER

TP_SB_SUS_CLK

PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L

PM_SB_PWROK

PM_BATLOW_L

PM_DPRSLPVR

PM_PWRBTN_L

PM_LAN_ENABLE

SV_SET_UP

TP_SB_GPIO25_DO_NOT_USE

SB_CLK100M_SATA_OE_L

SATA_C_PWR_EN_L

SMB_LINK_ALERT_L

SMLINK<1>

SMLINK<0>

PM_RI_L

PM_SYSRST_L

PM_SUS_STAT_L

BIOS_REC

TP_AZ_DOCK_EN_L

VR_PWRGD_CK410

PP3V3_S5

IDE_RESET_L

TP_SB_GPIO6

TP_SB_GPIO38

CRB_SV_DET

PP3V3_S5

FWH_MFG_MODE

BIOS_REC

PP3V3_S0

SMC_SB_NMI

PATA_PWR_EN_L

SMS_INT_L

SMC_WAKE_SCI_L

CRB_SV_DET

PP3V3_S0

SATA_C_PWR_EN_L

PP3V3_S5

PATA_PWR_EN_L

PM_STPPCI_L

TP_AZ_DOCK_RST_L

FWH_MFG_MODE

PM_STPCPU_L

PM_BMBUSY_L

SB_SPKR

SMBUS_SB_SDA

PP3V3_S5

INT_SERIRQ

PCIE_WAKE_L

PM_CLKRUN_L

SMB_ALERT_L

SB_GPIO26

PM_THRM_L

SMC_EXTSMI_L

SMC_RUNTIME_SCI_L

79

78

70

66

65

64

60

59

57

56

53

51

48

43

37

36

34

33

29

28

27

78

26

78

66

25

66

65

24

65

64

23

64

62

22

62

55

21

55

26

20

26

25

19

25

24

17

24

23

14

23

52

22

10

22

23

11

5

11

5

23

5

23

5

23

4

23

4

23

5

23

5

(6 OF 6)

VSS

V5REF_SUS

VCC3_3

VCCDMIPLL

VCCSATAPLL

VCC3_3

VCCRTC

VCCUSBPLL

VCCSAUS1_5

VCC PAUX

USB CORE

VCC1_5_A

ARX

USB

PCI

IDE

VCCA3GP

CORE

ATX

VCC1_5_A

VCC3_3

VCCSUS3_3

VCC1_5_A

VCCSUS3_3

VCC1_5_A

VCCLAN1_5

V_CPU_IO

VCC3_3/VCCHDA

VCCSUS3_3/VCCSUSHDA

VCCLAN_3_3

VCC1_05

V5REF

VCC1_5_B

(5 OF 6)

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

NOTE FOR VCCLAN_3_3: S3 IF INTERNAL LAN IS USED S0 OR S3 IF NOT

CHANGE SYMBOL TO 1.05

SO NO CONNECT HERE

VOLTAGE GENERATED INTERNALLY

SO NO CONNECT HERE

VOLTAGE GENERATED INTERNALLY

NOTE: VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V DEPENDING ON VIO OF AZALIA INTERFACE CODEC IC’S CONSIDERED SO FAR ARE 3.3V

0 0

U2100

A4

A23

B1

B8 B11 B14 B17 B20 B26 B28 C2 C6 C27

D10

D13 D18 D21 D24 E1 E2 E4 E8 E15 F3

F4

F5 F12 F27 F28 G1 G2 G5 G6 G9 G14

G18

G21 G24 G25 G26 H3 H4 H5 H24 H27 H28

J1

J2 J5 J24 J25 J26 K24 K27 K28 L13 L15

L24

L25 L26 M3 M4 M5 M12 M13 M14 M15 M16

M17

M24 M27 M28 N1 N2 N5 N6 N11 N12 N13

N14

N15

N16 AE24 AE25

AF2 AF4

AF8 AF11 AF27 AF28

N17

AG1

AG3

AG7

AG11 AG14 AG17 AG20 AG25 AH1 AH3

N18

AH7 AH12 AH23 AH27

N24

N25

N26

P3

P4 P12 P13 P14 P15 P16 P17

P24

P27 P28

R1 R11 R12 R13 R14 R15 R16 R17

R18

T6 T12 T13 T14 T15 T16 T17

U4 U12 U13

U14

U15 U16 U17 U24 U25 U26

V2 V13 V15 V24

V27

V28

W6 W24 W25 W26

Y3 Y24 Y27 Y28 AA1

AA24

AA25 AA26

AB4 AB6

AB11 AB14 AB16 AB19 AB21 AB24

AB27

AB28

AC2 AC5 AC9

AC11

AD1

AD3 AD4 AD7 AD8

AD11

AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21

OMIT

BGA

ICH7-M

SB

U2100

G10

AD17

F6

AE23 AE26 AH26

L11

P18 T11 T18 U11 U18 V11 V12 V14 V16 V17

L12

V18

L14 L16 L17 L18 M11 M18 P11

AB7 AC6

AB9 AC10 AD10 AE10 AF10

AF9

AG9

AH9

AB17 AC17

AC7

T7 F17 G17

AB8 AC8

A1 H6 H7 J6 J7

AD6

AE6

AF5

AF6

AG5

AH5

AB10

AA22 AA23

AD28

D26

D27

D28

E24

E25

E26

F23

F24

G22

AB22

G23

H22

H23

J22

J23

K22

K23

L22

L23

M22

AB23

M23

N22

N23

P22

P23

R22

R23

R24

R25

R26

AC23

T22

T23

T26

T27

T28

U22

U23

V22

V23

W22

AC24

W23

Y22

Y23

AC25 AC26 AD26 AD27

U6

B27

AH11

AG19

A5 B13 B16 B7 C10 D15 F9 G11 G12

AA7

G16

AB12 AB20 AC16 AD13 AD18 AG12 AG15

AG28

AA2

Y7

V5 V1 W2 W7

W5

AD2

K7 C28

G20

R7

P7 A24

L1 L2 L3 L6 L7 M6 M7 N7

E3

C24 D19 D22 G19

K3 K4 K5 K6

C1

OMIT

BGA

SB

ICH7-M

SB: 4 OF 4

SYNC_DATE=02/10/2006

SYNC_MASTER=M1_MLB

06

24 86

051-7023

PP1V5_S0_SB_VCC1_5_B

PP5V_S0_SB_V5REF

PP5V_S5_SB_V5REF_SUS

PP1V05_S0

PP3V3_S0

PP3V3_S5 PP1V05_S0

PP3V3_S0

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0

PP1V5_S0 PP3V3_S0

PP1V5_S0

PP3V3_S5

PP3V3_S0

PP3V3_G3C_SB_RTC_D

PP3V3_S5

PP1V5_S0

79

78

70

66

65

64

60

59

57

56

53

51

48

43

37

36

34

66

33

66

33

64

29

64

29

54

28

54

28

34

27

34

27

25

26

25

26

78

26

78

24

25

24

25

66

25

66

25

66

21

24

21

24

65

24

65

24

65

19

23

19

23

47

23

47

64

23

64

47

17

22

17

22

25

22

25

62

22

62

25

16

21

16

21

24

21

24

55

21

55

24

13

20

13

20

19

20

19

26

20

26

19

12

19

12

19

17

19

17

25

19

25

17

11

17

11

17

16

17

16

24

17

24

16

9

14

9

14

13

14

13

23

14

23

13

8

10

8

10

9

10

9

22

10

26

22

9

25

7

5

7

5

8

5

8

11

5

25

11

8

22

25

5

4

5

4

25

5

4

5

4

21

5

NC NC

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

(ICH IO,LOGIC 1.5V PWR)

ICH VCCA3GP(VCC1_5_B BYPASS

PLACE < 2.54MM OF SB ON

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE: PLACE CAPS AT EDGE OF SB

ICH VCC3_3/VCCHDA BYPASS (ICH INTEL HDA CORE 3.3V PWR)

PLACE NEAR PINS AE23, AE26 & AH26 OF SB

PLACE C2500 & C2505-07 < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ICH VCCUSBPLL BYPASS (ICH USB PLL 1.5V PWR)

(ICH DMI PLL 1.5V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH IDE I/O 3.3V PWR)

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PIN AH11

PLACEMENT NOTE:

ICH USB CORE/VCC1_5_A BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS A1 ... J7

(ICH USB CORE 1.5V PWR)

(ICH LOGIC&IO 1.5V PWR)

ICH VCC1_5A BYPASS

PLACEMENT NOTE:

ICH VCCSUS3_3 BYPASS (ICH SUSPEND 3.3V PWR)

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN U6

PLACE CAP UNDER SB NEAR PINS V1,

PLACEMENT NOTE:

(ICH CORE 1.05V PWR)

ICH CORE/VCC1_05 BYPASS

PLACEMENT NOTE:

ICH V5REF BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

SB: 4 OF 4

PLACEMENT NOTE:

PLACE CAPS NEAR PIN W5 OF SB

PLACEMENT NOTE: PLACE CAPS NEAR PINS

FOR 270UF

PLACEHOLDER

PLACEMENT NOTE:

3.56MM ON PRIMARY NEAR PIN AG5

3.56MM ON PRIMARY NEAR PIN AG9

(ICH IO BUFFER 3.3V PWR)

NEAR PINS A5 ... G16

DISTRIBUTE IN PCI SECTION OF SB

A24 ... G19 AND P7 OF SB

(ICH PCI I/O 3.3V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH IDE/VCC3_3 BYPASS

(ICH CPU I/O 1.05V PWR)

ICH V_CPU_IO BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

(ICH SATA PLL 1.5V PWR)

ICH VCCSATAPLL BYPASS

(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)

(ICH IO BUFFER 3.3V PWR)

ICH VCC1_5_A/ATX BYPASS

PLACEMENT NOTE:

NEAR PINS D28, T28, AD28

PLACE C2520 NEAR PIN C1 OF SB

K3 ... N7 OF SB

PLACE CAPS NEAR PINS

(ICH SUSPEND USB 3.3V PWR)

ICH USB/VCCSUS3_3 BYPASS

AB8 AND AC8 OF SB

PLACE CAPS NEAR PINS

PLACEMENT NOTE:

(ICH LAN I/F BUFFER 3.3V PWR)

ICH VCC_PAUX/VCCLAN3_3 BYPASS

3.56MM ON PRIMARY NEAR PIN AD2

3.56MM ON PRIMARY NEAR PINS AA7 ... AG19

V5, W2, OR W7

ICH VCCRTC BYPASS (ICH RTC 3.3V PWR)

ICH VCC3_3 BYPASS

PLACEMENT NOTE: PLACE C2509 NEAR PIN B27 OF SB

ICH VCC3_3 BYPASS

ICH VCC1_5_A/ARX BYPASS (ICH LOGIC&IO[ARX] 1.5V PWR)

(ICH LOGIC&IO[ATX] 1.5V PWR)

ICH VCCSUS3_3 BYPASS (ICH SUSPEND 3.3V PWR)

ICH V5REF_SUS BYPASS (ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)

PLACEMENT NOTE: PLACE C2504 < 2.54MM OF PIN F6 OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2503 < 2.54MM OF PIN AD17 OF SB

PLACEMENT NOTE:

PLACE C2520 NEAR PIN E3 OF SB

ICH VCCDMIPLL BYPASS

SECONDARY SIDE OR 3.56MM ON PRIMARY

C2500

1

2

20%

220UF

POLY

2.5V SMB2

C2510

1

2

X5R

16V

10%

0.1UF

402

0

C2512

1

2

402

0.1UF

10% 16V X5R

0

R2500

1 2

1

5%

1/10W MF-LF

603

C2524

1

2

4.7UF

20%

6.3V CERM 603

C2522

1

2

0.1UF

10% 16V X5R 402

D2502

1

6

5

BAT54DW

SOT-363

D2502

4

3

2

BAT54DW

SOT-363

L2507

1 2

1206

0.28-OHM

C2503

1

2

0.1UF

402

10% 16V X5R

0

C2504

1

2

X5R

16V

10%

0.1UF

402

0

R2501

1 2

5%

MF-LF

1/16W

402

10

L2500

1 2

100-OHM-EMI

SM-3

0

C2505

1

2

0.1UF

10% 16V X5R 402

C2506

1

2

X5R

16V

10%

0.1UF

402

C2507

1

2

0.1UF

16V

10% X5R

402

C2501

1

2

0.01UF

10% 16V CERM 402

C2508

1

2

603

10UF

20%

6.3V X5R

0

C2509

1

2

10% 16V X5R 402

0.1UF

0

C2511

1

2

X5R 402

16V

10%

0.1UF

0

C2517

1

2

0.1UF

402

X5R

16V

10%

0

C2513

1

2

0.1UF

10% 16V X5R 402

0

C2514

1

2

402

6.3V CERM

10%

1UF

0

C2520

1

2

0.1UF

10% 16V X5R 402

C2515

1

2

402

X5R

16V

10%

0.1UF

0

C2516

1

2

CASE-C2

POLY

20%

2.5V

330UF

R2502

1

2

5%

1/16W

402

MF-LF

100

C2502

1

2

1UF

10%

6.3V CERM 402

C2518

1

2

402

0.1UF

10% 16V X5R

0

C2519

1

2

X5R

16V

10%

0.1UF

402

0

C2521

1

2

0.1UF

10% 16V

402

X5R

0

C2523

1

2

X5R

16V

10%

0.1UF

402

0

C2525

1

2

0.1UF

X5R

16V

10% 402

0

C2526

1

2

X5R

16V

10%

0.1UF

402

C2527

1

2

X5R

16V

10%

0.1UF

402

C2528

1

2

X5R

16V

10%

0.1UF

402

C2529

1

2

402

0.1UF

10% 16V X5R

0

C2530

1

2

402

0.1UF

10% 16V X5R

C2534

1

2

402

0.1UF

10% 16V X5R

0

C2531

1

2

402

0.1UF

10% 16V X5R

C2532

1

2

402

0.1UF

10% 16V X5R

0

C2533

1

2

402

0.1UF

10% 16V X5R

051-7023

8625

06

PP5V_S0_SB_V5REF

VOLTAGE=5V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

PP5V_S5_SB_V5REF_SUS

MIN_NECK_WIDTH=0.25MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S0

PP3V3_S5

PP3V3_S0

PP5V_S5

PP3V3_G3C_SB_RTC_D

PP3V3_S0

PP1V5_S0

PP3V3_S5

PP1V5_S0

PP3V3_S0

PP1V5_S0

PP3V3_S0

PP3V3_S5

PP1V5_S0

PP3V3_S5

PP1V5_S0

PP3V3_S0

PP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP1V5_S0

VOLTAGE=1.5V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCC1_5_B

79

78

70

66

65

64

60

59

57

56

53

51

48

43

37

80

36

79

34

78

33

66

33

66

70

29

64

29

64

67

28

54

28

54

66

27

34

27

34

65

78

26

78

26

78

26

25

26

25

61

66

25

66

25

66

25

66

25

66

24

25

24

66

60

65

24

65

24

65

24

65

24

65

21

24

21

65

57

64

23

70

23

47

64

47

23

47

23

64

47

64

47

23

47

19

23

19

47

56

62

22

67

22

25

62

25

22

25

22

62

25

62

25

22

25

17

22

17

25

54

55

21

66

21

24

55

24

21

24

21

55

24

55

24

21

24

16

21

16

24

52

26

20

65

20

19

26

19

20

19

20

26

19

26

19

20

19

13

20

13

19

47

25

19

64

19

17

25

17

19

17

19

25

17

25

17

19

17

12

19

12

17

42

24

17

63

17

16

24

16

17

16

17

24

16

24

16

17

16

11

17

11

16

36

23

14

61

14

13

23

13

14

13

14

23

13

23

13

14

13

9

14

9

13

31

22

10

51

26

10

9

22

9

10

9

10

22

9

22

9

10

9

8

10

8

9

5

11

5

46

24

5

8

11

8

5

8

5

11

8

11

8

5

8

7

5

7

8

24

4

5

4

5

21

4

5

4

5

4

5

4

24

5

4

5

22

BI

IN

BI BI

BI

BI BI

OUT

IN

OUT

IN

OUT

IN

SYM_1

NCNC

IN

OUT

BI BI BI BI

BI

D

SIZE

OF

SHT

DRAWING NUMBER

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AGREES TO THE FOLLOWING

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

1

2

3

4

5

67

8

12

3

4

5

6

78

B

C

D

A

B

C

D

A

REV.

APPLE COMPUTER INC.

SCALE

NONE

fault protection for RTC battery.

NOTE: R2607 and D2600 form the double-

NC

Silk: "SYS RST"

Unbuffered

518S0226

NC

RTC Battery Connector

SB RTC Crystal Circuit

it provides a set of pads on the board to short or to solder a reset button.

1G00 used as small & cheap inverter

100-ohm on NB page

Linda Card represents 3 loads

Buffered

LIO represents X loads (2?)

This part is never stuffed,

NCNC

Initial resistor values are based on CRB, but may change after characterization.

Platform Reset Connections

22

22 37

22

4

22 37

22

R2600

1 2

MF-LF

5%

402

1/16W

20K

22

22 37

22

21

C2611

1

2

0.1UF

402

CERM

10V

20%

5

23

C2605

1

2

402

CERM

6.3V

10%

1UF

5

14 60

26 33 60

R2698

1

2

100K

MF-LF

402

5%

1/16W

OMIT

7

11

R2606

1

2

1M

402

MF-LF

1/16W

5%

5

23 50

R2697

1

2

10K

MF-LF

402

5%

1/16W

R2607

2 1

402

5%

MF-LF

1/16W

1K

C2608

1 2

12pF

CERM

402

5%

50V

C2609

1 2

12pF

50V

5%

402

CERM

Y2600

2 4

1 3

SM-2

CRITICAL

32.768K

R2610

1 2

0

402

MF-LF

1/16W

5%

R2609

1

2

10M

402

MF-LF

1/16W

5%

C2680

1

2

CERM

0.1UF

20% 10V

402

R2680

1

2

100K

5% 1/16W MF-LF 402

R2681

1 2

402

0

MF-LF

1/16W

5%

R2683

1 2

100

402

MF-LF

1/16W

5%

R2684

1 2

0

1/16W

5%

MF-LF

402

R2685

1 2

0

402

MF-LF

1/16W

5%

R2687

1 2

0

5% 1/16W MF-LF

402

R2682

1 2

0

402

MF-LF

1/16W

5%

5

14 22 26

J2600

3

4

1 2

CRITICAL

F-RT-SM

88460-0201

R2696

1 2

402

ITP

5% 1/16W MF-LF

1K

U2603

3

2

1

4

5

MC74VHC1G00

SC70-5

U2680

3

2

1

4

5

MC74VHC1G08

SC70

U2601

3

2

1

4

5

SC70

MC74VHC1G08

D2600

1

4

6

3

5

2

BAT54DW

SOT-363

50 65

R2611

1

2

402

MF-LF

1/16W

5%

1.8K

C2607

1

2

0.1UF

402

CERM

10V

20%

5

23

R2612

1

2

402

MF-LF

1/16W

5%

10K

R2622

1

2

10K

5% 1/16W MF-LF 402

R2623

1 2

8.2K

R2624

1 2

8.2K

R2625

1 2

8.2K

R2626

1 2

8.2K

R2627

1 2

8.2K

R2628

1 2

8.2K

R2629

1 2

8.2K

R2630

1 2

8.2K

R2631

1 2

8.2K

R2632

1 2

8.2K

R2633

1 2

8.2K

R2634

1 2

8.2K

R2636

1 2

8.2K

5

21

R2637

1 2

8.2K

R2638

1 2

8.2K

R2639

1 2

8.2K

R2640

1 2

8.2K

R2641

1 2

8.2K

R2642

1 2

8.2K

C2610

1

2

402

6.3V

10% CERM

1UF

22 37

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

26

051-7023

06

86

SB Misc

PLT_RST_BUF_L

TPM_LRESET_L

ENET_RST_L

MAKE_BASE=TRUE

PLT_RST_L

MAKE_BASE=TRUE VOLTAGE=3.3V

PP3V3_G3C_SB_RTC_D

SB_GPIO4

SB_GPIO2 SB_GPIO3

INT_PIRQD_L

INT_PIRQB_L INT_PIRQC_L

PCI_REQ3_L INT_PIRQA_L

PCI_REQ2_L

PCI_REQ1_L

PCI_REQ0_L

PCI_LOCK_L

PCI_PERR_L

PCI_DEVSEL_L

PCI_SERR_L

PCI_STOP_L

PCI_TRDY_L

PCI_IRDY_L

PCI_FRAME_L

PP3V3_S0

PP3V3_G3C_SB_RTC_D

PP3V42_G3H

PPVBATT_G3C_RTC_R

VOLTAGE=3.3V

PP3V3_S0

VR_PWRGOOD_DELAY

ALL_SYS_PWRGD

PM_SB_PWROK

PP3V3_S0

VR_PWRGD_CK410_L

MAKE_BASE=TRUE

PP3V3_S0

MAKE_BASE=TRUE

PM_SYSRST_L

XDP_DBRESET_L

SB_SM_INTRUDER_L

LIO_PLT_RESET_L

SB_RTC_X1

DEBUG_RST_L

SMC_LRESET_L

PEG_RESET_L

PLT_RST_L

PP3V3_S5

VR_PWRGD_CK410

VR_PWRGD_CK410_L

SB_RTC_RST_L

PPVBATT_G3C_RTC

VOLTAGE=3.3V

SB_RTC_X1_R

SB_RTC_X2

79

78

70

66

65

64

60

59

57

56

53

51

48

43

37

36

34

33

29

28

27

26

25

68

25

78

24

67

24

66

23

66

23

65

22

65

22

64

21

54

21

62

20

52

20

55

19

51

19

25

17

50

17

24

26

14

26

45

14

26

23

25

10

25

35

10

22

59

24

5

24

27

5

47

52

50

69

14

11

37

5

39

21

4

21

5

4

5

21

5

21