Apple 15MLB User Manual

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

Schematic / PCB #’s

08/18/2008

SCHEM,MBP 15"MLB

M98 SMBus Connections

45

DDR

07/22/2008

52

LPC+SPI Debug Connector

44

CHANG_M98_MLB

07/01/2008

51

SMC Support

43

AMASON_M98_MLB

06/18/2008

50

SMC

42

T18_MLB

06/18/2008

49

Front Flex Support

41

CHANG_M98_MLB

07/01/2008

48

External USB Connectors

40

AMASON_M98_MLB

07/02/2008

46

SATA Connectors

39

CHANG_M98_MLB

07/01/2008

45

FireWire Ports

38

SENSOR

08/14/2008

43

FireWire Port Power

37

SENSOR

08/14/2008

42

FireWire LLC/PHY (FW643)

36

SENSOR

08/14/2008

41

Ethernet Connector

35

SUMA_M98_MLB

07/01/2008

39

Ethernet & AirPort Support

34

SUMA_M98_MLB

07/01/2008

38

Ethernet PHY (RTL8211CL)

33

SUMA_M98_MLB

07/01/2008

37

ExpressCard Connector

32

YITE_M98_MLB

07/02/2008

35

Right Clutch Connector

31

YITE_M98_MLB

07/02/2008

34

DDR3 Support

30

T18_MLB

06/18/2008

33

DDR3 SO-DIMM Connector B

29

DDR

07/22/2008

32

DDR3 SO-DIMM Connector A

28

DDR

07/22/2008

31

FSB/DDR3/FRAMEBUF Vref Margining

27

DDR

07/22/2008

29

SB Misc

26

T18_MLB

12/17/2007

28

MCP Graphics Support

25

AMASON_M98_MLB

06/18/2008

26

MCP Standard Decoupling

24

T18_MLB

06/18/2008

25

MCP79 A01 Silicon Support

23

T18_MLB

03/31/2008

24

MCP Power & Ground

22

T18_MLB

06/18/2008

22

MCP HDA & MISC

21

T18_MLB

06/18/2008

21

MCP SATA & USB

20

T18_MLB

06/18/2008

20

MCP PCI & LPC

19

T18_MLB

06/18/2008

19

MCP Ethernet & Graphics

18

T18_MLB

06/18/2008

18

MCP PCIe Interfaces

17

T18_MLB

06/18/2008

17

MCP Memory Misc

16

T18_MLB

06/18/2008

16

MCP Memory Interface

15

T18_MLB

06/18/2008

15

MCP CPU Interface

14

T18_MLB

06/18/2008

14

eXtended Debug Port(MiniXDP)

13

M99_MLB

01/08/2008

13

CPU Decoupling & VID

12

M87_MLB

10/17/2007

12

CPU Power & Ground

11

M87_MLB

10/17/2007

11

CPU FSB

10

M87_MLB

10/17/2007

10

Signal Aliases

9

(MASTER)

9

Power Aliases

8

(MASTER)

8

Functional / ICT Test

7

N/A

7

JTAG Scan Chain

6

DDR

07/22/2008

6

BOM Configuration

5

N/A

5

Power Block Diagram

4

N/A

4

Power Block Diagram

3

T18_MLB

12/12/2007

3

System Block Diagram

2

T18_MLB

12/12/2007

2

MUXGFX

02/18/2008

90

103

MCP Constraints 2

MUXGFX

02/18/2008

89

102

MCP Constraints 1

MUXGFX

02/18/2008

88

101

Memory Constraints

MUXGFX

02/18/2008

87

100

CPU/FSB Constraints

MUXGFX

02/01/2008

86

99

Misc Power Supplies

YITE_M98_MLB

07/02/2008

85

98

LCD Backlight Support

YITE_M98_MLB

07/02/2008

84

97

LCD BACKLIGHT DRIVER

MUXGFX

07/10/2008

83

96

Graphics MUX (GMUX)

MUXGFX

07/10/2008

82

95

1.1V / 1V8 FB Power Supply

MUXGFX

07/10/2008

81

94

DisplayPort Connector

MUXGFX

07/10/2008

80

93

Muxed Graphics Support

MUXGFX

02/25/2008

79

90

LVDS Display Connector

M87_MLB

10/17/2007

78

89

GPU (G84M) Core Supply

MUXGFX

07/10/2008

77

88

NV G96 Video Interfaces

MUXGFX

07/09/2008

76

87

G96 GPIOs & Straps

MUXGFX

07/10/2008

75

86

NV G96 GPIO/MIO/Misc

MUXGFX

07/10/2008

74

85

GDDR3 Frame Buffer B (Top)

MUXGFX

07/10/2008

73

84

GDDR3 Frame Buffer A (Top)

MUXGFX

07/10/2008

72

82

NV G96 Frame Buffer I/F

MUXGFX

07/10/2008

71

81

NV G96 Core/FB Power

MUXGFX

07/10/2008

70

80

NV G96 PCI-E

PWRSQNC

05/12/2008

69

79

Power FETs

PWRSQNC

05/12/2008

68

78

Power Control

M99_MLB

12/14/2007

67

77

Misc Power Supplies

M99_MLB

12/14/2007

66

76

CPU VTT Power Supply

M99_MLB

01/08/2008

65

75

1.05V / MCP Core Regulator

M99_MLB

12/13/2007

64

73

1.5V DDR3 Supply

M99_MLB

01/09/2008

63

72

5V / 3.3V Power Supply

M87_MLB

10/17/2007

62

71

IMVP6 CPU VCore Regulator

M99_MLB

12/10/2007

61

70

PBus Supply & Battery Charger

T18_MLB

12/06/2007

60

69

DC-In & Battery Connectors

AUDIO

07/09/2008

59

68

AUDIO: JACK TRANSLATORS

AUDIO

07/09/2008

58

67

AUDIO: JACKS

AUDIO

07/09/2008

57

66

AUDIO:SPEAKER AMP

AUDIO

07/09/2008

56

65

AUDIO: HEADPHONE AMP

AUDIO

07/09/2008

55

63

AUDIO: LINE IN

AUDIO

07/09/2008

54

62

AUDIO:CODEC

CHANG_M98_MLB

07/01/2008

53

61

SPI ROM

SENSOR

08/14/2008

52

59

Sudden Motion Sensor (SMS)

PWRSQNC

05/12/2008

51

58

WELLSPRING 2

AMASON_M98_MLB

06/18/2008

50

57

WELLSPRING 1

M87_MLB

10/17/2007

49

56

Fan Connectors

SENSOR

08/14/2008

48

55

Thermal Sensors

SENSOR

08/14/2008

47

54

Current Sensing

96

109

PCB Rule Definitions

M99_MLB

01/22/2008

95

108

Project Specific Constraints

MUXGFX

02/21/2008

94

107

GPU (G96) Constraints

MUXGFX

02/18/2008

93

106

SMC Constraints

MUXGFX

02/18/2008

92

105

FireWire Constraints

MUXGFX

02/18/2008

SENSOR

08/14/2008

46

53

Current & Voltage Sensing

CRITICAL051-7546

1

SCH

SCHEM,FIBBO,M98

Contents Sync

Date

(.csa)

Page

Table of Contents

1

N/A

1

TITLE=MLB

ABBREV=DRAWING

91

104

Ethernet Constraints

MUXGFX

02/18/2008

Contents Sync

(.csa)

Date

Page

CRITICAL820-2330

1

PCBF,FIBBO,M98

PCB

Contents

(.csa)

Sync

Date

Page

A.0.0

SCHEM,MBP 15MLB

?

1

? ?

96

051-7546

LAST_MODIFIED=Mon Aug 18 01:48:34 2008

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

J9400

DISPLAY PORT

J9000

CONN

LVDS

PG 71

CONN

PG 71

Conn

J4520

PG 17

(UP TO 12 DEVICES)

4

TMDS OUT

Line Out

2

CTRL

IR

J4710

CLK

SATA

(UP TO FOUR PORTS)

Conns

J6800,6801,6802,6803

PG 41

MCP79

PG 19

PCI

PG 19

LPC

3 8 9

PG 40

SATA

U6301 U6500U6400

PG 59

PG 56PG 55

HEADPHONE

Audio

Codec

FSB

64-Bit

2 UDIMMs

XDP CONN

POWER SUPPLY

PG 28

J3400 U3900

PG 33

Conn

88E1116

PG 31

GB

E-NET

Amp

Speaker

Amps

PG 54

PG 53

U6200

J4720

PG 57

J4710

U4900

J6950

PG 12

U1000

U1300

J4510

U6600,6605,6610,6620

PG 40

J4700

PG 40

HD

E-NET

ODD

Conn

SYNTH

PG 39

U6100

J3900,4635,4655

EXTERNAL

USB

PG 40

KEYBOARD

TRACKPAD/

USB

PG 45

POWER SENSE

J5650,5600,5610,5611,5660,5720,5730,5750

PG 48,49

J4900

DC/BATT

PENRYN

2.X OR 3.X GHZ

INTEL CPU

SPI

PG 20

PG 18

MEMORY

MAIN

800/1067/1333 MHz

DDR2-800MHZ

DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

SPI

TEMP SENSOR

FAN CONN AND CONTROL

J5100

PG 43

Ser

FanADC

SMC

B,0

Prt

BSB

PWR

Misc

PG 14

Port80,serial

LPC Conn

GPIOs

SATA

1.05V/3GHZ.

RGB OUT

PG 38

PG 13

FSB INTERFACE

PG 24

SMB

PG 20

HDA

NVIDIA

PG 41

CAMERA

Connectors

PG 44

CONN

SMB

DIMM’s

10 5 6 7

Bluetooth

PG 52

Boot ROM

U1400

DVI OUT

PCI-E

PG 16

UP TO 20 LANES3

PG 17

LVDS OUT

DP OUT

HDMI OUT

RGMII

PG 18

AirPort

Mini PCI-E

U3700

Line In

Amp Amp

PG 60

PG 9

System Block Diagram

SYNC_DATE=12/12/2007

A.0.0

2 96

051-7546

SYNC_MASTER=T18_MLB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PP3V3_S0GPU_FET

P3V3S0_SS

(PAGE 42)

S0PGOOD_PWROK

P1V5S0_PGOOD

P3V3S3_SS

(18A MAX CURRENT)

GPUVCORE_IOUT

RSMRST_IN(P13)

IMVP_VR_ON

PLT_RST*

PWR_BUTTON(P90)

PM_PWRBTN_L

SMC_ONOFF_L

RSMRST_PWRGD

MCP_PS_PWRGD

PWROK

CPUPWRGD(GPIO49)

PLT_RST_L

CK_PWRGD

VR_PWRGD_CLKEN

VRMPWRGD

PP5V_S0_FET

(25A MAX CURRENT)

(5A MAX CURRENT)

PM_SLP_S3_DELAY_L

SMC_ADAPTER_EN

PPVBAT_G3H_CHGR_R

CHGR_BGATE

J6950

BATT_POS_F

6A FUSE

DCIN(16.5V)

U7000

ISL6258A

BATTERY CHARGER

PBUS SUPPLY/

(PAGE 60)

PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L

U4900

SLP_S3_L(P93)

SLP_S4_L(P94)

SLP_S5_L(P95)

SMC_RESET_L

PM_RSMRST_L

99ms DLY

RSMRST_OUT(P15)

PWRGD(P12)

IMVP_VR_ON(P16)

PP1V05_S5_MCP

(PAGE 68)

LTC2900

P1V8S0_PGOOD

CPUVTTS0_PGOOD

MCPCORES0_PGOOD

P5VRIGHT_PGOOD

P1V05S0_PGOOD

P5VS0_SS

Q7900

PP5V_S3_FET

P5VS3_SS

Q7910

PP3V3_S3_FET

PP3V3_S0_FET

P3V3GPU_SS

P3V3_ENET_FET

P3V3ENET_EN_L

(12A MAX CURRENT)

PPDDR_S3_REG

PPVTT_S0_DDR_LDO

PP5V_RT_REG

MCPCPCORE_S0_REG

(PAGE 65)

ISL6236

U7500

1.1V

MCP_CORE

P1V05S0_EN

MCPCORES0_EN

CPUVTTS0_EN

MCPDDR_EN

P1V8S0_EN

P5VRIGHT_EN

P5VS0_EN

PM_SLP_S3_L

Q3800

WOL_EN

PM_ENET_EN_L

DDRVTT_EN

DDRREG_EN

U7300

(PAGE 63)

TPS51116

0.9V

1.8V

PPVIN_S0_DDRREG_LDO

P1V2ENET_EN

ENETAVDD_EN

PP1V2_ENET_REG

PP1V9_ENET_REG

(PAGE 33)

U3850

LTC3407

GOSHAWK6P

PPVOUT_S0_LCDBKLT

Q7930

Q7970

P5V3V3_S5_PGOOD

P5V_RT_PGOOD

PP5V_RT_REG

PP3V3_S5_REG (5.5A MAX CURRENT)

PP5V_S5_REG (8A MAX CURRENT)

(PAGE 66)

U7750

ISL8009

CPUVTTS0_PGOOD

PPCPUVTT_S0_REG

CPUVTTS0_EN

PGOOD

(PAG 66)

U7600

TPS51117

VOUT

PP3V42_G3H_REG

(PAGE 59)

U6990

LT3470

3.425V G3HOT

GPU VCORE

U8900

ISL6263B

ISL9504B

CPU VCORE

(PAGE 62)

U7201

TPS51125

3.3V

5V

(PAGE 82)

U9500

TPS51124

1.8V(R/H)

1.103V(L/H)

VIN

U7400 SC417

(PAGE 64)

(PAGE 84)

U9701

V4

PP1V8_GPU_REG

VOUT1

RST*

U7870

V1 V2 V3 V4

PP1V5_S0_REG

PP3V3_S0

PP5V_S0

VIN

VOUT2

CPUVCORE_IOUT

PPVCORE_CPU_S0

VOUT2

VLDOIN

P3V3S5_EN

(R/H)

VOUT1

EN1

P1V1GPU_EN

PPBUS_G3H

U5400

PP1V1_S0GPU_REG

(PAGE 61)

Q7920

PM_ENET_EN_L

(S0)

P3V3S0_EN

DELAY

Q3805

SMC

LIO_DCIN_ISENSE

Q7055

VOUT1

VIN

EN0

VREG3

ENL

VIN

EN2

VIN

IN

SMC_RESET_L

ENABLE

U5000

RN5VD30A-F

VIN

(L/H)

ADAPTER

VOUT

P1V8FB_EN

VIN

VR_ON

VOUT

A

VIN

U2830

VOUT2

PGOOD1,2

VOUT2

U2850

CPU

U1000

SMC

PWRBTN#

PLTRST*

PWRGOOD

(PAGE 10,11)

RESET*

EN/PSV

S3

RUN1

ENA

EN2

VOUT1

RUN2

S5

VR_PWRGOOD_DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

RC

MCP79

RSMRST*

U1400

(PAGE 14~22)

U1400

3S2P

A

P60

P5V_RT_EN

PBUSB_VSENSE

Q5315

ENABLES

A

AC

PM_GPUVCORE_EN

SMC PWRGD

IMVP_VR_ON_R

(PAGE 78)

PGOOD

U5498

SMC_GPU_VSENSE

VOUT

D6905

VOUT

U4900

VIN

BKLT_EN

(PAGE 14~22)

SLP_S3#(G17)

SLP_S5#(H17)

Q3810

VOUT

VIN

(S0)

MCP79

(S0)

PBUSVSENS_EN

U7859

SMC_PM_G2_EN

(S5)

PGOOD

Q3801

WOW_EN

PM_ENET_EN

PM_WLAN_EN_L

P17(BTN_OUT)

(PAGE 42)

U5705

PPVCORE_GPU_REG

V

A

LIO_S3_EN

P5VS3_EN

P3V3S3_EN

(9 TO 12.6V)

U5715

8A FUSE

D6905

PPVBAT_G3H_CHGR_REG

SMC_BATT_ISENSE

EN_PSV

GPUVCORE_PGOOD

SMC_CPU_VSENSE

V

VR_PWRGD_CLKEN_L

VIN

U7100

PGOOD

RST*

ALL_SYS_PWRGD

VOUT2

EN1

DELAY

PPBUS_G3H

V

PPVIN_G3H_P3V42G3H

PP3V3_S5

PP5V_S3

(S5)

CHGR_EN

1.05V

EN_PSV

(PAGE 43)

CPU_PWRGD

(6A MAX CURRENT)

M98 POWER SYSTEM ARCHITECTURE

SYNC_MASTER=T18_MLB

051-7546

96

A.0.0

SYNC_DATE=12/12/2007

3

Power Block Diagram

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SYNC_MASTER=N/A

SYNC_DATE=N/A

4 96

A.0.0

051-7546

Power Block Diagram

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM Variants

Bar Code Labels / EEE #’s

Module Parts

M98 BOM Groups

M98_COMMON

ALTERNATE,COMMON,M98_COMMON1,M98_COMMON2,M98_COMMON3,M98_DEBUG,M98_PROGPARTS

M98_DEBUG

M98_PROGPARTS

M98_COMMON3

630-9586

M98_COMMON,EEE_2NJ,CPU_2_8GHZ,FB_512_QIMONDA

PCBA,2.8GHZ,512QIM_VRAM,M98

630-9335

M98_COMMON,EEE_0ZB,CPU_2_4GHZ,FB_256_HYNIX

PCBA,2.4GHZ,256HYN_VRAM,M98

630-9334

M98_COMMON,EEE_0ZA,CPU_2_4GHZ,FB_256_SAMSUNG

PCBA,2.4GHZ,256SAM_VRAM,M98

CRITICAL826-4393

1

EEE_2NH

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:2NH]

BOM Configuration

5 96

051-7546

SYNC_MASTER=N/A

SYNC_DATE=N/A

A.0.0

U4900

SMC_PROG

341S2289

1

CRITICAL

IC,SMC,DEVELOPMENT,M98

CRITICAL

MCP_B01

U1400

338S0600

1

IC,GMCP,MCP79-B01,35x35MM,BGA1437

CRITICAL

1

CPU_2_5GHZ

337S3640

IC,PDC,SL3BX,PRQ,2.53G,35W,1066,C0,6M,BGA

U1000

[EEE:0ZD]

1

EEE_0ZD

CRITICAL826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL826-4393

EEE_0ZB

[EEE:0ZB]

LBL,P/N LABEL,PCB,28MM X 6 MM

U4800

1

341S2384

IR,ENCORE II, CY7C63803-LQXC

CRITICAL

1

338S0554

IC,GPU,55nm,NV G96-GS,BGA969,LF

U8000

M98_COMMON,EEE_0ZD,CPU_2_5GHZ,FB_512_QIMONDA

630-9337

PCBA,2.5GHZ,512QIM_VRAM,M98

VRAM4,VRAM_256_HYNIX

FB_256_HYNIX

CRITICAL

1

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

EEE_2NJ

[EEE:2NJ]

CRITICAL

[EEE:0ZC]

826-4393

EEE_0ZC

1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

338S0563

U4900

SMC_BLANK

IC,SMC,HS8/2117,9MMX9MM,TLP

U8770

HDCP_YES

341S2272

1

IC,HDCP ROM,NVG96, 8 PIN SOIC,LF,HF

CRITICAL

1

CPU_2_4GHZ

337S3639

IC,PDC,SLB4N,PRQ,2.4G,25W,1066,M0,3M,BGA

U1000

630-9336

M98_COMMON,EEE_0ZC,CPU_2_5GHZ,FB_512_SAMSUNG

PCBA,2.5GHZ,512SAM_VRAM,M98

FB_512_QIMONDA

VRAM4,VRAM_512_QIMONDA

CRITICAL

1

U3700

338S0570

IC,RTL8211CL,GIGE TRANSCEIVER,48P TQFP

CRITICAL

1

U4100

338S0523

IC,FW643-06,1394B PHY/OHCI LINK/PCI-E,12

338S0635

IC,GMCP,MCP79-B02,35x35MM,BGA1437

CRITICAL

1

U1400

MCP_B02

BOOTROM_PROG

U6100

1

IC,EFI ROM,DEVELOPMENT,M98

341S2366 CRITICAL

CRITICAL

1

U6100

BOOTROM_BLANK

335S0384

IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8

IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA

U8400,U8450,U8500,U8550

VRAM_256_SAMSUNG

333S0482 CRITICAL

4

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

VRAM_512_QIMONDA

CRITICAL

4

333S0472

U8400,U8450,U8500,U8550

341S2383

IC,PSOC +W/USB,56PIN,MLF,M98

CRITICAL

1

U5701

TPAD_PROG

138S0603

ALL

138S0602

Murata alt to Samsung

U8400,U8450,U8500,U8550

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

VRAM_512_SAMSUNG

CRITICAL333S0481

4

U8400,U8450,U8500,U8550

333S0483

IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA

4

CRITICAL

VRAM_256_HYNIX

337S3641

CPU_2_8GHZU1000

CRITICAL

1

IC,PDC,SLB43,PRQ,2.8G,35W,1066,C0,6M,BGA

ALL

353S1294

LMV2011,OPAMP. GBW

353S1681

ALL

514-0608

FOXLINK RCVR ALT TO FOXCONN

514-0613

ALL

157S0055

Delta alt to TDK Magnetics

157S0058

ALL

514-0607514-0612

FOXLINK XCVR ALT TO FOXCONN

152S0796

ALL

152S0915

Maglayers alt to Cyntec IND

ALL

341S2366341S2367

Macronix alt to SST

353S1466

ALL INTERSIL ALT TO INTERSIL

353S2312

ALL

152S0876 152S0867

Maglayer alt to Delta

ALL

152S0276 152S0683

Maglayers alt to Dale/Vishay

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

EEE_0ZA

[EEE:0ZA]

VRAM4,VRAM_512_SAMSUNG

FB_512_SAMSUNG

630-9585

M98_COMMON,EEE_2NH,CPU_2_8GHZ,FB_512_SAMSUNG

PCBA,2.8GHZ,512SAM_VRAM,M98

M98_COMMON1

ONEWIRE_PU,ISL6258A,MEMRESET_HW,MEMRESET_MCP,MCP_B02,MCP_PROD,MCPSEQ_SMC

M98_COMMON2

BKLT_PLL_NOT,BMON_ENG,MIKEY,BOOT_MODE_USER,GPUVID_1P00V,MUXGFX

VRAM4,VRAM_256_SAMSUNG

FB_256_SAMSUNG

DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_HW,DP_CA_DET_EG_PLD,MCP_CS1_NO

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

SMC_DEBUG_YES,XDP,LPCPLUS,VREFMRGN

IN

B1

OE*

VCCB

B2 B3 B4

GND

A4

A3

A2

A1

VCCA

OUT

GND

VCC

NCNC

YA

NC NC

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TDO

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

From XDP connector

or via level translator

GPU

U9200

GMUX

U8000

MCP

U1400

From XDP connector

U1000

CPU

To XDP connector and/or level translator

XDP connector

TMS

TCK

TDI

GMUX CPLD Programming Port

6

10 13 87

NLSV4T244

UQFN

JTAG_ALLDEV

CERM

10V 402

20%

0.1UF

JTAG_ALLDEV

20% 10V CERM 402

JTAG_ALLDEV

0.1UF

JTAG_ALLDEV

5%

10K

1/16W MF-LF

402

0

1/16W

5%

MF-LF

402

NOSTUFF

13

CRITICAL

1909782

M-RT-SM

402

MF-LF

1/16W

5%

0

XDP

PLACEMENT_NOTE=Place near pin U1000.AB3

0

1/16W MF-LF

5%

402

XDP

PLACEMENT_NOTE=Place near pin U1400.F19

74LVC1G07

SOT886

PLACEMENT_NOTE=Place close to U0600

5%

MF-LF

1/16W

10K

NOSTUFF

402

PLACEMENT_NOTE=Place close to U8000

10K

5% 1/16W MF-LF 402

6

10 13 87

6

10 13 87

13

051-7546

A.0.0

966

SYNC_MASTER=DDR

SYNC_DATE=07/22/2008

JTAG Scan Chain

=PP1V05_S0_CPU

MAKE_BASE=TRUE

JTAG_MCP_TRST_L

XDP_TCK

XDP_TDO

JTAG_GMUX_TCK

GPU_JTAG_TRST_L

GPU_JTAG_TMS

=PP3V3_S0_XDP

JTAG_MCP_TDI

JTAG_GMUX_TMS

GPU_JTAG_TCK

GPU_JTAG_TDO

MAKE_BASE=TRUE

TP_GPU_JTAG_TDO

JTAG_MCP_TDO_CONN

GPU_JTAG_TMS

=PP3V3_GPU_VDD33

XDP_TRST_L

XDP_TMS

XDP_TCK XDP_TDI

XDP_TDO_CONN

MAKE_BASE=TRUE

JTAG_MCP_TDO

GPU_JTAG_TDI

XDP_TMS XDP_TRST_L

=PP3V3_S0_XDP

JTAG_LVL_TRANS_EN_L

JTAG_GMUX_TDO

JTAG_MCP_TMS

MAKE_BASE=TRUE

JTAG_MCP_TCK

JTAG_GMUX_TDI

U0600

2 3 4 5

10 9 8 7

6

12

1

11

C0601

1

2

C0602

1

2

R0601

1

2

R0602

1

2

J0600

7

8

1 2 3 4 5 6

R0603

1 2

R0604

1 2

U0601

2

3

1

5

6

4

R0605

1 2

R0606

1

2

62 13 12

87

11

13

23

76

13

23

10

21

10

87

75

8

21

83

75 75

10

8

83

21

83

8

13

6

10

83

75

6

13

9

75

6 8

21

75

6

9

13

9

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FUNC_TEST

5 TPs

SATA ODD Connectors

KEYBOARD CONN

Speaker Connectors

FUNC_TEST

Fan Connectors

IPD_FLEX_CONN

LVDS Connectors

POWER RAILS

6 TPs

5 TPs

FUNC_TEST

CPU FSB NO_TESTs

NO_TEST

ICT Test Points

FUNC_TEST

3 TPs

per Fan

4 TPs

Functional Test Points

per Fan

FUNC_TEST

EXCARD Connector

I557

I558 I559

I560

I561 I562

I563

I564 I565

I566

I567

I568

I569

I570 I571

I572

I573

I574

I575 I576

I577

I578 I579

I580

I581

I582

I583

I584

I585 I586

I587

I588

I589

I590

I591

I592

I593

I594

I595

I596

I597

I598

I600

I602 I603

I604

I605

I606

I607

I608

I609

I610

I611

I612

I613

I614

I615 I616

I617

I618 I619

I620 I621

I622

I623

I624

I625

I626

I627

I636

I637

I638

I639

I640

I641

I642

I643 I644

I645

I646

I647

I648

I649

I650

I651

I652

I653

I654 I655

I656

I657

I709

I710

I711

I712

I713

I714

I715 I716

I717

I718

I719

I720

I721

I722

I723

I724

I725

I726 I727

I728 I729

I730

I731 I732

I733

I734

I735

I736

I737

I739

I740

I741

I742

I743

I744

I745

I746

I747

I748

I749

I750

I751

I752

I753

I754

I755

I756

I757

I758

I759

I760

I761 I762

I763

I764

I765

7 96

A.0.0

051-7546

Functional / ICT Test

SYNC_MASTER=N/A

SYNC_DATE=N/A

PP3V3_S5_AVREF_SMC

TRUE

PP3V3_S3_LDO

TRUE

PP1V8_S0GPU_ISNS_R

TRUE

PP0V9R0V75_S0_DDRVTT

TRUE

PPCPUFSB_ISNS_R

PPCPUVTT_S0

TRUE

PP1V2R1V05_S5

TRUE

PP1V05_S0_REG

TRUE

PP1V8_S0

PP1V2_S0

TRUE

PP2V5_S0

TRUE

PP3V3_S0

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP5V_S0

TRUE

PP5V_S3

TRUE

PP3V42_G3H

TRUE

PPBUS_CPU_IMVP_ISNS

PPBUS_G3H

TRUE

PM_SLP_S3_L

TRUE

SATA_ODD_D2R_C_P

TRUE

SATA_ODD_D2R_C_N

TRUE

SATA_ODD_R2D_N

TRUE

SATA_ODD_R2D_P

PCIE_CLK100M_EXCARD_CONN_N

TRUE

FSB_DINV_L<3..0>

TRUE

FSB_DSTB_L_N<3..0>

TRUE

FSB_HIT_L

TRUE

FSB_DSTB_L_P<3..0>

TRUE

FSB_HITM_L

TRUE TRUE

FSB_LOCK_L

FSB_D_L<63..0>

TRUE

LED_RETURN_5

PCIE_EXCARD_D2R_P

TRUE

PP1V8_S0GPU_ISNS

TRUE

LED_RETURN_4

LED_RETURN_3

TRUE

=PP5V_S0_FAN_LT

EXCARD_CLKREQ_CONN_L

TRUE

SPKRCONN_S_N_OUT

SPKRCONN_R_P_OUT

TRUE

EXCARD_CPUSB_L

TRUE

EXCARD_CPPE_L

PLT_RESET_SWITCH_L

TRUE

PP1V5_S0_EXCARD_SWITCH

TRUE

PCIE_EXCARD_R2D_N

TRUE

BI_MIC_LO

FAN_LT_TACH

TRUE

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_CONN_B_DATA_P<0>

TRUE

LVDS_CONN_A_CLK_F_P

LVDS_CONN_A_DATA_N<2>

TRUE

LVDS_CONN_A_DATA_P<1>

TRUE

LVDS_CONN_A_DATA_N<1>

TRUE

LVDS_CONN_B_CLK_F_N

LVDS_CONN_B_DATA_N<1>

TRUE

FAN_RT_TACH

FSB_ADS_L

TRUE

FSB_ADSTB_L<1..0>

TRUE

FSB_A_L<31..3>

TRUE

LED_RETURN_2

TRUE

LED_RETURN_1

TRUE

LVDS_CONN_A_DATA_P<0>

LVDS_DDC_DATA

TRUE

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_A_DATA_P<2>

TRUE

FAN_LT_PWM

TRUE

LVDS_CONN_B_DATA_N<0>

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_DATA_N<2> LVDS_CONN_B_DATA_P<2>

TRUE

PCIE_CLK100M_EXCARD_CONN_P

TRUE

LED_RETURN_6

FAN_RT_PWM

TRUE

SMC_ODD_DETECT

TRUE

SPKRCONN_R_N_OUT

TRUE

BI_MIC_HI

SPKRCONN_L_P_OUT

TRUE

WS_KBD6

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

WS_KBD13

TRUE

WS_KBD14 WS_KBD15_CAP

TRUE TRUE

WS_KBD16_NUM

TRUE

WS_KBD20 WS_KBD21

TRUE TRUE

WS_KBD22

TRUE

WS_KBD23 WS_KBD_ONOFF_L

TRUE

PSOC_SCLK

TRUE

Z2_RESET

TRUE

Z2_KEY_ACT_L

Z2_HOST_INTN

TRUE

Z2_BOOST_EN

TRUE

WS_KBD2

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

SPKRCONN_L_N_OUT

TRUE

WS_KBD17

PP1V8R1V5_S0_FET

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_CONTROL_KBD

TRUE

TPAD_GND_F

KBDLED_ANODE

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD19

TRUE

WS_KBD5

TRUE

WS_KBD7

WS_KBD10

TRUE

WS_KBD18

TRUE

PPVCORE_S0_CPU

TRUE

PPMCPDDR_ISNS

PP3V3_S0GPU

TRUE

PPDCIN_G3H

TRUE

PPVOUT_S0_LCDBKLT

TRUE

PPVCORE_GPU

TRUE

PPVTTDDR_S3

TRUE

PP1V8_GPUIFPX

TRUE

PCIE_EXCARD_D2R_N

TRUE

USB2_EXCARD_CONN_P

TRUE

USB2_EXCARD_CONN_N

TRUE

PCIE_EXCARD_R2D_P

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

BI_MIC_SHIELD

TRUE

PSOC_MOSI

TRUE

PSOC_F_CS_L

TRUE

Z2_BOOT_CFG1

TRUE

PP3V42_G3H

TRUE

SPKRCONN_S_P_OUT

TRUE

LVDS_DDC_CLK

TRUE

BKL_SYNC

TRUE

PP3V3_SW_LCD

TRUE

=PP3V3_S0_DDC_LCD

TRUE

FSB_REQ_L<4..0>

TRUE

WS_KBD1

TRUE

WS_KBD4

WS_KBD3

TRUE

PP1V0_FW

PP1V1_S0GPU_REG

TRUE

PP1V8R1V5_S3

TRUE

PP1V2R1V05_ENET

PPVP_FW

TRUE

PP3V3_ENET_PHY

PSOC_MISO

TRUE

Z2_CLKIN

TRUE

Z2_SCLK

TRUE

Z2_MISO

TRUE

Z2_MOSI

TRUE

Z2_DEBUG3

TRUE

Z2_CS_L

TPAD_GND_F

TRUE

PP18V5_S3

TRUE

PICKB_L

TRUE

PP5V_SW_ODD

TRUE

PP3V3_S0_EXCARD_SWITCH

TRUE

PP3V3_S3_EXCARD_SWITCH

SMBUS_MCP_0_DATA

TRUE

SMBUS_MCP_0_CLK

TRUE

PPVCORE_S0_MCP

PPVCORE_S0_MCP_REG

TRUE

GND

TRUE

GND

83 81 68 44 42

90

43

37

87

89

95

94

87

94

95

89

95

43

95

79

87

45

43

95

8

46

34

89

95

14

84

32

84

49

58

89

59

80

94

80

94

80

94

80

14

84

80

94

80

95

84

42

58

59

58

51

93

58

51

84

32

95

89

93

59

51

8

58

80

84

76

14

51

21

42

51

8

7

8

21

39

32

10

79

17

8

79

8

32

57

32

58

49

79

49

10

79

49

79

32

79

49

39

57

58

57

50

51

50

45

57

50

8

50

7

51

50

8

79

8

17

32

45

58

50

7

57

79

8

10

50

8

50

7

51

50

39

32

13

8

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"G3Hot" (Always-Present) Rails

5300 mA

241 mA max load

1034 mA

Chipset "VCore" Rails

139 mA/ 0 mA

105 mA/241 mA

1182 mA

4500 mA

1.8V/DDR 1.5V Rails

5V Rails

3.3V-2.5V Rails

"GPU" Rails

500 mA max supply

"FW" (FireWire) Rails

190 mA

500 mA

130 mA

4771 mA

(1.1V for A01)

OR 0.75V

ENET Rails

Power Aliases

SYNC_MASTER=(MASTER)

051-7546

A.0.0

968

SYNC_DATE=(MASTER)

=PPVP_FW_PORT1 =PPVP_FW_PHY_CPS_FET

=PP3V3_S0GPU_FET

=PP3V3_FW_FWPHY

=PP1V0_FW_REG

=PP1V05_S0_MCP_SATA_AVDD0

PP1V2R1V05_S5

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

=PP3V3_FW_REG

=PP1V5_FC_CON

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_FW_REG

=PPBUS_G3H

PPBUS_CPU_IMVP_ISNS

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

=PP3V3_S3_FET

=PPVIN_S5_P5VP3V3

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_IMVP

=PP3V3_S0_XDP

=PP3V3_S0_MCPCOREISNS

=PP3V3_S0_FAN_RT

=PPVCORE_S0_MCP

PP1V2_S0

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.2V

=PP2V5_S0_GMUX

=PP1V05_ENET_FET

=PP3V3_S0_MCP

=PP1V8R1V5_S0_MCP_FET =PPVIN_S0_DDRREG_LDO

=PPVIN_S5_CPU_IMVP_ISNS

=PP3V42_G3H_CHGR

=PP3V42_G3H_TPAD

=PP3V42_G3H_CPUCOREISNS

=PP18V5_DCIN_CONN

=PP3V3_S0_EXCARD =PP3V3_S0_LVDSDDCMUX

=PP3V3_S0_ODD

=PP3V3_S0_AUDIO

=PPSPD_S0_MEM_B

=PPSPD_S0_MEM_A

=PP3V3_S0_DDC_LCD

=PP3V3_S0_PWRCTL

=PP3V3_S0_FAN_LT

=PPVIN_S0GPU_P1V8P1V1

=PP3V3_S0_GPUTHMSNS

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_GPU_SMBUS_SMC_0_S0

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP2V5_S0

VOLTAGE=2.5V

=PP1V2_S0_GMUX

=PP1V8_GPU_IFPX

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP1V8_GPUIFPX

MIN_NECK_WIDTH=0.15 mm

=PP1V1_GPU_IFPCD_IOVDD

=PP1V1_GPU_VID_PLLVDD

=PP1V1_GPU_H_PLLVDD

=PP1V1_GPU_PLLVDD

=PP1V1_S0GPU_REG

=PP1V1_GPU_PEX_PLLXVDD

=PP1V1_GPU_PEX_IOVDDQ =PP1V1_GPU_PEX_IOVDD

=PP1V1_GPU_FBPLLAVDD

MAKE_BASE=TRUE

PP1V8_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

=PP1V8_GPU_FB_VDDQ

=PP1V8_GPU_FBIO

=PP3V3_GPU_P1V8S0

=PP1V8_GPU_FB_VDD

=PP1V8_GPU_FBVDDQ

=PP1V8_S0GPU_ISNS

=PP1V5_S3_MEM_A =PP1V5_S3_MEM_B

=PP3V3_ENET_MCP_RMGT

=PPVTT_S0_VTTCLAMP

=PP0V75_S0_MEM_VTT_B

=PP0V75_S0_MEM_VTT_A

=PP1V05_ENET_P1V05ENETFET

=PP1V05_S5_MCP_VDD_AUXC

=PP5V_S3_MCPDDRFET

=PP5V_S3_GPUVCORE

=PP5V_S3_WLAN

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

PP5V_S3

VOLTAGE=5V

=PP5V_S3_BTCAMERA

PPVCORE_S0_CPU

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

=PP3V3_GPU_VCORELOGIC =PP3V3_S5_SMC =PP3V3_S5_LPCPLUS

=PP3V42_G3H_SMBUS_SMC_BSA

=PP1V8R1V5_S0_FET

=PP1V2_S0_REG

=PP2V5_S0_REG

=PP5V_S3_P1V05S0FET

=PP1V05_S5_P1V05S0FET

=PP3V3_ENET_FET

=PP3V3_ENET_PHY

=PP1V05_ENET_PHY

=PP1V05_ENET_MCP_RMGT

=PP1V05_ENET_MCP_PLL_MAC

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP3V3_ENET_PHY

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.05V

PP1V2R1V05_ENET

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

=PPVCORE_S0_CPU_REG

PP1V8_S0

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE

=PP3V3_GPU_MIO

=PP3V3_GPU_VDD33

=PP3V3R1V8_S0_MCP_IFP_VDD

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 mm

PP1V8_S0GPU_ISNS_R

=PPVCORE_GPU

=PP1V8_S0GPU_ISNS_R

=PPVCORE_GPU_REG

=PP1V8_GPU_REG

=PPBUS_S5_FW_FET

=PP1V0_FW_FWPHY

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.00V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V0_FW

=PPMCPCORE_S0_REG

=PPDDR_S3_REG

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

=PP3V3_S5_RTC_D

=PP5V_S3_AUDIO_PWR

=PP5V_RT_REG

=PP5V_S0_CPUVTTS0

=PP3V42_G3H_SMCUSBMUX

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V MAKE_BASE=TRUE

PPVP_FW

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

PPVCORE_S0_MCP_REG

=PPVTT_S3_DDR_BUF

=PP3V3_FW_P1V0FW

=PP5V_S0_CPU_IMVP

=PP5V_S3_RTUSB

=PP5V_S3_DDRREG

=PP5V_S3_IR

=PP5V_S3_SYSLED

=PPVIN_S5_SMCVREF

=PPVIN_S5_CPU_IMVP

=PP5V_S0_FAN_RT

=PP3V3_S3_P3V3S3FET

=PP3V3_S5_MCP_A01

=PP3V3_S5_REG

=PP3V3_FW_LATEVG_ACTIVE

=PP3V3_S5_MEMRESET

=PP3V3_S0_BATTCHARGERTMPSNSR

=PP5V_S3_REG

=PP3V42_G3H_REG

=PP1V05_S0_MCP_PEX_AVDD1

=PP3V3_S3_VREFMRGN

=PP1V05_S0_SMC_LS =PP1V05_S0_MCP_FSB

=PP1V05_S0_MCP_SATA_DVDD0

=PP5V_S3_VTTCLAMP

=PP5V_S0_FAN_LT

=PP5V_S0_KBDLED =PP5V_S0GPU_P1V1P1V8_GPU =PP5V_S0_LPCPLUS

=PPVIN_S0_CPUVTTS0

=PPVIN_S5_CPU_IMVP_ISNS_R

=PP1V8_S0_REG

=PP3V3_S0_TPAD

=PP1V05_S0_FET

PP1V8R1V5_S0_FET

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S3_MEMRESET

MIN_NECK_WIDTH=0.1 mm VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V8R1V5_S3

MIN_LINE_WIDTH=0.8 mm

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_PLL_UF

=PP3V3R1V5_S0_MCP_HDA

=PPVCORE_S0_CPU

=PP5V_S3_TPAD

=PPVIN_S0_P1V05S5

=PPDCIN_S5_CHGR

=PP3V42_G3H_LIDSWITCH

=PP3V42_G3H_BATT

=PP3V42_G3H_BMON_ISNS

=PP3V3_S3_SMS

=PPBUS_S0_LCDBKLT

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm

=PP3V3_S3_EXCARD

=PP3V3_S0_LPCPLUS

=PP3V3_S0_GPU1V8ISNS

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_SMC

MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE

PP3V3_S0

MIN_LINE_WIDTH=0.30MM VOLTAGE=3.3V

=PP3V3_S3_P1V8S0

=PP3V3_S3_SMBUS_SMC_MGMT

=PP3V3_S3_MCP_GPIO

=PP3V3_S3_WLAN

=PP1V8R1V5_S0_MCP_MEM

MAKE_BASE=TRUE

PPMCPDDR_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V

=PP1V05_S0_MCP_SATA_DVDD

=PP3V3_S0_GMUX

=PP3V3_S0_HDCPROM

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_P1V2P2V5

=PP3V3_S0_VMON

=PP3V3_FC_CON

MIN_LINE_WIDTH=0.60 MM VOLTAGE=5V

PP5V_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20 MM

=PP5V_S0_HDD

=PP5V_S0_ODD

=PP3V3_S3_TPAD

=PP3V3_S3_REMTHMSNS

=PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P1V05ENETFET

=PP3V3_S5_MCPPWRGD

=PP3V3_S0_P3V3S0FET

=PP3V3_S5_ROM

=PP3V3_FW_LATEVG

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

MAKE_BASE=TRUE

PP3V3_S3

VOLTAGE=3.3V

=PP1V05_S0_MCP_PEX_DVDD

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

=PP1V05_S5_MCP

=PPCPUVTT_S0_REG

=PP3V3_S0_DPCONN

=PP3V3_S0_DPMUX

=PPVTT_S0_DDR_LDO

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=0.75V

PPVTTDDR_S3

PP0V9R0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE

=PP1V05_S0_CPU

PPCPUVTT_S0

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_VMON

=PP1V05_S0_MCP_HDMI_VDD

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_AVDD_UF

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PP1V05_S0_REG

MAKE_BASE=TRUE

=PPMCPDDR_ISNS

=PP1V5_S0_MEM_B

=PP1V5_S0_MEM_A

=PPMCPDDR_ISNS_R =PP1V5_S0_CPU =PP1V5_S0_EXCARD

=PP1V5_S0_VMON

=PP3V3_GPU_LVDS_DDC

=PP3V3_GPU_PWRCTL

MIN_LINE_WIDTH=0.30MM

MAKE_BASE=TRUE

PP3V3_S0GPU

MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

PP1V1_S0GPU_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=1.1V

=PP1V8_GPUIFPX_REG

=PP3V3_S0_FET

=PP3V3_S0_SMBUS_MCP_0

=PPVBAT_G3H_P3V42G3H

=PPVIN_S3_DDRREG

=PPVIN_S0_P5VRTS0_MCPCORE

=PPVIN_GPU_GPUVCORE

=PPBUS_S5_FWPWRSW

MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PPDCIN_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S5

=PP3V3_S5_MCP_GPIO

=PP3V3_S5_MCP

=PP3V3_S5_P1V05FET

=PP3V3_S5_PWRCTL

=PP3V3_GPU_P3V3GPUFET

=PP3V3_S5_LCD

62 13

24

12

46

24

59

79

74

52

76

22

46

21

11

38

13

24

22

58

76

73

74

24

43

24

76

75

25

78

68

64

44

14

49

24

12

46

95

24

19

53

24

10

25

24

12

43

95

20

24

38

69

36

67

20

7

8

32

45

8

61

7

69

63

45

48

62

6

47

49

22

7

83

34

21

69

64

46

61

50

46

60

32

80

39

54

29

28

7

68

49

82

48

45

7

83

77

7

77

75

82

70

72

7

9

72

67

73

71

47

28

29

18

69

29

28

34

22

69

78

31

7

31

7

78

42

44

45

69

86

69

34

33

18

24

7

62

7

75

6

18

7

71

47

46

82

37

36

7

65

64

24

63

26

9

65

66

40

7

27

67

62

40

64

41

43

62

49

69

23

63

37

30

48

63

60

17

27

43

9

20

69

7

51

82

44

66

46

67

51

69

7

30

7

25

24

21

11

51

67

61

41

60

46

52

85

7

32

44

47

43

7

67

45

21

31

16

7

8

83

25

18

86

68

32

7

39

50

48

81

34

26

69

44

38

7

8

24

67

66

81

80

64

7

6

7

17

68

18

8

24

8

24

7

47

29

28

47

11

32

68

80

68

7

67

69

45

60

64

65

78

37

7

18

22

69

68

69

79

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Frame Holes

Thermal Module Holes

MCP79 PCIe PRSNT# Straps

Digital Ground

If found to be necessary, will move to page14.csa

Exist in MRB but not Intel designs. Here for CYA.

Extra FSB Pull-ups

TM Hole

CPU signals

TM Hole TM Hole

GPU signals

ETHERNET ALIASES

GMUX ALIASES

AUDIO ALIASES

Bottom Left GPU

Top GPU Right

Left CPU

TM Hole

Right CPU

These need work. Add other PRSNT# straps if needed. .

Bosses for VRAM HS

STDOFF-4.5OD.98H-1.1-3.48-TH

3R2P5

5% 1/16W

402

MF-LF

47K

5%

1/16W

402

0

MF-LF

17

10K

5% 1/16W MF-LF

402

SM

1%

MF-LF

402

10

1/16W

10

1/16W MF-LF

1%

402

STDOFF-4.5OD.98H-1.1-3.48-TH

3R2P5

TH

SL-3.1X2.7-6CIR-NSP

3R2P5

STDOFF-4.5OD.98H-1.1-3.48-TH

402

0

5% 1/16W MF-LF

17

83

NO STUFF

5%

1/16W

0

402

MF-LF

STDOFF-4.5OD.98H-1.1-3.48-TH

10 14 87

10 13 14 87

10 14 87

10 14 62 87

62

1/16W 402

5% MF-LF

NO STUFF

220

MF-LF

402

5%

1/16W

NO STUFF

200

MF-LF

1/16W

5%

402

1%

150

MF-LF

1/16W 402

NO STUFF

1%

402

1/16W MF-LF

150

NO STUFF

STDOFF-4.0OD3.0H-TH

VENICE

STDOFF-4.0OD3.0H-TH

VENICE

STDOFF-4.0OD3.0H-TH

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

4.0OD1.65H-M1.6X0.35

0

5%

1/16W

402

MF-LF

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SM

3R2P5

Signal Aliases

9 96

A.0.0

051-7546

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MIN_NECK_WIDTH=0.09MM

MIN_LINE_WIDTH=0.6MM VOLTAGE=0V

GND

GND_CHASSIS_CLUTCH

GND_BATT_CHGND

GND_CHASSIS_USB

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

=PP1V05_S0_MCP_SATA_AVDD1

LVDS_B_DATA_N<3>

MAKE_BASE=TRUE

JTAG_GMUX_TDO

IG_LCD_PWR_EN

IG_BKLT_EN

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_B_DATAP<3>

FSB_BREQ0_L

CPU_INTR

FC_PRSNT_L

MAKE_BASE=TRUE

PCIE_FC_R2D_C_N

MAKE_BASE=TRUE

=MCP_HDMI_TXD_N<0..2>

MAKE_BASE=TRUE

PCIE_FW_PRSNT_L

LVDS_A_DATA_P<3>

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

=RTL8211_REGOUT

=RTL8211_ENSWREG

=PP1V05_S0_MCP_SATA_DVDD1

PCIE_FC_D2R_N

MAKE_BASE=TRUE

TP_PE4_PRSNT_L

MCP_MII_PD

MAKE_BASE=TRUE

=MCP_MII_COL

GND_CHASSIS_FAN

TP_USB_EXTCP

MAKE_BASE=TRUE

USB_EXTC_P

=DVI_HPD_GMUX_INT

USB_MINI_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_DATAP<3>

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

GPU_RESET_L

MAKE_BASE=TRUE

DP_IG_DDC_DATA

=MCP_HDMI_DDC_CLK

DP_IG_ML_N<3>

MAKE_BASE=TRUE

=MCP_HDMI_TXC_N

DP_IG_ML_P<2..0>

MAKE_BASE=TRUE

=MCP_HDMI_TXD_P<0..2>

=MCP_HDMI_TXC_P

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

PCIE_RESET_L

VR_PWRGD_CLKEN_LTP_IMVP6_CLKEN_L

MAKE_BASE=TRUE

CPU_VID<0..6>

=MCP_BSEL<0..2>

=PEG_D2R_P<0..15>

IMVP6_VID<0..6>

CPU_BSEL<0..2>

MAKE_BASE=TRUE

PM_SLP_RMGT_L

LVDS_B_DATA_N<3>

LVDS_A_DATA_P<3>

LVDS_IG_B_CLK_N

LVDS_B_DATA_P<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_DATAP<3>

PCIE_CLK100M_FC_N

MAKE_BASE=TRUE

PCIE_FC_R2D_C_P

=MCP_MII_CRS

=MCP_MII_RXER

USB_EXTC_N

MAKE_BASE=TRUE

TP_USB_MININ

MAKE_BASE=TRUE

TP_USB_MINIP

USB_MINI_P

USB_EXTD_N

USB_EXTD_P

VOLTAGE=5V

PP5V_S3_AUDIO_AMP

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

NC_LVDS_B_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_A_DATAP<3>

MAKE_BASE=TRUE

AUD_IPHS_SWITCH_EN

PP5V_S3_AUDIO

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

TP_USB_EXTDP

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

TP_SPI_CS1_R_L_USE_MLB

=DDRVTT_ENMEM_VTT_EN

MAKE_BASE=TRUE

=SPI_CS1_R_L_USE_MLB

=PEG_D2R_N<0..15>

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

LVDS_IG_B_DATA_P<3>

LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3>

LVDS_A_DATA_N<3>

LVDS_IG_B_DATA_N<3>

LVDS_A_DATA_N<3>

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM

TP_USB_EXTDN

MAKE_BASE=TRUE

HDA_BIT_CLK

FC_RESET_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_DATAN<3>

=P3V3ENET_EN

=PP3V3_ENET_PHY_VDDREG

PCIE_FC_D2R_P

MAKE_BASE=TRUE

CPU_DPRSTP_L

GND_CHASSIS_BATTCONN

=PP1V05_S0_MCP_FSB

TP_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

PEG_PRSNT_L

=P1V05ENET_EN

MAKE_BASE=TRUE

TP_USB_EXTCN

MAKE_BASE=TRUE

DP_IG_ML_N<2..0>

LVDS_B_DATA_P<3>

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_A_DATAN<3>

MAKE_BASE=TRUE

CPU_NMI

GMUX_INT

MAKE_BASE=TRUE

PCIE_CLK100M_FC_P

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N

MCP_SPKR

LVDS_IG_B_CLK_P

FC_CLKREQ_L

MAKE_BASE=TRUE

MEM_B_A<15>

HDA_BITCLK

MAKE_BASE=TRUE

=PP5V_S3_AUDIO_PWR

MAKE_BASE=TRUE

TP_MEM_A_A<15>

GMUX_JTAG_TDO

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

GMUX_JTAG_TMS

ALL_EG_PGOOD

DP_IG_ML_P<3>

MAKE_BASE=TRUE

JTAG_GMUX_TDI

EG_RESET_L

MAKE_BASE=TRUE

MEM_A_A<15>

SMC_MCP_SAFE_MODE

MAKE_BASE=TRUE

TP_MEM_B_A<15>

EG_CLKREQ_OUT_L

CPU_PECI_MCP

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

=PEG_R2D_C_P<0..15>

TP_PCIE_CLK100M_PE4P

TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

GMUX_JTAG_TDI

MAKE_BASE=TRUE

LCD_BKLT_EN

LVDS_BKL_ON

TP_MCP_GPIO_17

MAKE_BASE=TRUE

AUD_IP_PERIPHERAL_DET

TP_PCIE_PE4_D2RN

TP_PCIE_PE4_D2RP

TP_PE4_CLKREQ_L

=PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

PEG_D2R_P<0..15>

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_B

GND_CHASSIS_SATA

=PP1V8_GPU_FB_VREF_A

MAKE_BASE=TRUE

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

LVDS_MUX_SEL_EG

=PP1V8_GPU_FB_VDDQ

DP_IG_DDC_CLK

MAKE_BASE=TRUE

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

DP_IG_HPD

MAKE_BASE=TRUE

JTAG_GMUX_TMS

FSB_CPURST_L

GND_CHASSIS_LVDS

ZT0980

ZT0940

1

R0930

1

2

R0925

R0902

1 2

XW0900

12

XW0901

12

R0900

R0901

ZT0981

ZT0982

ZT0983

ZT0984

ZT0985

ZT0986

ZT0987

ZT0945

1

ZT0950

ZT0965

1

ZT0960

1

ZT0990

1

ZT0989

1

ZT0988

1

ZT0991

1

R0926

R0927

ZT0930

R0960

1

2

R0950

1

2

R0970

1

2

R0980

1

2

R0990

1

2

ZT0931

1

ZT0932

1

ZT0933

1

ZT0934

1

ZT0935

1

SH0910

1

ZT0951

1

ZT0952

1

ZT0953

1

R0903

SH0912

1

SH0911

1

SH0913

1

SH0902

1

SH0900

1

SH0903

1

SH0901

1

ZT0915

1

24 22

61

83

95

90

80

89

26

87 87

87

89

95

90

59

56

69

44

89

90

95

14

89

95

89

83

89

80

83

60

20

9

6

83

18

9

32

18

9

33

20

32

17

18

20

18

20

9

70

76

18

80 18

18

70

17

62

11

14

17

62

10

21

9

18

9

32

18

20

57

9

19

54

64 26

21

17 70

18

9

18

9

21

32

9

34

33

32

8

34

80

9

83

32

17

21

18

32 29

54

8

17

18

19

83

80

6

83

28

42

14

17

19

83 85

17

70

74

73

83

76

18

68

6

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ON FSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4 PIN. MAKE SURE CPU_TEST4 IS

402

MF-LF

54.9

1/16W

1%

MF-LF 402

1/16W

5%

68

402

1K

MF-LF

1%

1/16W

402

1/16W

2.0K

MF-LF

1%

402

54.9

1/16W MF-LF

1%

402

1%

MF-LF

1/16W

27.4

402

54.9

1/16W MF-LF

1%

402

27.4

1/16W MF-LF

1%

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

9

14 62 87

14 87

62

13 14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

9

87

9

87

9

87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

7

14 87

9

14 87

7

14 87

7

14 87

7

14 87

13 87

6

10 87

13 26

14 43 62 87

48 95

14 43 87

14 87

9

13 14 87

14 87

6

10 13 87

6

10 13 87

6

10 13 87

6

10 13 87

48 95

14 87

9

14 87

9

14 87

402

NOSTUFF

5%

MF-LF

1/16W

0

402

NOSTUFF

1K

MF-LF

5% 1/16W

402

54.9

MF-LF

1%

1/16W

402

54.9

1/16W MF-LF

1%

402

1%

MF-LF

1/16W

54.9

402

1%

MF-LF

1/16W

54.9

14 87

402

1%

MF-LF

1/16W

649

402

MF-LF

NOSTUFF

1K

5%

1/16W

402

16V

10%

0.1uF

NOSTUFF

X5R

402

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

54.9

1/16W MF-LF

1%

OMIT

PENRYN

FCBGA

OMIT

PENRYN

FCBGA

CPU FSB

10

A.0.0

051-7546

96

SYNC_MASTER=M87_MLB

SYNC_DATE=10/17/2007

XDP_TCK

XDP_TDO

XDP_TMS

XDP_TDI

XDP_TRST_L

=PP1V05_S0_CPU

TP_CPU_RSVD8

TP_CPU_RSVD7

TP_CPU_RSVD6

TP_CPU_RSVD5

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_IGNNE_L

CPU_THERMD_N

FSB_A_L<11>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_BPRI_L

FSB_A_L<12> FSB_A_L<13>

FSB_ADSTB_L<0>

FSB_A_L<17>

FSB_A_L<19>

FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_FERR_L

CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L

TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4

FSB_BNR_L

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L

FSB_BREQ0_L

CPU_IERR_L

FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L

FSB_HIT_L FSB_HITM_L

XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L

CPU_PROCHOT_L CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P FSB_CLK_CPU_N

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<0>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<6>

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_REQ_L<1>

CPU_TEST1

FSB_D_L<10>

FSB_D_L<15> FSB_DSTB_L_N<0>

FSB_D_L<3> FSB_D_L<4>

FSB_D_L<17>

CPU_PSI_L

FSB_CPUSLP_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<1>

CPU_COMP<0>

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

TP_CPU_TEST5

CPU_TEST4

TP_CPU_TEST3

CPU_GTLREF

FSB_DSTB_L_N<1>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<16>

FSB_D_L<5>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<32>

FSB_D_L<0>

FSB_D_L<18> FSB_D_L<19>

FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<25>

FSB_D_L<30> FSB_D_L<31>

FSB_DINV_L<1>

FSB_DSTB_L_P<1>

CPU_TEST2

TP_CPU_TEST7

TP_CPU_TEST6

=PP1V05_S0_CPU

FSB_A_L<25>

FSB_A_L<18>

FSB_A_L<16>

FSB_A_L<14>

R1002

1

2

R1004

1

2

R1005

1

2

R1006

1

2

R1019

R1018

R1017

R1016

R1030

R1007

1

2

R1003

1

2

R1020

R1021

R1022

R1023

R1012

1

2

C1000

1

2

R1024

U1000

N3 P5 P2 L2 P4 P1 R1

Y2 U5 R3 W6

A6

U4 Y5 U1 R4 T5 T3 W2 W5 Y4

J4

U2 V4

W3 AA4 AB2 AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22 A21

E2

AD4 AD3 AD1 AC4

G5

F1

C20

E1

H5 F21

A5

G6 E4

D20

C4

B3

C6

B4

H4

AC2 AC1

D21

K3

H2

K2

J3

L1

C1 F3 F4 G3

M4

N5

T2

V3

B2

F6

D2 D22

D3

A3

D5

AC5 AA6 AB3

A24 B25

C7

AB5

G2

AB6

U1000

B22 B23 C21

R26 U26 AA1 Y1

E22 F24

J24 J23 H22 F26 K22 H23

N22 K25 P26 R23

E26

L23 M24 L22 M23 P25 P23 P22 T24 R24 L25

G22

T25 N25

Y22 AB24 V24 V26 V23 T22 U25 U23

F23

Y25 W22 Y23 W24 W25 AA23 AA24 AB25

AE24 AD24

G25

AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21

E25

AC22 AD23 AF22 AC23

E23 K24 G24

H25

N24

U22

AC20

E5 B5 D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6 D7

C23 D25 C24

AF26

AF1 A26

C3

62

13

12

87

11

13

87

13

10

8

87

8

6

87

87 27

6

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

30.4 A (LFM)

2500 mA (after VCC stable)

4500 mA (before VCC stable)

16.0 A (Deep Sleep SuperLFM)

16.8 A (Sleep SuperLFM)

41.0 A (HFM)

(CPU CORE POWER)

130 mA

(CPU IO POWER 1.05V)

(CPU INTERNAL PLL POWER 1.5V)

Low Voltage:

23.0 A (Design Target)

18.7 A (LFM) TBD A (SuperLFM)

TBD A (Sleep SuperLFM)

TBD A (Deeper Sleep)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (HFM) TBD A (LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep LFM)

25.5 A (SuperLFM)

27.4 A (Sleep HFM)

25.0 A (Deep Sleep HFM)

11.5 A (Deeper Sleep)

9.4 A (Enhanced Deeper Sleep)

TBD A (Sleep HFM)

21.0 A (HFM)

TBD A (Deep Sleep HFM)

TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep LFM)

TBD A (Deep Sleep HFM)

TBD A (Deep Sleep SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

44.0 A (Design Target)

Standard Voltage:

Ultra Low Voltage:

17.0 A (Design Target)

TBD A (Enhanced Deeper Sleep)

9

87

9

87

9

87

9

87

9

87

9

87

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

MF-LF 402

100

1% 1/16W

9

87

62 87

MF-LF 402

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

1/16W

1%

100

OMIT

PENRYN

FCBGA

OMIT

PENRYN

FCBGA

SYNC_DATE=10/17/2007

SYNC_MASTER=M87_MLB

CPU Power & Ground

051-7546

A.0.0

11 96

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

=PPVCORE_S0_CPU

R1101

1

2

R1100

1

2

U1000

A7 A9

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10

A10

C12 C13 C15 C17 C18

D9 D10 D12 D14 D15

A12

D17 D18

E7

E9 E10 E12 E13 E15 E17 E18

A13

E20

F7

F9 F10 F12 F14 F15 F17 F18 F20

A15

AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9

A17

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7 AC7

A18

AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12

A20

AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17

B7

AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

B26 C26

G21 V6

R21 R6 T21 T6 V21 W21

J6 K6 M6 J21 K21 M21 N21 N6

AF7

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AE7

U1000

A4 A8

B11

W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5

B13

AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8

B16

AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11

B19

AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13

B21

AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16

B24

AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19

C5

AF21 A25 AF25

B1

C8 C11 C14

A11

C16 C19

C2 C22 C25

D1

D4

D8 D11 D13

A14

D16 D19 D23 D26

E3

E6

E8 E11 E14 E16

A16

E19 E21 E24

F5

F8 F11 F13 F16 F19

F2

A19

F22 F25

G4

G1 G23 G26

H3

H6 H21 H24

A23

J2

J5 J22 J25

K1

K4 K23 K26

L3

L6

AF2

L21 L24

M2

M5 M22 M25

N1

N4 N23 N26

B6

P3

P6 P21 P24 R2 R5 R22 R25 T1 T4

B8

T23 T26 U3 U6 U21 U24 V2 V5 V22 V25

62 13

46

12

46

12

10

12

11

12

8

11

8

6

8

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1x 10uF, 1x 0.01uF

CPU VCORE HF AND BULK DECOUPLING

4x 330uF, 20x 22uF 0805

1x 470uF, 6x 0.1uF 0402

VCCP (CPU I/O) DECOUPLING

WF: Consider sharing bulk cap with NB Vtt?

VCCA (CPU AVdd) DECOUPLING

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

2.5V D2T

20%

470UF

POLY

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

22UF

X5R-CERM 603

6.3V

20%

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

6.3V

20%

22UF

603

X5R-CERM

CRITICAL

20% X5R-CERM

603

22UF

6.3V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

X5R-CERM

22UF

603

20%

6.3V

CRITICAL

X5R-CERM

22UF

6.3V

20% 603

CRITICAL

22UF

X5R-CERM 603

20%

6.3V

20%

0.1UF

CERM 402

10V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

CRITICAL

22UF

X5R-CERM 603

20%

6.3V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

20% CERM

402

0.1UF

10V

20% CERM

402

0.1UF

10V

20%

0.1UF

CERM 402

10V

20% CERM

402

0.1UF

10V

20% CERM

402

0.1UF

10V

CRITICAL

X5R-CERM 603

20%

22UF

6.3V

PLACEMENT_NOTE=Place near CPU pin B26.

CERM 402

16V

10%

0.01UF

X5R

6.3V

20%

10uF

603

20%

D2T-SM2

POLY-TANT

2.0V

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL

330UF

20%

POLY-TANT

D2T-SM2

PLACEMENT_NOTE=Place in CPU center cavity.

2.0V

20%

POLY-TANT

CRITICAL

330UF

2.0V

PLACEMENT_NOTE=Place in CPU center cavity.

D2T-SM2

PLACEMENT_NOTE=Place in CPU center cavity.

20%

D2T-SM2

POLY-TANT

CRITICAL

330UF

2.0V

CPU Decoupling & VID

SYNC_MASTER=M87_MLB

9612

A.0.0

SYNC_DATE=10/17/2007

051-7546

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

C1208C1207

C1219C1218

C1206C1204

C1216C1214

C1203C1202C1201

C1213C1212C1211

C1200

1

2

C1210

C1236

1

2

C1205 C1209

C1215 C1217

C1237

1

2

C1238

1

2

C1239

1

2

C1240

1

2

C1241

1

2

C1281

1

2

C1280

1

2

C1250

1

2 3

C1251

1

2 3

C1252

1

2 3

C1253

1

2 3

C1235

1

2 3

62 13 11

46

10

11

8

6

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

BI BI

OUT

IN

IN IN

IN OUT OUT OUT

OUT

NC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TCK0

OBSDATA_A3

OBSDATA_A1

OBSFN_C0

OBSDATA_C0 OBSDATA_C1

OBSDATA_C3

Mini-XDP Connector

VCC_OBS_CD

DBR#/HOOK7

Please avoid any obstructions on even-numbered side of J1300

NOTE: This is not the standard XDP pinout.

VCC_OBS_AB

TDO

TDI

RESET#/HOOK6

OBSFN_D0

SCL

SDA

TRSTn

HOOK3

HOOK2

HOOK1

TMS

OBSDATA_D0

TCK1

OBSDATA_B2

PWRGD/HOOK0

OBSFN_D1

OBSDATA_B3

XDP_PRESENT#

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSFN_B0

OBSDATA_C2

OBSFN_C1

Direction of XDP module

998-1571

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1OBSDATA_B1

OBSDATA_B0

OBSFN_B1

OBSDATA_A2

OBSDATA_A0

OBSFN_A1

OBSFN_A0

Use with 920-0620 adapter board to support CPU, MCP debugging.

MCP79-specific pinout

10 14 87

1K

402

MF-LF

XDP

5%

1/16W

7

21 45 90

7

21 45 90

54.9

MF-LF

1/16W

1%

402

XDP

402

0.1uF

XDP

16V

10% X5R X5R

10%

0.1uF

XDP

16V 402

10 87

6

10 87

9

10 14 87

XDP

402

MF-LF

1/16W

5%

1K

PLACEMENT_NOTE=Place close to CPU to minimize stub.

10 87

6

21

6

21 23

6

21 23

19 90

6

21

6

14 87

6

10 87

6

10 87

6

10 87

10 26

19 23

F-ST-SM

LTH-030-01-G-D-NOPEGS

CRITICAL XDP_CONN

SYNC_DATE=01/08/2008

051-7546

SYNC_MASTER=M99_MLB

13

A.0.0

96

eXtended Debug Port(MiniXDP)

FSB_CPURST_L

CPU_PWRGD

XDP_TMS

XDP_TDO_CONN XDP_TRST_L XDP_TDI

FSB_CLK_ITP_N

FSB_CLK_ITP_P

MCP_DEBUG<5>

JTAG_MCP_TMS

MCP_DEBUG<3>

MCP_DEBUG<1>

JTAG_MCP_TRST_L

JTAG_MCP_TDO_CONN

XDP_BPM_L<5> XDP_BPM_L<4>

XDP_BPM_L<2>

XDP_BPM_L<1> XDP_BPM_L<0>

TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B0

XDP_PWRGD

TP_XDP_OBSDATA_B3

XDP_OBS20

PM_LATRIGGER_L JTAG_MCP_TCK

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

XDP_TCK

MCP_DEBUG<0>

XDP_DBRESET_L

XDP_CPURST_L

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<4>

JTAG_MCP_TDI

MCP_DEBUG<2>

TP_XDP_OBSDATA_B2

=PP1V05_S0_CPU

=PP3V3_S0_XDP

XDP_BPM_L<3>

TP_XDP_OBSFN_B0

R1399

1 2

R1315

1

2

C1300

1

2

C1301

1

2

R1303

1 2

J1300

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

78 9

62 12 11 10

8

87

6

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

BI BI BI

BI

IN

BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

IN

BI BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#

CPU_A22# CPU_A23# CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2# CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6# CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15# CPU_A16#

CPU_A19#

CPU_A17# CPU_A18#

CPU_A20# CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT# CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0# CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4# CPU_D5# CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17# CPU_D18#

CPU_D16#

CPU_D19# CPU_D20# CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39# CPU_D40# CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44# CPU_D45# CPU_D46# CPU_D47#

CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK# CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY# CPU_DRDY#

CPU_REQ1#

FSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

270 mA (A01) 206 mA

15 mA

29 mA

20 mA

(MCP_BSEL<0>)

(MCP_BSEL<1>)

(MCP_BSEL<2>)

Loop-back clock for delay matching.

9

10 87

9

10 13 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

7

10 87

9

10 87

7

10 87

7

10 87

7

10 87

13 87

10 87

9

10 87

9

10 87

10 13 87

10 87

9

10 62 87

9

10 43 62 87

10 43 87

10 87

49.9

1/16W

1%

402

MF-LF

1/16W

1%

402

MF-LF

49.9

MF-LF

402

1%

1/16W

49.9

1/16W

1%

402

MF-LF

NO STUFF

1K

402

5% 1/16W MF-LF

1K

NO STUFF

402

MF-LF

5%

1/16W

1K

5%

402

MF-LF

NO STUFF

1/16W

402

MF-LF

62

5%

1/16W

402

MF-LF

54.9

1%

NO STUFF

150

1/16W 402

MF-LF

5%

OMIT

MCP79-TOPO-B

(1 OF 11)

BGA

1/16W 402

MF-LF

62

5%

A.0.0

SYNC_DATE=06/18/2008

MCP CPU Interface

051-7546

9614

SYNC_MASTER=T18_MLB

PM_THRMTRIP_L

FSB_D_L<13>

MCP_BCLK_VML_COMP_GND

FSB_DPWR_L

CPU_DPSLP_L

FSB_D_L<38>

FSB_D_L<43>

FSB_D_L<45>

CPU_DPRSTP_L

CPU_STPCLK_L

FSB_CPUSLP_L

FSB_CPURST_L

CPU_PWRGD

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_A20M_L

FSB_CLK_MCP_P FSB_CLK_MCP_N

FSB_CLK_ITP_N

FSB_CLK_ITP_P

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_DEFER_L

FSB_BPRI_L

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<44>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<15>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

MCP_CPU_COMP_GND

MCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_VDD

FSB_RS_L<2>

FSB_RS_L<1>

CPU_PROCHOT_L

CPU_PECI_MCP

FSB_TRDY_L

FSB_LOCK_L

FSB_HITM_L

FSB_HIT_L

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_ADSTB_L<1>

FSB_ADSTB_L<0>

FSB_A_L<35>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_DINV_L<3>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<2>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<1>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

=PP1V05_S0_MCP_FSB

PP1V05_S0_MCP_PLL_FSB

FSB_D_L<14>

FSB_D_L<7>

FSB_A_L<10>

FSB_A_L<25>

FSB_A_L<34>

FSB_A_L<33>

FSB_DBSY_L FSB_DRDY_L

FSB_BNR_L

FSB_RS_L<0>

CPU_FERR_L

FSB_BREQ0_L

FSB_ADS_L

FSB_BREQ1_L

=PP1V05_S0_MCP_FSB

=MCP_BSEL<2>

=MCP_BSEL<0>

=MCP_BSEL<1>

R1436

1

2

R1431

1

2

R1430

1

2

R1435

1

2

R1422

1

2

R1421

1

2

R1420

1

2

R1415

1

2

R1410

1

2

R1440

1

2

U1400

AK41 AJ40

G41

G42

AL42

AL43

AK42

AL41

AM40

AM39

AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33

AF41

AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37

AC34

AJ34 AL38 AL35 AN34 AR39 AN35

AE38 AE34 AC37 AE37 AE35 AB35

AD42

AE36 AK35

AD43

AA41

AE40 AL32

F41

D42

F42

AM42

AM43

Y43 W42

R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34

Y40

AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38

W41

R33 U37 N34 N33 R34 R35 P35 R39 R37 R38

Y39

L37 L39 L38 N36 N38 J39 J38 J37 L42 M42

V42

P41 N41 N40 M40 H40 K42 H41 L41 H43 H42

Y41

K41 J40 H39 M43

Y42 P42 U41

V41

V35

N35

J41

AD39

AA40

AN32

AN33 AM32

AD41

U40

W37

L36

M41

T40

W39

N37

M39

AH40

AB42 AD40

AH39 AH42 AF42

AC43

AG41

E41

AJ41

AH43

AC38 AA33 AC39 AC33 AC35

H38

AC41 AB41 AC42

AM33

AH41

AG42

AG43

AE41

AG27

AH28

AG28

AH27

R1416

1

2

24

22

14

14 9 9

87

8

24

87

8

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1 MCKE0A_0

MODT0A_1 MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8 MA0_7

MA0_9

MA0_10

MA0_11

MA0_13 MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2 MDQM0_1 MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4 MDQ0_3 MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12

MDQ0_16

MDQ0_21 MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22

MDQ0_26

MDQ0_29 MDQ0_28 MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35 MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40 MDQ0_39

MDQ0_42

MDQ0_47 MDQ0_46

MDQ0_43

MDQ0_45 MDQ0_44

MDQ0_51 MDQ0_50 MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55 MDQ0_54 MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61 MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

MEMORY

CONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60 MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56 MDQ1_55 MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51 MDQ1_50

MDQ1_48 MDQ1_47 MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42 MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36 MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31 MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11 MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6 MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4 MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1# MCAS1#

MWE1#

MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1# MCS1A_0#

MCLK1A_0_N

MODT1A_1 MODT1A_0

MCKE1A_0

MCKE1A_1

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BGA

MCP79-TOPO-B

OMIT

(2 OF 11)

28 88

29 88

BGA

MCP79-TOPO-B

OMIT

(3 OF 11)

29 88

96

051-7546

A.0.0

15

SYNC_MASTER=T18_MLB

SYNC_DATE=06/18/2008

MCP Memory Interface

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

TP_MEM_B_CLK2N

TP_MEM_B_CLK2P

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

U1400

AR19

AT19

AN19

AW21

AN23

AU15

AR23

AU19

AV19

AN21

AR21

AP21

AU21

AR22

AV21

AW17

AP19

AP23

AP17

AT23

AU23

BC20

BB20

AY24

BA24

AV33

AW33

AR18

AT15

AP35

AR35

AV31

AT31

AW37

AV37

AR33

AU31

AN31

AV29

AN29

AV27

AW38

AR31

AP31

AR29

AP29

AR27

AP27

AR25

AP25

AU27

AT27

AV38

AU25

AR26

AU13

AR14

AT11

AR11

AW13

AV13

AV11

AU11

AR38

AV9

AU9

AY5

AW6

AP11

AW9

AU8

AU7

AV5

AU6

AR37

AR5

AN10

AW5

AV6

AR7

AR6

AN7

AN6

AL7

AL6

AV39

AN9

AP9

AL9

AL8

AW39

AU37

AT37

AR34

AV35

AW29

AN27

AN13

AR10

AU5

AN5

AT39

AU39

AU35

AT35

AU29

AU30

AW25

AV25

AR13

AP13

AW8

AW7

AR9

AR8

AL11

AL10

AV15

AP15

AV17

AR17

U1400

BA18

BB25

BA17

BC28

AW28

BA14

BA29

BA25

BB26

BA26

BA27

AY27

BA28

AY28

BB28

BB17

BB18

BB29

BA15

BB30

AY31

AY19

BA19

BA22

BB22

BB42

BA42

BB16

BB14

AP42

AR41

BC40

BA40

AV41

AV42

AW40

BB40

AY39

BA38

BB36

BA36

AU41

AY40

BA39

AW36

BC36

AY35

BA34

BB32

BA32

AY36

BA35

AU40

AW32

BC32

BA12

AY12

BB9

BB8

AW12

BB12

BB10

BA9

AN40

AY8

BA7

BC4

BB4

BC8

BA8

BA5

BB5

BB2

BA3

AP41

AW3

AW4

BC3

BB3

AY3

AY4

AU3

AU2

AR3

AR4

AT41

AV3

AV2

AT3

AT4

AT40

AW41

AW42

AR42

AY43

BB38

BB34

BA11

AY7

BA2

AT5

AT43

AT42

AY42

BA43

BA37

BB37

BA33

BB33

AY11

BA10

BA6

BB6

AY1

AY2

AT1

AT2

AY15

BB13

AW16

BA16

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55 GND56 GND57 GND58

GND60

GND59

GND61 GND62 GND63 GND64

GND52 GND53 GND54

GND51

GND49 GND50

GND48

GND47

GND46

GND44 GND45

GND43

GND42

GND41

GND39 GND40

GND38

GND37

GND36

GND35

GND33 GND34

GND32

GND31

GND30

GND28 GND29

GND27

GND26

GND25

GND24

GND18 GND19

GND17

GND16

GND15

GND13 GND14

GND10

GND12

GND11

GND8 GND9

GND7

GND6

GND5

GND2 GND3 GND4

GND1

MEM_COMP_VDD MEM_COMP_GND

MODT0B_0 MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0# MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE +V_VPLL

+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8

+VDD_MEM9 +VDD_MEM10 +VDD_MEM11

+VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34

+VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41

+VDD_MEM43 +VDD_MEM44 +VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22 GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

87 mA (A01)

39 mA

TP or NC for DDR2.

19 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

12 mA

17 mA

4771 mA (A01, DDR3)

1%

40.2

1/16W

402

MF-LF

402

1%

1/16W

40.2

(4 OF 11)

MCP79-TOPO-B

OMIT

BGA

30

MCP Memory Misc

16 96

A.0.0

051-7546

SYNC_DATE=06/18/2008

SYNC_MASTER=T18_MLB

TP_MEM_B_CKE<3>

TP_MEM_B_CKE<2>

TP_MEM_B_CS_L<2>

MCP_MEM_RESET_L

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_COMP_GND

TP_MEM_A_CLK4N TP_MEM_A_CLK3P

TP_MEM_A_ODT<2> TP_MEM_A_ODT<3>

TP_MEM_A_CKE<2> TP_MEM_A_CKE<3>

TP_MEM_A_CLK5P TP_MEM_A_CLK5N

TP_MEM_A_CLK4P

TP_MEM_A_CLK3N

TP_MEM_A_CS_L<2> TP_MEM_A_CS_L<3>

PP1V05_S0_MCP_PLL_CORE

TP_MEM_B_CLK5P TP_MEM_B_CLK5N

TP_MEM_B_CLK4P TP_MEM_B_CLK4N

TP_MEM_B_CLK3P TP_MEM_B_CLK3N

TP_MEM_B_CS_L<3>

TP_MEM_B_ODT<2> TP_MEM_B_ODT<3>

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_COMP_VDD

R1610

1

2

R1611

1

2

U1400

AA22

AA39 AB22

AB7 AD22 AE20 AF24 AG24 AH35

AK7 AM28

AP12

AT25 AP30 AR36 AU10

F28 BC21

AY9

BC9

D34

F24

G30

G32

H31

K7

M38

M5 M6 M7 M9

N39

N8

P10

P33

P34

P37

P4

P40

P7 R36 R40 R43

R5

T10

T18 T20

AK11

T24 T26

T33 T34 T35 T37 T38

T6

T7 T9 U18 U20 U22

V10 V34

W5

AV23 AN25

BA30 BA31

BB21

BA21

BC24

BB24

AU34

AU33

AY20

BA20

BA23

AY23

BB41

BA41

AU17 AR15

BC16 BA13

AM41

AN41

AN17 AN15

AY16 BC13

AY32

U27

U28

T27

T28

AM17

AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20

AM19

AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24

AM21

AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25

AM23

AY26 AW19 AW24 BC25 AL30 AM31

AM25 AM27 AM29 AN16 BC29

24

16

8

88

24

8

88

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7 +AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N PE0_TX15_P

PE0_TX13_N PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N

PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N PE0_TX6_P

PE0_TX4_N PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

IN

IN IN

OUT

OUT OUT

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

Minimum 1.025V for Gen2 supportMinimum 1.025V for Gen2 support

Int PU

84 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Int PU

206 mA (A01, AVDD0 & 1)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

57 mA (A01, DVDD0 & 1)

Int PU (S5)

MCP79-TOPO-B

(5 OF 11)

OMIT

BGA

9

70 89

9

31 89

9

36

23 31 32

36 89

7

32 89

7

32 89

31

32

31 89

36 89

32 89

31 89

32 89

9

2.37K

402

MF-LF

1% 1/16W

NO STUFF

PLACEMENT_NOTE=Place within 12.7mm of U1400

9

26

83

9

SYNC_MASTER=T18_MLB

MCP PCIe Interfaces

17 96

A.0.0

051-7546

SYNC_DATE=06/18/2008

AUD_IP_PERIPHERAL_DET

TP_PE4_CLKREQ_L

PCIE_EXCARD_PRSNT_L

TP_PE4_PRSNT_L

=PP1V05_S0_MCP_PEX_AVDD1

GMUX_JTAG_TDO

=PEG_D2R_N<15>

=PEG_D2R_N<14>

GMUX_JTAG_TCK_L

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_P

FW_CLKREQ_L PCIE_FW_PRSNT_L

=PEG_D2R_N<1>

=PEG_D2R_P<1>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_P<5>

=PEG_D2R_P<3>

=PEG_D2R_N<7>

=PEG_D2R_N<6> =PEG_D2R_P<7>

=PEG_D2R_N<5>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

=PEG_D2R_P<10>

=PEG_D2R_P<9>

=PEG_D2R_P<8>

=PEG_D2R_N<10>

=PEG_D2R_N<12>

=PEG_D2R_N<11>

=PEG_D2R_P<13>

=PEG_D2R_P<11>

=PEG_D2R_P<12>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_N<13>

PEG_PRSNT_L

PCIE_MINI_D2R_P

PCIE_WAKE_L

PCIE_EXCARD_D2R_P

PCIE_FW_D2R_P

PCIE_MINI_D2R_N

PCIE_EXCARD_D2R_N TP_PCIE_PE4_D2RP

TP_PCIE_PE4_D2RN

MCP_PEX_CLK_COMP

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<1> =PEG_R2D_C_N<1>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<2> =PEG_R2D_C_N<2>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3> =PEG_R2D_C_N<3>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<6>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<6> =PEG_R2D_C_P<7> =PEG_R2D_C_N<7>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<8> =PEG_R2D_C_N<8>

=PEG_R2D_C_P<10>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<10> =PEG_R2D_C_P<11> =PEG_R2D_C_N<11>

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<12> =PEG_R2D_C_N<12>

=PEG_R2D_C_P<14>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_N<15>

PCIE_CLK100M_MINI_P

PEG_CLK100M_P PEG_CLK100M_N

PCIE_CLK100M_FW_P

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N

PCIE_MINI_R2D_C_P

PCIE_RESET_L

TP_PCIE_CLK100M_PE6N

PCIE_FW_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_N TP_PCIE_PE4_R2D_CP

TP_PCIE_PE4_R2D_CN

PCIE_MINI_PRSNT_L

=PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2>

=PEG_D2R_N<0>

PP1V05_S0_MCP_PLL_PEX

=PEG_D2R_N<2>

=PEG_D2R_P<0>

PCIE_FW_D2R_N

=PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD0

MINI_CLKREQ_L

TP_MCP_GPIO_18

U1400

Y12

AC12 AD12 V12 W12

AA12 AB12 M12 P12 R12 N12 T12 U12

M13 N13 P13

T17 W19 U17 V19 W16 W17 W18 U16

T19 U19

T16

C9 D11

E11

E7

F7

L8

L9

L6

L7

N10

N11

P9

N9

N6

N7

N4

N5

C7

D7

F6

E6

F5

E5

E3

E4

D3

C3

H5

G5

J6

J7

J4

J5

L10

L11

D4

C5

J1

H1

J3

J2

K3

K2

L3

L4

M3

M4

M1

M2

B4

C4

A3

A4

B2

B3

D1

C1

E1

D2

F2

E2

F4

F3

H4

G3

H2

H3

F11

G11

J9

K9

G9

H9

E9

F9

G7

H7

C8

D8

A8

B8

B7

A7

C6

B6

J10

J11

F13

G13

H13

J13

K14

L14

M14

N14

F17

D5 D9

E8

C10

M15 B10

L16 L18

M16

M18

M17 M19

A11

K11

R1710

1

2

9

8

9

89

9

24

8

IN

BI

OUT

IN IN IN IN

IN IN

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

IN

IN OUT

IN IN IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

BI

OUT

BI

OUT

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)

103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable: Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1 0

MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

DP_IG_DDC_CLK

TP_DP_IG_AUX_CHP/N

TMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0>

MCP Signal

=MCP_HDMI_DDC_CLK

=MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_DDC_DATA

TMDS_IG_HPD

=MCP_HDMI_HPD DP_IG_AUX_CH_P/N

8 mA 8 mA

16 mA (A01)

95 mA (A01)

LVDS: Power +VDD_IFPx at 1.8V

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

DP_IG_AUX_CH_P/N

DP_IG_HPD

DP_IG_DDC_DATA

DP_IG_ML_P/N<0>

Interface Mode

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting. IFP interface can

level-shifters.

NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used): In MCP79 these pins have undocumented internal

24

33 91

34 91

33 91

25 89

9

80 89

9

25 89

1% 1/16W MF-LF

402

49.9

1/16W MF-LF

49.9

402

1%

80

25

9

(6 OF 11)

BGA

MCP79-TOPO-B

OMIT

10K

402

1/16W

5% MF-LF

402

5%

100K

1/16W MF-LF

402

MF-LF

5%

1/16W

100K

44

5%

47K

402

MF-LF

1/16W

33 91

83 89

33 91

83 89

9

89

9

89

9

89

9

89

83 89

33 91

83 89

9

89

9

89

80

9

25 89

33 91

25 89

33 91

18 96

A.0.0

051-7546

SYNC_DATE=06/18/2008

SYNC_MASTER=T18_MLB

MCP Ethernet & Graphics

=DVI_HPD_GMUX_INT

LVDS_IG_BKL_PWM

MCP_CLK27M_XTALOUT

TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF

LPCPLUS_GPIO

=PP1V05_ENET_MCP_RMGT

=PP3V3_S5_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3>

ENET_CLK125M_TXCLK ENET_TX_CTRL

MCP_MII_VREF

CRT_IG_VSYNC

CRT_IG_HSYNC

CRT_IG_B_COMP_PB

=MCP_MII_CRS

=MCP_MII_COL

=MCP_MII_RXER

TP_ENET_PWRDWN_L

ENET_MDC

ENET_RESET_L

ENET_RXD<1> ENET_RXD<2>

ENET_CLK125M_RXCLK ENET_RX_CTRL

ENET_RXD<3>

TP_ENET_INTR_L

ENET_RXD<0>

MCP_TV_DAC_RSET

MCP_IFPAB_VPROBE

MCP_IFPAB_RSET

=MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_CLK_N

LVDS_IG_B_CLK_P

LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_CLK_P

CRT_IG_G_Y_Y

CRT_IG_R_C_PR

TP_MCP_RGB_VSYNC

TP_MCP_RGB_HSYNC

TP_MCP_RGB_BLUE

TP_MCP_RGB_GREEN

TP_MCP_RGB_RED

MCP_DDC_CLK0 MCP_DDC_DATA0

MCP_CLK25M_BUF0_R

ENET_MDIO

=MCP_HDMI_HPD

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

MCP_TV_DAC_VREF

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

MCP_CLK27M_XTALIN

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXC_P

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

MCP_MII_COMP_VDD MCP_MII_COMP_GND

PP3V3_S0_MCP_DAC

=PP3V3R1V8_S0_MCP_IFP_VDD

PP3V3_S0_MCP_VPLL

=PP1V05_S0_MCP_HDMI_VDD

PP1V05_ENET_MCP_PLL_MAC

DP_IG_CA_DET

MCP_HDMI_VPROBE

MCP_HDMI_RSET

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_CLK_N

=MCP_HDMI_TXD_P<2>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_N<0>

R1810

1

2

R1811

1

2

U1400

E23

B31

C30

D31

A31

B30

E31

C43

D43

E16 B15

J31

E35

D35

F35

G35

G33

F33

H33

J33

J30

C31 F31

C35

B35

A32

B32

C32

D32

C33

D33

C34

B34

E32 G31

K31

L31

H29

J29

K29

L29

K30

L30

M30

N30

G39 E37 F40

B26

B27

C27

B22

J23

F23

E28

J24 K24

T23

U23 V23

M29

M28

J32 K32

T25

M27 M26

B40

A39

A40

B39

C39 B38

A41

J22

D21 C21

G23

A23 C22

C23 B23 E24 A24

D24 C26

B24 C24 C25 D25

C36

B36

D36

A36

E36 A35

C37

C38 D38

R1850

1

2

R1861

1

2

R1860

1

2

R1820

1

2

24

21

24

20

18

19

18

25

8

25

91

25

8

25

8

24

OUT

BI BI BI BI

LPC PCIGND

PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0# LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5 PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10 PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15 PCI_AD16 PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21 PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66 GND67

GND69

GND68

GND70 GND71 GND72

GND74

GND73

GND75 GND76 GND77

GND79

GND78

GND80 GND81

GND84

GND83

GND82

GND85 GND86 GND87

GND89

GND88

GND90 GND91 GND92

GND94

GND93

GND95 GND96 GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR# PCI_STOP#

PCI_RESET0# PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105 GND106 GND107

GND109

GND108

GND110 GND111 GND112

GND115

GND114

GND113

GND116 GND117

GND120

GND119

GND118

GND121 GND122 GND123

GND125

GND124

GND126 GND127 GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0# PCI_REQ1#/FANRPM2

IN

BI

OUT

IN

OUT

BI BI BI BI BI BI BI BI

OUT

OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU Int PU Int PU

Int PU (S5)

42 44 83 90

26 83 90

42 44 83 90

BGA

(7 OF 11)

MCP79-TOPO-B

OMIT

42 44

42 44 26 90

42 44

PLACEMENT_NOTE=Place close to pin R8

MF-LF 402

1/16W

5%

22

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

402

MF-LF1/16W

5%

8.2K

5%

1/16W MF-LF

402

19

MF-LF 402

1/16W

5%

10K

1/16W MF-LF

402

22

5%

1/16W MF-LF22402

5%

1/16W MF-LF22402

22

5%

1/16W MF-LF

402 402

MF-LF1/16W

5%

22

26

36

19

13 23

13 90

9

59

9

051-7546

A.0.0

9619

MCP PCI & LPC

SYNC_DATE=06/18/2008

SYNC_MASTER=T18_MLB

GMUX_JTAG_TDI

GMUX_JTAG_TMS

TP_PCI_INTX_L

TP_PCI_INTZ_L

FW_PME_L TP_LPC_DRQ0_L LPC_SERIRQ

PM_CLKRUN_L

=PP3V3_S0_MCP_GPIO

MCP_RS232_SIN_L

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<5>

MCP_DEBUG<4>

MCP_DEBUG<3>

MCP_DEBUG<2>

MCP_DEBUG<1>

MCP_DEBUG<0>

MCP_RS232_SIN_L

AUD_IPHS_SWITCH_EN

CRTMUX_SEL_TV_L

TP_PCI_AD<12> TP_PCI_AD<13> TP_PCI_AD<14>

TP_PCI_AD<16> TP_PCI_AD<17> TP_PCI_AD<18> TP_PCI_AD<19> TP_PCI_AD<20> TP_PCI_AD<21> TP_PCI_AD<22> TP_PCI_AD<23> TP_PCI_AD<24> TP_PCI_AD<25> TP_PCI_AD<26> TP_PCI_AD<27> TP_PCI_AD<28> TP_PCI_AD<29> TP_PCI_AD<30> TP_PCI_AD<31>

TP_PCI_INTW_L

TP_PCI_TRDY_L

TP_PCI_INTY_L

TP_PCI_AD<15>

PCI_REQ0_L PCI_REQ1_L

TP_PCI_AD<8>

TP_PCI_AD<10> TP_PCI_AD<11>

TP_PCI_AD<9>

TP_PCI_PERR_L

MEM_VTT_EN_R

PCI_CLK33M_MCP

TP_PCI_CLK1 PCI_CLK33M_MCP_R

LPC_PWRDWN_L LPC_RESET_L

LPC_FRAME_R_L

LPC_CLK33M_SMC_R

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_AD_R<0>

TP_PCI_CLK0

TP_PCI_RESET1_L

PM_LATRIGGER_L

TP_PCI_STOP_L

TP_PCI_SERR_L

TP_PCI_PAR

TP_PCI_IRDY_L

TP_PCI_FRAME_L

TP_PCI_DEVSEL_L

TP_PCI_C_BE_L<3>

TP_PCI_C_BE_L<2>

TP_PCI_C_BE_L<1>

TP_PCI_C_BE_L<0>

MCP_RS232_SOUT_L

TP_PCI_GNT1_L

TP_PCI_GNT0_L

LPC_AD<0>

LPC_FRAME_L

LPC_AD<2> LPC_AD<3>

LPC_AD<1>

MCP_RS232_SOUT_L

PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L

U1400

AB18 H34 AB20 AB21 AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33 AD34

U24 U26 U39

U4

U8 V16 V17 V18 V20 V22 V24 V26 V27 V28 V33 V37

V4 V40

V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22 Y24 Y25

Y26 Y27

AD3 AD2 AD1 AD5

AE9

AE1

AE2

AD4 AE12

AE5

AE6

AC3

AE10

AC9

AC10 AC11

AA1 AA5

Y5

W3

W6

W4

W7

AC4

V3

W8

V2

W9

U3 W11

U2

U5

U1

U6

AE11

T5

U7

AB3 AC6 AB2 AC7 AC8 AA2

AA3 AA6 AA11 W10

R6 R7 R8

R9

AD11

AA9 Y4

R3 U10 R4 U11 P3

P2

N3

N2

N1

AA10 Y1 AB9

T1

T2

V9

T3

U9

T4

R10 R11

AA7 Y2

Y3

R1910

1

2

R1989

1 2

R1991

1 2

R1990

1 2

R1994

1 2

R1992

1 2

R1961

1

2

R1960

1 2

R1950

1 2

R1951

1 2

R1952

1 2

R1953

1 2

21 18

90

8

19

90

44

19

BI BI

IN IN IN IN

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158 GND159

GND157

GND156

GND155

GND153 GND154

GND152

GND151

GND150

GND148 GND149

GND147

GND146

GND145

GND143 GND144

GND142

GND141

GND140

GND139

GND136

GND133 GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9

+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT OUT

IN

OUT OUT

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

127 mA (A01, AVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Geyser Trackpad/Keyboard

AirPort (PCIe Mini-Card)

External D

External A

Camera

Bluetooth

IR

External B

External C

19 mA (A01)

Minimum 1.025V for Gen2 support

ExpressCard

43 mA (A01, DVDD0 & 1)

84 mA (A01)

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

Minimum 1.025V for Gen2 support

40 90

9

90

9

90

9

90

9

90

31 90

41 90

50 90

31 90

40 90

32 90

9

90

9

90

40

32 43

2.49K

402

1/16W

1% MF-LF

402

1/16W

1%

MF-LF

806

402

1/16W MF-LF

8.2K

5%

8.2K

5%

MF-LF

1/16W

402

MF-LF 402

1/16W

8.2K

5%

8.2K

5%

MF-LF

1/16W

402

BGA

OMIT

MCP79-TOPO-B

(8 OF 11)

39 89

SYNC_DATE=06/18/2008

20 96

A.0.0

051-7546

MCP SATA & USB

SYNC_MASTER=T18_MLB

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_SATA_DVDD0

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

SATA_HDD_D2R_N SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

TP_SATA_C_D2RP

TP_SATA_C_D2RN

PP1V05_S0_MCP_PLL_SATA

USB_EXTA_OC_L

TP_USB_11N

TP_USB_11P

TP_USB_10P

USB_EXTC_N

USB_EXCARD_N

USB_EXTB_N

USB_EXTB_P

USB_BT_N

USB_BT_P

USB_TPAD_N

USB_TPAD_P

USB_IR_N

USB_IR_P

USB_CAMERA_N

USB_CAMERA_P

USB_EXTD_N

USB_EXTD_P

USB_MINI_N

USB_EXTA_N

USB_EXTA_P

MCP_SATA_TERMP

TP_SATA_F_D2RP

TP_SATA_F_D2RN

TP_SATA_F_R2D_CN

TP_SATA_E_D2RN

TP_SATA_D_R2D_CN

TP_SATA_C_R2D_CN

TP_SATA_C_R2D_CP

TP_MCP_SATALED_L

TP_SATA_D_D2RN

TP_SATA_E_R2D_CP TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

USB_EXTC_P

USB_EXCARD_P

TP_SATA_D_D2RP

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD0

TP_SATA_F_R2D_CP

TP_SATA_D_R2D_CP

USB_EXTB_OC_L

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

EXCARD_OC_L

TP_USB_10N

USB_EXTC_OC_L

=PP3V3_S5_MCP_GPIO

USB_MINI_P

R2010

1

2

R2060

1

2

R2053

1

2

R2052

1

2

R2051

1

2

R2050

1

2

U1400

AD35 AD37 AD38 AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18 AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24

AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13

AN14 AL14 AM13 AM14

AF19 AG16 AG17 AG19

AH17 AH19

AE16

L28

AJ5 AJ4

AJ6

AJ7

AJ9 AK9

AJ10

AJ11

AJ2 AJ1

AJ3

AK2

AL4 AK3

AL3

AM4

AM2 AM3

AM1

AN1

AN3 AN2

AP2

AP3

E12

AE3

D29

C29

G25

F25

L23

K23

D28

C28

B28

A28

G29

F29

L27

K27

J27

J26

G27

F27

E27

D27

L25

K25

J25

H25

L21 K21 J21 H21

A27

18

9

8

24

89

9

8

24

90

8

OUT

BI

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

IN IN IN

OUT

HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK

HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

THERM_DIODE_N

EXT_SMI/GPIO_32#

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME#

KBRDRSTIN#

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_RESET#

HDA_SYNC

HDA_BITCLK

HDA_SDATA_OUT

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST#

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI JTAG_TDO

RTC_RST#

PS_PWRGD

PWRGD_SB

INTRUDER#

LID# LLB#

PWRBTN# RSTBTN#

CPU_DPRSLPVR

SLP_S5#

SLP_S3#

HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA

HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK

A20GATE

GPIO_12/SUS_STAT#/ACCLMTR

HDA_SDATA_IN0

GPIO_1/PWRDN_OK/SPI_CS1

HDA_PULLDN_COMP

THERM_DIODE_P

SLP_RMGT#

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT#/GPIO_64

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11

SPI_DI/GPIO_8 SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1 +V_DUAL_HDA2

+V_PLL_NV_H +V_PLL_SP_SPREF

HDA

MISC

OUT

IN

OUT

IN

OUT

IN

OUT

IN

IN IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(MGPIO2)

(MGPIO3)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

HDA Output Caps

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5)

Int PU

25 MHz

42 MHz

0

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0 1

1

0

SPI_CLK

SPI_DO

0

1 1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0 SPI1

I/F HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

1

0

LPC_FRAME#

0

1

0

1

Int PU

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

(MXM_OK for MXM systems)

SAFE mode: For ROMSIP recovery

USER mode: Normal

Connects to SMC for automatic recovery.

44 90

7

34 37 42 44 68 81 83

40 42 43 68

7

13 45 90

45 90

7

13 45 90

45 90

21 65

48 95

21 65

21 31 34

48 95

9

62 87

23 42

54 90

9

90

54 90

MF-LF

1/16W

1%

402

49.9K

1%

49.9K

MF-LF

402

1/16W

1K

MF-LF

1% 1/16W

402

26 90

23 42

MF-LF

402

5%

22

1/16W

MF-LF

5%

1/16W

402

22

5%

22

MF-LF

1/16W

402

5%

10K

MF-LF

1/16W

MF-LF

8.2K

5% 1/16W

402

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

5%

10K

402

MF-LF

BOOT_MODE_USER

1/16W

402

5%

22

1/16W MF-LF

9

44

49.9

MF-LF

1/16W

1%

402

1/16W MF-LF

5%

10K

6

13 23

6

13 23

6

13

6

13

6

10PF

50V

5%

402

CERM

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

50V

10PF

5%

402

CERM

BGA

(9 OF 11)

MCP79-TOPO-B

OMIT

39

21 59

26 26

34 37 42 43

21 28 29 42

402

1/16W MF-LF

5%

100K

10K

5% 1/16W

402

MF-LF

402

1/16W MF-LF

5%

10K

22K

5% MF-LF

1/16W 402

22K

5% MF-LF

1/16W 402402

1/16W

22K

5% MF-LF

402

MF-LF

5% 1/16W

100K

1/16W MF-LF

5%

100K

402

MF-LF 402

1/16W

5%

10K10K

5% MF-LF

1/16W 402

9

21 43

26

42

23 42

23 26

44 90

MCP HDA & MISC

SYNC_DATE=06/18/2008

SYNC_MASTER=T18_MLB

21 96

A.0.0

051-7546

TP_MCP_BUF_SIO_CLK

=PP3V3R1V5_S0_MCP_HDA

MCP_GPIO_4

AP_PWR_EN

=PP3V3_S3_MCP_GPIO

AUD_I2C_INT_L

MCP_GPIO_4

MCP_CPU_VLD

MCP_VID<0>

PM_DPRSLPVR

HDA_SDIN0

MCP_VID<0>

MCP_THMDIODE_P

SMBUS_MCP_1_CLK

TP_MCP_LID_L

PM_PWRBTN_L

RTC_RST_L

MCP_PS_PWRGD

JTAG_MCP_TDI JTAG_MCP_TDO

SMBUS_MCP_1_DATA AP_PWR_EN

MCP_VID<2>

SMBUS_MCP_0_DATA

PM_BATLOW_L

HDA_SDOUT_R

HDA_BIT_CLK_R

=SPI_CS1_R_L_USE_MLB

SPI_CLK_R

SMC_RUNTIME_SCI_L

MCP_VID<1>

PM_SLP_RMGT_L

TP_SB_A20GATE

MCP_HDA_PULLDN_COMP

PP1V05_S0_MCP_PLL_NV

SPI_CS0_R_L

RTC_CLK32K_XTALOUT

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT

MCP_CLK25M_XTALIN

JTAG_MCP_TCK

PM_CLK32K_SUSCLK_R

SPI_MISO SPI_MOSI_R

SMBUS_MCP_0_CLK

MCP_THMDIODE_N

PM_SYSRST_DEBOUNCE_L

TP_MCP_KBDRSTIN_L

HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

PP3V3_G3_RTC

=PP3V3R1V5_S0_MCP_HDA

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

HDA_BIT_CLK_R

MCP_VID<2>

MCP_VID<1>

JTAG_MCP_TMS

MCP_TEST_MODE_EN

JTAG_MCP_TRST_L

PM_RSMRST_L

SM_INTRUDER_L

ARB_DETECT

HDA_SYNC

HDA_RST_R_L

ODD_PWR_EN_L

MEM_EVENT_L

SMC_WAKE_SCI_L

=PP3V3_S0_MCP_GPIO

MEM_EVENT_L SMC_IG_THROTTLE_L

SMC_ADAPTER_EN

TP_MLB_RAM_VENDOR

TP_MLB_RAM_SIZE

HDA_SYNC_R

AUD_I2C_INT_L

PM_SLP_S3_L

PM_SLP_S4_L

=PP3V3_S0_MCP

MCP_SPKR

MCP_CPUVDD_EN

ARB_DETECT

SMC_IG_THROTTLE_L

R2121

1

2

R2120

1

2

R2190

1

2

R2170

1 2

R2171

1 2

R2173

1 2

R2163

1

2

R2160

1

2

R2180

1

2

R2181

1

2

R2172

1 2

R2110

1

2

R2150

1

2

C2171

1

2

C2173

1

2

C2170

1

2

C2172

1

2

U1400

K13

AE7

M22

C17 D17

C18

A12

C12

B12

D12

L26

L24

E15

K17 L17

A15

K15

G15

J14

J15

F15

L15

B20

G19

E19 F19 J19 J18

L13

M25 M24

L20 M20 M21

J16 K16

AE18 AE17

L22

E20

C16

D20

D16

C20

C19

J17

G17

H17

M23

L19

G21

K19

F21

D13

C14

C15 B14

C13

B18

K22

C11

B11

A16

A19

B16

B19

R2147

1

2

R2142

1

2

R2141

1

2

R2157

1

2

R2156

1

2

R2155

1

2

R2151

1

2

R2154

2

1

R2143

1

2

R2140

1

2

42

24

34

24

19

29

24

21

31

59

65

90

26

21

90

65

90

18

28

43

90

22

8

21

8

21

23

21

90

24

22

8

21

8

21

8

21

GND

GND161

GND165 GND166

GND164

GND163

GND162

GND167 GND168

GND171

GND170

GND169

GND172 GND173

GND176

GND175

GND174

GND177 GND178

GND181

GND180

GND179

GND182 GND183 GND184

GND187

GND186

GND185

GND188 GND189

GND192

GND191

GND190

GND193 GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206 GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213 GND214

GND217

GND216

GND215

GND218 GND219

GND222

GND221

GND220

GND223 GND224 GND225

GND228

GND227

GND226

GND229 GND230

GND233

GND232

GND231

GND234 GND235

GND238

GND237

GND236

GND239 GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331 GND332

GND330

GND329

GND328

GND326 GND327

GND325

GND324

GND323

GND321 GND322

GND320

GND319

GND318

GND316 GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305 GND306 GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285 GND286

GND284

GND283

GND282

GND280 GND281

GND279

GND278

GND277

GND275 GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264 GND265 GND266

GND263

GND262

GND259 GND260 GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6

+VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19

+VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30

+VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37

+VDD_CORE39 +VDD_CORE40 +VDD_CORE41

+VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3 +3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

80 uA (S0)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

10 uA (G3)

16 mA

266 mA (A01)

450 mA (A01)

1182 mA (A01)

BGA

OMIT

MCP79-TOPO-B

(11 OF 11) (10 OF 11)

BGA

MCP79-TOPO-B

OMIT

SYNC_DATE=06/18/2008

SYNC_MASTER=T18_MLB

051-7546

A.0.0

9622

MCP Power & Ground

=PP1V05_S0_MCP_FSB

=PPVCORE_S0_MCP

PP3V3_G3_RTC

=PP3V3_S0_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S5_MCP

U1400

AH26 AH33 AH34 AH37 AH38 AJ39

AJ8 AK10 AK33 AK34 AK37

AK4 AK40 AL36 AL40

AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38

AM5

AM6

AM7

AM9 AP26 AN28 AN30 AN39

AN4

Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37

AP4

AP40

AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29 AT33

AT6

AT7

AT9 AY21 AY22

L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38

AU4

G28

F20 AV28 AV32 AV36

AV4

AV7 AW11

G20 AR43 AW43 AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41

AV40 BA1 BA4 AW31 AY6 L35 BC33 BC37 BC41 AY14 BC5 C2 D10 D14 D15 D18 D19 D22 D23 D26 D30 D37 D6 E13 E17 E21 E25 E29 E33 F12 F16 F32 F8 G10 G12 G14 G16 BC12 G22 G24 AW20 G34 G4 G43 G6 G8 H11 H15 AW35 H23 AN8 G40 J12 J8 K10 K12 K18 K26 K37 K4 K40 K8 AU1 L40 L43 L5 M10 M34 M35 M37 Y28 Y33 Y34 Y35 Y37 Y38 AB17 AB16 AN26 AD7 M11 AA4 AB19 AY13 P11 Y6 T11 V11 Y11 AH16 T22

U1400

AD10 AE8 AB10 AD9 Y10 AB11 AA8 Y9

G18 H19 J20 K20

G26 H27 J28 K28

A20

T21 U21 V21

AA25

AA26 AA27 AA28 AC16 AC17 AC18 AC19 AC20 AC21 AA17

AC23

AC24 AC25 AC26 AC27 AC28 AD21 AD23

W27 V25

AA18

U25

AE19 AE21 AE23 AE25 AE26 AE27 AE28 AF10 AF11 AA19

AH12

AF2 AF21 AF23 AF25

AF3

AF4

AF7 AH23

AF9 AA20

AG10

AG11 AG12 AG21 AG23 AG25

AG3

AG4 AA21

AG6

AG7

AG5

AG8

AG9

AH1 AH10 AH11

W26

AH2 AA23

W28 AH25

Y21

AH21

AH3

AH4

AH5

AH6

AH7

AH9 AA24

W21

W23

Y23

W25 AF12

AA16

R32

P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32

AC32

B41 B42 C40 C41 C42 D39 D40 D41 E38 E39

E40

F37 F38 F39 G36 G37 G38 H35 H37 J34 J35

J36

K33 K34 K35 L32 L33 L34 M31 M32 M33 N31

N32

P32 Y32 AA32

T32 U32 V32 W32

AG32

24 14 46

24

9

24

26

21

24

8 8

21

8

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.3V Interface Pull-ups

These internal pull-ups are missing in Revs A01 & A01P.

MCP_A01&MCP_A01P&MCP_A01Q

402

MF-LF1/16W

5%

10K

MCP_A01&MCP_A01P&MCP_A01Q

402

MF-LF1/16W

5%

10K

MCP_A01&MCP_A01P&MCP_A01Q

5%

1/16W MF-LF

402

10K

5%

1/16W MF-LF

402

10K

MCP_A01&MCP_A01P&MCP_A01Q

5%

1/16W MF-LF

402

10K

MCP_A01&MCP_A01P&MCP_A01Q

5%

1/16W MF-LF

402

10K

13 19

17 31 32

6

13 21

6

13 21

21 26

21

21 42

MCP_A01&MCP_A01P&MCP_A01Q

5%

1/16W MF-LF

402

10K

MCP_A01&MCP_A01P&MCP_A01Q

402

MF-LF1/16W

5%

10K

MCP_A01&MCP_A01P&MCP_A01Q

10K

402

MF-LF1/16W

5%

MCP_A01&MCP_A01P&MCP_A01Q

5%

1/16W MF-LF

402

10K

SYNC_DATE=03/31/2008

SYNC_MASTER=T18_MLB

MCP79 A01 Silicon Support

051-7546

A.0.0

9623

PM_LATRIGGER_L

PM_SYSRST_DEBOUNCE_L

SMC_WAKE_SCI_L

PM_BATLOW_L

PM_PWRBTN_L

SMC_RUNTIME_SCI_L

JTAG_MCP_TMS

JTAG_MCP_TDI

PCIE_WAKE_L

MAKE_BASE=TRUE

MCP_LID_L

TP_MCP_LID_L

=PP3V3_S5_MCP_A01

R2412

1 2

R2411

1 2

R2410

1 2

R2403

1 2

R2402

1 2

R2401

1 2

R2400

1 2

R2404

1 2

R2413

1 2

R2405

1 2

44

8

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

5 mA (A01)

MCP SATA (DVDD) Power

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) Apple: 4x 2.2uF 0402 (8.8 uF)

1182 mA (A01)

7 mA (A01)

19 mA (A01)

333 mA (A01)

4771 mA (A01, DDR3)

MCP Core Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Power

MCP Memory Power

MCP FSB (VTT) Power

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 7x 2.2uF 0402 (15.4 uF)

Apple: 5x 2.2uF 0402 (11 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 1.05V AUX Power

5 mA (A01)

MCP 3.3V/1.5V HDA Power

266 mA (A01)

MCP 3.3V AUX/USB Power

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP79 Ethernet VRef

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Ethernet Power

MCP 1.05V RMGT Power

(No IG vs. EG data)

23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

MCP PCIE (DVDD) Power

105 mA (A01) 131 mA (A01)

83 mA (A01)

84 mA (A01)

87 mA (A01)

37 mA (A01)

206 mA (A01)

127 mA (A01)

43 mA (A01)57 mA (A01)

450 mA (A01)

19 mA (A01)

562 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF)

270 mA (A01)

402

X5R

20%

4.7UF

4V

402

X5R

4V

4.7UF

20%

402

X5R

4V

20%

4.7UF

402

X5R

20%

4.7UF

4V

6.3V

2.2UF

20% 402-LF

CERM

402

X5R

20%

4V

4.7UF

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

10V 402

20% CERM

0.1UF

10V 402

20% CERM

0.1UF

10V 402

20% CERM

0.1UF

10V 402

20% CERM

0.1UF

10V 402

20% CERM

0.1UF

10V 402

20% CERM

0.1UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

6.3V

2.2UF

20%

CERM 402-LF

20%

2.2UF

6.3V

10V

10%

1UF

402-1

X5R

10V

10%

1UF

402-1

X5R

402

X5R

20%

4V

4.7UF

CERM 402-LF

20%

2.2UF

6.3V

402

X5R

20%

4.7UF

4V

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

402-LF

CERMCERM

402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

20%

6.3V

2.2UF

CERM 402-LF

20%

2.2UF

6.3V

10V 402

CERM

20%

0.1UF

10V 402

CERM

20%

0.1UF

10V 402

CERM

20%

0.1UF

10V 402

CERM

20%

0.1UF

10V 402

CERM

20%

0.1UF

10V 402

CERM

20%

0.1UF

10V 402

CERM

20%

0.1UF

10V 402

0.1UF

CERM

20%

10V 402

20% CERM

0.1UF

402

X5R

4V

4.7UF

20%

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

402

X5R

4V

20%

4.7UF

30-OHM-5A

0603

30-OHM-5A

0402

30-OHM-1.7A

0402

30-OHM-1.7A

0402

30-OHM-1.7A

0402

30-OHM-1.7A

0402

402

20%

4V

4.7UF

402

X5R

20%

4V

4.7UF

10V 402

0.1uF

20% CERM

10V 402

0.1uF

20% CERM

CERM 402-LF

20%

2.2UF

6.3V

10V 402

20%

0.1UF

CERM

10V 402

20%

0.1UF

CERM

402

X5R

4V

4.7UF

20%

0402

30-OHM-1.7A

402

MF-LF

1%

1/16W

1.47K

10V 402

20% CERM

0.1UF

402

1.47K

1/16W

1%

MF-LF

18

10V 402

0.1uF

20% CERM

10V 402

CERM

20%

0.1uF

10V 402

20% CERM

0.1uF

10V 402

20%

0.1UF

CERM

10V 402

0.1UF

CERM

20%

10V 402

0.1UF

CERM

20%

10V 402

0.1UF

20% CERM

10V 402

0.1uF

20% CERM

402

X5R

4V

4.7uF

20%

402

X5R

20%

4V

4.7UF

96

051-7546

A.0.0

24

MCP Standard Decoupling

SYNC_MASTER=T18_MLB

SYNC_DATE=06/18/2008

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_NV

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_SATA_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PEX_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_USB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_PEX

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_ENET_MCP_PLL_MAC

=PP1V05_ENET_MCP_PLL_MAC

=PP3V3_ENET_MCP_RMGT

MCP_MII_VREF

=PP3V3_S0_MCP

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S5_MCP

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_FSB

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_ENET_MCP_RMGT

=PP3V3_S0_MCP_PLL_UF

=PPVCORE_S0_MCP

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_PLL_UF

6.3V

20%

VOLTAGE=1.05V

20% CERM

6.3V 402-LF

2.2UF

X5R

6.3V

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

PP1V05_S0_MCP_PLL_FSB

0603

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

402-HF

MF

1/6W

0.2

1%

C2503

1

2

C2582

1

2

C2588

1

2

C2584

1

2

C2586

1

2

C2555

1

2

C2502

1

2

C2507

1

2

C2506

1

2

C2505

1

2

C2504

1

2

C2511

1

2

C2510

1

2

C2509

1

2

C2508

1

2

C2513

1

2

C2512

1

2

C2536

1

2

C2535

1

2

C2534

1

2

C2533

1

2

C2532

1

2

C2531

1

2

C2530

1

2

C2517

1

2

C2516

1

2

C2515

1

2

C2572

1

2

C2571

1

2

C2520

1

2

C2570

1

2

C2574

1

2

C2573

1

2

C2576

1

2

C2575

1

2

C2553

1

2

C2552

1

2

C2551

1

2

C2550

1

2

C2549

1

2

C2548

1

2

C2547

1

2

C2546

1

2

C2545

1

2

C2544

1

2

C2543

1

2

C2542

1

2

C2541

1

2

C2540

1

2

C2562

1

2

C2564

1

2

C2580

1

2

L2570

1 2

L2575

1 2

L2582

1 2

L2584

1 2

L2588

1 2

L2586

1 2

L2555

1 2

C2500

1

2

C2501

1

2

C2526

1

2

C2525

1

2

C2560

1

2

C2589

1

2

C2590

1

2

C2595

1

2

L2595

1 2

R2590

1

2

C2591

1

2

R2591

1

2

C2521

1

2

C2518

1

2

C2519

1

2

C2581

1

2

C2583

1

2

C2585

1

2

C2587

1

2

C2596

1

2

C2529

1

2

C2528

1

2

R2580

1 2

22

24

22

14

46

24

18

21

22

9

16

22 18

22

18

21

16

8

20

17

20

14

18

8

8 8

8

8 8

8

A2

A1

SCL

A0

VCC

SDA

WP

GND

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

206 mA (A01)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

206 mA (A01)

Apple: 2x 2.2uF 0402 (4.4 uF)

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: ???

HDCP ROM

16 mA (A01)

190 mA (A01, 1.8V)

WF: Open question on which packge option(s) nVidia can support.

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

95 mA (A01)

6.3V CERM 402-LF

NO STUFF

2.2UF

20%

NO STUFF

30-OHM-1.7A

0402

NO STUFF

20%

0.1UF

402

10V

NO STUFF

402

1K

1% 1/16W MF-LF

0.1UF

20%

402

CERM

NO STUFF

10V

20%

4.7UF

4V

402

X5R

CERM

4.7UF

6.3V

20% 603

30-OHM-1.7A

0402

20% 402

CERM

10V

0.1uF

OMIT

SOIC

AT24C08

402

10V

0.1UF

20%

CERM

10K

MF-LF

5%

1/16W

402

45

402

MF-LF

1/16W

5%

0

MF-LF

1K

1% 1/16W

CERM 402-LF

20%

2.2UF

6.3V

SYNC_DATE=06/18/2008

SYNC_MASTER=AMASON_M98_MLB

MCP Graphics Support

25 96

A.0.0

051-7546

TP_MCP_RGB_RED TP_MCP_RGB_GREEN

CRT_IG_B_COMP_PB

MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MCP_IFPAB_VPROBE

MCP_TV_DAC_RSET MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

TP_MCP_RGB_DAC_VREF

=PP3V3_S0_MCP_DAC_UF

MCP_HDMI_VPROBE

HDCPROM_WP

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_VPLL

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNCTP_MCP_RGB_HSYNC

TP_MCP_RGB_VSYNC

TP_MCP_RGB_BLUE

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

MAKE_BASE=TRUE

NC_MCP_RGB_RED

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

CRT_IG_R_C_PR

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

TP_MCP_RGB_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

CRT_IG_VSYNC

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

CRT_IG_HSYNC

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

CRT_IG_G_Y_Y

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDD

=PP3V3_S0_MCP_VPLL_UF

=I2C_HDCPROM_SDA =I2C_HDCPROM_SCL

=PP3V3_S0_HDCPROM

MCP_IFPAB_RSET

CERM

402

MCP_HDMI_RSET

CERM

20%

2.2UF

402-LF

6.3V

R2620

1

2

C2610

1

2

C2650

1

2

L2650

1 2

C2620

1

2

R2630

1

2

C2630

1

2

C2615

1

2

C2640

1

2

L2640

1 2

C2641

1

2

C2616

1

2

U2695

1 2 3

4

6

5

8

7

C2690

1

2

R2690

1

2

R2651

1

2

89

18

89 89

18

8

18

8

18

8

18

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

OUTY

B

A

VIN

GND

VOUTEN

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

but results in MCP79 ROMSIP sequence happening after CPU powers up.

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

Reset Button

10K pull-up to 3.3V S0 inside MCP

LPC Reset (Unbuffered)

Platform Reset Connections

PCIE Reset (Unbuffered)

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for

MCP S0 PWRGD & CPU_VLD

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,

MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization.

RTC Crystal

RTC Power Sources

MCP 25MHz Crystal

10 13 21 23

5%

CERM

402

12pF

50V

5%

50V

CERM

402

12pF

402

1/16W

0

5%

MF-LF

1/16W MF-LF

5%

402

10M

NO STUFF

19 83 90

402

0

5%

MF-LF

1/16W

XDP

PLACEMENT_NOTE=Place close to U1400

33

MF-LF

5%

1/16W

402

33

5% 1/16W MF-LF

PLACEMENT_NOTE=Place close to U1400

402

MF-LF

402

1/16W

5%

0

402

MF-LF

1/16W

5%

0

OMIT

SILK_PART=FP SYS RESET

44

42

21

9

17

PLACEMENT_NOTE=Place close to U1400

33

5%

MF-LF

1/16W

402

5%

33

MF-LF

1/16W

PLACEMENT_NOTE=Place close to U1400

402

19 90

12pF

402

CERM

5%

50V

12pF

5%

CERM

402

CRITICAL

25.0000M

SM-3.2X2.5MM

402

5%

MF-LF

1/16W

0

1M

5%

1/16W

402

MF-LF

NO STUFF

21

42 90

PLACEMENT_NOTE=Place close to U1400

402

MF-LF

5% 1/16W

22

21 90

1/16W

5%

MF-LF

33

402

10V X5R

10%

1UF

NO STUFF

36

MF-LF

1/16W

5%

0

402

9

33

402

5% 1/16W MF-LF

19

42

44 90

42 90

CRITICAL

32.768K

7X1.5X1.4-SM

0

5% 1/16W MF-LF

402

27

402

MF-LF

1/16W

5%

0

85

402

MF-LF

1/16W

5%

0

32

31

1/16W

0

402

5%

MF-LF

33

MF-LF

402

1/16W

5%

PLACEMENT_NOTE=Place close to U1400

83

21

62

42 68

402

0

1/16W

5%

MF-LF

MCPSEQ_MIX

20%

MCPSEQ_SMC

10V CERM 402

0.1UF

PLACEMENT_NOTE=Place close to U1400

402

0

1/16W MF-LF

5%

MCPSEQ_SMC

21

MF-LF

5%

1/16W

0

402

MCPSEQ_SMC

21

MF-LF

5%

1/16W

0

402

MCPSEQ_MIX

MCPSEQ_SMC

TC7SZ08AFEAPE

SOT665

1UF

10% 10V X5R 402

TSOT-23-5

MIC5232-2.8YD5

10

5%

402

1/16W MF-LF

1.0M

5%

NO STUFF

1/10W

603

MF-LF

6.3V

10% 402

CERM

1UF

2%

0.08F

XHHG SM

3.3V

100

5% 1/16W MF-LF 402

051-7546

26

A.0.0

96

SB Misc

SYNC_MASTER=T18_MLB

SYNC_DATE=12/17/2007

PCIE_RESET_L

VR_PWRGOOD_DELAY

S0_AND_IMVP_PGOOD

ALL_SYS_PWRGD

XDP_DBRESET_L

PM_SYSRST_DEBOUNCE_L

PM_SYSRST_L

LPC_RESET_L

DEBUG_RESET_L

SMC_LRESET_L

LPC_CLK33M_LPCPLUS

LPC_CLK33M_SMC

PM_CLK32K_SUSCLK

LPC_CLK33M_GMUX

MEM_VTT_EN

MINI_RESET_L

EXCARD_RESET_L

BKLT_PLT_RST_L

FW_RESET_L

PCA9557D_RESET_L

LPC_CLK33M_SMC_R

MEM_VTT_EN_R

PM_CLK32K_SUSCLK_R

MAKE_BASE=TRUE

GMUX_PCIE_RESET_L

=GMUX_PCIE_RESET_L

MCP_CPUVDD_EN

MCP_CPU_VLD

MCP_PS_PWRGD

=PP3V3_S5_MCPPWRGD

PP3V3_G3_SUPERCAP

RTC_DISCHARGE_R

MCP_CLK25M_XTALOUT_R

PP3V3_G3_RTC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm VOLTAGE=3.3V

=PP3V3_S5_RTC_D

RTC_CLK32K_XTALOUT_R

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALIN

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

C2810

1 2

C2811

1 2

R2810

1 2

R2811

1

2

R2896

1 2

R2883

1 2

R2881

1 2

R2890

1 2

R2897

1

2

R2826

1 2

R2825

1 2

C2815

1 2

C2816

1 2

Y2815

2 4

1 3

R2815

1 2

R2816

1

2

R2829

1 2

R2899

1 2

C2899

1

2

R2892

1 2

R2870

1 2

Y2810

1 4

R2891

1 2

R2893

1 2

R2895

1 2

R2894

1 2

R2827

1 2

R2851

1 2

C2850

1

2

R2850

1 2

R2853

1 2

R2852

1 2

U2850

C2802

1

2

U2801

3

2

4

1

5

R2801

1

2

R2802

12

C2801

1

2

C2800

1

2

R2800

1

2

22 8 21

8

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

MEM B VREF DQMEM A VREF DQ

(per DAC LSB)

Signal aliases required by this page:

NO_VREFMRGN

VREFMRGN

- =I2C_PCA9557D_SDA

- =I2C_PCA9557D_SCL

Required zero ohm resistors when no VREF margining circuit stuffed

Power aliases required by this page:

ADDR=0x30(WR)/0x31(RD)

Place close to J3100.1

ADDR=0x98(WR)/0x99(RD)

- =PP3V3_S3_VREFMRGN

- =PPVTT_S3_DDR_BUF

10mA max load

- =I2C_VREFDACS_SDA

Page Notes

Place close to U1000.AD26

Place close to U8500, U8550

BOM options provided by this page:

- =I2C_VREFDACS_SCL

- =PP3V3_S5_VREFMRGN

CPU FSB VREF

FRAME BUFFER VREF

MEM B VREF CA

Place close to J3200.1

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA

Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF

DAC channel A B A B C D

MEM A VREF CA

Place close to J3100.126

Place close to J3200.126

Place close to U8400, U8450

9

1/16W MF-LF

VREFMRGN

1%

49.9

402

10 87

VREFMRGN

0.1UF

20% 10V

402

CERM

100

402

1%

VREFMRGN

1/16W MF-LF

5%

VREFMRGN

MF-LF

402

1/16W

100K

VREFMRGN

1%

200

1/16W MF-LF

402

MF-LF

1/16W

5%

VREFMRGN

402

100K

9

MF-LF

1/16W

402

49.9

1%

VREFMRGN

UCSP

MAX4253

VREFMRGN

UCSP

VREFMRGN

MAX4253

UCSP

VREFMRGN

MAX4253

UCSP

MAX4253

VREFMRGN

UCSP

VREFMRGN

MAX4253

UCSP

MAX4253

VREFMRGN

1%

200

1/16W MF-LF

402

1/16W

402

200

1%

MF-LF

VREFMRGN

1%

200

1/16W MF-LF

402

VREFMRGN

5%

100K

1/16W MF-LF

402

VREFMRGN

100K

1/16W

5%

402

MF-LF

VREFMRGN

402

100

1% 1/16W MF-LF

VREFMRGN

MF-LF

402

1% 1/16W

100

VREFMRGN

402

MF-LF

1/16W

1%

100

VREFMRGN

MF-LF

VREFMRGN

402

1/16W

100K

5%

PCA9557

VREFMRGN

QFN

VREFMRGN

402

0.1UF

20% CERM

10V

402

100

MF-LF

1% 1/16W

VREFMRGN

5%

402

1/16W

100K

MF-LF

VREFMRGN

26

45

DAC5574

MSOP

VREFMRGN

45

10V 402

VREFMRGN

0.1UF

CERM

20%

2.2UF

CERM

6.3V

20%

VREFMRGN

402-LF

VREFMRGN

20% CERM

402

10V

0.1UF

CERM

0.1UF

VREFMRGN

402

20% 10V

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=DDR

051-7546

A.0.0

9627

SYNC_DATE=07/22/2008

1 R2909 CRITICAL

NO_VREFMRGN

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL1 R2911

NO_VREFMRGN

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

R2903 CRITICAL

NO_VREFMRGN

1116S0004

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL1 R2905

NO_VREFMRGN

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

=PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CPUFSB_EN

VREFMRGN_CPUFSB_BUF

VREFMRGN_FRAMEBUF_EN

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMM

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_FRAMEBUF_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CPUFSB_EN

=I2C_VREFDACS_SDA

PCA9557D_RESET_L

VREFMRGN_DQ_SODIMMA_EN

=I2C_VREFDACS_SCL

VREFMRGN_CA_SODIMMB_EN

CPU_GTLREF

GPU_FB_B_VREF_DIV

GPU_FB_A_VREF_DIV

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

=PP3V3_S3_VREFMRGN

VREFMRGN_CPUFSB

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMB_BUF

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

MIN_NECK_WIDTH=0.2 mm

U2901

3 4 5

8

6 7 9 10 11 12 13 14

15

1 2

17

16

C2903

1

2

C2902

1

2

R2902

1 2

R2901

1 2

R2904

1 2

R2906

1 2

R2910

1 2

R2907

1 2

C2904

1

2

R2912

1 2

R2908

1 2

U2900

9

10

3

6

7

8

1

2

4

5

C2901

1

2

C2900

1

2

C2905

1

2

R2916

1 2

R2914

1 2

R2913

1 2

R2903

1 2

R2915

1 2

R2917

1 2

U2902

C3

C2

C1

C4

B1

B4

U2903

A3

A2

A1

A4

B1

B4

U2902

A3

A2

A1

A4

B1

B4

U2903

C3

C2

C1

C4

B1

B4

U2904

A3

A2

A1

A4

B1

B4

U2904

C3

C2

C1

C4

B1

B4

R2905

1 2

R2909

1 2

R2911

1 2

64

8

28

27

8

28

29

A6

A7

A11

A5

DQ33

VDD A10/AP

VDD

VSS

SA1 VTT

VSS

DQS4* DQS4 VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43 VSS

DM5 VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0 VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI BI

IN

BI

IN

BI BI

BI

IN

BI BI

BI

OUT

BI IN

IN

IN IN

BI BI

BI

IN

BI

BI BI

IN

BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(NONE)

BOM options provided by this page:

- =PP1V5_S3_MEM_A

- =I2C_SODIMMA_SCL

- =PP0V75_S0_MEM_VTT_A

Power aliases required by this page:

- =I2C_SODIMMA_SDA

"Factory" (top) slot

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

Signal aliases required by this page:

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP1V5_S0_MEM_A

SPD ADDR=0xA0(WR)/0xA1(RD)

Page Notes

516-0196

DDR3-SODIMM-DUAL-M97-3

F-RT-THB

15 88

0.1UF

CERM 402

20% 10V

6.3V CERM 402-LF

20%

2.2UF

15 88

29 30

15 88

DDR3-SODIMM-DUAL-M97-3

CRITICAL

F-RT-THB

15 88

9

15 88

10V

20%

402

CERM

0.1UF

402-LF

20%

6.3V

2.2UF

CERM

15 88

21 29 42

45

15 88

10K

5%

402

1/16W MF-LF

10K

MF-LF

1/16W

5%

402

2.2UF

20%

CERM 402-LF

6.3V

10UF

20% X5R

6.3V 603

6.3V

10UF

X5R 603

20%

CERM 402

10V

20%

0.1UF 0.1UF

402

CERM

10V

20%

CERM

0.1UF

20% 10V

402

CERM 402

0.1UF

10V

20%

10V

0.1UF

402

CERM

20%

0.1UF

20%

402

CERM

10V 10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

20%

402

CERM

0.1UF

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CERM

SYNC_MASTER=DDR

SYNC_DATE=07/22/2008

DDR3 SO-DIMM Connector A

051-7546

A.0.0

9628

MEM_A_BA<2>

MEM_A_DQ<60>

MEM_A_DQ<58> MEM_A_DQ<59>

MEM_A_SA<0>

=PP1V5_S0_MEM_A

MEM_A_DQ<3> MEM_A_DQ<2>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DM<0>

MEM_A_DQ<13>

MEM_A_DQ<9>

MEM_A_DQS_N<1> MEM_A_DQS_P<1>

MEM_A_DQ<11> MEM_A_DQ<14>

MEM_A_DQ<18>

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

MEM_A_DQ<23> MEM_A_DQ<19>

MEM_A_DQ<30>

MEM_A_DQ<24>

MEM_A_DQ<5>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

MEM_A_DQ<6> MEM_A_DQ<7>

MEM_A_DQ<8> MEM_A_DQ<12>

MEM_A_DM<1> MEM_RESET_L

MEM_A_DQ<15> MEM_A_DQ<10>

MEM_A_DQ<21> MEM_A_DQ<20>

MEM_A_DM<2>

MEM_A_DQ<17> MEM_A_DQ<22>

MEM_A_DQ<29> MEM_A_DQ<28>

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MEM_A_DQ<26> MEM_A_DQ<31>

MEM_A_DQ<4>

MEM_A_DM<3>

MEM_A_DQ<16>

=PPSPD_S0_MEM_A

MEM_A_CKE<1>

MEM_A_A<15> MEM_A_A<14>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_CLK_N<1>

MEM_A_RAS_L

MEM_A_ODT<0>

MEM_A_ODT<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<36> MEM_A_DQ<37>

MEM_A_DM<4>

MEM_A_DQ<38> MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<47>

MEM_A_DQS_N<5>

MEM_A_CKE<0>

MEM_A_A<12> MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<3> MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_BA<0>

MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<13> MEM_A_CS_L<1>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<44> MEM_A_DQ<41>

MEM_A_DQ<46>

MEM_A_DQS_P<5>

MEM_A_DQ<43>

MEM_A_DQ<48> MEM_A_DQ<53>

MEM_A_DM<6>

MEM_A_DQ<50> MEM_A_DQ<49>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_EVENT_L

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

MEM_A_DQ<45>

MEM_A_DM<5>

MEM_A_DQ<42>

MEM_A_DQ<52> MEM_A_DQ<51>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<61>

MEM_A_DM<7>

MEM_A_CLK_N<0>

MEM_A_DQ<35>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

=PP0V75_S0_MEM_VTT_A

MEM_A_SA<1>

MEM_A_A<10>

MEM_A_DQ<32>

MEM_A_A<5>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<6>

MEM_A_DQ<27> MEM_A_DQ<25>

=PP1V5_S3_MEM_A

MEM_A_CS_L<0>

MEM_A_BA<1>

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

C3131

1

2

C3130

1

2

J3100

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

C3136

1

2

C3135

1

2

R3141

1

2

R3140

1

2

C3140

1

2

C3100

1

2

C3101

1

2

C3110

1

2

C3111

1

2

C3112

1

2

C3113

1

2

C3114

1

2

C3115

1

2

C3116

1

2

C3117

1

2

C3118

1

2

C3119

1

2

C3120

1

2

C3121

1

2

C3122

1

2

C3123

1

2

8

27

8

27

8

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

IN

BI BI

IN

BI BI

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

IN

BI BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

Power aliases required by this page:

Signal aliases required by this page:

(NONE)

"Expansion" (bottom) slot

- =PP1V5_S0_MEM_B

SPD ADDR=0xA2(WR)/0xA3(RD)

516s0704

Page Notes

BOM options provided by this page:

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =PP0V75_S0_MEM_VTT_B

- =PP1V5_S3_MEM_B

15 88

21 28 42

45

10V

20%

402

CERM

0.1UF

15 88

CERM 402-LF

6.3V

20%

2.2UF

10K

1/16W MF-LF

5%

402

10K

5%

402

MF-LF

1/16W

2.2UF

6.3V

402-LF

CERM

20%

603

6.3V X5R

20%

10UF

20%

603

X5R

10UF

6.3V

0.1UF

20% 10V

402

CERM

20% 10V CERM 402

0.1UF

402

10V

20%

0.1UF

CERM

20% 10V

0.1UF

402

CERM

15 88

20% CERM

402

0.1UF

10V 10V

CERM 402

20%

0.1UF

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

0.1UF

CERM 402

20% 10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

CERM 402

20%

0.1UF

10V

15 88

DDR3-SODIMM

F-RT-BGA3

15 88

28 30

15 88

CRITICAL

DDR3-SODIMM

F-RT-BGA3

15 88

9

15 88

CERM

0.1UF

20%

402

10V

2.2UF

6.3V CERM

20%

402-LF

15 88

SYNC_MASTER=DDR

29 96

A.0.0

051-7546

SYNC_DATE=07/22/2008

DDR3 SO-DIMM Connector B

=PP1V5_S0_MEM_B

MEM_B_DQ<9>

MEM_B_DQ<18> MEM_B_DQ<22>

MEM_B_DQ<4>

MEM_B_DQ<23>

MEM_B_DQ<19>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQ<16>

MEM_B_DQ<20>

MEM_B_DQ<11>

MEM_B_DQ<14>

MEM_B_DM<1>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_RESET_L

MEM_B_DM<3>

MEM_B_DQ<25>

MEM_B_DQ<29>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQ<5>

MEM_B_DQ<21> MEM_B_DQ<17>

MEM_B_DQ<10>

MEM_B_DQ<15>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQ<8>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQ<28>

MEM_B_DM<0>

MEM_B_DQ<0> MEM_B_DQ<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQ<3>

MEM_B_DQ<2>

=PPSPD_S0_MEM_B

MEM_B_DQ<59>

MEM_B_DQ<63>

MEM_B_SA<0>

MEM_B_SA<1>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DM<7>

MEM_B_CAS_L

MEM_B_DQS_P<4>

MEM_B_DQ<35>

MEM_B_CLK_N<0>

MEM_B_A<10>

MEM_B_DQ<52> MEM_B_DQ<51>

MEM_B_DQS_N<6> MEM_B_DQS_P<6>

=I2C_SODIMMB_SDA =I2C_SODIMMB_SCL

=PP0V75_S0_MEM_VTT_B

MEM_EVENT_L

MEM_B_DQ<58>

MEM_B_DQS_N<7> MEM_B_DQS_P<7>

MEM_B_DQ<60> MEM_B_DQ<61>

MEM_B_DQ<50>

MEM_B_DQ<53>

MEM_B_DM<6>

MEM_B_DQ<54>

MEM_B_DQ<48>

MEM_B_DQ<46>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<41>

MEM_B_DQ<34>

MEM_B_DQ<32> MEM_B_DQ<37>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_WE_L

MEM_B_BA<0>

MEM_B_CLK_P<0>

MEM_B_BA<2>

MEM_B_DQS_N<5>

MEM_B_DQ<44> MEM_B_DQ<45>

MEM_B_DQ<39>

MEM_B_DM<4>

MEM_B_DQ<36>

MEM_B_DQ<33>

PP0V75_S3_MEM_VREFCA_B

MEM_B_ODT<1>

MEM_B_CS_L<0> MEM_B_ODT<0>

MEM_B_BA<1> MEM_B_RAS_L

MEM_B_A<0>

MEM_B_CLK_P<1>

MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

MEM_B_DM<5>

MEM_B_DQS_N<4>

MEM_B_DQ<40>

MEM_B_DQ<55>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8> MEM_B_A<5>

MEM_B_A<3> MEM_B_A<1>

=PP1V5_S3_MEM_B

MEM_B_CKE<0>

MEM_B_DQ<24>

MEM_B_DQ<38>

MEM_B_DQ<49>

MEM_B_DQ<62>

MEM_B_DM<2>

MEM_B_CLK_N<1>

J3200

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206 207 208 209 210 211 212

203 204

113

C3231

1

2

C3230

1

2

J3200

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

C3236

1

2

C3235

1

2

R3241

1

2

R3240

1

2

C3240

1

2

C3200

1

2

C3201

1

2

C3210

1

2

C3211

1

2

C3212

1

2

C3213

1

2

C3214

1

2

C3215

1

2

C3216

1

2

C3217

1

2

C3218

1

2

C3219

1

2

C3220

1

2

C3221

1

2

C3222

1

2

C3223

1

2

8

27

8

27

8

Apple 15MLB User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual