Anritsu MP1632C Data Sheet

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PULSE PATTERN GENERAT ORS/ERROR DETECTORS

2

For Development, Manufacturing and Inspection of Transmission Systems, Optical Modules and Logic Devices

DIGITAL DATA ANALYZER

MP1632C

50 MHz to 3.2 GHz

Core networks and computer networks are increasing rapidly as the
volume of data transmitted in this multimedia data is growing. In ad­dition to the STM-16/OC-48 (2.488 Gbit/s), Fibre channel, Giga-bit
Ethernet, etc. are being commercialized. Compact and high perfor­mance digital data analyzer are required for inspecting products like
digital transmission systems, optical modules, and logic devices.
The MP1632C realizes a compact solution that incorporates former
measuring equipment (MP1652A Pulse Pattern Generator and
MP1653A Error Detector) into a case.
MX163201A TEXT to MP1632A/C Pattern Conversion Software,
MX163202A MP165X to MP1632A/C Pattern Conversion Software,
MX163205A Q and Eye Analysis Software, and MX163206A SDH/
SONET Pattern Editor are available as application software.

Features

•

3.2 Gb/s PPG and ED in a case

•

Eye diagram measurement and burst signal measurement supported

Performance and functions

•

Easy operation

The MP1632C has a large, color LCD with touch screen. Microsoft
Windows®operating system version 3.1 displays measurement re­sults graphically. Customized screens enable one-key and one-para­meter operation.

•

High-quality pulse pattern generator

Programmable patterns of 8 Mbit max, PRBS patterns [(27– 1) to
(2

31

– 1) with variable mark ratio], and zero substitution patterns can
be generated. Variable cross-point of data output waveform is also
supported.

H: 100 ps/div, V: 1 V/div
MU163220C output waveform (3.2 GHz)

•

Error detector with many functions

High input sensitivity (25 mVp-p∗) and wide phase margin (250 ps∗)
performance is provided. The autosearch function enables PRBS
pattern search with usual phase and threshold search. Insertion er­ror and omission error can be measured simultaneously.

∗Typical values at 3 Gb/s, PRBS 2

23

– 1

•

Internal synthesizer with high signal purity (Option)

Highly pure signals, SSB phase noise characteristics of –85 dBc/Hz
or less (10 kHz offset), is generated.

•

Support of various applications

The MP1632C supports testing of SDH/SONET (STM-0, 1, 4, 16/
OC-1, 3, 12, 48) devices and modules, research and dev elopment on
WDM components, Fibre channels, Giga-bit Ethernet, evaluation of
E/O and O/E module, GaAs IC, and high-speed ASIC/FPGAs

DATA

Clock

GPIB

OPTION

PULSE PATTERN GENERAT ORS/ERROR DETECTORS

124 For product ordering information, see pages 3 – 6

Specifications

•

MU163220C 3.2G Pulse Pattern Generator

Operating frequency 10 MHz to 3.2 GHz (50 MHz to 3.2 GHz when using MP1632C-03 3.2G Internal Synthesizer)
External clock input 0.5 to 2 Vp-p (<0.5 GHz: square wave, ≥0.5 GHz: square wave or sine wave, 50% duty cycle)

Pseudo random pattern (PRBS)

Pattern length: 2

n

– 1 (n: 7, 9, 11, 15, 20, 23, 31)

Mark ratio: 1/2, 1/4, 1/8, 0/8, 1/2, 3/4, 7/8, 8/8
AND bit shift upon mark ratio setting: 1, 3 bits

Data pattern

Generation pattern

Data length: 2 to 8,338,608 bits

Zero substitution pattern

Continuous 0 bit length: 1 to (pattern length – 1) bits
Pattern length: 2

n

(n: 7, 9, 11, 15)

Error insertion

Error ratio: 10

–n

(n: 3, 4, 5, 6, 7, 8, 9), single error

External error input: Provided

Number of outputs: 2 (DATA/DATA, independent)
Amplitude: 0.5 to 2 Vp-p (10 mV steps, setting error: ±15% or ±0.1 V, whichever is greater)
Offset voltage

V

OH

: –2 to +2 V (at 2 Vp-p amplitude), –3.5 to +2 V (at 0.5 Vp-p amplitude)
(5 mV steps, setting error: ±15% of offset voltage, ±0.1 V or ±15% of amplitude, whichever is the greatest)
Display: V

OH

, VTH, and VOLselectable

Data output Rise/fall time: ≤80 ps (10% to 90% of amplitude)

Pattern jitter: ≤30 psp-p
Waveform distortion: 10% or 0.1 V of amplitude, whichever is greater
Load impedance: 50 Ω (with back termination)
Connector: SMA

DATA/DATA tracking: DATA amplitude and offset voltage can be set to same value as DATA.
Crosspoint adjustment function: Provided

Number of output: 2 (CLOCK/CLOCK, independent)
Amplitude: 0.5 to 2 Vp-p (10 mV steps, setting error: ±15% or ±0.1 V, whichever is greater)
Offset voltage

V

OH

: –2 to +2 V (at 2 Vp-p amplitude), –3.5 to +2 V (at 0.5 Vp-p amplitude)

(5 mV steps, setting error: ±15% of offset voltage, ±0.1 V or ±15% of amplitude, whichever is the greatest)

Clock output

Display: V

OH

, VTH, and VOLselectable
Rise/fall time: ≤80 ps (10% to 90% of amplitude)
Load impedance: 50 Ω (with back termination)
Connector: SMA
Clock delay: –1 to +1 ns (2 ps steps)

External burst trigger input

Input level: 0/–1 V, connector: SMA

Internal burst signal Burst cycle: 2 µs to 50 ms (1 µs steps), Enable length: 1 µs to 49.999 ms (1 µs steps)
Burst trigger output Output level: 0/–1 V, connector: SMA
Sync signal output Number of outputs: 1 (1/8 clock, variable pattern synchronization output selectable), Output level: 0/–1 V, Connector: SMA
Operating temperature +5 to +45˚C
Power ≤200 VA
Dimensions and mass 232 (W) x 49 (H) x 449 (D) mm, ≤4.5 kg

•

MU163240C 3.2G Error Detector

Operating frequency 10 MHz to 3.2 GHz (50 MHz to 3.2 GHz when using MP1632C-03 3.2G Internal Synthesizer)

Input waveform: NRZ
Input voltage: 0.5 to 4 Vp-p

Data input Variable threshold voltage: –4 to +4 V (1 mV steps)

Termination: Connected to GND, –2 V or +3 V via 50 Ω
Connector: SMA

Input waveform: Square wave (<0.5 GHz), square wave or sine wave (≥0.5 GHz), duty: 50%
Input amplitude: 0.5 to 4 Vp-p

Clock input

Variable input delay: –1 to +1 ns (2 ps steps)
Polarity inversion: POS/NEG inversion selectable
Termination: Connected to GND, –2 V or +3 V via 50 Ω
Connector: SMA

Auto search function Phase, threshold, phase & threshold, PRBS patter n (allowed if the mark ratio is between 1/8 and 7/8)

Pseudo random pattern (PRBS)

Pattern length: 2

n

– 1 (n: 7, 9, 11, 15, 20, 23, 31)

Marker ratio: 1/2, 1/4, 1/8, 0/8, 1/2, 3/4, 7/8, 8/8
AND bit shift upon mark ratio setting: 1, 3 bits

Receive pattern Data pattern

Data length: 2 to 8,338,608 bits

Zero substitution pattern

Continuous 0 bit length: 1 to (pattern length – 1) bits
Pattern length: 2

n

(n: 7, 9, 11, 15)
Sync mode Normal, frame
Sync threshold AUTO or 10–n(n: 2, 3, 4, 5, 6, 7, 8)
Error detection mode Omission, insertion, total

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