ANALOG DEVICES AD5623R, AD5643R, AD5663R Service Manual

5 ppm/°C On-Chip Reference

AD5623R/AD5643R/AD5663R

Rev. E

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2006–2012 Analog Devices, Inc. All rights reserved.

INTERFACE

LOGIC

SCLK

SYNC

DIN

CLR

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

V

DD

GND

POWER-ON

RESET

STRING

DAC A

STRING

DAC B

BUFFER

BUFFER

V

REFIN/VREFOUT

POWER-DOWN

LOGIC

V

OUT

A

V

OUT

B

AD5623R/AD5643R/AD5663R

LDAC

LDAC

05858-001

1.25V/2.5V

REFERENCE

Data Sheet

FEATURES

Low power, smallest pin-compatible, dual nanoDAC

AD5663R: 16 bits
AD5643R: 14 bits
AD5623R: 12 bits

User-selectable external or internal reference

External reference default
On-chip 1.25 V/2.5 V, 5 ppm/°C reference

10-lead MSOP and 3 mm × 3 mm LFCSP

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
Serial interface up to 50 MHz
Hardware

LDAC

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

and

CLR

functions

Dual 12-/14-/16-Bit nanoDAC® with

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Table 1. Related Devices

Part No. Description

AD5663 2.7 V to 5.5 V, dual 16-bit nanoDAC, with external

reference

GENERAL DESCRIPTION

The AD5623R/AD5643R/AD5663R, members of the nanoDAC
family, are low power, dual 12-, 14-, and 16-bit buffered voltage­out digital-to-analog converters (DAC) that operate from a single

2.7 V to 5.5 V supply and are guaranteed monotonic by design.

The AD5623R/AD5643R/AD5663R have an on-chip reference.
The AD5623R-3/AD5643R-3/AD5663R-3 have a 1.25 V, 5 ppm/°C
reference, giving a full-scale output of 2.5 V; and the AD5623R-5/
AD5643R-5/AD5663R-5 have a 2.5 V, 5 ppm/°C reference,
giving a full-scale output of 5 V. The on-chip reference is off at
power-up, allowing the use of an external reference; and all
devices can be operated from a single 2.7 V to 5.5 V supply.
The internal reference is turned on by writing to the DAC.

The parts incorporate a power-on reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place. The part contains a power-down feature that
reduces the current consumption of the device to 480 nA at 5 V
and provides software-selectable output loads while in power­down mode.

Information furnishe d by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

The low power consumption of this part in normal operation
makes it ideally suited to portable, battery-operated equipment.

The AD5623R/AD5643R/AD5663R use a versatile, 3-wire serial
interface that operates at clock rates up to 50 MHz, and they are
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The on-chip precision output amplifier
enables rail-to-rail output swing to be achieved.

PRODUCT HIGHLIGHTS

1. Dual 12-, 14-, and 16-bit DAC.

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 10-lead MSOP and 10-lead, 3 mm ×

3 mm LFCSP.

4. Low power; typically consumes 0.6 mW at 3 V and

1.25 mW at 5 V.

5. 4.5 µs maximum settling time for the AD5623R.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD5623R/AD5643R/AD5663R Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Output Amplifier ........................................................................ 20

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AD5623R-5/AD5643R-5/AD5663R-5 ....................................... 3

AD5623R-3/AD5643R-3/AD5663R-3 ....................................... 5

AC Characteristics ........................................................................ 6

Timing Characteristics ................................................................ 7

Timing Diagram ........................................................................... 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Internal Reference ...................................................................... 20

External Reference ..................................................................... 20

Serial Interface ............................................................................ 20

Input Shift Register .................................................................... 21

SYNC

Interrupt .......................................................................... 21

Power-On Reset .......................................................................... 22

Software Reset ............................................................................. 22

Power-Down Modes .................................................................. 22

LDAC

Function .......................................................................... 23

Internal Reference Setup ........................................................... 24

Microprocessor Interfacing ....................................................... 25

Applications Information .............................................................. 26

Using a Reference as a Power Supply ....................................... 26

Bipolar Operation Using the AD5663R .................................. 26

Using the AD5663R with a Galvanically Isolated Interface . 26

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Digital-to-Analog Section ......................................................... 20

Resistor String ............................................................................. 20

REVISION HISTORY

4/12—Rev. D to Rev. C

Changes to Table 2 ............................................................................ 3

Updated Outline Dimensions ....................................................... 28

Changes to Ordering Guide .......................................................... 29

4/11—Rev. C to Rev. D

Changes to Ordering Guide .......................................................... 29

6/10—Rev. B to Rev. C

Changes to Ordering Guide .......................................................... 28

Power Supply Bypassing and Grounding ................................ 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 29

4/10—Rev. A to Rev. B

Updated Outline Dimensions ....................................................... 28

12/06—Rev. 0 to Rev. A

Changes to Table 2 ............................................................................. 3

Changes to Table 3 ............................................................................. 5

Changes to Figure 3 ........................................................................... 9

Changes to Ordering Guide .......................................................... 28

4/06—Revision 0: Initial Version

Rev. E | Page 2 of 32

Data Sheet AD5623R/AD5643R/AD5663R

AD5663R

DC Crosstalk (External Reference)

10

10 µV

Due to full-scale output change;

Power-Up Time

4 4 μs

Coming out of power-down mode;

Reference Input Range

0.75 VDD

0.75 VDD

V

SPECIFICATIONS

AD5623R-5/AD5643R-5/AD5663R-5

VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 2.

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE2

Resolution 16 Bits
Relative Accuracy ±8 ±16 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design

AD5643R

Resolution 14 Bits
Relative Accuracy ±2 ±4 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design

AD5623R

Resolution 12 Bits
Relative Accuracy ±1 ±2 ±0.5 ±1 LSB

Differential Nonlinearity ±1 ±0.25 LSB Guaranteed monotonic by design
Zero-Scale Error +2 +10 +2 +10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 ±1 ±10 mV
Full-Scale Error −0.1 ±1 −0.1 ±1 % of

Gain Error ±1.5 ±1.5 % of

Zero-Scale Error Drift ±2 ±2 µV/°C
Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 −100 dB DAC code = midscale ; VDD = 5 V ±

= VDD; all specifications T

REFIN

FSR

FSR

MIN

to T

unless otherwise noted.

MAX,

All 1s loaded to DAC register

10%

RL = 2 kΩ to GND or V

DD

10 10 µV/mA Due to load current change
5 5 µV Due to powering down (per channel)

DC Crosstalk (Internal Reference) 25 25 µV

Due to full-scale output change;
R

= 2 kΩ to GND or V

L

DD

20 20 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 5 V

VDD = 5 V

REFERENCE INPUTS

Reference Current 170 200 170 200 µA V

= VDD = 5.5 V

REF

Reference Input Impedance 26 26 kΩ

Rev. E | Page 3 of 32

AD5623R/AD5643R/AD5663R Data Sheet

VDD = 4.5 V to 5.5 V

0.25

0.45 0.25

0.45

mA

Internal reference off

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

REFERENCE OUTPUT

Output Voltage 2.495 2.505 2.495 2.505 V At ambient
Reference Temperature Coefficient3 ±10 ±5 ±10 ppm/°C MSOP package models
±10 ±10 ppm/°C LFCSP package models
Output Impedance 7.5 7.5 kΩ

LOGIC INPUTS3

Input Current ±2 ±2 µA All digital inputs
Input Low Voltage (V
Input High Voltage (V
Pin Capacitance 3 3 pF DIN, SCLK, and

19 19 pF

POWER REQUIREMENTS

VDD 4.5 5.5 4.5 5.5 V

IDD (Normal Mode)4 VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 0.8 1 0.8 1 mA Internal reference on
IDD (All Power-Down Modes)5
VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 µA VIH = VDD and VIL = GND

1

Temperature range: A, B grade = −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064).

Output unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

Both DACs powered down.

) 0.8 0.8 V VDD = 5 V

INL

) 2 2 V VDD = 5 V

INH

LDAC

and

CLR

SYNC

Rev. E | Page 4 of 32

Data Sheet AD5623R/AD5643R/AD5663R

Relative Accuracy

±8

±16

LSB

DC Crosstalk (External Reference)

10 µV

Due to full-scale output change;

Reference Input Range

0.75 VDD

V

AD5623R-3/AD5643R-3/AD5663R-3

VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 3.

B Grade1
Parameter Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE2

AD5663R

Resolution 16 Bits

Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5643R

Resolution 14 Bits

Relative Accuracy ±2 ±4 LSB

Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
AD5623R

Resolution 12 Bits

Relative Accuracy ±0.5 ±1 LSB

Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design
Zero-Scale Error +2 +10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 mV
Full-Scale Error −0.1 ±1 % of FSR All 1s loaded to DAC register
Gain Error ±1.5 % of FSR
Zero-Scale Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 3 V ± 10%

= VDD; all specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

RL = 2 kΩ to GND or V

DD

10 µV/mA Due to load current change
5 µV Due to powering down (per channel)

DC Crosstalk (Internal Reference) 25 µV

Due to full-scale output change;

= 2 kΩ to GND or V

R

L

DD

20 µV/mA Due to load current change
10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5 Ω
Short Circuit Current 30 mA VDD = 3 V
Power-Up Time 4 µs Coming out of power-down mode; VDD = 3 V

REFERENCE INPUTS

Reference Current 170 200 µA V

= VDD = 3.6 V

REF

Reference Input Impedance 26 kΩ

REFERENCE OUTPUT

Output Voltage 1.247 1.253 V At ambient
Reference Temperature Coefficient3 ±5 ±15 ppm/°C MSOP package models
±10 ppm/°C LFCSP package models
Output Impedance 7.5 kΩ

Rev. E | Page 5 of 32

AD5623R/AD5643R/AD5663R Data Sheet

Digital Crosstalk

0.1 nV-s

Multiplying Bandwidth

340 kHz

V

= 2 V ± 0.1 V p-p

B Grade1
Parameter Min Typ Max Unit Conditions/Comments

LOGIC INPUTS3

Input Current ±2 µA All digital inputs
V

, Input Low Voltage 0.8 V VDD = 3 V

INL

V

, Input High Voltage 2 V VDD = 3 V

INH

Pin Capacitance 3 pF DIN, SCLK, and
19 pF

LDAC

and

CLR

POWER REQUIREMENTS

VDD 2.7 3.6 V

IDD (Normal Mode)4 VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 200 425 µA Internal reference off
VDD = 2.7 V to 3.6 V 800 900 µA Internal reference on
IDD (All Power-Down Modes)5
VDD = 2.7 V to 3.6 V 0.2 1 µA VIH = VDD and VIL = GND

1

Temperature range: B grade = −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064).

Output unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

Both DACs powered down.

SYNC

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 4.

Parameter

1, 2

Min Ty p Max Unit Conditions/Comments3

Output Voltage Settling Time

AD5623R 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5643R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB

AD5663R 4 7 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.8 V/µs
Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB V

Analog Crosstalk 1 nV-s External reference
4 nV-s Internal reference
DAC-to-DAC Crosstalk 1 nV-s External reference
4 nV-s Internal reference

Total Harmonic Distortion −80 dB V
Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 15 μV p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range: A, B grade = −40°C to +105°C, typical at +25°C.

= VDD; all specifications T

REFIN

to T

MIN

= 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz

REF

REF

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REF

, unless otherwise noted.

MAX

Rev. E | Page 6 of 32

Data Sheet AD5623R/AD5643R/AD5663R

05858-002

t

4

t

3

SCLK

SYNC

DIN

t

1

t

2

t

5

t

6

t

7

t

8

DB23

t

9

t

10

t

11

t

12

LDAC

1

LDAC

2

t

14

1

ASYNCHRONOUS LDAC UPDATE MODE .

2

SYNCHRONOUS LDAC UPDATE MODE .

CLR

t

13

t

15

V

OUT

DB0

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
V

= 2.7 V to 5.5 V; all specifications T

DD

Table 5.

Limit at T
Parameter

2

t

20 ns min SCLK cycle time

1

VDD = 2.7 V to 5.5 V Unit Conditions/Comments

MIN

t2 9 ns min SCLK high time
t3 9 ns min SCLK low time
t4 13 ns min
t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 0 ns min
t8 15 ns min
t9 13 ns min

t10 0 ns min
t11 10 ns min
t12 15 ns min
t13 5 ns min
t14 0 ns min
t15 300 ns max

1

Guaranteed by design and characterization, not production tested.

2

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

to T

MIN

, T

MAX

, unless otherwise noted.1

MAX

to SCLK falling edge setup time

SYNC

SCLK falling edge to
Minimum
SYNC

SYNC

rising edge to SCLK fall ignore

SCLK falling edge to

pulse width low

LDAC

SCLK falling edge to

pulse width low

CLR
SCLK falling edge to

pulse activation time

CLR

SYNC

high time

SYNC

LDAC

LDAC

rising edge

fall ignore

rising edge

falling edge

TIMING DIAGRAM

Figure 2. Serial Write Operation

Rev. E | Page 7 of 32

AD5623R/AD5643R/AD5663R Data Sheet

θJA Thermal Impedance

142°C/W

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

V

REFIN/VREFOUT

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θJA
LFCSP Package (4-Layer Board)

θJA Thermal Impedance 61°C/W
MSOP Package (4-Layer Board)

θJC Thermal Impedance 43.7°C/W
Reflow Soldering Peak Temperature

Pb-Free 260(+0/−5)°C

to GND −0.3 V to VDD + 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. E | Page 8 of 32

Data Sheet AD5623R/AD5643R/AD5663R

05858-003

1

V

OUT

A

10

V

REFIN

/V

REFOUT

2

V

OUT

B

9

V

DD

3

GND

8

DIN

4

LDAC

7

SCLK

5

CLR

6

SYNC

AD5623R/
AD5643R/

AD5663R

TOP VIEW

(Not to Scale)

NOTE:
EXPOSED PAD TIED TO GND ON
LFCSP PACKAG E .

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

3 GND Ground. Reference point for all circuitry on the part.
4

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.

LDAC

This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

5

CLR

Asynchronous Clear Input. The
ignored. When

is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.

CLR

input is falling edge sensitive. While

CLR

CLR

is low, all

The part exits clear code mode on the 24th falling edge of the next write to the part. If

pulses are

LDAC

is activated during

CLR

a write sequence, the write is aborted.

6

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.

SYNC

When
following clocks. The DAC is updated following the 24th clock cycle unless
in which case the rising edge of

goes low, it enables the input shift register, and data is transferred in on the falling edges of the

SYNC

is taken high before this edge,

SYNC

acts as an interrupt and the write sequence is ignored by the DAC.

SYNC

7 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates up to 50 MHz.

8 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge

of the serial clock input.

9 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with

a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

10 V

REFIN/VREFOUT

Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output

pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.

Rev. E | Page 9 of 32

AD5623R/AD5643R/AD5663R Data Sheet

CODE

INL ERROR ( LSB)

10

4

6

8

0

2

–6

–10

–8

–2
–4

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

V

DD

= V

REF

= 5V

TA = 25°C

05858-005

CODE

INL ERROR ( LSB)

4

–4

0 2.5k 5.0k 7.5k 10.0k 12.5k 15.0k

–3

–2

–1

0

1

2

3

V

DD

= V

REF

= 5V

T

A

= 25°C

05858-006

CODE

INL ERROR ( LSB)

1.0

–1.0

0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

–0.8

–0.6

–0.4

0

0.4

0.2

–0.2

0.6

0.8

V

DD

= V

REF

= 5V

T

A

= 25°C

05858-007

CODE

DNL ERROR (L S B)

1.0

0.6

0.4

0.2

0.8

0

–0.4

–0.2

–0.6

–1.0

–0.8

0 10k 20k 30k 40k 50k 60k

VDD = V

REF

= 5V

T

A

= 25°C

05858-008

DNL ERROR (L S B)

0.5

0.3

0.2

0.1

0.4

0

–0.2

–0.1

–0.3

–0.5

–0.4

VDD = V

REF

= 5V

T

A

= 25°C

CODE

0 2.5k 5.0k 7.5k 10.0k 12.5k 15.0k

05858-009

DNL ERROR (L S B)

0.20

0.10

0.05

0.15

0

–0.05

–0.10

–0.20

–0.15

CODE

0 0.5k 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k

VDD = V

REF

= 5V

T

A

= 25°C

05858-010

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. INL—AD5663R, External Reference

Figure 5. INL—AD5643R, External Reference

Figure 7. DNL—AD5663R, External Reference

Figure 8. DNL—AD5643R, External Reference

Figure 6. INL—AD5623R, External Reference

Figure 9. DNL—AD5623R, External Reference

Rev. E | Page 10 of 32