Analog Devices AD5641 a Datasheet

2.7 V to 5.5 V, <100 µA, 14-Bit

nano

DAC™, SPI® Interface in SC70 Package

FEATURES

6-lead SC70 package
Micropower operation: 100 µA max at 5 V
Power-down to typically 0.2 µA at 3 V
Single 14-bit DAC
A version: ±16 LSB INL

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC

interrupt facility

APPLICATIONS

Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5641, a member of the nanoDAC fam ily, is a single,
14-bit, buffered, voltage-out DAC that operates from a single

2.7 V to 5.5 V supply, typically consuming 75 µA at 5 V. The
part comes in a tiny SC70 package. Its on-chip precision output
amplifier allows rail-to-rail output swing to be achieved. The
AD5641 utilizes a versatile 3-wire serial interface that operates
at clock rates up to 30 MHz and is compatible with SPI, QSPI™,
MICROWIRE™, and DSP interface standards. The reference for
AD5641 is derived from the power supply inputs and, therefore,
gives the widest dynamic output range. The part incorporates a
power-on reset circuit, which ensures that the DAC output
powers up to 0 V and remains there until a valid write to the
device takes place.

The AD5641 contains a power-down feature that reduces
current consumption typically 0.2 µA at 3 V, and provides
software-selectable output loads while in power-down mode.
The part is put into power-down mode over the serial interface.
The low power consumption of the part in normal operation
makes it ideally suited to portable battery-operated equipment.
The combination of small package and low power makes this
nanoDAC device ideal for level-setting requirements such as
generating bias or control voltages in space-constrained and
power-sensitive applications.

AD5641

FUNCTIONAL BLOCK DIAGRAM

V

DD

GND

POWER-ON

RESET

REF(+)

14-BIT

DAC

POWER-DOWN

CONTROL LOGIC

Figure 1.

OUTPUT
BUFFER

SYNC

DAC

REGISTER

INPUT

CONTROL

LOGIC

SCLK SDIN

Table 1. Related Devices

Part Number Description

AD5601/AD5611/AD5621 2.7 V to 5.5 V, <100 µA, 8-/10-/12-Bit

nanoDAC, SPI Interface in SC70 Package

PRODUCT HIGHLIGHTS

1. Available in a space-saving, 6-lead SC70 package.

2. Low power, single-supply operation. The AD5641 operates

from a single 2.7 V to 5.5 V supply and with a maximum
current consumption of 100 µA, making it ideal for
battery-powered applications.

3. The on-chip output buffer amplifier allows the output of

the DAC to swing rail-to-rail with a typical slew rate of

0.5 V/µs.

4. Reference derived from the power supply.

5. High speed serial interface with clock speeds up to

30 MHz. Designed for very low power consumption. The
interface powers up only during a write cycle.

6. Power-down capability. When powered down, the DAC

typically consumes 0.2 µA at 3 V.

7. Power-on reset with brownout detection.

AD5641

RESISTOR
NETWORK

V

OUT

04611-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5641

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Te r m in o l o g y ...................................................................................... 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 13

D/A Section................................................................................. 13

Resistor String............................................................................. 13

Output Amplifier........................................................................ 13

Serial Interface............................................................................ 13

REVISION HISTORY

3/05—Rev. 0 to Rev. A

Changes to Timing Characteristics................................................ 4

Changes to Absolute Maximum Ratings ....................................... 5

Changes to Full-Scale Error Section .............................................. 7

Changes to Figures 28 and 30 ....................................................... 12

Change to Resistor String Section................................................ 13

Changes to Power-Down Mode Section...................................... 14

1/05—Revision 0: Initial Version

Input Shift Register .................................................................... 13

SYNC

Interrupt .......................................................................... 13

Power-On Reset.......................................................................... 14

Power-Down Modes .................................................................. 14

Microprocessor Interfacing ...................................................... 15

Applications..................................................................................... 17

Choosing a Reference as Power Supply for the AD5641 ...... 17

Bipolar Operation Using the AD5641..................................... 17

Using the AD5641 with an Opto-Isolated Interface.............. 18

Power Supply Bypassing and Grounding................................ 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. A | Page 2 of 20

AD5641

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

Table 2.

A Grade

1

Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution 14 Bits
Relative Accuracy

2

±16 LSB A grade
Differential Nonlinearity2 ±1 LSB Guaranteed monotonic by design
Zero-Code Error 0.5 10 mV All 0s loaded to DAC register
Offset Error ±0.063 ±10 mV
Full-Scale Error ±0.5 mV All 1s loaded to DAC register
Gain Error ±0.0004 ±0.037 % of FSR
Zero-Code Error Drift 5.0 µV/°C
Gain Temperature Coefficient 2.0 ppm of FSR/°C

OUTPUT CHARACTERISTICS

Output Voltage Range 0 V

3

DD

V
Output Voltage Settling Time 6 10 µs Code ¼ scale to ¾ scale
Slew Rate 0.5 V/µs
Capacitive Load Stability 470 pF RL = ∞
1000 pF RL = 2 kΩ
Output Noise Spectral Density 120

nV/√Hz
Noise 2 µV DAC code = midscale, 0.1 Hz to 10 Hz bandwidth
Digital-to-Analog Glitch Impulse 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.2 nV-s
DC Output Impedance 0.5 Ω
Short-Circuit Current 15 mA VDD = 3 V/5 V

LOGIC INPUTS

Input Current
V

, Input Low Voltage 0.8 V VDD = 4.5 V to 5.5 V

INL

4

± 2 µA

0.6 V VDD = 2.7 V to 3.6 V
V

, Input High Voltage 1.8 V VDD = 4.5 V to 5.5 V

INH

1.4 V VDD = 2.7 V to 3.6 V
Pin Capacitance 3 pF

POWER REQUIREMENTS

V

DD

2.7 5.5 V All digital inputs at 0 V or V

IDD (Normal Mode) DAC active and excluding load current

VDD = 4.5 V to 5.5 V 75 100 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 60 90 µA VIH = VDD and VIL = GND

IDD (All Power-Down Modes)

VDD = 4.5 V to 5.5 V 0.5 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 0.2 µA VIH = VDD and VIL = GND

POWER EFFICIENCY

I

OUT/IDD

1

Temperature range for A grade: −40°C to +125°C; typical at +25°C.

2

Linearity calculated using a reduced code range (Code 256 to Code 16128).

3

Guaranteed by design and characterization, not production tested.

4

Total current flowing into all pins.

96 % I

MIN

to T

, unless other wise noted.

MAX

DAC code = midscale, 1 kHz

= 2 mA and VDD = ±5 V, full scale loaded

LOAD

DD

Rev. A | Page 3 of 20

AD5641

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications T

Table 3.

Parameter Limit

2

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 30 MHz.

1

33 ns min SCLK cycle time
5 ns min SCLK high time
5 ns min SCLK low time
10 ns min
5 ns min Data setup time

4.5 ns min Data hold time
0 ns min

20 ns min
13 ns min

MIN

to T

, unless otherwise noted. See Figure 2.

MAX

Unit Test Conditions/Comments

SYNC to SCLK falling edge setup time

SCLK falling edge to
Minimum

SYNC high time

SYNC rising edge

SYNC rising edge to next SCLK falling edge ignored

SCLK

SYNC

SDIN

t

4

t

8

t

t

2

1

t

3

t

6

t

5

t

9

t

7

D0D1D2D14D15

D15 D14

04611-002

Figure 2. Timing Diagram

Rev. A | Page 4 of 20

AD5641

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
V

to GND –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (A Grade) –40°C to +125°C

Storage Temperature Range –65°C to +160°C
Maximum Junction Temperature 150°C
SC70 Package

θJA Thermal Impedance 433.34°C/W
θJC Thermal Impedance 149.47°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

ESD 2.0 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada­tion or loss of functionality.

Rev. A | Page 5 of 20

AD5641

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

16

SYNC

SDIN

AD5641

TOP VIEW

25

(Not to Scale)

34

V

OUT

GNDSCLK

V

DD

Figure 3. 6-Lead SC70 Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Function

1

2 SCLK

SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow.
The DAC is updated following the 16
rising edge of

SYNC acts as an interrupt and the write sequence is ignored by the DAC.

th

clock cycle unless SYNC is taken high before this edge, in which case the

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.

3 SDIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.

4 V

DD

Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND.
5 GND Ground Reference Point for All Circuitry on the AD5641.
6 V

OUT

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

04611-003

Rev. A | Page 6 of 20