ANALOG DEVICES AD5641 Service Manual

SPI Interface in LFCSP and SC70

AD5641

Rev. D

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AD5641

V

DD

V

OUT

GND

POWER-ON

RESET

DAC

REGISTER

14-BIT

DAC

INPUT

CONTROL

LOGIC

POWER-DOWN

CONTROL LOGIC

OUTPUT
BUFFER

RESISTOR
NETWORK

REF(+)

SCLK SDIN

04611-001

SYNC

Data Sheet

FEATURES

6-lead LFCSP and SC70 packages
Micropower operation: 100 µA maximum at 5 V
Power-down to typically 0.2 µA at 3 V
Single 14-bit DAC
B version: ±4 LSB INL
A version: ±16 LSB INL

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation

interrupt facility

SYNC

APPLICATIONS

Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5641, a member of the nanoDAC® family, is a single,
14-bit, buffered, voltage-out DAC that operates from a single

2.7 V to 5.5 V supply, typically consuming 75 µA at 5 V. The
part comes in tiny LFCSP and SC70 packages. Its on-chip
precision output amplifier allows rail-to-rail output swing to be
achieved. The AD5641 uses a versatile 3-wire serial interface
that operates at clock rates up to 30 MHz and is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The
reference for AD5641 is derived from the power supply inputs
and, therefore, gives the widest dynamic output range. The part
incorporates a power-on reset circuit, which ensures that the
DAC output powers up to 0 V and remains there until a valid
write to the device takes place.

The AD5641 contains a power-down feature that reduces
current consumption typically to 0.2 µA at 3 V, and provides
software-selectable output loads while in power-down mode.
The part is put into power-down mode over the serial interface.
The low power consumption of the part in normal operation
makes it ideally suited to portable battery-operated equipment.
The combination of small package and low power makes this
nanoDAC device ideal for level-setting requirements such as
generating bias or control voltages in space-constrained and
power-sensitive applications.

2.7 V to 5.5 V, <100 µA, 14-Bit nanoDAC,

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Table 1. Related Devices

Part Number Description

AD5601 2.7 V to 5.5 V, <100 µA, 8-bit nanoDAC,

SPI interface in LFCSP and SC70 packages

AD5611 2.7 V to 5.5 V, <100 µA, 10-bit nanoDAC,

SPI interface in LFCSP and SC70 packages

AD5621 2.7 V to 5.5 V, <100 µA, 12-bit nanoDAC,

SPI interface in LFCSP and SC70 packages

PRODUCT HIGHLIGHTS

1. Available in space-saving 6-lead LFCSP and SC70

packages.

2. Low power, single-supply operation. The AD5641 operates

from a single 2.7 V to 5.5 V supply and with a maximum
current consumption of 100 µA, making it ideal for
battery-powered applications.

3. The on-chip output buffer amplifier allows the output of

the DAC to swing rail-to-rail with a typical slew rate of

0.5 V/µs.

4. Reference derived from the power supply.

5. High speed serial interface with clock speeds up to

30 MHz. Designed for very low power consumption. The
interface powers up only during a write cycle.

6. Power-down capability. When powered down, the DAC

typically consumes 0.2 µA at 3 V.

7. Power-on reset with brownout detection.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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AD5641 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

Digital-to-Analog Section ......................................................... 13

Resistor String ............................................................................. 13

Output Amplifier ........................................................................ 13

Serial Interface ............................................................................ 13

Input Shift Register .................................................................... 13

SYNC

Interrupt .......................................................................... 13

Power-On Reset .......................................................................... 14

Power-Down Modes .................................................................. 14

Microprocessor Interfacing ....................................................... 15

Applications ..................................................................................... 16

Choosing a Reference as Power Supply for the AD5641....... 16

Bipolar Operation Using the AD5641 ..................................... 16

Using the AD5641 with a Galvanically Isolated Interface .... 17

Power Supply Bypassing and Grounding ................................ 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 19

REVISION HISTORY

2/12—Rev. C to Rev. D

Added 6-Lead LFCSP ......................................................... Universal

Changes to Title, Features Section, General Description Section,

Tabl e 1, and Product Highlights Section, ...................................... 1

Changes to Table 4 ............................................................................ 5

Added Figure 4; Renumbered Sequentially .................................. 6

Changes to Table 5 ............................................................................ 6

Change to Choosing a Reference as Power Supply for the

AD5641 Section .............................................................................. 16

Updated Outline Dimensions ....................................................... 18

Changes to Ordering Guide .......................................................... 19

10/07—Rev. B to Rev. C

Added B Grade .................................................................... Universal

Changes to Offset Error and Gain Error Specifications .............. 3

Changes to Table 4 ............................................................................ 5

Changes to Typical Performance Characteristics ......................... 7

Changes to Ordering Guide .......................................................... 18

7/05—Rev. A to Rev. B

Change to Galvanically Isolated Interface Section ..................... 18

Changes to Figure 44 ...................................................................... 18

3/05—Rev. 0 to Rev. A

Changes to Timing Characteristics ................................................. 4

Changes to Absolute Maximum Ratings ........................................ 5

Changes to Full-Scale Error Section ............................................... 7

Changes to Figures 28 and 30 ....................................................... 12

Change to Resistor String Section ................................................ 13

Changes to Power-Down Mode Section ..................................... 14

1/05—Revision 0: Initial Version

Rev. D | Page 2 of 20

Data Sheet AD5641

OUTPUT CHARACTERISTICS2

LOGIC INPUTS

IDD (Normal Mode)

DAC active and excluding load current

VDD = 2.7 V to 3.6 V

0.2

0.2 µA

VIH = VDD and VIL = GND

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; −40°C < TA < +125°C; typical at +25°C; all specifications T
unless otherwise noted.

MIN

to T

MAX

,

Table 2.

A Grade

B Grade

Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution 14 14 Bits
Relative Accuracy1 ±16 ±4 LSB
Differential Nonlinearity1 ±1 ±1 LSB Guaranteed monotonic by design
Zero-Code Error 0.5 10 0.5 10 mV All 0s loaded to DAC register
Offset Error ±0.63 ±10 ±0.63 ±10 mV
Full-Scale Error ±0.5 ±0.5 mV All 1s loaded to DAC register
Gain Error ±0.004 ±0.037 ±0.004 ±0.037 % of FSR
Zero-Code Error Drift 5.0 5.0 µV/°C
Gain Temperature Coefficient 2.0 2.0 ppm of

FSR/°C

Output Voltage Range 0 VDD 0 VDD V
Output Voltage Settling Time 6 10 6 10 µs Code ¼ scale to ¾ scale, to ±1 LSB
Slew Rate 0.5 0.5 V/µs
Capacitive Load Stability 470 470 pF RL = ∞
1000 1000 pF RL = 2 kΩ
Output Noise Spectral Density 120 120

nV/√Hz

DAC code = midscale, 1 kHz

Noise 2 2 µV DAC code = midscale, 0.1 Hz to

10 Hz bandwidth

Digital-to-Analog Glitch

5 5 nV-s 1 LSB change around major carry

Impulse
Digital Feedthrough 0.2 0.2 nV-s
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 15 15 mA VDD = 3 V/5 V

Input Current
V

, Input Low Voltage 0.8 0.8 V VDD = 4.5 V to 5.5 V

INL

3

±2 ±2 µA

0.6 0.6 V VDD = 2.7 V to 3.6 V
V

, Input High Voltage 1.8 1.8 V VDD = 4.5 V to 5.5 V

INH

1.4 1.4 V VDD = 2.7 V to 3.6 V
Pin Capacitance 3 3 pF

POWER REQUIREMENTS

VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or VDD

VDD = 4.5 V to 5.5 V 75 100 75 100 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 60 90 60 90 µA VIH = VDD and VIL = GND

IDD (All Power-Down Modes)

VDD = 4.5 V to 5.5 V 0.5 0.5 µA VIH = VDD and VIL = GND

POWER EFFICIENCY

I

96 96 % I

OUT/IDD

= 2 mA and VDD = ±5 V, full-scale

LOAD

loaded

1

Linearity calculated using a reduced code range (Code 256 to Code 16,128).

2

Guaranteed by design and characterization, not production tested.

3

Total current flowing into all pins.

Rev. D | Page 3 of 20

AD5641 Data Sheet

t6

4.5

ns min

Data hold time

t

4

t

3

t

2

t

5

t

7

t

6

D0D1D2D14D15

SYNC

SCLK

04611-002

t

9

t

1

t

8

D15 D14

SDIN

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications T

Table 3.

Parameter Limit1 Unit Test Conditions/Comments

2

t

33 ns min SCLK cycle time

1

t2 5 ns min SCLK high time
t3 5 ns min SCLK low time
t4 10 ns min

t5 5 ns min Data setup time

MIN

to T

, unless otherwise noted. See Figure 2.

MAX

to SCLK falling edge setup time

SYNC

t7 0 ns min SCLK falling edge to
t8 20 ns min Minimum
t9 13 ns min

1

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 30 MHz.

rising edge to next SCLK falling edge ignored

SYNC

SYNC

high time

SYNC

rising edge

Figure 2. Timing Diagram

Rev. D | Page 4 of 20

Data Sheet AD5641

Maximum Junction Temperature

150°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
V

to GND –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial –40°C to +125°C

Storage Temperature Range –65°C to +160°C

SC70 Package

θJA Thermal Impedance 433.34°C/W
θJC Thermal Impedance 149.47°C/W

LFCSP Package

θJA Thermal Impedance 95°C/W

Reflow Soldering

Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec

ESD 2.0 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. D | Page 5 of 20

AD5641 Data Sheet

S

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

16

SYNC

SDIN

AD5641

TOP VIEW

25

(Not to Scale)

34

V

OUT

GNDSCLK

V

DD

04611-003

Figure 3. 6-Lead SC70 Pin Configuration

DD

CLK

NOTES:

1. CONNECT T HE EXPOSE D PAD TO GND.

Figure 4. 6-Lead LFCSP Pin Configuration

Table 5. Pin Function Descriptions

SC70
Pin No.

1 4

LFCSP
Pin No. Mnemonic Description

SYNC

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input
data. When SYNC

goes low, it enables the input shift register and data is transferred in on the falling
edges of the clocks that follow. The DAC is updated following the 16th clock cycle unless SYNC is
taken high before this edge, in which case the rising edge of SYNC
sequence is ignored by the DAC.

2 2 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.

3 3 SDIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.

4 1 VDD

Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. V
GND.

5 5 GND Ground Reference Point for All Circuitry on the AD5641.
6 6 V

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

OUT

EP Exposed Pad. Connect to GND.

1V

2

3SDIN

6V

AD5641

TOP VIEW

(Not to Scale)

OUT

5GND

4 SYNC

04611-045

acts as an interrupt and the write

should be decoupled to

DD

Rev. D | Page 6 of 20