Analog Devices AD5628 48 68 prb Datasheet

Octal, 12-14-16 Bit Dac with 10ppm/°C Max

On-Chip Reference in 14-Lead TSSOP

Preliminary Technical Data

FEATURES

Low Power Smallest Pin compatible Octal DACs
AD5668: 16 Bits
AD5648: 14 Bits
AD5628: 12 Bits
14/16-Lead TSSOP Package
On-chip 1.25/2.5V, 10ppm/°C Reference
Power-Down to 200 nA @ 5V, 50 nA @ 3V
3V/5V Power Supply
Guaranteed Monotonic by Design
Power-On-Reset to Zero/Midscale
Three Power-Down Functions
Hardware /LDAC and /CLR functions
Rail-to-Rail Operation

APPLICATIONS

ProcessControl
Data Acquisition Systems
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources

GENERAL DESCRIPTION

The AD5628/48/68 family of devices are low power, octal, 12­14-16-bit buffered voltage-out DACs. All devices operate from
a single +2.7V to +5.5V, and are guaranteed monotonic by
design.

The AD5628/48/68 have an on-chip reference with an internal
gain of two. The AD56x8-1 has a 1.25V 10ppm/°C max
reference and the AD56x8-2,-3 have a 2.5V 10ppm/°C max
reference. The on-board reference is off at power-up allowing
the use of an external reference. The internal reference is
turned on by writing to the DAC. The part incorporates a
power-on-reset circuit that ensures that the DAC output
powers up to zero volts (AD56x8-1,-2/) or midscale (AD5668-

3) and remains there until a valid write takes place. The part
contains a power-down feature that reduces the current
consumption of the device to 200nA at 5V and provides
software selectable output loads while in power-down mode for
any or all DACs channels.

AD5628/AD5648/AD5668

Programmable Attenuators

V

I

NPUT

REGISTER

I

NPUT

REGISTER

I

NPUT

REGISTER

I

NPUT

REGISTER

I

NPUT

REGIS-

TER

I

NPUT

REGISTER

I

NPUT

REGISTER

I

NPUT

REGISTER

POWER-ON

DD

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

RESET

SCLK

SYNC

DIN

*RU-16 PACKAGE ONLY

AD5628/AD5648/AD5668

LDAC

INTERFACE

LOGIC

LDAC*

CLR*

Figure 1. Functional Block Diagram

The outputs of all DACs may be updated simultaneously using
the /LDAC function, with the added functionality of selecting
through software any number of DAC channels to synchronize.
There is also an asynchronous active low /CLR that clears all
DACs to a software selectable code - 0 V, midscale or fullscale .

The AD5628/48/68 utilizes a versatile three-wire serial
interface that operates at clock rates up to 50 MHz and is
compatible with standard SPI™, QSPI™, MICROWIRE™ and
DSP interface standards. Its on-chip precision output amplifier
allows rail-to-rail output swing to be achieved.

PRODUCT HIGHLIGHTS

1. Octal 12/14/16-Bit DAC

2. On-chip 1.25/2.5V, 10ppm/°C max Reference.

3. Available in 14/16-lead TSSOP package.

4. Power-On-Reset to Zero volts or Midscale.

5. Power-down capability. When powered down, the

DAC typically consumes 50nA at 3V and 200nA at 5V.

DAC

DAC

DAC

D

AC

REGISTER

D

AC

D

AC

D

AC

D

AC

V

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING
DAC D

STRING
DAC E

STRING

DAC F

STRING
DAC G

STRING

DAC H

REF

1.25/2.5V
Ref

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOWN

GND

LOGIC

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

V

E

OUT

V

F

OUT

V

G

OUT

V

H

OUT

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD5628/AD5648/AD5668

Rev. PrB | Page 2 of 24

TABLE OF CONTENTS

Features.......................................................................................... 1

Applications................................................................................... 1

General Description..................................................................... 1

Product Highlights....................................................................... 1

AD5628/AD5648/AD5668–Specifications ................................... 3

Timing Characteristics..................................................................... 9

Pin Configuration and Function Descriptions........................... 10

Absolute Maximum Ratings.......................................................... 11

ESD Caution................................................................................ 11

Terminology ................................................................................ 12

REVISION HISTORY

Preliminary Technical Data

AD5628/AD5648/AD5668–Typical Performance

Characteristics ................................................................................ 14

General Description................................................................... 17

Serial Interface............................................................................ 17

Microprocessor Interfacing............................................................

Applications .....................................................................................

Outline Dimensions....................................................................... 24

Ordering Guide ...............................................................................

Revision 0: Initial Version

Rev.PrB | Page 2 of 25

Preliminary Technical Data

Rev. PrB | Page 3 of 24

AD5628/AD5648/AD5668

AD5628/AD5648/AD5668–SPECIFICATIONS

(VDD = +4.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all specifications T
noted)

Table 1.

A Grade

B Version

Parameter Min Typ Max Unit

STATIC PERFORMANCE

3,4

Conditions/Comments

1,2

AD5628
Resolution 12 Bits
Relative Accuracy ±0.5 ±6 LSB See Figure 4
Differential Nonlinearity ±1 LSB Guaranteed Monotonic by Design. See Figure 5.
AD5648
Resolution 14 Bits
Relative Accuracy ±2 ±8 LSB See Figure 4
Differential Nonlinearity ±1 LSB Guaranteed Monotonic by Design. See Figure 5.
AD5668
Resolution 16 Bits
Relative Accuracy ±32 LSB See Figure 4
Differential Nonlinearity ±1 LSB Guaranteed Monotonic by Design. See Figure 5.
Load Regulation 2 LSB/mA

VDD=Vref=5V, Midscale

sourcing/sinking
Zero Code Error +1 +9 mV All Zeroes Loaded to DAC Register. See Figure 8.
Zero Code Error Drift3 ±20 µV/°C
Full-Scale Error -0.15 -1.25 % of FSR All Ones Loaded to DAC Register. See Figure 8.
Gain Error ±1.5 % of FSR
Gain Temperature Coefficient ±5 ppm of FSR/°C
Offset Error ±1 ±9 mV
Offset Temperature Coefficient 1.7 µV/°C

DC Power Supply Rejection Ratio6

DC Crosstalk6 (Ext Ref)

DC Crosstalk6 (Int Ref)

10

4.5

10

20

4.5

20

–80

dB VDD ±10%

µV
µV/mA
µV
µV
µV/mA
µV

RL = 2 k. to GND or VDD

Due to Load current change

Due to Powering Down (per channel)

RL = 2 k. to GND or VDD

Due to Load current change

Due to Powering Down (per channel)

OUTPUT CHARACTERISTICS6
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 pF RL=∞
10 pF RL=2 kΩ
DC Output Impedance 0.5 Ω
Short Circuit Current 30 mA VDD=+5V
Power-Up Time 4 µs Coming out of Power-Down Mode. VDD=+5V

1

Temperature ranges are as follows: B Version: -40°C to +125°C, typical at 25°C.

2

Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.

3

DC specifications tested with the outputs unloaded unless stated otherwise.

4

Linearity is tested using a reduced code range: AD5628 (Code 48 to Code 4047), AD5648 (Code / to Code /), and AD5668 (Code 485 to 64714).

6

Guaranteed by design and characterization; not production tested.

8

Interface inactive. All DACs active. DAC outputs unloaded.

9

All eight DACs powered down.

Specifications subject to change without notice.

MIN

to T

unless otherwise

MAX

Iout=0mA to 1mA

Rev. PrB| Page 3 of 25

AD5628/AD5648/AD5668

Rev. PrB | Page 4 of 24

A Grade

Parameter Min Typ Max Unit

REFERENCE INPUTS3

Reference Input voltage

Reference Current 35 45 µ A V

Reference Input Range 0 VDD

Reference Input Impedance 14.6

REFERENCE OUTPUT
Output Voltage
AD5628/AD5648/AD5668x-2/3 2.495 2.5 2.505 V
Reference TC ±10 ppm/°C
Reference Output Impedance 2

LOGIC INPUTS3
Input Current ±1 µA
V

, Input Low Voltage 0.8 V VDD=+5 V

INL

V

, Input High Voltage 2 V VDD=+5 V

INH

Pin Capacitance 3 pF
POWER REQUIREMENTS
VDD 4.5 5.5 V All Digital Inputs at 0 or VDD
IDD (Normal Mode)8 DAC Active and Excluding Load Current
VDD=4.5 V to +5.5 V 2 4 mA VIH=VDD and VIL=GND
IDD (All Power-Down Modes)9
VDD=4.5 V to +5.5 V 0.2 1 µA VIH=VDD and VIL=GND
POWER EFFICIENCY
I

89 % I

OUT/IDD

VDD

V ±1% for specified performance

kΩ

kΩ

Preliminary Technical Data

B Version
Conditions/Comments

REF

Per DAC channel

LOAD

1,2

= VDD = +5.5V (per DAC channel)

=2 mA, VDD=+5 V

Rev.PrB | Page 4 of 25

Preliminary Technical Data

Rev. PrB | Page 5 of 24

1

AC CHARACTERISTICS

specifications T

MIN

to T

unless otherwise noted)

MAX

(VDD = +4.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all

AD5628/AD5648/AD5668

Parameter2 Min Typ Max Unit

Output Voltage Settling Time
AD5628 6 8 µs ¼ to ¾ scale settling to ±2LSB
AD5648 7 9 µs ¼ to ¾ scale settling to ±2LSB
AD5668 8 10 µs ¼ to ¾ scale settling to ±2LSB
Settling Time for 1LSB Step
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse 5 nV-s 1 LSB Change Around Major Carry. See Figure 21.
Channel –to-Channel Isolation 100 dB
Digital Feedthrough 0.1 nV-s
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz VREF = 2V ± 0.1 V p-p.
Total Harmonic Distortion -80 dB VREF = 2V ± 0.1 V p-p. Frequency = 10kHz
Output Noise Spectral Density 120 nV/√Hz DAC code=8400H, 1kHz
100 nV/√Hz DAC code=8400H, 10kHz
Output Noise 15

1

µVp-p

B Version
Conditions/Comments

0.1Hz to 10Hz;

NOTES

1Guaranteed by design and characterization; not production tested.
2See the Terminology section.
3Temperature range (Y Version): –40°C to +125°C; typical at +25°C.

Specifications subject to change without notice.

Rev. PrB| Page 5 of 25

AD5628/AD5648/AD5668

Rev. PrB | Page 6 of 24

Preliminary Technical Data

AD5628/AD5648/AD5668–SPECIFICATIONS

(VDD = +2.7 V to +3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = V
noted)

Table 2.

A Grade

Parameter Min Typ Max Unit

STATIC PERFORMANCE
AD5628
Resolution 12 Bits
Relative Accuracy ±0.5 ±6 LSB See Figure 4
Differential Nonlinearity ±1 LSB

AD5648
Resolution 14 Bits
Relative Accuracy ±2 ±8 LSB See Figure 4
Differential Nonlinearity ±1 LSB

AD5668
Resolution 16 Bits
Relative Accuracy ±32 LSB See Figure 4
Differential Nonlinearity ±1 LSB

Load Regulation 4 LSB/mA

Zero Code Error +1 +9 mV

Zero Code Error Drift1 ±20 µV/°C
Full-Scale Error -0.15 -1.25 % of FSR

Gain Error ±0.7 % of FSR
Gain Temperature Coefficient ±5 ppm of FSR/°C
Offset Error ±1 ±9 mV
Offset Temperature Coefficient 1.7 µV/°C

DC Power Supply Rejection Ratio6

DC Crosstalk6 (Ext Ref)

DC Crosstalk6 (Int Ref)

OUTPUT CHARACTERISTICS6
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 pF RL=∞
10 pF RL=2 kΩ
DC Output Impedance 0.5 Ω
Short Circuit Current 30 mA VDD=+3V
Power-Up Time 5 µs Coming Out of Power-Down Mode. VDD=+3V

REFERENCE INPUTS3

Reference Input voltage

3,4

–80

10

4.5

10

20

4.5

20

V

DD

V ±1% for specified performance

dB VDD ±10%

µV
µV/mA
µV
µV
µV/mA
µV

; all specifications T

DD

B Version
Conditions/Comments

Guaranteed Monotonic by Design. See Figure

5.

Guaranteed Monotonic by Design. See Figure

5.

Guaranteed Monotonic by Design. See Figure

5.

VDD=Vref=3V, Midscale

sourcing/sinking
All Zeroes Loaded to DAC Register. See Figure

8.

All Ones Loaded to DAC Register. See Figure

8.

RL = 2 k. to GND or VDD

Due to Load current change

Due to Powering Down (per channel)

RL = 2 k. to GND or VDD

Due to Load current change

Due to Powering Down (per channel)

1,1

to T

MIN

unless otherwise

MAX

Iout=0mA to 7.5mA

Rev.PrB | Page 6 of 25

Preliminary Technical Data

Rev. PrB | Page 7 of 24

AD5628/AD5648/AD5668

Reference Current 20 20 µ A V

= VDD = +3.6V (per DAC channel)

REF

Reference Input Range 0 VDD

Reference Input Impedance 14.6

kΩ

Per DAC channel

REFERENCE OUTPUT
Output Voltage
AD5628/AD5648/AD5668x-1 1.248 1.25 1.252 V
Reference TC ±10 ppm/°C
Reference Output Impedance 2

kΩ

LOGIC INPUTS3
Input Current ±1 µA
V

, Input Low Voltage 0.8 V VDD=+3 V

INL

V

, Input High Voltage 2 V VDD=+3 V

INH

Pin Capacitance 3 pF
POWER REQUIREMENTS
VDD 2.7 3.6 V All Digital Inputs at 0 or VDD
IDD (Normal Mode)8 DAC Active and Excluding Load Current
VDD=2.7 V to +3.6 V 2 4 mA VIH=VDD and VIL=GND
IDD (All Power-Down Modes)9
VDD=2.7 V to +3.6 V 0.2 1 µA VIH=VDD and VIL=GND
POWER EFFICIENCY
I

89 % I

OUT/IDD

=2 mA, VDD=+5 V

LOAD

AC CHARACTERISTICS1

(VDD = +2.7 V to +3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all specifications T
noted)

B Version

Parameter2 Min Typ Max Unit

Conditions/Comments

1

Output Voltage Settling Time
AD5628 6 8 µs ¼ to ¾ scale settling to ±2LSB
AD5648 7 9 µs ¼ to ¾ scale settling to ±2LSB
AD5668 8 10 µs ¼ to ¾ scale settling to ±2LSB
Settling Time for 1LSB Step
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB Change Around Major Carry. See Figure 21.
Channel –to-Channel Isolation 100 dB
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz VREF = 2V ± 0.1 V p-p.
Total Harmonic Distortion -80 dB VREF = 2V ± 0.1 V p-p. Frequency = 10kHz
Output Noise Spectral Density 120 nV/√Hz DAC code=8400H, 1kHz
100 nV/√Hz DAC code=8400H, 10kHz
Output Noise 15

NOTES

1Guaranteed by design and characterization; not production tested.
2See the Terminology section.
3Temperature range (Y Version): –40°C to +125°C; typical at +25°C.

Specifications subject to change without notice.

µVp-p

0.1Hz to 10Hz;

MIN

to T

unless otherwise

MAX

Rev. PrB| Page 7 of 25

Preliminary Technical Data

Rev. PrB | Page 8 of 24

AD5628/AD5648/AD5668

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

See Figure 2.

= +2.7 V to +5.5 V; all specifications T

(V

DD

Limit at T

Parameter V

= 2.7 V to 3.6 V VDD= 3.6 V to 5.5 V Unit Conditions/Comments

DD

MIN

to T

MIN

unless otherwise noted)

MAX

, T

MAX

t1 1 20 20 ns min SCLK Cycle Time
t2 11 9 ns min SCLK High Time

t3 9 9 ns min SCLK Low Time
t4 13 13 ns min

SYNC

to SCLK Falling Edge Setup Time
t5 4 4 ns min Data Setup Time
t6 4 4 ns min Data Hold Time
t7 0 0 ns min

t8 25 20 ns min
t9 13 13 ns min
t10 0 0 ns min
t11 20 20 ns min
t12 20 20 ns min

SCLK Falling Edge to
Minimum
SYNC

SYNC

Rising Edge to SCLK Fall Ignore

SCLK Falling Edge to

LDAC Pulsewidth Low

SCLK Falling Edge to LDAC Rising Edge

SYNC

High Time

SYNC

Rising Edge

Fall Ignore

t13 20 20 ns min /CLR Pulse Width Low
t14 0 0 ns min

SCLK Falling Edge to LDAC Falling Edge

t15 tbd tbd ns min /CLR Pulse Activation Time (AD5380?)

t

10

SCLK

t

8

SYNC

DIN

LDAC1

LDAC2

CLR

NOTES

1. ASYNCHRONOUS LDAC UPDATE MODE.

2. SYNCHRONOUS LDAC UPDATE MODE.

DB31

t

4

t

5

1

3Maximum SCLK frequency is 50 MHz at VDD = +2.7 V to +5.5 V

t

1

t

t

3

t

6

2

Figure 2. Serial Write Operation

DB0

t

t14

t

9

7

t11

t12

t13

Rev. PrB| Page 9 of 25