ANALOG DEVICES AD5624R Service Manual

Quad, 12-/14-/16-Bit nanoDACs with

VDDV

/

S

FEATURES

Low power, smallest pin-compatible, quad nanoDACs

AD5664R: 16 bits AD5644R: 14 bits AD5624R: 12 bits

User-selectable external or internal reference

External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference

10-lead MSOP and 3 mm × 3 mm LFCSP_WD

2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface, up to 50 MHz

APPLICATIONS

Process controls Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

5 ppm/°C On-Chip Reference

AD5624R/AD5644R/AD5664R

FUNCTIONAL BLOCK DIAGRAM

GND

AD5624R/AD5644R/AD5664R

INPUT

REGISTER

POWER-ON

LOGIC

Figure 1.

REGISTER

SCLK

REGISTER

YNC

DIN

INTERFACE

LOGIC

Table 1. Related Devices

Part No. Description

AD5624/AD5664

2.7 V to 5.5 V quad, 12-/16-bit DACs, external reference

AD5666

2.7 V to 5.5 V quad, 16-bit DAC, internal reference, LDAC

DAC

V

REFIN

REFOUT

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

, CLR pins

1.25V/2.5V REF

BUFFER

POWER-

DOWN LOGIC

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

5856-001

GENERAL DESCRIPTION

The AD5624R/AD5644R/AD5664R, members of the nanoDAC® family, are low power, quad, 12-/14-/16-bit buffered voltage-out DACs. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design.

The AD5624R/AD5644R/AD5664R have an on-chip reference. The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference, giving a fullscale output range of 2.5 V; the AD56x4R-5 has a 2.5 V, 5 ppm/°C reference giving a full-scale output range of 5 V. The on-chip reference is off at power-up, allowing the use of an external reference; all devices can be operated from a single 2.7 V to 5.5 V supply. The internal reference is enabled via a software write.

The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The low power consumption of

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

this part in normal operation makes it ideally suited to portable battery-operated equipment.

The AD5624R/AD5644R/AD5664R use a versatile 3-wire serial interface that operates at clock rates up to 50 MHz, and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing.

PRODUCT HIGHLIGHTS

1. Quad 12-/14-/16-bit DACs.

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm,

LFCSP_WD.

4. Low power, typically consumes 1.32 mW at 3 V and

2.25 mW at 5 V.

AD5624R/AD5644R/AD5664R

REVISION HISTORY

4/08—Rev. A to Rev. B

Changes to Figure 50 ...................................................................... 20

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 28

11/06—Rev. 0 to Rev. A

Changes to Reference Output Parameter in Table 2 .................... 3

Changes to Reference Output Parameter in Table 3 .................... 5

Added Note to Figure 3 .................................................................... 9

4/06—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD5624R/AD5644R/AD5664R

SPECIFICATIONS

AD5624R-5/AD5644R-5/AD5664R-5

VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

= VDD; all specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

Table 2.

B Grade

1

Parameter Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5664R

Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design

AD5644R

Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design

AD5624R

Resolution 12 Bits Relative Accuracy ±0.5 ±1 LSB

Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 mV All zeroes loaded to DAC register Offset Error ±1 ±10 mV Full-Scale Error −0.1 ±1 % of FSR All ones loaded to DAC register Gain Error ±1.5 % of FSR Zero-Code Error Drift ±2 μV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 5 V ± 10% DC Crosstalk

External Reference 10 μV Due to full-scale output change, RL = 2 kΩ to GND or V

10 μV/mA Due to load current change

5 μV Due to powering down (per channel)

Internal Reference 25 μV Due to full-scale output change, RL = 2 kΩ to GND or V

20 μV/mA Due to load current change

10 μV Due to powering down (per channel) OUTPUT CHARACTERISTICS

3

Output Voltage Range 0 VDD V Capacitive Load Stability 2 nF RL = ∞ 10 nF RL = 2 kΩ DC Output Impedance 0.5 Ω Short-Circuit Current 30 mA VDD = 5 V Power-Up Time 4 μs Coming out of power-down mode; VDD = 5 V

REFERENCE INPUTS

Reference Current 170 200 μA V

= VDD = 5.5 V

REF

Reference Input Range 0.75 VDD V Reference Input Impedance 26 kΩ

REFERENCE OUTPUT

Output Voltage 2.495 2.505 V At ambient Reference TC

3

±5 ±10 ppm/°C MSOP package models

±10 ppm/°C LFCSP package models Output Impedance 7.5 kΩ

DD

Rev. B | Page 3 of 28

AD5624R/AD5644R/AD5664R

B Grade

1

Parameter Min Typ Max Unit Conditions/Comments

LOGIC INPUTS

3

Input Current ±2 μA All digital inputs V

, Input Low Voltage 0.8 V VDD = 5 V

INL

V

, Input High Voltage 2 V VDD = 5 V

INH

Pin Capacitance 3 pF

POWER REQUIREMENTS

VDD 4.5 5.5 V IDD VIH = VDD, VIL = GND, VDD = 4.5 V to 5.5 V

Normal Mode

4

0.45 0.9 mA Internal reference off

0.95 1.2 mA Internal reference on All Power-Down Modes

1

Temperature range: B grade: −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output

unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All DACs powered down.

5

0.48 1 μA

AD5624R-3/AD5644R-3/AD5664R-3

VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 3.

B Grade

1

Parameter Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5664R

Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design

AD5644R

Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design

AD5624R

Resolution 12 Bits Relative Accuracy ±0.5 ±1 LSB

Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 mV All zeroes loaded to DAC register Offset Error ±1 ±10 mV Full-Scale Error −0.1 ±1 % of FSR All ones loaded to DAC register Gain Error ±1.5 % of FSR Zero-Code Error Drift ±2 μV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 3 V ± 10% DC Crosstalk

External Reference 10 μV Due to full-scale output change, RL = 2 kΩ to GND or V

10 μV/mA Due to load current change 5 μV Due to powering down (per channel)

Internal Reference 25 μV Due to full-scale output change, RL = 2 kΩ to GND or V

20 μV/mA Due to load current change 10 μV Due to powering down (per channel)

= VDD; all specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

DD

Rev. B | Page 4 of 28

AD5624R/AD5644R/AD5664R

B Grade

1

Parameter Min Typ Max Unit Conditions/Comments

OUTPUT CHARACTERISTICS

3

Output Voltage Range 0 VDD V Capacitive Load Stability 2 nF RL = ∞ 10 nF RL = 2 kΩ DC Output Impedance 0.5 Ω Short-Circuit Current 30 mA VDD = 3 V Power-Up Time 4 μs Coming out of power-down mode; VDD = 3 V

REFERENCE INPUTS

Reference Current 170 200 μA V

= VDD = 3.6 V

REF

Reference Input Range 0 VDD V Reference Input Impedance 26 kΩ

REFERENCE OUTPUT

Output Voltage 1.247 1.253 V At ambient Reference TC

3

±5 ±15 ppm/°C MSOP package models

±10 ppm/°C LFCSP package models Output Impedance 7.5 kΩ

LOGIC INPUTS

3

Input Current ±2 μA All digital inputs V

, Input Low Voltage 0.8 V VDD = 3 V

INL

V

, Input High Voltage 2 V VDD = 3 V

INH

Pin Capacitance 3 pF

POWER REQUIREMENTS

VDD 2.7 3.6 V IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 3.6 V

Normal Mode

4

0.44 0.85 mA Internal reference off

0.95 1.15 mA Internal reference on All Power-Down Modes

1

Temperature range: B grade: −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output

unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All DACs powered down.

5

0.2 1 μA

Rev. B | Page 5 of 28

AD5624R/AD5644R/AD5664R

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

= VDD; all specifications T

REFIN

MIN

to T

, unless otherwise noted.1

MAX

Table 4.

Parameter

2

Min Typ Max Unit Conditions/Comments

3

Output Voltage Settling Time

AD5624R 3 4.5 μs ¼ to ¾ scale settling to ±0.5 LSB AD5644R 3.5 5 μs ¼ to ¾ scale settling to ±0.5 LSB AD5664R 4 7 μs ¼ to ¾ scale settling to ±2 LSB

Slew Rate 1.8 V/μs Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dB V

= 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz

REF

Digital Crosstalk 0.1 nV-s Analog Crosstalk 1 nV-s External reference 4 nV-s Internal reference DAC-to-DAC Crosstalk 1 nV-s External reference 4 nV-s Internal reference Multiplying Bandwidth 340 kHz V Total Harmonic Distortion −80 dB V

= 2 V ± 0.1 V p-p

REF

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REF

Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 μV p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical at 25°C.

Rev. B | Page 6 of 28

AD5624R/AD5644R/AD5664R

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). V

= 2.7 V to 5.5 V; all specifications T

DD

Table 5.

Limit at T Parameter VDD = 2.7 V to 5.5 V Unit Conditions/Comments

2

t

1

20 ns min SCLK cycle time t2 9 ns min SCLK high time t3 9 ns min SCLK low time t4 13 ns min

t5 5 ns min Data setup time t6 5 ns min Data hold time t7 0 ns min t8 15 ns min

t9 13 ns min t10 0 ns min

1

Guaranteed by design and characterization, not production tested.

2

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

TIMING DIAGRAM

t

10

SCLK

t

8

SYNC

DIN

MIN

t

to T

MIN

, T

MAX

4

, unless otherwise noted.1

MAX

t

1

t

3

t

6

t

5

2

DB0DB23

Figure 2. Serial Write Operation

to SCLK falling edge setup time

SYNC

SCLK falling edge to SYNC Minimum SYNC

rising edge to SCLK fall ignore

SYNC SCLK falling edge to SYNC

t

9

t

7

high time

rising edge

fall ignore

05856-002

Rev. B | Page 7 of 28

AD5624R/AD5644R/AD5664R

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to VDD + 0.3 V

OUT

V

REFIN/VREFOUT

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Operating Temperature Range

Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θJA Thermal Impedance

LFCSP_WD Package (4-Layer Board)

MSOP Package (4-Layer Board)

Reflow Soldering Peak Temperature

Pb-Free 260°C ± 5°C

to GND −0.3 V to VDD + 0.3 V

θJA

θJA 142°C/W θJC 43.7°C/W

61°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 8 of 28

AD5624R/AD5644R/AD5664R

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

A

OUT

V

OUT

V

OUT

V

OUT

AD5624R/

2

B

AD5644R/

3

GND

AD5664R

4

C

TOP VIEW

(Not to Scale)

5

D

EXPOSED PAD TIED TO

GND ON LFCSP PACKAGE

10

V

REFIN/VREFOUT

9

V

DD

8

DIN

7

SCLK

6

SYNC

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

3 GND Ground Reference Point for all Circuitry on the Part. 4 V 5 V 6

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

SYNC

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

7 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz.

8 DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

9 VDD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

10 V

REFIN/VREFOUT

The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input.

05856-003

Rev. B | Page 9 of 28

ANALOG DEVICES AD5624R Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AD5624R-5/AD5644R-5/AD5664R-5

AD5624R-3/AD5644R-3/AD5664R-3

AC CHARACTERISTICS

TIMING CHARACTERISTICS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS