Analog Devices AD5308 18 28 b Datasheet

2.5 V to 5.5 V Octal Voltage Output

8-/10-/12-Bit DACs in 16-Lead TSSOP

FEATURES
AD5308: 8 Buffered 8-Bit DACs in 16-Lead TSSOP

A Version: ⴞ1 LSB INL, B Version: ⴞ0.75 LSB INL

AD5318: 8 Buffered 10-Bit DACs in 16-Lead TSSOP

A Version: ⴞ4 LSB INL, B Version: ⴞ3 LSB INL

AD5328: 8 Buffered 12-Bit DACs in 16-Lead TSSOP

A Version: ⴞ16 LSB INL, B Version: ⴞ12 LSB INL
Low Power Operation: 0.7 mA @ 3 V
Guaranteed Monotonic by Design over All Codes
Power-Down to 120 nA @ 3 V, 400 nA @ 5 V
Double-Buffered Input Logic
Buffered/Unbuffered/V
Output Range: 0 V to V

Reference Input Options

DD

or 0 V to 2 V

REF

REF

Power-On Reset to 0 V
Programmability

Individual Channel Power-Down

Simultaneous Update of Outputs (LDAC)
Low Power, SPI

®

, QSPI™, MICROWIRE™, and DSP

Compatible 3-Wire Serial Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40ⴗC to +105ⴗC

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Optical Networking
Automatic Test Equipment

FUNCTIONAL BLOCK DIAGRAM

V

DD

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

SCLK

SYNC

DIN

LDAC

INTERFACE

LOGIC

AD5308/AD5318/AD5328

Mobile Communications
Programmable Attenuators
Industrial Process Control

GENERAL DESCRIPTION

The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP. They operate
from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typ at 3 V.
Their on-chip output amplifiers allow the outputs to swing
rail-to-rail with a slew rate of 0.7 V/µs. The AD5308/AD5318/
AD5328 use a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with standard
SPI, QSPI, MICROWIRE, and DSP interface standards.

The references for the eight DACs are derived from two reference
pins (one per DAC quad). These reference inputs can be
configured as buffered, unbuffered, or VDD inputs. The parts
incorporate a power-on reset circuit, which ensures that the DAC
outputs power up to 0 V and remain there until a valid write to
the device takes place. The outputs of all DACs may be updated
simultaneously using the asynchronous LDAC input. The parts
contain a power-down feature that reduces the current consump­tion of the devices to 400 nA at 5 V (120 nA at 3 V). The eight
channels of the DAC may be powered down individually.

All three parts are offered in the same pinout, which allows
users to select the resolution appropriate for their application
without redesigning their circuit board.

V

ABCD

REF

V

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

STRING
DAC A

STRING
DAC B

STRING
DAC C

STRING
DAC D

STRING
DAC E

STRING
DAC F

STRING
DAC G

STRING
DAC H

DD

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

GAIN-SELECT

LOGIC

A

V

OUT

B

V

OUT

C

V

OUT

D

V

OUT

E

V

OUT

V

F

OUT

G

V

OUT

H

V

OUT

*

POWER-ON

RESET

LDAC

*Protected by U.S.Patent No. 5,969,657; other patents pending.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

GAIN-SELECT

LOGIC

V

DD

EFGH

V

REF

POWER-DOWN

LOGIC

GND

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5308/AD5318/AD5328–SPECIFICATIONS

GND; C

= 200 pF to GND; all specifications T

L

Parameter

DC PERFORMANCE

1

3, 4

Min Typ Max Min Typ Max Unit Conditions/Comments

to T

MIN

A Version

, unless otherwise noted.)

MAX

2

B Version

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to

REF

AD5308

Resolution 8 8 Bits
Relative Accuracy ±0.15 ±1 ±0.15 ±0.75 LSB
Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed Monotonic by Design over All Codes

AD5318

Resolution 10 10 Bits
Relative Accuracy ±0.5 ±4 ±0.5 ±3 LSB
Differential Nonlinearity ±0.05 ±0.50 ±0.05 ±0.50 LSB Guaranteed Monotonic by Design over All Codes

AD5328

Resolution 12 12 Bits
Relative Accuracy ±2 ±16 ±2 ±12 LSB

Differential Nonlinearity ±0.2 ±1.0 ±0.2 ±1.0 LSB Guaranteed Monotonic by Design over All Codes
Offset Error ±5 ±60 ±5 ±60 mV VDD = 4.5 V, Gain = +2. See Figures 2 and 3.
Gain Error ±0.30 ±1.25 ±0.30 ±1.25 % of FSR VDD = 4.5 V, Gain = +2. See Figures 2 and 3.
Lower Deadband

Upper Deadband

Offset Error Drift
Gain Error Drift
DC Power Supply Rejection Ratio
DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 1.0 VDD1.0 V

REF

V

Input Impedance (R

REF

5

5

6

6

6

6

6

) >10.0 >10.0 MΩ Buffered Reference Mode and Power-Down Mode

DAC

10 60 10 60 mV See Figure 2. Lower deadband exists only if offset

error is negative.

10 60 10 60 mV See Figure 3. Upper deadband exists only if V

VDD and offset plus gain error is positive.

–12 –12 ppm of FSR/°C
–5 –5 ppm of FSR/°C
–60 –60 dB VDD = ± 10%
200 200 µVR

V Buffered Reference Mode

0.25 VDD0.25 V

DD

V Unbuffered Reference Mode

DD

37.0 45.0 37.0 45.0 kΩ Unbuffered Reference Mode. 0 V to V

18.0 22.0 18.0 22.0 kΩ Unbuffered Reference Mode. 0 V to 2 V

= 2 kΩ to GND or V

L

Output Range.

Output Range.

DD

REF

REF

Reference Feedthrough –70.0 –70.0 dB Frequency = 10 kHz
Channel-to-Channel Isolation –75.0 –75.0 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

6

7

7

0.001 0.001 V This is a measure of the minimum and maximum
VDD – 0.001 VDD – 0.001 V drive capability of the output amplifier.

DC Output Impedance 0.5 0.5 Ω
Short Circuit Current 25.0 25.0 mA VDD = 5 V

16.0 16.0 mA VDD = 3 V

Power-Up Time 2.5 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V.

5.0 5.0 µs Coming Out of Power-Down Mode. VDD = 3 V.

LOGIC INPUTS

6

Input Current ±1 ±1 µA
VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

0.8 0.8 V VDD = 3 V ± 10%

0.7 0.7 V VDD = 2.5 V

VIH, Input High Voltage 1.7 1.7 V VDD = 2.5 V to 5.5 V; TTL and CMOS

Compatible

Pin Capacitance 3.0 3.0 pF

POWER REQUIREMENTS

V

DD

IDD (Normal Mode)

8

2.5 5.5 2.5 5.5 V
VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 1.0 1.8 1.0 1.8 mA All DACs in Unbuffered Mode. In Buffered mode,
VDD = 2.5 V to 3.6 V 0.7 1.5 0.7 1.5 mA extra current is typically x µA per DAC; x = (5 µA

IDD (Power-Down Mode)

9

+ V
VIH = VDD and VIL = GND

REF/RDAC

)/4.

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA
VDD = 2.5 V to 3.6 V 0.12 1 0.12 1 µA

NOTES

1

See the Terminology section.

2

Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.

3

DC specifications tested with the outputs unloaded unless stated otherwise.

4

Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).

5

This corresponds to x codes. x = deadband voltage/LSB size.

6

Guaranteed by design and characterization; not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its maximum voltage, V
must be positive.

8

Interface inactive. All DACs active. DAC outputs unloaded.

9

All eight DACs powered down.

= VDD and offset plus gain error

REF

Specifications subject to change without notice.

REF

=

REV. B–2–

AD5308/AD5318/AD5328

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

1

AC CHARACTERISTICS

Parameter

2

otherwise noted.)

A, B Version

3

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

= VDD = 5 V

REF

MIN

to T

MAX

, unless

AD5308 6 8 µs 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5318 7 9 µs 1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
AD5328 8 10 µs 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)

Slew Rate 0.7 V/µs
Major-Code Change Glitch Energy 12 nV-s 1 LSB Change around Major Carry
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

1, 2, 3

= 2 V ± 0.1 V p-p. Unbuffered Mode.

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz.

REF

A, B Version

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

NOTES

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figures 2 and 3.

Specifications subject to change without notice.

33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
13 ns min SYNC to SCLK Falling Edge Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
50 ns min Minimum SYNC High Time
20 ns min LDAC Pulsewidth
20 ns min SCLK Falling Edge to LDAC Rising Edge
0 ns min SCLK Falling Edge to LDAC Falling Edge

MIN

, T

MAX

Unit Conditions/Comments

t

1

REV. B

SCLK

t

8

SYNC

DIN DB15

1

LDAC

2

LDAC

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE

2

SYNCHRONOUS LDAC UPDATE MODE

t

t

t

4

t

6

t

5

3

2

t

7

DB0

t

9

t

11

t

10

Figure 1. Serial Interface Timing Diagram

–3–

AD5308/AD5318/AD5328

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

V

OUT

A–V

D to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (A, B Version) . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

J MAX

1, 2

+ 0.3 V

DD

+ 0.3 V

DD

) . . . . . . . . . . . . . . . . . . . 150°C

16-Lead TSSOP

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

J MAX

– TA)/␪

␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5308ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5308ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRUZ* –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRUZ-REEL* –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRUZ-REEL7* –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16

*Z = Pb-free part.

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5308/AD5318/AD5328 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. B–4–

PIN CONFIGURATION

AD5308/AD5318/AD5328

LDAC

1

SYNC

2

AD5308/

V

3

AD5318/

DD

A

4

B

5

(Not to Scale)

C

6

D

7

8

AD5328

TOP VIEW

V

OUT

V

OUT

V

OUT

V

OUT

V

ABCD

REF

SCLK

16

DIN

15

GND

14

H

V

13

OUT

G

V

12

OUT

F

V

11

OUT

V

E

10

OUT

V

EFGH

9

REF

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 LDAC This active low-control input transfers the contents of the input registers to their respective DAC registers.

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

2 SYNC Active Low-Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

3V

DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4V

5V

6V

7V

8V

ABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

BBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

CBuffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

DBuffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

ABCD Reference Input Pin for DACs A, B, C, and D. It may be configured as a buffered, unbuffered, or V

REF

DD

input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range

9V

EFGH Reference Input Pin for DACs E, F, G, and H. It may be configured as a buffered, unbuffered, or V

REF

from 0.25 V to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

DD

input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

10 V

11 V

12 V

13 V

from 0.25 V to V

EBuffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

OUT

FBuffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

OUT

GBuffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

OUT

HBuffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

OUT

14 GND Ground Reference Point for All Circuitry on the Part.

15 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input. The DIN input buffer is powered down after each write cycle.

16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after
each write cycle.

REV. B

–5–

AD5308/AD5318/AD5328

TERMINOLOGY
Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus code plots can be seen in TPCs 1, 2, and 3.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in TPCs 4, 5, and 6.

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier (see Figures 2 and 3). It can be negative or positive,
and is expressed in mV.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V

OUT

to a change in VDD for full-scale output of the DAC. It is mea­sured in dB. V

DC Crosstalk

is held at 2 V and VDD is varied ±10%.

REF

This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in µV.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC out­put to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dB.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in dB.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital input pins of the device,
but is measured when the DAC is not being written to (SYNC
held high). It is specified in nV-s and is measured with a full­scale change on the digital input pins, i.e., from all 0s to all 1s
and vice versa.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with LDAC low and
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonics present
on the DAC output. It is measured in dB.

REV. B–6–