ANALOG DEVICES AD5308, AD5318, AD5328 Service Manual

2.5 V to 5.5 V Octal Voltage Output

FEATURES

AD5308: 8 buffered 8-bit DACs in 16-lead TSSOP

A version: ±1 LSB INL, B version: ±0.75 LSB INL

AD5318: 8 buffered 10-bit DACs in 16-lead TSSOP

A version: ±4 LSB INL, B version: ±3 LSB INL

AD5328: 8 buffered 12-bit DACs in 16-lead TSSOP

A version: ±16 LSB INL, B version: ±12 LSB INL Low power operation: 0.7 mA @ 3 V Guaranteed monotonic by design over all codes Power-down to 120 nA @ 3 V, 400 nA @ 5 V Double-buffered input logic Buffered/unbuffered/V Output range: 0 V to V Power-on reset to 0 V Programmability

Individual channel power-down

Simultaneous update of outputs ( Low power, SPI-®, QSPI-™, MICROWIRE-™, and DSP-

compatible 3-wire serial interface On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +125°C Qualified for automotive applications

reference input options

DD

or 0 V to 2 V

REF

LDAC

)

8-/10-/12-Bit DACs in 16-Lead TSSOP

AD5308/AD5318/AD5328

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Optical networking Automatic test equipment Mobile communications Programmable attenuators Industrial process control

GENERAL DESCRIPTION

The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit buffered voltage output DACs in a 16-lead TSSOP. They operate from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/s. The AD5308/ AD5318/AD5328 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.

The references for the eight DACs are derived from two reference pins (one per DAC quad). These reference inputs can be configured as buffered, unbuffered, or V

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

inputs. The parts

DD

incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. The outputs of all DACs may be updated simultaneously using the asynchronous

LDAC

The parts contain a power-down feature that reduces the current consumption of the devices to 400 nA at 5 V (120 nA at 3 V). The eight channels of the DAC may be powered down individually.

All three parts are offered in the same pinout, which allows users to select the resolution appropriate for their application without redesigning their circuit board.

input.

AD5308/AD5318/AD5328

REVISION HISTORY

4/11—Rev. E to Rev. F

Added Automotive Products Information................. Throughout

2/11—Rev. D to Rev. E

Change to Temperature Range ....................................Throughout

Changes to Table 3, t

3/07—Rev. C to Rev. D

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings Section......................... 7

9/05—Rev. B to Rev. C

Updated Format..................................................................Universal

Change to Equation........................................................................ 21

11/03—Rev. A to Rev. B

Changes to Ordering Guide............................................................ 4

Changes to Y axis on TPCs 12, 13, and 15.................................... 9

8/03—Rev. 0 to Rev. A

Added A Version.................................................................Universal

Changes to Features.......................................................................... 1

Changes to Specifications................................................................ 2

Edits to Absolute Maximum Ratings ............................................. 4

Edits to Ordering Guide .................................................................. 4

Updated Outline Dimensions....................................................... 18

Timing Characteristics.............................. 6

4

Rev. F | Page 2 of 28

AD5308/AD5318/AD5328

V

A

FUNCTIONAL BLOCK DIAGRAM

V

DD

REF

BCD

V

DD

GAIN-SELECT

LOGIC

SCLK

SYNC

DIN

LDAC

INTERFACE

LOGIC

LDAC

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

RESET

INPUT

REGISTER

POWER-ON

RESET

DAC

REGISTER

STRING

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

Figure 1.

STRING

BUFFER

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

STRING

DAC E

STRING

DAC F

STRING

DAC G

STRING

DD

DAC H

V

REF

EFGH

V

DD

BUFFERBUFFER

GND

GAIN-SELECT

LOGIC

POWER-DOWN

LOGIC

GND

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

02812-001

A

B

C

D

E

F

G

H

Rev. F | Page 3 of 28

AD5308/AD5318/AD5328

SPECIFICATIONS

VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

REF

MIN

to T

, unless otherwise specified.

MAX

Table 1.

A Version1

B Version

Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments

DC PERFORMANCE

3, 4

AD5308

Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.75 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by

AD5318

Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±3 LSB Differential Nonlinearity ±0.05 ±0.50 ±0.05 ±0.50 LSB Guaranteed monotonic by

AD5328

Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±12 LSB Differential Nonlinearity ±0.2 ±1.0 ±0.2 ±1.0 LSB Guaranteed monotonic by

Offset Error ±5 ±60 ±5 ±60 mV VDD = 4.5 V, gain = 2, see

1

design over all codes

Figure 27 and Figure 28

Gain Error ±0.30 ±1.25 ±0.30 ±1.25 % of FSR VDD = 4.5 V, gain = 2, see

Figure 27 and Figure 28

Lower Deadband5 10 60 10 60 mV Lower deadband exists only

if offset error is negative, see

Figure 27

Upper Deadband5

10 60 10 60 mV Upper deadband exists only

= VDD and offset plus

if V

REF

gain error is positive, see

Figure 28

Offset Error Drift6 −12 −12 ppm of

FSR/°C

Gain Error Drift6

−5 −5 ppm of FSR/°C

DC Power Supply Rejection Ratio6 DC Crosstalk6

DAC REFERENCE INPUTS6

V

Input Range 1.0 VDD 1.0 VDD V Buffered reference mode

REF

−60 −60 dB V

200 200 μV R

= ±10%

DD

= 2 kΩ to GND or VDD

L

0.25 VDD 0.25 VDD V Unbuffered reference mode V

Input Impedance (R

REF

) >10.0 >10.0 MΩ Buffered reference mode

DAC

and power-down mode

37.0 45.0 37.0 45.0 kΩ Unbuffered reference mode,

0 V to V

output range

REF

18.0 22.0 18.0 22.0 kΩ Unbuffered reference mode,

0 V to 2 V

output range

REF

Reference Feedthrough −70.0 −70.0 dB Frequency = 10 kHz Channel-to-Channel Isolation −75.0 −75.0 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS6

Minimum Output Voltage7 0.001 0.001 V This is a measure of the

minimum and maximum

Maximum Output Voltage7

V

−

DD

0.001

V

− 0.001 V Drive capability of the

DD

output amplifier

DC Output Impedance 0.5 0.5 Ω

Rev. F | Page 4 of 28

AD5308/AD5318/AD5328

A Version1

B Version

1

Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments

Short Circuit Current 25.0 25.0 mA VDD = 5 V

16.0 16.0 mA VDD = 3 V Power-Up Time 2.5 2.5 μs Coming out of power-down

mode, V

= 5 V

DD

5.0 5.0 μs Coming out of power-down = 3 V

DD

LOGIC INPUTS6

mode, V

Input Current ±1 ±1 μA VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

0.8 0.8 V VDD = 3 V ± 10%

0.7 0.7 V VDD = 2.5 V VIH, Input High Voltage 1.7 1.7 V VDD = 2.5 V to 5.5 V, TTL and

CMOS compatible

Pin Capacitance 3.0 3.0 pF

POWER REQUIREMENTS

VDD 2.5 5.5 2.5 5.5 V IDD (Normal Mode)8 VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 1.0 1.8 1.0 1.8 mA All DACs in unbuffered

mode, in buffered mode

VDD = 2.5 V to 3.6 V 0.7 1.5 0.7 1.5 mA Extra current is typically x μA

per DAC; x = (5 μA +

)/4

V

REF/RDAC

IDD (Power-Down Mode)9 VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 μA VDD = 2.5 V to 3.6 V 0.12 1 0.12 1 μA

1

Temperature range (A, B version): −40°C to +125°C; typical at 25°C.

2

See the Terminology section.

3

DC specifications tested with the outputs unloaded unless stated otherwise.

4

Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).

5

This corresponds to x codes. x = deadband voltage/LSB size.

6

Guaranteed by design and characterization; not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V

gain error must be positive.

8

Interface inactive. All DACs active. DAC outputs unloaded.

9

All eight DACs powered down.

= VDD and offset plus

REF

V

= 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

DD

1

Table 2. AC Characteristics

MIN

to T

, unless otherwise noted.

MAX

A, B Version2 Parameter3 Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

= VDD = 5 V

REF

AD5308 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0) AD5318 7 9 μs 1/4 scale to 3/4 scale change (0x100 To 0x300) AD5328 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)

Slew Rate 0.7 V/μs Major-Code Change Glitch Energy 12 nV-sec 1 LSB change around major carry Digital Feedthrough 0.5 nV-sec Digital Crosstalk 0.5 nV-sec Analog Crosstalk 1 nV-sec DAC-to-DAC Crosstalk 3 nV-sec Multiplying Bandwidth 200 kHz V Total Harmonic Distortion −70 dB V

1

Guaranteed by design and characterization; not production tested.

2

Temperature range (A, B version): –40°C to +125°C; typical at 25°C.

3

See the Terminology section.

= 2 V ± 0.1 V p-p, unbuffered mode

REF

= 2.5 V ± 0.1 V p-p, frequency = 10 kHz

REF

Rev. F | Page 5 of 28

AD5308/AD5318/AD5328

Table 3. Timing Characteristics

1, 2, 3

A, B Version Parameter Limit at T

MIN

, T

Unit Conditions/Comments

MAX

t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min

to SCLK falling edge setup time; temperature range (A, B

SYNC verstion): −40°C to +105°C

15 ns min

to SCLK falling edge setup time; temperature range (A, B

SYNC

verstion): −40°C to +125°C t5 5 ns min Data set up time t6 4.5 ns min Data hold time t7 0 ns min

t8 50 ns min t9 20 ns min t10 20 ns min t11 0 ns min

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 2.

SCLK falling edge to SYNC

Minimum SYNC

pulse width

LDAC

high time

SCLK falling edge to LDAC

t

1

rising edge

rising edge falling edge

SCLK

t

8

SYNC

DIN DB15

1

LDAC

2

LDAC

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE.

2

SYNCHRONOUS LDAC UPDATE MODE.

t

4

t

6

t

5

3

2

t

7

DB0

t

9

t

11

t

10

02812-002

Figure 2. Serial Interface Timing Diagram

Rev. F | Page 6 of 28

AD5308/AD5318/AD5328

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise specified.

Table 4.

Parameter Rating1

VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Reference Input Voltage to GND −0.3 V to VDD + 0.3 V V

OUTA–VOUTD

Operating Temperature Range

Industrial (A, B Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature (T 16-Lead TSSOP

Power Dissipation (T

θJA Thermal Impedance 150.4°C/W Lead Temperature JEDEC industry-standard

Soldering J-STD-020

1

Transient currents of up to 100 mA do not cause SCR latch-up.

to GND −0.3 V to VDD + 0.3 V

) 150°C

J MAX

− TA)/θJA

J MAX

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. F | Page 7 of 28

AD5308/AD5318/AD5328

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

LDAC

2

SYNC

AD5308/

3

V

DD

AD5318/

4

V

A

OUT

V

OUT

V

OUT

V

OUT

ABCD V

REF

B C D

AD5328

5

TOP VIEW

6

(Not to Scale)

7

8

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

This active low control input transfers the contents of the input registers to their respective DAC registers. Pulsing

LDAC

this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.

2

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

SYNC

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC

is taken high before the 16th falling edge, the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the device.

3 VDD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF

capacitor in parallel with a 0.1 μF capacitor to GND. 4 V 5 V 6 V 7 V 8 V

9 V

10 V 11 V 12 V 13 V

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

ABCD

REF

EFGH

REF

E Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

OUT

F Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

OUT

G Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

OUT

H Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

OUT

Reference Input Pin for DACs A, B, C, and D. It can be configured as a buffered, unbuffered, or V

DACs, depending on the state of the BUF and V

mode and from 1 V to V

in buffered mode.

DD

control bits. It has an input range from 0.25 V to VDD in unbuffered

DD

Reference Input Pin for DACs E, F, G, and H. It can be configured as a buffered, unbuffered, or V

DACs, depending on the state of the BUF and V

mode and from 1 V to V

in buffered mode.

DD

control bits. It has an input range from 0.25 V to VDD in unbuffered

DD

14 GND Ground Reference Point for All Circuitry on the Part. 15 DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input. The DIN input buffer is powered down after each write cycle. 16 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

16

SCLK

15

DIN

14

GND

13

H

V

OUT

12

V

G

OUT

11

F

V

OUT

10

V

E

OUT

9

EFGH

REF

02812-003

input to the four

DD

input to the four

DD

Rev. F | Page 8 of 28

AD5308/AD5318/AD5328

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.5

T V

= 25°C

A

= 5V

DD

0.3

0.2

0.1

TA = 25°C V

= 5V

DD

0

INL ERROR (LSB)

–0.5

–1.0

0 50 100 150 200 250

CODE

Figure 4. AD5308 Typical INL Plot

3

= 25°C

T

A

= 5V

V

DD

2

1

0

INL ERROR (LSB)

–1

–2

–3

0 200 400 600 800 1000

CODE

Figure 5. AD5318 Typical INL Plot

02812-006

02812-007

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

0 50 100 150 200 250

CODE

Figure 7. AD5308 Typical DNL Plot

0.6 TA = 25°C

V

= 5V

DD

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

0 200 400 600 800 1000

CODE

Figure 8. AD5318 Typical DNL Plot

02812-009

02812-010

12

TA = 25°C V

= 5V

DD

8

4

0

INL ERROR (LSB)

–4

–8

–12

20001500500 10000 2500 3000 3500 4000

CODE

02812-008

Figure 6. AD5328 Typical INL Plot

1.0 TA = 25°C

V

= 5V

DD

0.5

0

DNL ERROR (LSB)

–0.5

–1.0

20001500500 10000 2500 3000 3500 4000

CODE

02812-011

Figure 9. AD5328 Typical DNL Plot

Rev. F | Page 9 of 28

ANALOG DEVICES AD5308, AD5318, AD5328 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS