Analog Devices AD5307 17 27 a Datasheet

2.5 V to 5.5 V, 400 ␮A, Quad Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP

FEATURES
AD5307: 4 Buffered 8-Bit DACs in 16-Lead TSSOP

A Version: ⴞ1 LSB INL, B Version: ⴞ0.625 LSB INL

AD5317: 4 Buffered 10-Bit DACs in 16-Lead TSSOP

A Version: ⴞ4 LSB INL, B Version: ⴞ2.5 LSB INL

AD5327: 4 Buffered 12-Bit DACs in 16-Lead TSSOP

A Version: ⴞ16 LSB INL, B Version: ⴞ10 LSB INL

Low Power Operation: 400 ␮A @ 3 V, 500 ␮A @ 5 V

2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 90 nA @ 3 V, 300 nA @ 5 V (PD Pin)
Double-Buffered Input Logic
Buffered/Unbuffered Reference Input Options
Output Range: 0 V to V

or 0 V to 2 V

REF

REF

Power-On Reset to 0 V
Simultaneous Update of Outputs (LDAC Pin)
Asynchronous Clear Facility (CLR Pin)
Low Power, SPI

®

, QSPI™, MICROWIRE™, and DSP

Compatible 3-Wire Serial Interface
SDO Daisy-Chaining Option
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40ⴗC to +105ⴗC

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources

AD5307/AD5317/AD5327

*

Programmable Attenuators
Industrial Process Control

GENERAL DESCRIPTION

The AD5307/AD5317/AD5327 are quad 8-, 10-, and 12-bit
buffered voltage-output DACs in a 16-lead TSSOP package that
operate from a single 2.5 V to 5.5 V supply, consuming 400 mA
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/ms. The AD5307/
AD5317/AD5327 utilize a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface standards.

The references for the four DACs are derived from two refer­ence pins (one per DAC pair). These reference inputs can be
configured as buffered or unbuffered inputs. The parts incorpo­rate a power-on reset circuit, which ensures that the DAC outputs
power up to 0 V and remain there until a valid write to the device
takes place. There is also an asynchronous active low CLR pin
that clears all DACs to 0 V. The outputs of all DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the cur­rent consumption of the devices to 300 nA @ 5 V (90 nA @
3 V). The parts may also be used in daisy-chaining applications
using the SDO pin.

All three parts are offered in the same pinout, which allows users
to select the amount of resolution appropriate for their applica­tion without redesigning their circuit board.

FUNCTIONAL BLOCK DIAGRAM

AD5307/AD5317/AD5327

LDAC

INPUT

REGISTER

SCLK

SYNC

DIN

SDO

*Protected by U.S. Patent No. 5,969,657; other patents pending.

INTERFACE

LOGIC

DCEN

LDAC PD

CLR

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON

RESET

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

V

V

DD

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

V

REF

AB

CD

GAIN-SELECT

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOWN

LOGIC

LOGIC

GND

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

AD5307/AD5317/AD5327–SPECIFICATIONS

= 200 pF to GND; all specifications T

GND; C

L

Parameter

DC PERFORMANCE

1

3, 4

A Version
Min Typ Max Min Typ Max Unit Conditions/Comments

MIN

to T

, unless otherwise noted.)

MAX

2

B Version

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to

REF

AD5307

Resolution 8 8 Bits
Relative Accuracy ± 0.15 ± 1 ± 0.15 ± 0.625 LSB
Differential Nonlinearity ± 0.02 ± 0.25 ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design

over All Codes

AD5317

Resolution 10 10 Bits
Relative Accuracy ± 0.5 ± 4 ± 0.5 ± 2.5 LSB
Differential Nonlinearity ± 0.05 ± 0.5 ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design

over All Codes

AD5327

Resolution 12 12 Bits
Relative Accuracy ± 2 ± 16 ± 2 ± 10 LSB
Differential Nonlinearity ± 0.2 ± 1 ± 0.2 ± 1 LSB Guaranteed Monotonic by Design

over All Codes

Offset Error ± 5 ± 60 ± 5 ± 60 mV V

= 4.5 V, Gain = 2;

DD

See Figures 4 and 5

Gain Error ± 0.3 ± 1.25 ± 0.3 ± 1.25 % of FSR V

Lower Deadband

Upper Deadband

Offset Error Drift

Gain Error Drift

6

5

5

6

10 60 10 60 mV See Figure 4. Lower deadband exists

10 60 10 60 mV See Figure 5. Upper deadband exists

–12 –12 ppm of

FSR/∞C

–5 –5 ppm of

= 4.5 V, Gain = 2;

DD

See Figures 4 and 5.

only if offset error is negative.

only if V

= VDD and offset plus

REF

gain error is positive.

FSR/∞C

DC Power Supply Rejection

6

Ratio

DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 1 V

REF

6

6

0.25 V

Input Impedance (R

V

REF

) >10 >10 MW Buffered Reference Mode and

DAC

–60 –60 dB ⌬VDD = ± 10%
200 200 mVR

1V

DD

0.25 V

DD

V Buffered Reference Mode

DD

V Unbuffered Reference Mode

DD

= 2 kW to GND or V

L

DD

Power-Down Mode

74 90 74 90 kW Unbuffered Reference Mode.

0 V to V

Output Range

REF

37 45 37 45 kW Unbuffered Reference Mode.

0 V to 2 V

Output Range

REF

Reference Feedthrough –90 –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –75 –75 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

6

7

7

0.001 0.001 V This is a measure of the minimum
VDD – 0.001 VDD – 0.001 V and maximum drive capability of the

output amplifier.

DC Output Impedance 0.5 0.5 W
Short Circuit Current 25 25 mA V

16 16 mA V

DD

DD

= 5 V
= 3 V

Power-Up Time 2.5 2.5 ms Coming out of Power-Down Mode.

= 5 V

V

DD

55ms Coming out of Power-Down Mode.

VDD = 3 V

REV. A–2–

AD5307/AD5317/AD5327

Parameter

1

LOGIC INPUTS

A Version

2

B Version

Min Typ Max Min Typ Max Unit Conditions/Comments

6

2

Input Current ± 1 ± 1 mA

, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

V

IL

, Input High Voltage

V

IH

(Excluding DCEN) 1.7 1.7 V V

0.6 0.6 V V

0.5 0.5 V V

= 3 V ± 10%

DD

= 2.5 V

DD

= 2.5 V to 5.5 V; TTL and 1.8 V

DD

CMOS Compatible

, Input High Voltage

V

IH

(DCEN) 2.4 2.4 V V

2.1 2.1 V V

2.0 2.0 V V

= 5 V ± 10%

DD

= 3 V ± 10%

DD

= 2.5 V

DD

Pin Capacitance 3 3 pF

LOGIC OUTPUT (SDO)

6

VDD = 4.5 V to 5.5 V

Output Low Voltage, V
Output High Voltage, V

V

= 2.5 V to 3.6 V

DD

Output Low Voltage, V
Output High Voltage, V

OL

OL

OH

OH

0.4 0.4 V I

VDD – 1 VDD – 1 V I

0.4 0.4 V I

VDD – 0.5 VDD – 0.5 V I

= 2 mA

SINK

SOURCE

= 2 mA

SINK

SOURCE

= 2 mA

= 2 mA

Floating State Leakage Current ± 1 ± 1 mA DCEN = GND
Floating State Output

Capacitance 3 3 pF DCEN = GND

POWER REQUIREMENTS

V

DD

(Normal Mode)

I

DD

V

= 4.5 V to 5.5 V 500 900 500 900 mA All DACs in Unbuffered Mode.

DD

8

2.5 5.5 2.5 5.5 V
VIH = VDD and VIL = GND

In Buffered Mode, extra current is
typically x mA per DAC

= 2.5 V to 3.6 V 400 750 400 750 mA where x = 5 mA + V

V

DD

(Power-Down Mode) VIH = VDD and VIL = GND

I

DD

= 4.5 V to 5.5 V 0.3 1 0.3 1 mA

V

DD

VDD = 2.5 V to 3.6 V 0.09 1 0.09 1 mA

NOTES

1

See the Terminology section.

2

Temperature range (A, B Versions): –40∞C to +105∞C; typical at +25∞C.

3

DC specifications tested with the outputs unloaded, unless stated otherwise.

4

Linearity is tested using a reduced code range: AD5307 (Code 8 to 255); AD5317 (Code 28 to 1023); AD5327 (Code 115 to 4095).

5

This corresponds to x codes. x = Deadband Voltage/LSB size.

6

Guaranteed by design and characterization; not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its maximum voltage, V
plus gain error must be positive.

8

Interface inactive. All DACs active. DAC outputs unloa-ded.

Specifications subject to change without notice.

REF/RDAC

REF

.

= VDD and offset

REV. A

–3–

AD5307/AD5317/AD5327

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

AC CHARACTERISTICS

Parameter

2

1

otherwise noted.)

A, B Versions

3

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

= VDD = 5 V

REF

MIN

to T

, unless

MAX

AD5307 6 8 ms 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5317 7 9 ms 1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
AD5327 8 10 ms 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)

Slew Rate 0.7 V/ms
Major-Code Change Glitch Energy 12 nV-s 1 LSB Change around Major Carry
Digital Feedthrough 0.5 nV-s
SDO Feedthrough 4 nV-s Daisy-Chain Mode; SDO Load is 10 pF
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range (A, B Versions): –40∞C to +105∞C; typical at +25∞C.

Specifications subject to change without notice.

1, 2, 3

TIMING CHARACTERISTICS

(VDD = 2.5 V to 5.5 V; all specifications T

= 2 V ± 0.1 V p-p. Unbuffered Mode

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

REF

to T

MIN

, unless otherwise noted.)

MAX

A, B Versions

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

4, 5

t

13

5

t

14

5

t

15

5

t

16

NOTES

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figures 2 and 3.

4

This is measured with the load circuit of Figure 1. t13 determines maximum SCLK frequency in Daisy-Chain mode.

5

Daisy-chain mode only.

Specifications subject to change without notice.

33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
13 ns min SYNC to SCLK Falling Edge Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
50 ns min Minimum SYNC High Time
20 ns min LDAC Pulsewidth
20 ns min SCLK Falling Edge to LDAC Rising Edge
20 ns min CLR Pulsewidth
0 ns min SCLK Falling Edge to LDAC Falling Edge
20 ns max SCLK Rising Edge to SDO Valid (VDD = 3.6 V to 5.5 V)
25 ns max SCLK Rising Edge to SDO Valid (V
5 ns min SCLK Falling Edge to SYNC Rising Edge
8 ns min SYNC Rising Edge to SCLK Rising Edge
0 ns min SYNC Rising Edge to LDAC Falling Edge

MIN

, T

MAX

Unit Conditions/Comments

= 2.5 V to 3.5 V)

DD

REV. A–4–

2mA

AD5307/AD5317/AD5327

I

OL

Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications

SCLK

t

t

8

SYNC

DIN

1

LDAC

2

LDAC

CLR

NOTES

ASYNCHRONOUS LDAC UPDATE MODE.

1

SYNCHRONOUS LDAC UPDATE MODE.

2

DB15

TO OUTPUT

PIN

C

L

50pF

I

2mA

OH

t

1

t

2

DB0

t

7

t

9

t

12

t

4

t

5

3

t

6

Figure 2. Serial Interface Timing Diagram

V

OH (MIN)

t

10

t

11

REV. A

SCLK

SYNC

LDAC

DIN

SDO

t

1

t

t

t

t

4

8

t

5

DB15

INPUT WORD FOR DAC N INPUT WORD FOR DAC (N+1)

3

t

6

UNDEFINED INPUT WORD FOR DAC N

2

DB0 DB15' DB0'

t

13

DB15

t

14

DB0

t

15

t

16

t

9

Figure 3. Daisy-Chaining Timing Diagram

–5–

AD5307/AD5317/AD5327

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

V

OUT

A–V

D to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . –40∞C to +105∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature (T

max) . . . . . . . . . . . . . . . . . . . 150∞C

J

1, 2

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

16-Lead TSSOP

Power Dissipation . . . . . . . . . . . . . . . . . . (T

max – TA)/␪

J

␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4∞C/W

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5307ARU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5307ARU-REEL 7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5307BRU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5307BRU-REEL –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5307BRU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317ARU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317ARU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317BRU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317BRU-REEL –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317BRU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327ARU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327ARU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327BRU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327BRU-REEL –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327BRU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5307/AD5317/AD5327 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. A–6–

PIN CONFIGURATION

AD5307/AD5317/AD5327

V

V

LDAC

V

OUT

V

OUT

V

OUT

REF

REF

CLR

V

AB

CD

DD

1

2

3

4

A

5

B

(Not to Scale)

6

C

7

8

AD5307/
AD5317/

AD5327

TOP VIEW

16

SDO

15

SYNC

14

SCLK

13

DIN

12

GND

11

V

D

OUT

10

PD

DCEN

9

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 CLR Active Low Control Input that Loads All Zeros to All Input and DAC Registers. Therefore, the outputs

also go to 0 V.

2 LDAC Active Low Control Input that Transfers the Contents of the Input Registers to their Respective DAC

Registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied
permanently low.

3V

DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 mF capacitor in parallel with a 0.1 mF capacitor to GND.

4V

5V

6V

7V

ABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

BBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

CBuffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

AB Reference Input Pin for DACs A and B. It may be configured as a buffered or an unbuffered input to each or

REF

both of the DACs, depending on the state of the BUF bits in the serial input words to DACs A and B. It

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

8V

CD Reference Input Pin for DACs C and D. It may be configured as a buffered or an unbuffered input to each or

REF

has an input range from 0.25 V to V

both of the DACs, depending on the state of the BUF bits in the serial input words to DACs C and D. It
has an input range from 0.25 V to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

9 DCEN This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a

daisy chain. The pin should be tied low if it is being used in standalone mode.

10 PD Active low control input that acts as a hardware power-down option. All DACs go into power-down

mode when this pin is tied low. The DAC outputs go into a high impedance state and the current con­sumption of the part drops to 300 nA @ 5 V (90 nA @ 3 V).

11 V

DBuffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

12 GND Ground Reference Point for All Circuitry on the Part.

13 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input. The DIN input buffer is powered down after each write cycle.

14 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after
each write cycle.

15 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

16 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading

back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge
of SCLK and is valid on the falling edge of the clock.

REV. A

–7–

AD5307/AD5317/AD5327

TERMINOLOGY
Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus code plots can be seen in TPCs 1, 2, and 3.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in TPCs 4, 5, and 6.

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier. (See Figures 4 and 5.) It can be negative or positive.
It is expressed in mV.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/∞C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/∞C.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V

OUT

to a change in VDD for full-scale output of the DAC. It is mea­sured in dB. V

DC Crosstalk

is held at 2 V and VDD is varied ± 10%.

REF

This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in mV.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC output
to the reference input when the DAC output is not being updated
(i.e., LDAC is high). It is expressed in dB.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in dB.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . .
00 or 100 . . . 00 to 011 . . . 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital input pins of the device,
but is measured when the DAC is not being written to the (SYNC
held high). It is specified in nV-s and is measured with a full­scale change on the digital input pins, i.e., from all 0s to all 1s
or vice versa.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with LDAC low and
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonics present
on the DAC output. It is measured in dB.

REV. A–8–