Analog Devices AD5306 16 26 d Datasheet

2.5 V to 5.5 V, 400 µA, 2-Wire Interface,

FEATURES

AD5306: 4 buffered 8-bit DACs in 16-lead TSSOP
A version: ±1 LSB INL, B version: ±0.625 LSB INL
AD5316: 4 buffered 10-bit DACs in 16-lead TSSOP
A version: ±4 LSB INL, B version: ±2.5 LSB INL
AD5326: 4 buffered 12-bit DACs in 16-lead TSSOP
A version: ±16 LSB INL, B version: ±10 LSB INL
Low power operation: 400 µA @ 3 V, 500 µA @ 5 V
2-wire (I

2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 90 nA @ 3 V, 300 nA @ 5 V (

Double-buffered input logic
Buffered/unbuffered reference input options
Output range: 0 V to V
Power-on reset to 0 V
Simultaneous update of outputs (

Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
Temperature range −40°C to +105°C

APPLICATIONS

Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control

1

Protected by U.S. Patent Numbers 5,969,657 and 5,684,481.

2

C®-compatible) serial interface

or 0 V to 2 V

REF

LDAC

REF

pin)

pin or bit)

PD

Quad Voltage Output, 8-/10-/12-Bit DACs

AD5306/AD5316/AD5326

FUNCTIONAL BLOCK DIAGRAM

V

DD

AD5306/AD5316/AD5326

LDAC

SCL
SDA

A1
A0

POWER-ON

RESET

LDAC

INTERFACE

LOGIC

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

Figure 1.

GENERAL DESCRIPTION

The AD5306/AD5316/AD53261 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP, which operate
from a single 2.5 V to 5.5 V supply, consuming 500 µA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/µs. A 2-wire serial interface, which
operates at clock rates up to 400 kHz, is used. This interface is
SMBus-compatible at V
placed on the same bus.

Each DAC has a separate reference input that can be configured
as buffered or unbuffered. The outputs of all DACs may be
updated simultaneously using the asynchronous

The parts incorporate a power-on reset circuit, which ensures
that the DAC outputs power up to 0 V and remain there until a
valid write to the device takes place. The software clear function
clears all DACs to 0 V. The parts contain a power-down feature
that reduces the current consumption of the device to 300 nA @
5 V (90 nA @ 3 V).

All three parts have the same pinout, which allows users to select
the amount of resolution appropriate for their application without
redesigning their circuit board.

< 3.6 V. Multiple devices can be

DD

REF

REF

V

A

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

D

V

REF

REF

BV

BUFFER

BUFFER

BUFFER

BUFFER

CV

POWER-DOWN

LOGIC

LDAC

V

V

V

V

GNDPD

input.

A

OUT

B

OUT

C

OUT

D

OUT

02066-001

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5306/AD5316/AD5326

TABLE OF CONTENTS

Specifications..................................................................................... 3

AC Characteristics ............................................................................ 5

Timing Characteristics..................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Te r mi n ol o g y ...................................................................................... 9

Typical Performance Characteristics ........................................... 11

Functional Description .................................................................. 15

Digital-to-Analog Section ......................................................... 15

Resistor String............................................................................. 15

DAC Reference Inputs ............................................................... 15

Output Amplifier........................................................................ 15

Power-On Reset .......................................................................... 16

Serial Interface ............................................................................16

Read/Write Sequence................................................................. 16

Pointer Byte Bits ......................................................................... 16

Input Shift Register..................................................................... 16

Default Readback Conditions................................................... 17

Multiple-DAC Write Sequence................................................. 17

Multiple-DAC Readback Sequence ......................................... 17

Write Operation.......................................................................... 18

Read Operation........................................................................... 18

Double-Buffered Interface........................................................ 19

Load DAC Input

Power-Down Mode .................................................................... 19

Applications..................................................................................... 20

Typical Application Ci r c u it ....................................................... 20

Driving V

Bipolar Operation Using the AD5306/AD5316/AD5326..... 20

Multiple Devices on One Bus ................................................... 20

AD5306/AD5316/AD5326 as a Digitally Programmable
Window Detector

Coarse and Fine Adjustment Using the
AD5306/AD5316/AD5326

Power Supply Decoupling ......................................................... 22

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

LDAC

............................................................. 19

from the Reference Voltage................................ 20

DD

....................................................................... 21

....................................................... 21

REVISION HISTORY

11/04—Rev. C to Rev. D

Change to Figure 31 ....................................................................... 16

Changes to Pointer Byte Section................................................... 16

Change to Figure 32 ....................................................................... 17

8/03—Rev. B to Rev. C

Added A Version.................................................................Universal

Changes to FEATURES ................................................................... 1

Changes to SPECIFICATIONS....................................................... 2

Changes to ABSOLUTE MAXIMUM RATINGS ........................ 5

Edits to ORDERING GUIDE.......................................................... 5

Changes to TPC 21......................................................................... 11

Added OCTALS section to Table I............................................... 18

Updated OUTLINE DIMENSIONS ............................................ 19

Rev. D | Page 2 of 24

4/01—Rev. A to Rev. B

Edit to Figure 6 ............................................................................... 13

Edits to RIGHT/LEFT section of Pointer Byte Bits section...... 13

Edits to Input Shift Register section ............................................ 13

Edits to Figure 7.............................................................................. 13

Edits to Figure 8.............................................................................. 14

Edits to Figure 9.............................................................................. 14

Edit to Figure 12 ............................................................................. 16

2/01—Rev. 0 to Rev. A

6/00—Revision 0: Initial Version

AD5306/AD5316/AD5326

SPECIFICATIONS

VDD = 2.5 V to 5.5 V; V

Table 1.

A Version

Parameter

DC PERFORMANCE

DAC REFERENCE INPUTS6

OUTPUT CHARACTERISTICS6

16 16 mA VDD = 3 V

5 5 µs

LOGIC INPUTS

2

3, 4

AD5306

Resolution 8 8 Bits
Relative Accuracy ±0.15 ±1 ±0.15 ±0.625 LSB
Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB

AD5316

Resolution 10 10 Bits
Relative Accuracy ±0.5 ±4 ±0.5 ±2.5 LSB
Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB

AD5326

Resolution 12 12 Bits
Relative Accuracy ±2 ±16 ±2 ±10 LSB
Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB

Offset Error ±5 ±60 ±5 ±60 mV

Gain Error ±0.3 ±1.25 ±0.3 ±1.25 % of FSR

Lower Deadband

5

Upper Deadband5 10 60 10 60 mV

Offset Error Drift

6

Gain Error Drift6 –5 –5 ppm of FSR/°C
DC Power Supply

Rejection Ratio

6

DC Crosstalk6 200 200 µV

V

Input Range 1 V

REF

0.25 V
V

Input Impedance >10 >10

REF

148 180 148 180

74 90 74 90

Reference Feedthrough −90 −90 dB Frequency = 10 kHz
Channel-to-Channel Isolation −75 −75 dB Frequency = 10 kHz

Minimum Output Voltage

Maximum Output Voltage7
DC Output Impedance 0.5 0.5

Short Circuit Current 25 25 mA VDD = 5 V

Power-Up Time 2.5 2.5 µs

= 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

REF

1

B Version1

Min Typ Max Min Typ Max Unit Conditions/Comments

10 60 10 60 mV

−12 –12 ppm of FSR/°C

–60 –60 dB

DD

DD

1 V

0.25 V

7

0.001 0.001 V

V

– 0.001 VDD – 0.001 V

DD

MIN

to T

, unless otherwise noted.

MAX

Guaranteed monotonic by
design over all codes

Guaranteed monotonic by
design over all codes

Guaranteed monotonic by
design over all codes

V

= 4.5 V, gain = 2;

DD

See Figure 4 and Figure 5
V

= 4.5 V, gain = 2;

DD

See Figure 4 and Figure 5
See Figure 4; lower deadband

exists only if offset error is
negative.

See Figure 5; upper
deadband exists only if V
V

and offset plus gain error

DD

is positive

ΔV

= ±10%

DD

R

= 2 kΩ to GND or V

L

DD

DD

V Buffered reference mode
V Unbuffered reference mode
MΩ

Buffered reference mode and

=

REF

DD

power-down mode

kΩ

kΩ

Unbuffered reference mode;
0 V to V

output range

REF

Unbuffered reference mode;
0 V to 2 V

output range

REF

This is a measure of the
minimum and maximum
drive capability of the output
amplifier.

Ω

Coming out of power-down
mode; V

DD

= 5 V

Coming out of power-down
mode; V

DD

= 3 V

Rev. D | Page 3 of 24

AD5306/AD5316/AD5326

A Version

Parameter

2

Min Typ Max Min Typ Max Unit Conditions/Comments

1

B Version1

(Excluding SCL, SDA)6

Input Current ±1 ±1 µA

VIL, Input Low Voltage 0.8 0.8 V VDD= 5 V ± 10%

0.6 0.6 V VDD= 3 V ± 10%

0.5 0.5 V VDD = 2.5 V

VIH, Input High Voltage 1.7 1.7 V

V

= 2.5 V to 5.5 V; TTL and

DD

1.8 V CMOS-compatible

Pin Capacitance 3 3 pF

LOGIC INPUTS (SCL, SDA)6

VIH, Input High Voltage 0.7 VDD VDD + 0.3 0.7 VDD VDD + 0.3 V

VIL, Input Low Voltage −0.3 0.3 VDD −0.3 0.3 VDD V

SMBus-compatible at
V

< 3.6 V

DD

SMBus-compatible at
V

< 3.6 V

DD

IIN, Input Leakage Current ±1 ±1 mA

V

, Input Hysteresis 0.05 VDD 0.05 VDD V See Figure 20

HYST

CIN, Input Capacitance 8 8 pF

Glitch Rejection 50 50 ns

Input filtering suppresses
noise spikes of less than 50 ns

LOGIC OUTPUT (SDA)6

VOL, Output Low Voltage 0.4 0.4 V I

0.6 0.6 V I

= 3 mA

SINK

= 6 mA

SINK

Three-State Leakage Current ±1 ±1 mA

Three-State Output

8 8 pF

Capacitance

POWER REQUIREMENTS

VDD 2.5 5.5 2.5 5.5 V

IDD (Normal Mode)8

V

= VDD and VIL = GND;

IH

Interface inactive

VDD = 4.5 V to 5.5 V 500 900 500 900 µA All DACs in unbuffered mode

Buffered mode, extra current
is typically x mA per DAC
where x = 5 µA + V

VDD = 2.5 V to 3.6 V 400 750 400 750 µA

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.3 1 0.3 1 µA

VDD = 2.5 V to 3.6 V 0.09 1 0.09 1 µA

V

= VDD and VIL = GND;

IH

interface inactive
I

= 3 µA (max) during

DD

readback on SDA
I

= 1.5 µA (max) during

DD

0 readback on SDA

1

Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.

2

See the Terminology section.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095).

5

This corresponds to x codes. x = deadband voltage/LSB size.

6

Guaranteed by design and characterization; not production tested.

7

For the amplifier output to reach its minimum voltage, the offset error must be negative; for the amplifier output to reach its maximum voltage, V

offset plus gain error must be positive.

8

Interface inactive; all DACs active. DAC outputs unloaded.

= VDD and the

REF

REF/RDAC

Rev. D | Page 4 of 24

AD5306/AD5316/AD5326

AC CHARACTERISTICS

VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

Table 2.

A, B Versions

1, 2

Parameter3 Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

AD5306 6 8 µs 1/4 scale to 3/4 scale change (0x40 to 0xC0)
AD5316 7 9 µs 1/4 scale to 3/4 scale change (0x100 to 0x300)

AD5326 8 10 µs 1/4 scale to 3/4 scale change (0x400 to 0xC00
Slew Rate 0.7 V/µs
Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion

−70

dB V

1

Guaranteed by design and characterization; not production tested.

2

Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.

3

See the section. Terminology

MIN

to T

, unless otherwise noted.

MAX

= VDD = 5 V

REF

= 2 V ± 0.1 V p-p, unbuffered mode

REF

= 2.5 V ± 0.1 V p-p, frequency = 10 kHz

REF

Rev. D | Page 5 of 24

AD5306/AD5316/AD5326

A

TIMING CHARACTERISTICS

1

VDD = 2.5 V to 5.5 V; all specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 3.

A, B Versions

Parameter

2

Limit at T

MIN

, T

MAX

Unit Conditions/Comments

t1 2.5 µs min SCL cycle time
t2 0.6 µs min t
t3 1.3 µs min t
t4 0.6 µs min tHD,
t5 100 ns min t

3

t

6

0.9 µs max tHD,

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

STA

, data setup time

SU,DAT

, data hold time

DAT

0 µs min
t7 0.6 µs min t
t8 0.6 µs min t
t9 1.3 µs min t

, setup time for repeated start

SU,STA

, stop condition setup time

SU,STO

, bus free time between a stop and a start condition

BUF

t10 300 ns max tR, rise time of SCL and SDA when receiving
0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible)
t11 250 ns max tF, fall time of SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS-compatible)
300 ns max tF, fall time of SCL and SDA when receiving
20 + 0.1C
t12 20 ns min

t

13

400 ns min

4

ns min tF, fall time of SCL and SDA when transmitting

B

LDAC pulse width
SCL rising edge to

LDAC rising edge

CB 400 pF max Capacitive load for each bus line

1

See Figure 2.

2

Guaranteed by design and characterization; not production tested.

3

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of

SCL’s falling edge.

4

CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

START
CONDITION

SD

t

9

t

3

SCL

t

4

1

LDAC

2

LDAC

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE.

2

SYNCHRONOUS LDAC UPDATE MODE.

t

10

t

6

t

11

t

2

t

5

REPEATED START
CONDITION

t

4

t

7

STOP
CONDITION

t

1

t

13

t

12

t

8

t

12

02066-002

Figure 2. 2-Wire Serial Interface Timing Diagram

Rev. D | Page 6 of 24

AD5306/AD5316/AD5326

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter

VDD to GND −0.3 V to +7 V
SCL, SDA to GND −0.3 V to VDD + 0.3 V
A0, A1, LDAC, PD to GND
Reference Input Voltage to GND −0.3 V to VDD + 0.3 V
V

OUT

Operating Temperature Range

Industrial (A, B Versions) −40°C to +105°C

Storage Temperature Range −65°C to +150°C

Junction Temperature (TJ max) 150°C
16-Lead TSSOP

Power Dissipation

θJA Thermal Impedance

Reflow Soldering

Peak Temperature 220°C

Time at Peak Temperature 10 s to 40 s

________________________

1

Transient currents of up to 100 mA do not cause SCR latch-up.

1

A–D to GND −0.3 V to VDD + 0.3 V

Value

−0.3 V to V

max – TA)/θ

(T

J

150.4°C/W

+ 0.3 V

DD

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. D | Page 7 of 24

AD5306/AD5316/AD5326

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

LDAC

2

V

DD

3

V

A

OUT

V

OUT

V

OUT

V

REF

V

REF

V

REF

AD5306/

AD5316/

4

B
C
A
B
CV

5

TOP VIEW

(Not to Scale)

6

7

8

AD5326

16

A1

15

A0

14

SCL

13

SDA

12

GND

11

V

D

OUT

10

PD

9

D

REF

02066-003

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Function

1

LDAC

Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

2 VDD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled

with a10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
3 V
4 V
5 V
6 V

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

REF

A

Reference Input Pin for DAC A. This pin may be configured as a buffered or an unbuffered input depending

on the state of the BUF bit in the input word to DAC A. It has an input range from 0.25 V to V

in buffered mode.

DD

7 V

REF

B

mode and from 1 V to V

Reference Input Pin for DAC B. This pin may be configured as a buffered or an unbuffered input depending

on the state of the BUF bit in the input word to DAC B. It has an input range from 0.25 V to V

8 V

REF

C

mode and from 1 V to V

Reference Input Pin for DAC C. This pin may be configured as a buffered or an unbuffered input depending

in buffered mode.

DD

on the state of the BUF bit in the input word to DAC C. It has an input range from 0.25 V to V

9 V

REF

D

mode and from 1 V to V

Reference Input Pin for DAC D. This pin may be configured as a buffered or an unbuffered input depending

in buffered mode.

DD

on the state of the BUF bit in the input word to DAC D. It has an input range from 0.25 V to V

in buffered mode.

DD

10

mode and from 1 V to V

PD Active Low Control Input. Acts as a hardware power-down option. All DACs go into power-down mode when

this pin is tied low. The DAC outputs go into a high impedance state. The current consumption of the part

drops to 300 nA @ 5 V (90 nA @ 3 V).
11 V

D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

12 GND Ground Reference Point for All Circuitry on the Part.
13 SDA

Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift register.

It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor.
14 SCL

Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift register.

Clock rates of up to 400 kbit/s can be accommodated in the I
15 A0 Address Input. Sets the LSB of the 7-bit slave address.
16 A1 Address Input. Sets the second LSB of the 7-bit slave address.

2

C-compatible interface.

in unbuffered

DD

in unbuffered

DD

in unbuffered

DD

in unbuffered

DD

Rev. D | Page 8 of 24