FEATURES
250 MHz Operation
Driver/Comparator and Active Load Included
On-Chip Schottky Diode Bridge
52-Lead LQFP Package with Built-in Heatsink
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
PRODUCT DESCRIPTION
The AD53032 is a single chip that performs the pin electronics
functions of driver, comparator and active load in ATE VLSI
and memory testers. In addition, a Schottky diode bridge for the
active load and a VCOM buffer are included internally.
The driver is a proprietary design that features three active
states: Data High Mode, Data Low Mode and Term Mode as
well as an Inhibit State. This facilitates the implementation of
high speed active termination. The output voltage range is –3 V
to +8 V to accommodate a wide variety of test devices. The
output leakage is typically less than 250 nA over the entire signal range.
The dual comparator, with an input range equal to the driver
output range, features built-in latches and ECL-compatible
outputs. The outputs are capable of driving 50 Ω signal lines
terminated to –2 V. Signal tracking capability is upwards of
5 V/ns.
The active load can be set for up to 35 mA load current with
less than a 10 µA linearity error through the entire set range.
I
OH
Onboard Schottky diodes provide high speed switching and low
capacitance.
Also included on the chip is an onboard temperature sensor
whose purpose is to give an indication of the surface tempera-
ture of the DCL. This information can be used to measure θ
and θ
the sensor is a current sink that is proportional to absolute tem-
perature. The gain is trimmed to a nominal value of 1.0 µA/K.
As an example, the output current can be sensed by using a
10 kΩ resistor connected from +10 V to the THERM (IOUT) pin.
A voltage drop across the resistor will be developed that equals:
10K × 1 µA/K = 10 mV/K = 2.98 V at room temperature.
, IOL and the buffered VCOM are independently adjustable.
or flag an alarm if proper cooling is lost. Output from
JA
Active Load on a Single Chip
AD53032
FUNCTIONAL BLOCK DIAGRAM
JC
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
(All specifications are at TJ = +85ⴗC ⴞ 5ⴗC, +VS = +12 V ⴞ 3%, –VS = –7 V = ⴞ3% unless otherwise noted. All temperature coefficients are
measured at TJ = +75ⴗC to +95ⴗC). CHDCPL = CLDCPL = 39 nF.
ParameterMinTypMaxUnitsTest Conditions
DIFFERENTIAL INPUT CHARACTERISTICS
(DATA to DATA, IOD to IOD, RLD to RLD)
Input Voltage–20V
Differential Input RangeECL
Bias Current–250+250µAV
REFERENCE INPUTS
Bias Currents–50+50µAV
OUTPUT CHARACTERISTICS
Logic High Range–28VDATA = H, VH = –2 V to +8 V
Logic Low Range–35VDATA = L, VL = –3 V to +5 V, VH = +6 V
Amplitude (VH and VL)0.19VVL = 0.0 V, VH = +0.1 V, VT = 0 V
Absolute AccuracyVL = –2 V, VH = +7 V, VT = 0 V
VH Offset–50+50mVDATA = H, VH = 0 V, VL = –3 V, VT = +3 V
VH Gain + Linearity Error0.3 – 5+0.3 + 5% of VH + mVDATA = H, VH = –2 V to +8 V, VL = –3 V, VT = +3 V
VL Offset–50+50mVDATA = L, VL = –3 V, VH = +6 V, VT = +7.5 V
VL Gain + Linearity Error–0.3 – 5+0.3 + 5% of VL + mVDATA = L, VL = 0 V , VH = +6 V, VT = +7.5 V
Offset TC0.5mV/°CV
Output Resistance
V
= –2 V444648ΩV
H
V
= +8 V444648ΩV
H
V
= –3 V444648ΩV
L
V
= +5 V444648ΩV
L
V
= +3 V46ΩV
H
Dynamic Current Limit100mAC
Static Current Limit–85+85mAOutput to –3 V, VH = +8 V, VL = –1 V, VT = 0 V
V
ERM
T
Voltage Range–38.0VTERM MODE, VT = –3 V to +8 V, VL = 0 V, VH = 3 V
Delay Time, Active to Inhibit1.54.0nsMeasured at 50%, VH = +2 V, VL = –2 V
Delay Time, Inhibit to Active1.53.5nsMeasured at 50%, VH = +2 V, VL = –2 V
±1.0ns
Delay Time Matching (Z)2.2nsZ = Delay Time Active to Inhibit Test (Above)—
Delay Time Inhibit to Active Test (Above)
(Of Worst Two Edges)
I/O Spike<200mV, p-pVH = 0 V, VL = 0 V
Rise, Fall Time, Active to Inhibit3.5nsVH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)
Rise, Fall Time, Inhibit to Active2.2nsVH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)
DYNAMIC PERFORMANCE , V
Delay Time, VH to V
Delay Time, VL to V
Delay Time, V
to VH and V
TERM
TERM
TERM
Overshoot and Preshoot–3.0 + 75+3.0 + 75 % of Step + mVVH/VL, V
V
Mode Rise Time4.0nsVL, VH = 0 V, V
TERM
V
Mode Fall Time5.5nsVL, VH = 0 V, V
TERM
PSRR, DRIVE or TERM Mode35dBVS = V
Specifications subject to change without notice.
TERM
TERM
to V
3.0nsMeasured at 50%, VL = VH = +0.4 V, V
5.0nsMeasured at 50%, VL = VH = +0.4 V, V
L
4.0nsMeasured at 50%, VL = VH = +0.4 V, V
= (+0.4 V, –0.4 V), (0.0 V, –2.0 V),
TERM
TERM
TERM
TERM
= –0.4 V
= –0.4 V
= –0.4 V
(0.0 V, +7.0 V)
= –2 V, 20%–80%
TERM
= –2 V, 20%–80%
TERM
± 3%
S
COMPARATOR SPECIFICATIONS
(All specifications are at TJ = +85ⴗC ⴞ 5ⴗC, +VS = +12 V ⴞ 3%, –VS = –7 V = ⴞ3% unless otherwise noted. All temperature coefficients are
measured at TJ = +75ⴗC to +95ⴗC).
ParameterMinTypMaxUnitsTest Conditions
DC INPUT CHARACTERISTICS
Offset Voltage (VOS)–2525mVCMV = 0 V
Offset Voltage (Drift)50µV/°CCMV = 0 V
HCOMP, LCOMP Bias Current–5050µAV
Voltage Range (VCM)–38.0V
Differential Voltage (V
)9.0V
DIFF
Gain and Linearity–0.050.05% FSRVIN = –3 V to +8 V
LATCH ENABLE INPUTS
Logic “1” Current (I
Logic “0” Current (I
)250µALE, LE = –0.8 V
IH
)–250µALE, LE = –1.8 V
IL
DIGITAL OUTPUTS
Logic “1” Voltage (V
Logic “0” Voltage (V
)–0.98VQ or Q, 50 Ω to –2 V
OH
)–1.5VQ or Q, 50 Ω to –2 V
OL
Slew Rate1V/ns
SWITCHING PERFORMANCE
Propagation Delay
Input to Output0.92.5nsVIN = 2 V p-p,
Latch Enable to Output2nsHCOMP = +1 V, LCOMP = +1 V