Analog Devices AD5303, AD5323, AD5313 Datasheet

+2.5 V to +5.5 V, 230 ␮A, Dual Rail-to-Rail

a

FEATURES
AD5303: Two Buffered 8-Bit DACs in One Package
AD5313: Two Buffered 10-Bit DACs in One Package
AD5323: Two Buffered 12-Bit DACs in One Package
16-Lead TSSOP Package
Micropower Operation: 300 ␮A @ 5 V (Including

Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.5 V to +5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic By Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–V
Power-On-Reset to Zero Volts
SDO Daisy-Chaining Option
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Serial Interface with Schmitt-Triggered

Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers

APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

or 0–2 V

REF

REF

Voltage Output 8-/10-/12-Bit DACs

AD5303/AD5313/AD5323*

GENERAL DESCRIPTION

The AD5303/AD5313/AD5323 are dual 8-, 10- and 12-bit
buffered voltage output DACs in a 16-lead TSSOP package that
operate from a single +2.5 V to +5.5 V supply consuming 230 µA
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/µs. The AD5303/
AD5313/AD5323 utilize a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI, MICROWIRE™ and DSP interface
standards.

The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured
as buffered or unbuffered inputs. The parts incorporate a power­on-reset circuit that ensures that the DAC outputs power-up to
0 V and remain there until a valid write to the device takes place.
There is also an asynchronous active low CLR pin that clears
both DACs to 0 V. The outputs of both DACs may be updated
simultaneously using the asynchronous LDAC input. The
parts contain a power-down feature that reduces the current
consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and
provides software-selectable output loads while in power-down
mode. The parts may also be used in daisy-chaining applications
using the SDO pin.

The low power consumption of these parts in normal operation
make them ideally suited to portable battery operated equip­ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at
3 V, reducing to 1 µW in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

V

DD

BUF A

POWER-ON

RESET

INPUT

REGISTER

SYNC

SCLK

DIN

SDO

*Protected by U.S. Patent No. 5684481; other patents pending.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

DCEN

INTERFACE

LOGIC

>

CLR

LDAC

INPUT

REGISTER

PD

DAC

REGISTER

DAC

REGISTER

BUF B

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

V

A

REF

AD5303/AD5313/AD5323

STRING

DAC

POWER-DOWN

LOGIC

STRING

DAC

B

V

REF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

BUFFER

BUFFER

GAIN-SELECT

LOGIC

GND

RESISTOR
NETWORK

RESISTOR
NETWORK

V

A

OUT

B

V

OUT

AD5303/AD5313/AD5323–SPECIFICATIONS

(VDD = +2.5 V to +5.5 V; V

Parameter

DC PERFORMANCE

DAC REFERENCE INPUTS

OUTPUT CHARACTERISTICS

LOGIC INPUTS

LOGIC OUTPUT (SDO)

POWER REQUIREMENTS

1

AD5303

Resolution 8 Bits
Relative Accuracy ± 0.15 ± 1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design Over All Codes

AD5313

Resolution 10 Bits
Relative Accuracy ± 0.5 ± 3 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design Over All Codes

AD5323

Resolution 12 Bits
Relative Accuracy ± 2 ± 12 LSB

Differential Nonlinearity ± 0.2 ± 1 LSB Guaranteed Monotonic by Design Over All Codes
Offset Error ± 0.4 ± 3 % of FSR See Figures 3 and 4
Gain Error ± 0.15 ± 1 % of FSR See Figures 3 and 4
Lower Deadband 10 60 mV See Figures 3 and 4
Offset Error Drift
Gain Error Drift
Power Supply Rejection Ratio
DC Crosstalk

V

Input Range 1 V

REF

V

Input Impedance >10 MΩ Buffered Reference Mode

REF

5

5

5

Reference Feedthrough –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –80 dB Frequency = 10 kHz

Minimum Output Voltage

Maximum Output Voltage

DC Output Impedance 0.5 Ω
Short Circuit Current 50 mA VDD = +5 V

Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = +5 V

5

Input Current ± 1 µA
VIL, Input Low Voltage 0.8 V VDD = +5 V ± 10%

VIH, Input High Voltage 2.4 V VDD = +5 V ± 10%

Pin Capacitance 2 3.5 pF

VDD = +5 V ± 10%

Output Low Voltage 0.4 V I

Output High Voltage 4.0 V I
VDD = +3 V ± 10%

Output Low Voltage 0.4 V I

Output High Voltage 2.4 V I
Floating-State Leakage Current 1 µA DCEN = GND
Floating State O/P Capacitance 3 pF DCEN = GND

V

DD

(Normal Mode) Both DACs Active and Excluding Load Currents

I

DD

= +4.5 V to +5.5 V 300 450 µA Both DACs in Unbuffered Mode. VIH = VDD and

V

DD

= +2.5 V to +3.6 V 230 350 µAV

V

DD

(Full Power-Down)

I

DD

= +4.5 V to +5.5 V 0.2 1 µA

V

DD

VDD = +2.5 V to +3.6 V 0.05 1 µA

= +2 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

REF

B Version

2

Min Typ Max Units Conditions/Comments

3, 4

–12 ppm of FSR/°C

5

–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%
30 µV

5

0V

DD

DD

V Buffered Reference Mode
V Unbuffered Reference Mode

180 kΩ Unbuffered Reference Mode. 0–V

90 kΩ Unbuffered Reference Mode. 0–2 V

5

6

6

0.001 V mi

n This is a measure of the minimum and maximum

VDD – 0.001 V max drive capability of the output amplifier.

20 mA VDD = +3 V

5 µs Coming Out of Power-Down Mode. VDD = +3 V

0.6 V VDD = +3 V ± 10%

0.5 V VDD = +2.5 V

2.1 V VDD = +3 V ± 10%

2.0 V VDD = +2.5 V

5

2.5 5.5 V IDD Specification Is Valid for All DAC Codes

to T

MIN

Input Impedance = R

Input Impedance = R

SINK

SOURCE

SINK

SOURCE

= GND. In Buffered Mode, extra current is

IL

unless otherwise noted.)

MAX

DAC

DAC

= 2 mA

= 2 mA

= 2 mA

= 2 mA

Output Range,

REF

Output Range,

REF

typically x µA per DAC where x = 5 µA + V

REF/RDAC

.

–2–

REV. 0

AD5303/AD5313/AD5323

NOTES

1

See Terminology.

2

Temperature range: B Version: –40°C to +105°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5303 (Code 8 to 248); AD5313 (Code 28 to 995); AD5323 (Code 115 to 3981).

5

Guaranteed by design and characterization, not production tested.

6

In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
VDD and “Offset plus Gain” Error must be positive.

Specifications subject to change without notice.

REF

=

(VDD = +2.5 V to +5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

AC CHARACTERISTICS

Parameter

Output Voltage Settling Time V

2

1

otherwise noted.)

B Version
Min Typ Max Units Conditions/Comments

3

= VDD = +5 V

REF

AD5303 6 8 µs 1/4 Scale to 3/4 Scale
AD5313 7 9 µs 1/4 Scale to 3/4 Scale
AD5323 8 10 µs 1/4 Scale to 3/4 Scale

Change
Change
Change

MIN

(40 Hex to C0 Hex)
(100 Hex to 300 Hex)

(400 Hex to C00 Hex)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry

(011 . . . 11 to 100 . . . 00)
Digital Feedthrough 0.10 nV-s
Analog Crosstalk 0.01 nV-s
DAC-to-DAC Crosstalk 0.01 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization, not production tested.

2

See Terminology.

3

Temperature range: B Version: –40°C to +105°C.

Specifications subject to change without notice.

1, 2, 3

TIMING CHARACTERISTICS

Limit at T

MIN

(VDD = +2.5 V to +5.5 V; all specifications T

, T

MAX

= 2 V ± 0.1 V p-p. Unbuffered Mode

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

REF

to T

MIN

unless otherwise noted.)

MAX

Parameter (B Version) Units Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

4, 5

t

12

4, 5

t

13

5

t

14

5

t

15

NOTES

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figures 1 and 2.

4

These are measured with the load circuit of Figure 1.

5

Daisy-Chain Mode only (see Figure 45).

Specifications subject to change without notice.

33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
0 ns min SYNC to SCLK Rising Edge Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
100 ns min Minimum SYNC High Time
20 ns min LDAC Pulsewidth
20 ns min SCLK Falling Edge to LDAC Rising Edge
20 ns min CLR Pulsewidth
5 ns min SCLK Falling Edge to SDO Invalid
20 ns max SCLK Falling Edge to SDO Valid
0 ns min SCLK Falling Edge to SYNC Rising Edge
10 ns min SYNC Rising Edge to SCLK Rising Edge

to T

MAX

unless

REV. 0

–3–

AD5303/AD5313/AD5323

2mA

I

OL

TO

OUTPUT

PIN

50pF

Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications

SCLK

t

t

8

SYNC

DIN*

LDAC

LDAC

CLR

*SEE PAGE 12 FOR DESCRIPTION OF INPUT REGISTER

DB15

t

4

t

6

t

5

3

Figure 2. Serial Interface Timing Diagram

C

L

2mA

t

1

t

2

DB0

t

7

+1.6V

I

OH

t

9

t

10

t

11

–4–

REV. 0

AD5303/AD5313/AD5323

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C unless otherwise noted)

A

1, 2

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

V

OUT

A, V

B to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

Max) . . . . . . . . . . . . . . . . .+150°C

J

16-Lead TSSOP Package

Power Dissipation . . . . . . . . . . . . . . . . . . (T

Max – TA)/θ

J

JA

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

PIN CONFIGURATION

CLR

LDAC

V

V

REF

V

REF

V

OUT

BUF A

BUF B

DD

B

A

A

1

2

AD5303/

3

AD5313/

AD5323

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

SDO

GND

15

14

DIN

13

SCLK

12

SYNC

11

V

OUT

10

PD

9

DCEN

B

Model Temperature Range Package Description Package Option

AD5303BRU –40°C to +105°C Thin Shrink Small Outline Package (TSSOP) RU-16
AD5313BRU –40°C to +105°C Thin Shrink Small Outline Package (TSSOP) RU-16
AD5323BRU –40°C to +105°C Thin Shrink Small Outline Package (TSSOP) RU-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5303/AD5313/AD5323 features proprietary ESD protection circuitry, perma­nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

AD5303/AD5313/AD5323

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 CLR Active low control input that loads all zeroes to both input and DAC registers.
2 LDAC Active low control input that transfers the contents of the input registers to their respective DAC

registers. Pulsing this pin low allows either or both DAC registers to be updated if the input regis­ters have new data. This allows simultaneous update of both DAC outputs

3V

4V

5V

6V

DD

B Reference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buff-

REF

A Reference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a

REF

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

7 BUF A Control pin that controls whether the reference input for DAC A is unbuffered or buffered. If this

8 BUF B Control pin that controls whether the reference input for DAC B is unbuffered or buffered. If this

9 DCEN This pin is used to enable the daisy-chaining option. This should be tied high if the part is being

10 PD Active low control input that acts as a hardware power-down option. This pin overrides any soft-

11 V

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

12 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When

13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

14 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the

15 GND Ground reference point for all circuitry on the part.
16 SDO Serial Data Output that can be used for daisy-chaining a number of these devices together or for

Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply should be
decoupled to GND.

ered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from
0 V to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

buffered or an unbuffered input depending on the state of the BUF A pin. It has an input range
from 0 to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.

pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.

used in a daisy-chain. The pin should be tied low if it is being used in stand-alone mode.

ware power-down option. Both DACs go into power-down mode when this pin is tied low. The
DAC outputs go into a high impedance state and the current consumption of the part drops to
200 nA @ 5 V (50 nA @ 3 V).

SYNC goes low, it powers-on the SCLK and DIN buffers and enables the input shift register. Data
is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the
16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the device.

input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered-down
after each write cycle.

falling edge of the serial clock input. The DIN input buffer is powered-down after each write cycle.

reading back the data in the shift register for diagnostic purposes. The serial data output is valid on
the falling edge of the clock.

TERMINOLOGY

RELATIVE ACCURACY

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 5.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of ±1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design. A
typical DNL vs. code plot can be seen in Figure 8.

–6–

OFFSET ERROR

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

GAIN ERROR

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

GAIN ERROR DRIFT

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

REV. 0