Analog Devices AD5302 12 22 a Datasheet

2.5 V to 5.5 V, 230 ␮A Dual Rail-to-Rail,
Voltage Output 8-/10-/12-Bit DACs

FEATURES
AD5302: Two 8-Bit Buffered DACs in 1 Package

A Version: ⴞ1 LSB INL, B Version: ⴞ0.5 LSB INL

AD5312: Two 10-Bit Buffered DACs in 1 Package

A Version: ⴞ4 LSB INL, B Version: ⴞ2 LSB INL

AD5322: Two 12-Bit Buffered DACs in 1 Package

A Version: ⴞ16 LSB INL, B Version: ⴞ8 LSB INL
10-Lead MSOP Package
Micropower Operation: 300 ␮A @ 5 V (Including

Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V

2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design over All Codes
Buffered/Unbuffered Reference Input Options
0 V to V

Output Voltage

REF

Power-On-Reset to 0 V
Simultaneous Update of DAC Outputs via LDAC
Low Power Serial Interface with Schmitt-Triggered Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

AD5302/AD5312/AD5322

*

GENERAL DESCRIPTION

The AD5302/AD5312/AD5322 are dual 8-, 10-, and 12-bit buffered
voltage output DACs in a 10-lead MSOP package that operate from
a single 2.5 V to 5.5 V supply, consuming 230 µA at 3 V. Their
on-chip output amplifiers allow the outputs to swing rail-to-rail
with a slew rate of 0.7 V/µs. The AD5302/AD5312/AD5322
utilize a versatile 3-wire serial interface that operates at clock rates
up to 30 MHz and is compatible with standard SPI

®

, QSPI™,

MICROWIRE™, and DSP interface standards.

The references for the two DACs are derived from two reference
pins (one per DAC). The reference inputs may be configured as
buffered or unbuffered inputs. The outputs of both DACs may be
updated simultaneously using the asynchronous LDAC input. The
parts incorporate a power-on reset circuit, which ensures that the
DAC outputs power-up to 0 V and remain there until a valid write
takes place to the device. The parts contain a power-down feature
that reduces the current consumption of the devices to 200 nA at
5V (50 nA at 3 V) and provides software-selectable output loads
while in power-down mode.

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery operated equipment.
The power consumption is 1.5 mW at 5 V, 0.7 mW at 3 V, reducing
to 1 µW in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

V

DD

POWER-ON

RESET

REGISTER

SYNC

SCLK

DIN

*Patent Pending; protected by U.S. Patent No. 5684481.

INTERFACE

LOGIC

LDAC

REGISTER

INPUT

INPUT

DAC

REGISTER

DAC

REGISTER

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

V

A

REF

AD5302/AD5312/AD5322

STRING

DAC

POWER-DOWN

LOGIC

STRING

DAC

B

V

REF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

BUFFER

BUFFER

GND

RESISTOR
NETWORK

RESISTOR
NETWORK

V

A

OUT

B

V

OUT

AD5302/AD5312/AD5322–SPECIFICATIONS

GND; CL = 200 pF to GND; all specifications T

Parameter

1

DC PERFORMANCE

3, 4

A Version
Min Typ Max Min Typ Max Unit Conditions/Comments

to T

MIN

, unless otherwise noted.)

MAX

2

B Version

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to

REF

AD5302

Resolution 8 8 Bits
Relative Accuracy ± 0.15 ± 1 ± 0.15 ± 0.5 LSB
Differential Nonlinearity ±0.02 ± 0.25 ±0.02 ±0.25 LSB Guaranteed Monotonic by Design over All Codes

AD5312

Resolution 10 10 Bits
Relative Accuracy ± 0.5 ± 4 ± 0.5 ± 2 LSB
Differential Nonlinearity ±0.05 ± 0.5 ±0.05 ±0.5 LSB Guaranteed Monotonic by Design over All Codes

AD5322

Resolution 12 12 Bits
Relative Accuracy ± 2 ±16 ± 2 ± 8 LSB

Differential Nonlinearity ±0.2 ± 1 ±0.2 ±1LSB Guaranteed Monotonic by Design over All Codes
Offset Error ± 0.4 ± 3 ± 0.4 ± 3% of FSR See Figures 2 and 3
Gain Error ± 0.15 ± 1 ± 0.15 ± 1% of FSR See Figures 2 and 3
Lower Deadband 10 60 10 60 mV See Figures 2 and 3
Offset Error Drift
Gain Error Drift
Power Supply Rejection Ratio
DC Crosstalk

DAC REFERENCE INPUTS

VREF Input Range 1 V

5

5

5

5

5

–12 –12 ppm of FSR/°C
–5 –5 ppm of FSR/°C
–60 –60 dB VDD = ± 10%
30 30 µV

1V

DD

0V

0V

DD

V Buffered Reference Mode

DD

V Unbuffered Reference Mode

DD

VREF Input Impedance >10 >10 MΩ Buffered Reference Mode

180 180 kΩ Unbuffered Reference Mode,

Input Impedance = R

DAC

Reference Feedthrough –90 –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –80 –80 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

5

6

6

0.001 0.001 V min This is a measure of the minimum and maximum

VDD – 0.001 VDD – 0.001 V max drive capability of the output amplifier.
DC Output Impedance 0.5 0.5 Ω
Short Circuit Current 50 50 mA V

DD

= 5 V

20 20 mA VDD = 3 V
Power-Up Time 2.5 2.5 µs Coming out of Power-Down Mode. V

DD

55µs Coming out of Power-Down Mode. VDD = 3 V

LOGIC INPUTS

5

Input Current ± 1 ± 1 µA

, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

V

IL

0.6 0.6 V VDD = 3 V ± 10%

, Input High Voltage 2.4 2.4 V VDD = 5 V ± 10%

0.5 0.5 V V

V

IH

= 2.5 V

DD

2.1 2.1 V VDD = 3 V ± 10%

2.0 2.0 V V

= 2.5 V

DD

Pin Capacitance 2 3.5 2 3.5 pF

POWER REQUIREMENTS

V

DD

(Normal Mode) Both DACs active and excluding load currents

I

DD

= 4.5 V to 5.5 V 300 450 300 450 µA Both DACs in unbuffered mode. VIH = VDD and

V

DD

VDD = 2.5 V to 3.6 V 230 350 230 350 µAV

2.5 5.5 2.5 5.5 V IDD specification is valid for all DAC Codes.

= GND. In buffered mode, extra current is

IL

typically x µA per DAC where x = 5 µA + V

(Full Power-Down)

I

DD

VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 µA
VDD = 2.5 V to 3.6 V 0.05 1 0.05 1 µA

NOTES

1

See Terminology section.

2

Temperature range: A, B Version: –40°C to +105°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981).

5

Guaranteed by design and characterization, not production tested.

6

In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage,
V

= VDD and offset plus gain error must be positive.

REF

Specifications subject to change without notice.

= 5 V

REF/RDAC

.

REV. A–2–

AD5302/AD5312/AD5322

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

AC SPECIFICATIONS

Parameter

2

1

otherwise noted.)

A, B Version
Min Typ Max Unit Conditions/Comments

3

Output Voltage Settling Time V

= VDD = 5 V

REF

MIN

to T

, unless

MAX

AD5302 6 8 µs 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5312 7 9 µs 1/4 Scale to 3/4 Scale Change (0x100 to 0x300)

AD5322 8 10 µs 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change around Major Carry (011 . . . 11 to 100 . . . 00)
Digital Feedthrough 0.10 nV-s
Analog Crosstalk 0.01 nV-s
DAC-to-DAC Crosstalk 0.01 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization, not production tested.

2

See Terminology section.

3

Temperature range: A, B Version: –40°C to +105°C.

Specifications subject to change without notice.

MIN

, T

1, 2, 3

MAX

(VDD = 2.5 V to 5.5 V; all specifications T

TIMING CHARACTERISTICS

Limit at T

= 2 V ± 0.1 V p-p, Unbuffered Mode

REF

= 2.5 V ± 0.1 V p-p, Frequency = 10 kHz

REF

to T

MIN

, unless otherwise noted.)

MAX

Parameter (A, B Version) Unit Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

NOTES

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 1.

Specifications subject to change without notice.

33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
0 ns min SYNC to SCLK Active Edge Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
100 ns min Minimum SYNC High Time
20 ns min LDAC Pulse Width
20 ns min SCLK Falling Edge to LDAC Rising Edge

REV. A

SCLK

t

8

SYNC

DIN*

LDAC

LDAC

*SEE INPUT SHIFT REGISTER SECTION.

DB15

t

4

t

6

t

5

Figure 1. Serial Interface Timing Diagram

t

1

t

2

DB0

t

7

t

9

t

10

t

3

–3–

AD5302/AD5312/AD5322

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1, 2

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . . –0.3 V to V

V

OUT

A, V

B to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (A, B Version) . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

Max) . . . . . . . . . . . . . . . . . +150°C

J

10-Lead MSOP Package

Power Dissipation . . . . . . . . . . . . . . . . . . . . (T

Max–TA)/

J

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD5302ARM –40°C to +105°C 10-Lead MSOP RM-10 D5A
AD5302ARM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 D5A
AD5312ARM –40°C to +105°C 10-Lead MSOP RM-10 D6A
AD5312ARM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 D6A
AD5322ARM –40°C to +105°C 10-Lead MSOP RM-10 D7A
AD5322ARM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 D7A
AD5302BRM –40°C to +105°C 10-Lead MSOP RM-10 D5B
AD5302BRM-REEL –40°C to +105°C 10-Lead MSOP RM-10 D5B
AD5302BRM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 D5B
AD5312BRM –40°C to +105°C 10-Lead MSOP RM-10 D6B
AD5312BRM-REEL –40°C to +105°C 10-Lead MSOP RM-10 D6B
AD5312BRM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 D6B
AD5322BRM –40°C to +105°C 10-Lead MSOP RM-10 D7B
AD5322BRM-REEL –40°C to +105°C 10-Lead MSOP RM-10 D7B
AD5322BRM-REEL7 –40°C to +105°C 10-Lead MSOP RM-10 D7B

JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W



JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5302/AD5312/AD5322 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATION

LDAC

V

REF

V

REF

V

OUT

V

DD

B

A

A

1

2

AD5302/
AD5312/

3

AD5322

TOP VIEW

4

(Not to Scale)

5

10

GND

9

DIN

8

SCLK

7

SYNC

6

V

B

OUT

REV. A–4–

AD5302/AD5312/AD5322

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 LDAC Active Low Control Input that Transfers the Contents of the Input Registers to their Respective DAC

Registers. Pulsing this pin low allows either or both DAC registers to be updated if the input registers
have new data. This allows simultaneous update of both DAC outputs.

2V

3V

4V

5V

6V

DD

BReference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buffered or

REF

AReference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a buffered or

REF

ABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

BBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

7 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

8 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

9DIN Serial Data Input. This device has a 16-bit input shift register. Data is clocked into the register on the

10 GND Ground Reference Point for All Circuitry on the Part.

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be
decoupled to GND.

an unbuffered input, depending on the BUF bit in the control word of DAC B. It has an input range
from 0 V to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

an unbuffered input depending on the BUF bit in the control word of DAC A. It has an input range from
0 V to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after
each write cycle.

falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle.

TERMINOLOGY
Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL versus code plot can be seen in TPC 1.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL versus code plot can be
seen in TPC 4.

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC regis­ter changes state. It is normally specified as the area of the glitch
in nV-secs and is measured when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-secs and is measured
with a full-scale change on the digital input pins, i.e., from all 0s
to all 1s and vice versa.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code
change (all 0s to all 1s and vice versa) while keeping LDAC
high. Then pulse LDAC low and monitor the output of the
DAC whose digital code was not changed. The area of the glitch
is expressed in nV-secs.

REV. A

–5–