Analog Devices AD53020 Datasheet

a

Four Channel ECL Delay Line

AD53020

FEATURES
Four Delay Lines with the Ability to Independently

Adjust All Edges

Pin Compatible and Functionally Equivalent with the

BT624
Reduced Power Dissipation
44-Lead PLCC Package with Internal Heat Spreader

APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Clocked ECL Circuits

PRODUCT DESCRIPTION

The AD53020 is a four-channel delay line designed for use in
automatic test equipment and digital logic systems. High speed
bipolar transistors and a 44-lead plastic PLCC package with
internal heat spreader provide high frequency performance at a
minimum of space, cost and power dissipation.

Featuring full pin compatibility and functional equivalence to
the BT624, the AD53020 offers independent analog control of
positive and negative edges with five delay ranges. The AD53020
offers attractive performance with optimized power dissipation
and linear delay vs. program voltage control. This device is also
very stable over operating conditions and has very low jitter.

Digital inputs are ECL compatible. They can either be pro­vided independently for each channel (IN1, IN1 through IN4,

IN4), or fanned out to all channels from Channel 2 (IN2,
IN2). The choice of these two options is made by setting the

DRVMODE input, with ECL Logic 0 providing four indepen­dent channels, and ECL Logic 1 enabling a logical OR function
between each channel and the Channel Number 2.

For maximum timing accuracy, differential signals are recom­mended for use with the digital inputs. However, single-ended
operation is also supported and it is facilitated through the use
of the V
this feature, connect the V
each channel. It is also advisable, when using the V

midpoint level generated on-chip. To make use of

BB

output to the inverting input of

BB

output,

BB

to decouple this signal with a 0.1 µF ceramic capacitor to ground.

The outputs of the AD53020 are ECL compatible and should

be terminated by 50 Ω to –2.0 V at the inputs of the gates

they drive.

FUNCTIONAL BLOCK DIAGRAM

GND S0 S1

VWIDTH1

OUT1

OUT1

VDELAY1
VWIDTH2

OUT2

OUT2

VDELAY2
VWIDTH3

OUT3

OUT3

VDELAY3
VWIDTH4

OUT4

OUT4

VDELAY4

IN1, IN1

IN2, IN2

DRVMODE

IN3, IN3

IN4, IN4

V

EE

AD53020

V

COMP1 COMP2 REXT1 REXT2

BB

The delay is programmed through the VDELAY and VWIDTH
pins for each channel. The acceptable range is –1.3 V to –0.1 V,
representing the longest and the shortest delays provided by the

device. An 0.01 µF ceramic capacitor to ground is recom-

mended for each input. The bias current for each input is fixed
by an internal current mirror. The value of the bias current is

set by the external resistor at REXT1. A 1.3 kΩ resistor to

ground at this pin establishes 1 mA bias in each input. The
nominal voltage at the REXT1 pin is –1.3 V.

The VDELAY affects both the positive and negative edges in all
modes. The VWIDTH is an additional delay adjustment that is
active in Modes 2, 3 and 5. VWIDTH has no effect in Modes 0
and 1. For Modes 2 and 3, the effect of the VWIDTH adjust­ment is to increase or decrease the delay of the negative edge
relative to the positive edge. In Mode 5, the total delay for both
positive and negative edges is set by the combination of VDELAY
and VWIDTH.

(continued on page 4)

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD53020–SPECIFICATIONS

AD53020-Test Conditions (Unless otherwise noted): Recommended Operating

Conditions with all OUT and OUT outputs terminated through 50 ⍀ to –2.0 V, REXT1 = 1.3 k⍀, REXT2 = 2.94 k⍀. Typical values are based on
nominal temperature, TA = +25ⴗC, and nominal supply voltage, VEE = –5.2 V.

DC CHARACTERISTICS

1

Parameter Symbol T(ⴗC) Min Typ Max Units

DIGITAL INPUT HIGH VOLTAGE

IN, IN, DRVMODE, S0, S1 V

IH

70 –1.070 0.000 V

DIGITAL INPUT LOW VOLTAGE

IN, IN, DRVMODE, S0 V

DIGITAL INPUT LOW VOLTAGE, S1 V

IL

IL

S1 THIRD STATE (EXTENDED DELAY) Full V

DIGITAL OUTPUT HIGH VOLTAGE V

DIGITAL OUTPUT LOW VOLTAGE V

OH

OL

70 –1.950 –1.450 V

70 V

EE

EE

–1.450 V

–3.2 V

70 –1.000 –0.735 V

70 –1.950 –1.600 V

DIGITAL INPUT BIAS CURRENT –100 to

IN, IN, DRVMODE, S0, S1 I

POWER SUPPLY REJECTION RATIO

V

SUPPLY CURRENT

EE

2

Mode 0 I
Modes 1, 2 I
Modes 3, 5 I

NOTES

1

The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least two
minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board.

2

This parameter is fully characterized, but not production tested.

Specifications subject to change without notice.

IN

PSRR Full 0.5 % Tpd/V

EE

EE

EE

Full 174 200 mA
Full 225 250 mA
Full 267 290 mA

+100 µA

AC CHARACTERISTICS

1

Parameter Symbol Min Typ Max Units

MINIMUM PROPAGATION DELAYS

2

Mode S1 S0 VDELAY
0 0 0 –0.1 V Tpd Min 3.6 4.5 5.4 ns
1 0 1 –0.1 V Tpd Min 4.9 6.3 7.3 ns
2 1 0 –0.1 V Tpd Min 3.9 5.3 6.8 ns
3 1 1 –0.1 V Tpd Min 5.2 7.1 8.8 ns
5VEE1 –0.1 V Tpd Min 6.8 8.8 10.3 ns

DELAY ADJUSTMENT RANGES

Mode S1 S0
0 0 0 Tpd Span 14.0 19.0 24.7 ns
1 0 1 Tpd Span 22.9 31.4 37.8 ns
2 1 0 Tpd Span 13.2 18.9 24.6 ns
3 1 1 Tpd Span 22.0 31.5 40.6 ns
5VEE1 Tpd Span 29.3 44.5 52.0 ns

MINIMUM PULSEWIDTH

RISING EDGE DELAY VS. VWIDTH DELAY

Change (Modes 2 and 3)

DELAY VS. DUTY CYCLE

3

3

3, 4

1.9 ns

30 ps

50 ps

VWIDTH RANGE OF ADJUSTMENT

(VDELAY = –0.6 V, MODES 2 AND 3, DELAY

RELATIVE TO VWIDTH = –0.7 V)
VWIDTH = –0.1 V –5.5 –4.0 ns
VWIDTH = –1.1 V +5.5 ns
VWIDTH = –1.3 V +4.0 +6.5 ns

–2– REV. A