Analog Devices AD5300 Datasheet

+2.7 V to +5.5 V, 140 ␮A, Rail-to-Rail Output

POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

AD5300

V

DD

GND

V

OUT

SYNC

SCLK

DIN

8-BIT

DAC

REF (+) REF (–)

OUTPUT
BUFFER

POWER-DOWN

CONTROL LOGIC

RESISTOR
NETWORK

a

FEATURES
Single 8-Bit DAC
6-Lead SOT-23 and 8-Lead ␮SOIC Packages
Micropower Operation: 140 ␮A @ 5 V
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.7 V to +5.5 V Power Supply
Guaranteed Monotonic by Design
Reference Derived from Power Supply
Power-On-Reset to Zero Volts
Three Power-Down Functions
Low Power Serial Interface with Schmitt-Triggered

Inputs

On-Chip Output Buffer Amplifier, Rail-to-Rail

Operation

SYNC Interrupt Facility

APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

8-Bit DAC in an SOT-23

AD5300*

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD5300 is a single, 8-bit buffered voltage out DAC that
operates from a single +2.7 V to +5.5 V supply consuming

115 µA at 3 V. Its on-chip precision output amplifier allows

rail-to-rail output swing to be achieved. The AD5300 utilizes a
versatile three-wire serial interface that operates at clock rates up
to 30 MHz and is compatible with standard SPI™, QSPI™,
MICROWIRE™ and DSP interface standards.

The reference for AD5300 is derived from the power supply
inputs and thus gives the widest dynamic output range. The part
incorporates a power-on-reset circuit that ensures that the DAC
output powers up to zero volts and remains there until a valid
write takes place to the device. The part contains a power-down
feature that reduces the current consumption of the device to
200 nA at 5 V and provides software selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface.

The low power consumption of this part in normal operation
makes it ideally suited to portable battery operated equipment.

The power consumption is 0.7 mW at 5 V reducing to 1 µW in

power-down mode.

The AD5300 is one of a family of pin-compatible DACs. The
AD5310 is the 10-bit version and the AD5320 is the 12-bit
version. The AD5300/AD5310/AD5320 are available in 6-lead

SOT-23 packages and 8-lead µSOIC packages.

PRODUCT HIGHLIGHTS

1. Available in 6-lead SOT-23 and 8-lead µSOIC packages.

2. Low power, single supply operation. This part operates from
a single +2.7 V to +5.5 V supply and typically consumes

0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for
battery powered applications.

3. The on-chip output buffer amplifier allows the output of the

DAC to swing rail-to-rail with a slew rate of 1 V/µs.

4. Reference derived from the power supply.

5. High speed serial interface with clock speeds up to 30 MHz.
Designed for very low power consumption. The interface
only powers up during a write cycle.

6. Power-down capability. When powered down the DAC
typically consumes 50 nA at 3 V and 200 nA at 5 V.

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
*Patent pending; protected by U.S. Patent No. 5684481.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

(VDD = +2.7 V to +5.5 V; RL = 2 k⍀ to GND; CL = 500 pF to GND; all specifications
T

to T

AD5300–SPECIFICATIONS

MIN

B Version

Parameter Min Typ Max Units Conditions/Comments

STATIC PERFORMANCE

2

Resolution 8 Bits

Relative Accuracy ±1 LSB See Figure 2.
Differential Nonlinearity ±0.25 LSB Guaranteed Monotonic by Design. See Figure 3.

Zero Code Error +0.5 +3.5 LSB All Zeros Loaded to DAC Register. See Figure 6.
Full-Scale Error –0.5 –3.5 LSB All Ones Loaded to DAC Register. See Figure 6.

Gain Error ±1.25 % of FSR
Zero Code Error Drift –20 µV/°C
Gain Temperature Coefficient –5 ppm of FSR/°C

OUTPUT CHARACTERISTICS

3

Output Voltage Range 0 V

Output Voltage Settling Time 4 6 µs 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex).
Slew Rate 1 V/µs

Capacitive Load Stability 470 pF R

1000 pF R
Digital-to-Analog Glitch Impulse 20 nV-s 1 LSB Change Around Major Carry. See Figure 19.
Digital Feedthrough 0.5 nV-s

DC Output Impedance 1 Ω

Short Circuit Current 50 mA V

20 mA V

Power-Up Time 2.5 µs Coming Out of Power-Down Mode. V

5 µs Coming Out of Power-Down Mode. V

LOGIC INPUTS

3

Input Current ±1 µA

V

, Input Low Voltage 0.8 V VDD = +5 V

INL

V

, Input Low Voltage 0.6 V VDD = +3␣ V

INL

V

, Input High Voltage 2.4 V VDD = +5 V

INH

V

, Input High Voltage 2.1 V VDD = +3 V

INH

Pin Capacitance 3 pF

unless otherwise noted)

MAX

1

V

DD

R

= 2 kΩ; 0 pF < C

L

=

∞

L

= 2 kΩ

L

= +5 V

DD

= +3 V

DD

< 500 pF. See Figure 16.

L

= +5␣ V

DD

= +3␣ V

DD

POWER REQUIREMENTS

V

DD

I

(Normal Mode) DAC Active and Excluding Load Current

DD

V

= +4.5 V to +5.5 V 140 250 µAV

DD

V

= +2.7 V to +3.6 V 115 200 µAV

DD

I

(All Power-Down Modes)

DD

V

= +4.5 V to +5.5 V 0.2 1 µAV

DD

V

= +2.7 V to +3.6 V 0.05 1 µAV

DD

2.7 5.5 V

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

POWER EFFICIENCY

I

OUT/IDD

NOTES

1

Temperature ranges are as follows: B Version: –40°C to +105°C.

2

Linearity calculated using a reduced code range of 4 to 251. Output unloaded.

3

Guaranteed by design and characterization, not production tested.

Specifications subject to change without notice.

93 % I

= 2 mA. VDD = +5 V

LOAD

–2– REV. A

TIMING CHARACTERISTICS

WARNING!

ESD SENSITIVE DEVICE

1, 2

(VDD = +2.7 V to +5.5 V; all specifications T

MIN

to T

unless otherwise noted)

MAX

AD5300

Limit at T

MIN

, T

MAX

Parameter VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Units Conditions/Comments

3

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

See Figure 1.

3

Maximum SCLK frequency is 30 MHz at VDD = +3.6 V to +5.5 V and 20 MHz at VDD = +2.7 V to +3.6 V.

Specifications subject to change without notice.

50 33 ns min SCLK Cycle Time
13 13 ns min SCLK High Time

22.5 13 ns min SCLK Low Time
0 0 ns min SYNC to SCLK Rising Edge Setup Time
5 5 ns min Data Setup Time

4.5 4.5 ns min Data Hold Time
0 0 ns min SCLK Falling Edge to SYNC Rising Edge
50 33 ns min Minimum SYNC High Time

t

1

SCLK

SYNC

DIN

t

8

t

4

t

5

DB15

t

3

t

6

t

2

t

7

DB0

Figure 1. Serial Write Operation

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

V

OUT

+ 0.3 V

DD

Operating Temperature Range

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

ORDERING GUIDE

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

Max) . . . . . . . . . . . . . . . . .+150°C

J

SOT-23 Package

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

Max–T

J

)/θ

A

Model Range Information Options*

AD5300BRT –40°C to +105°C D2B RT-6

JA

AD5300BRM –40°C to +105°C D2B RM-8

Temperature Branding Package

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 240°C/W

Lead Temperature, Soldering

*RT = SOT-23; RM = µSOIC.

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C

␣ Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

µSOIC Package

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

Max–T

J

)/θ

A

JA

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W

θ

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. A

AD5300

PIN CONFIGURATIONS

SOT-23 mSOIC

V

OUT

GND

V

DD

1

AD5300

2

TOP VIEW

3

(Not to Scale)

6

5

4

SYNC

SCLK
DIN

1

V

DD

2

NC

3

NC

(Not to Scale)

4

V

OUT

NC = NO CONNECT

AD5300

TOP VIEW

8

7

6

5

GND
DIN
SCLK

SYNC

PIN FUNCTION DESCRIPTIONS

SOT-23 Pin Numbers

Pin
No. Mnemonic Function

1V

OUT

Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
2 GND Ground reference point for all circuitry on the part.
3V

DD

Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and VDD should be de-

coupled to GND.
4 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the

falling edge of the serial clock input.
5 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates up to 30 MHz.
6 SYNC Level triggered control input (active low). This is the frame synchronization signal for the input

data. When SYNC goes low, it enables the input shift register and data is transferred in on the fall-

ing edges of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC

is taken high before this edge in which case the rising edge of SYNC acts as an interrupt and the

write sequence is ignored by the DAC.

–4– REV. A