ANALOG DEVICES AD5293 Service Manual

Single Channel, 1024-Position, 1% R-Tol, Digital

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Potentiometer

Preliminary Technical Data

FEATURES

Single-channel, 1024-position resolution 20 kΩ, 50 kΩ and 100 kΩ nominal resistance Calibrated 1% Nominal Resistor Tolerance Rheostat mode temperature coefficient: 35 ppm/°C Voltage divider temperature coefficient: 5 ppm/°C +21V to +30V single-supply operation ±10.5V to ±15V dual-supply operation SPI® compatible serial interface Wiper setting readback

APPLICATIONS

Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage to current conversion Programmable filters, delays, time constants Programmable power supply Low resolution DAC replacement Sensor calibration

GENERAL DESCRIPTION

The AD5293 is a single-channel, 1,024-position digital potentiometer error. The AD5293 performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. This device is capable of operating at high-voltages; supporting both dual supply ±10.5 to ±15V and single supply operation +21V to +30V.

The AD5293 offers guaranteed industry leading low resistor tolerance errors of ±1% with a nominal temperature coefficient of 35 ppm/ºC. The low resistor tolerance feature simplifies open-loop applications as well as precision calibration and tolerance matching applications.

with less than 1% end-to-end Resistor Tolerance

AD5293

FUNCTIONAL BLOCK DIAGRAM

Figure 1. 14ld TSSOP

The AD5293 is available in a compact 14ld TSSOP package. The part is guaranteed to operate over the extended industrial temperature range of −40°C to +105°C.

The terms digital potentiometer and RDAC are used interchangeably.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5293 Preliminary Technical Data

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TABLE OF CONTENTS

REVISION HISTORY

Revision: Preliminary Version

Rev.PrA | Page 2 of 15

Preliminary Technical Data AD5293

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SPECIFICATIONS

ELECTRICAL CHARACTERISTICS – 20KΩ VERSION

VDD = 21V to 30V, VSS = 0V; VDD = 10.5V to 16.5V, VSS = -10.5V to -16.5V; V unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS— RHEOSTAT MODE

Resolution N 10 Bits Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB Resistor Integral Nonlinearity2 R-INL R R-INL R

= 20KΩ, |V

Nominal Resistor Tolerance3 ∆RAB/RAB −1 0.5 +1 % Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C Wiper Resistance RW TBD TBD Ω

DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE

Resolution N 10 Bits Differential Nonlinearity4 DNL −1 +1 LSB Integral Nonlinearity4 INL −1 +1 LSB Voltage Divider Temperature

(∆V

)/∆T × 106 Code = half-scale 5 ppm/°C

W/VW

Coefficient Full-Scale Error V Zero-Scale Error V

Code = full scale −6 0 LSB

WFSE

Code = zero scale 0 TBD LSB

WZSE

RESISTOR TERMINALS

Terminal Voltage Range5 V Capacitance6 A, B C

A, B, W

f = 1 MHz, measured to GND,

A, B

Code = half-scale

Capacitance6 W CW f = 1 MHz, measured to GND,

Code = half-scale

Common-Mode Leakage Current6 ICM V

= VB = VW 0.001 50 nA

DIGITAL INPUTS JEDEC compliant

Input Logic High VIH V V

Input Logic Low VIL V Input Current IIL V Input Capacitance6 C

5 pF

= 4.5V to 5.5 V 2.0 V

LOGIC

= 2.7V to 3.6 V 1.8 V

LOGIC

= 2.7V to 5.5 V 0.8 V

LOGIC

= 0 V or V

DIGITAL OUTPUTS(SDO and RDY)

Output High Voltage VOH R

Output Low Voltage VOL R

PULL_UP

Three state Leakage Current -1 1 µA Output Capacitance6 COL 5 pF

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 21 30 V

Dual-Supply Power Range VDD/VSS ±10.5 ±16.5 V Positive Supply Current IDD V Negative Supply Current ISS V Logic Supply Range V Logic Supply Current I I Memory Read Current

6,7

2.7 5.5 V

LOGIC

LOGIC_FUSE_READ

VIH = 5 V or VIL = GND TBD mA

/ VSS = ±16.5 V TBD TBD µA

/VSS = ±16.5 V TBD TBD µA

= 5 V; VIH = 5 V or VIL = GND TBD TBD µA

LOGIC

= 3 V; VIH = 3 V or VIL = GND TBD TBD µA

LOGIC

= 2.7V to 5.5V, VA = VDD, VB = VSS , −40°C < TA < +105°C,

LOGIC

− V

| = 26V to 30V −1.5 +1.5 LSB

− V

| = 21V to 26V −2 +2 LSB

VDD V

50 pF

40 pF

±1 µA

LOGIC

= 2.2kΩ to V

LOGIC

0.4

= 2.2kΩ to V

Gnd

LOGIC

+0.4V

Rev. PrA | Page 3 of 15

AD5293 Preliminary Technical Data

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Parameter Symbol Conditions Min Typ1 Max Unit

Power Dissipation8 P Power Supply Rejection Ratio6 PSSR ∆VDD/∆VSS = ±15 V ± 10% 0.0006 0.002 %/%

DYNAMIC CHARACTERISTICS

6, 9

Bandwidth BW −3 dB TBD kHz Total Harmonic Distortion THDW V

VW Settling Time tS

Resistor Noise Density e

Typicals represent average readings at 25°C,VDD = 15 V, VSS = -15 V and V

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions.

±1% resistor tolerance code range; R

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0V. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions.

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.

Guaranteed by design and not subject to production test.

Different from operating current; supply current for fuse read lasts approximately TBDµs..

is calculated from (IDD × VDD) + (ISS × VSS) + (I

DISS

All dynamic characteristics use VDD = +15 V, VSS = −15 V and V

= 20KΩ: 250 to 1,023 for | VDD - VSS | = 26V to 30V and 383 to 1,023 for | VDD - VSS | = 21V to 26V

DISS

= 5 V or VIL = GND TBD TBD µW

= 1 V rms, VB = 0 V, f = 1 kHz

= 20 kΩ

= 50 kΩ

= 100 kΩ

= 10 V, VB = 0 V,

±1 LSB error band, R

= 20 kΩ

= 50 kΩ

= 100 kΩ

N_WB

× V

LOGIC

= 5 V.

LOGIC

= 5 kΩ, TA = 25°C, TBD

= 5 V.

LOGIC

-90

-99

2.5 5

µs

nV/√Hz

Rev. PrA | Page 4 of 15

Preliminary Technical Data AD5293

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ELECTRICAL CHARACTERISTICS – 50KΩ AND 100KΩ VERSIONS

VDD = 21V to 30V, VSS = 0V; VDD = 10.5V to 16.5V, VSS = -10.5V to -16.5V; V unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS— RHEOSTAT MODE

Resolution N 10 Bits Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB Resistor Integral Nonlinearity2 R-INL −1 +1 LSB Nominal Resistor Tolerance3 ∆RAB/RAB −1 0.5 +1 % Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C Wiper Resistance RW TBD TBD Ω

DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE

Resolution N 10 Bits Differential Nonlinearity4 DNL −1 +1 LSB Integral Nonlinearity4 INL −1 +1 LSB Voltage Divider Temperature

(∆V

)/∆T × 106 Code = half-scale 5 ppm/°C

W/VW

Coefficient Full-Scale Error V Zero-Scale Error V

Code = full scale −6 0 LSB

WFSE

Code = zero scale 0 TBD LSB

WZSE

RESISTOR TERMINALS

Terminal Voltage Range5 V Capacitance6 A, B C

A, B, W

f = 1 MHz, measured to GND,

A, B

Code = half-scale

Capacitance6 W CW f = 1 MHz, measured to GND,

Code = half-scale

Common-Mode Leakage Current6 ICM V

= VB = VW 0.001 50 nA

DIGITAL INPUTS JEDEC compliant

Input Logic High VIH V V

Input Logic Low VIL V Input Current IIL V Input Capacitance6 C

5 pF

= 4.5V to 5.5 V 2.0 V

LOGIC

= 2.7V to 3.6 V 1.8 V

LOGIC

= 2.7V to 5.5 V 0.8 V

LOGIC

= 0 V or V

DIGITAL OUTPUTS(SDO and RDY)

Output High Voltage VOH R

Output Low Voltage VOL R

PULL_UP

Three state Leakage Current -1 1 µA Output Capacitance6 COL 5 pF

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 21 30 V

Dual-Supply Power Range VDD/VSS ±10.5 ±16.5 V Positive Supply Current IDD V Negative Supply Current ISS V Logic Supply Range V Logic Supply Current I I OTP Read Current

6,7

Power Dissipation8 P

2.7 5.5 V

LOGIC

LOGIC_FUSE_READ

DISS

VIH = 5 V or VIL = GND TBD mA

/ VSS = ±16.5 V TBD TBD µA

/VSS = ±16.5 V TBD TBD µA

= 5 V; VIH = 5 V or VIL = GND TBD TBD µA

LOGIC

= 3 V; VIH = 3 V or VIL = GND TBD TBD µA

LOGIC

= 5 V or VIL = GND TBD TBD µW

Power Supply Rejection Ratio6 PSSR ∆VDD/∆VSS = ±15 V ± 10% 0.0006 0.002 %/%

= 2.7V to 5.5V, VA = VDD, VB = VSS , −40°C < TA < +105°C,

LOGIC

VDD V

50 pF

40 pF

±1 µA

LOGIC

= 2.2kΩ to V

LOGIC

0.4

= 2.2kΩ to V

Gnd

LOGIC

+0.4V

Rev. PrA | Page 5 of 15

AD5293 Preliminary Technical Data

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Parameter Symbol Conditions Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth BW −3 dB TBD kHz Total Harmonic Distortion THDW V

VW Settling Time tS

Resistor Noise Density e

Typicals represent average readings at 25°C,VDD = 15 V, VSS = -15 V and V

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions.

VDD - VSS | = 26V to 30V and 105 to 1,023 for | VDD - VSS | = 21V to 26V;

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0V. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions.

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.

Guaranteed by design and not subject to production test.

Different from operating current; supply current for fuse read lasts approximately TBDµs..

is calculated from (IDD × VDD) + (ISS × VSS) + (I

DISS

All dynamic characteristics use VDD = +15 V, VSS = −15 V and V

6, 9

µs

nV/√Hz

R R R V

±1 LSB error band, R R R

N_WB

= 5 V.

LOGIC

× V

LOGIC

= 5 V.

LOGIC

= 1 V rms, VB = 0 V, f = 1 kHz

= 20 kΩ

= 50 kΩ

= 100 kΩ

= 10 V, VB = 0 V,

= 20 kΩ

= 50 kΩ

= 100 kΩ

= 5 kΩ, TA = 25°C, TBD

-90

-99

2.5 5

Rev. PrA | Page 6 of 15

Preliminary Technical Data AD5293

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INTERFACE TIMING SPECIFICATIONS

VDD / V

Table 3.

Parameter

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Maximum SCLK frequency is 50 MHz

PULL_UP

= ±15 V, V

20 ns min SCLK cycle time

t2 t3 t4 t5 t6 t7 t8 t9

OTP

= 2.2kΩ to V

= 2.7V to 5.5V, and −40°C < TA < + 105°C. All specifications T

LOGIC

Unit

Unit Test Conditions/Comments

10 ns min SCLK high time 10 ns min SCLK low time 15 ns min

SYNC to SCLK falling edge setup time 5 ns min Data setup time 5 ns min Data hold time 0 ns min

TBD µs min

13 ns min TBD ns min TBD ns min

SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK fall ignore RDY rise to SYNC falling edge

SYNC rise to RDY fall time TBD ns min RDY Low Time – RDAC Register write command execute time TBD ns min RDY Low Time – RDAC Register read command execute time

125 ns max SCLK rising edge to SDO valid

TBD(40) ns min SCLK to SDO Data hold time

TBD µs max Power-on OTP restore time

LOGIC

to T

MIN

, unless otherwise noted.

MAX

Figure 2. AD5293 Input Register Content

Rev. PrA | Page 7 of 15

AD5293 Preliminary Technical Data

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TIMING DIAGRAMS

Figure 3. Write Timing Diagram

Figure 4. Read Timing Diagram

Rev. PrA | Page 8 of 15

Preliminary Technical Data AD5293

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND –0.3 V, +35 V VSS to GND +0.3 V, −16.5 V V

to GND -0.3 V to +7 V

LOGIC

VDD to VSS 35 V VA, VB, VW to GND VSS−0.3 V, VDD+0.3 V IA, IB, IW

Pulsed1 ±TBD mA Continuous 20KΩ End-to-End resistance ±3 mA

50KΩ and 100 KΩ End-to-End resistance ±2 mA Digital Input and Output Voltage to GND -0.3 V to V Operating Temperature Range −40°C to +105°C Maximum Junction Temperature (TJ max) 150°C Storage Temperature −65°C to +150°C Reflow Soldering

Peak Temperature 260°C

Time at peak temperature 20 sec to 40 sec Thermal Resistance Junction-to-Ambient2

,TSSOP-14

Thermal Resistance Junction-to-Case3 θJC,

TSSOP-14 Package Power Dissipation (TJ max − TA)/θJA

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.

Thermal Resistance (JEDEC 4 layer(2S2P) board).

93°C/W

20°C/W

LOGIC

+0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrA | Page 9 of 15

AD5293 Preliminary Technical Data

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. 14-pin TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

2 VSS

3 A 4 W 5 B 6 VDD 7 EXT_CAP 8 V

9 GND Ground Pin, Logic Ground Reference. 10 DIN

11 SCLK

13 SDO

14 RDY

RESET

LOGIC

SYNC

Hardware reset pin. Sets the RDAC register to midscale. RESET is activated at the logic high transition. Tie RESET to V

Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF capacitors.

Terminal A of RDAC. VSS ≤ VA ≤ VDD Wiper terminal of RDAC. VSS ≤ VW ≤ VDD Terminal B of RDAC. VSS ≤ VB ≤ VDD Positive Power Supply. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF capacitors. Connect a 1µF capacitor to EXT_CAP. Logic Power Supply; 2.7V to 5.5V. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF

capacitors.

Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz.

Falling edge Synchronisation signal. This is the frame synchronization signal for the input data. When SYNC

register and data is transferred in on the falling edges of the following clocks. The selected DAC register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle the rising edge of SYNC

Serial Data Output. Open Drain Output requires external pull-up resistor. SDO can be used to clock data from the serial register in daisy chain or readback mode.

Ready pin. Active-high open-drain output. Identifies the completion of a write or read operation to/from the RDAC Register or read operation from memory Memory.

if not used.

LOGIC

goes low, it enables the input shift

acts as an interrupt, and the write sequence is ignored by the DAC.

Rev. PrA | Page 10 of 15

Preliminary Technical Data AD5293

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THEORY OF OPERATION

The AD5293 digital potentiometer is designed to operate as a true variable resistor for analog signals that remain within the terminal voltage range of V potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The RDAC register can be programmed with any position setting using the standard SPI serial interface by loading the 16-bit data-word.

< V

< VDD. The digital

TERM

input (DIN) words with the serial data output appearing at the SDO pin in hexadecimal format for an RDAC write and read.

Table 6. RDAC Register Write and Read

DIN SDO Action

0x1802 0xXXXX Enable update of wiper position

0x0600 0x1803 Write 0x100 to the RDAC register,

Wiper moves to ¼ fullscale position.

The AD5293 also features a patented 1% end-to-end resistor tolerance. This simplifies precision, rheostat mode, and openloop applications where knowledge of absolute resistance is critical.

RDAC REGISTER

The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with all zeros, the wiper is connected to Terminal B of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. The RDY pin can be used to monitor the completion of a write to or read from the RDAC register. Prior to 20-TP activation, the AD5293 presets to mid-scale on power-up.

WRITE PROTECTION

On power-up, the serial data input register write command for the RDAC register is disabled. The RDAC write protect bit, C1 of the control register (Table 8), is set to 0 by default. This disables any change of the RDAC register content regardless of the software commands, except that the RDAC register can be refreshed to midscale using the software reset command (command #3) or through hardware by the

enable programming of the variable resistor wiper position (programming the RDAC register) the write protect bit C1 of the control register must first be programmed. This is accomplished by loading the serial data input register with Command #4 (Table 7).

RESET

pin. To

BASIC OPERATION

The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command #1 (Table 7) and the desired wiper position data. The

monitor the completion of this RDAC register write command. (Command #2, Table 7) can be used to readback the contents of the RDAC register. After issuing the readback command the

pin can be monitored to indicate when the data is

RDY available to be read out on SDO in the next SPI operation.

Instead of monitoring the

can be implemented when executing a write or read command. Table 6, provides an example listing of a sequence of serial data

pin, a minimum delay(Table 3)

RDY

pin can be used to

RDY

0x0800 0x0600 Prepare data read from RDAC

0x0000 0x0100 NOP instruction 0 sends 16-bit

word out of SDO, where last 10bits contain the contents of the RDACl Register.

POWER-DOWN MODE

The AD5293 can be powered down by executing the software powerdown command, command 6 (Table 7), and setting the LSB to 1. This feature reduces the power supply current to (TBD) µA and places the RDAC in a zero-power-consumption state where Terminal Ax is open-circuited and the Wiper Wx is connected to Terminal Bx.

RESET

A low to high transition of the hardware

RDAC Register with midscale. The AD5293 can also be reset through software by executing command 3(Table 7).

RESET

pin loads the

SERIAL DATA INTERFACE

The AD5293 contains a serial interface (

SDO), which is compatible with SPI interface standards, as well as most DSPs. This device allows writing of data via the serial interface to every register.

, SCLK, DIN and

SYNC

INPUT SHIFT REGISTER

For the AD5293 the input shift register is 16 bits wide (see Figure 2). The 16-bit word consists of two unused bits (should be set to zero), followed by four control bits, and ten RDAC data bits. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command (Table 7). Figure 3 shows a timing diagram of a typical AD5293 write sequence.

The write sequence begins by bringing the

pin must be held low until the complete data-word is

SYNC loaded from the DIN pin. When

data-word is decoded according to the instructions in Table 7. The command bits (Cx) control the operation of the digital

returns high, the serial

SYNC

line low. The

Rev. PrA | Page 11 of 15

AD5293 Preliminary Technical Data

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potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5293 has an internal counter that counts a multiple of 16 bits (a frame) for proper operation. For example, the AD5293 works with a 32-bit word, but it cannot work properly with a 31-bit or 33-bit word. The AD5293 does not require a continuous SCLK and dynamic power can be saved by only transmitting clock pulses during a serial write. All interface pins should be operated at close to the supply rails to minimize power consumption in the digital input buffers.

DAISY-CHAIN OPERATION

The serial data output pin (SDO) serves two purposes. It can be used to read the contents of the wiper setting using Command 2 (Table 7) or it can be used for daisy chaining multiple devices. The remaining instructions are valid for daisy-chaining multiple devices in simultaneous operations. Daisy-chaining minimizes the number of port pins required from the controlling IC. The SDO pin contains an open-drain N-Ch FET that requires a pull-up resistor, if this function is used. As shown in Figure 6, users need to tie the SDO pin of one package

to the DIN pin of the next package. Users might need to increase the clock period, because the pull-up resistor and the capacitive loading at the SDO–DIN interface might require additional time delay between subsequent devices.

When two AD5293s are daisy-chained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits go to U1. The

clocked into their respective serial registers. The

then pulled high to complete the operation.

pin should be kept low until all 32 bits are

SYNC

Figure 6. Daisy-Chain Configuration Using SD

SYNC

pin is

Table 7. Command Operation Truth Table

Command Data Operation

Command Number

0 0 0 0 0 X X X X X X X X X X NOP: Do nothing. 1 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

2 0 0 1 0 X X X X X X X X X X

3 0 1 0 0 X X X X X X X X X X Reset: Refresh RDAC with midscale code 4 0 1 1 0 X X X X X X X D2 D1 D0

5 0 1 1 1 X X X X X X X X X X

6 1 0 0 0 X X X X X X X X X D0 Software Powerdown

Table 8. Control Register and special function codes

Control X X X X X X X C2 C1 X C1 = RDAC Register Write Protect.

B13 B9 B8 B7 B0 C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Operation

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 = Wiper position frozen to Midscale(Default) 1 = Allow update of wiper position through Digital Interface C2 = Calibration Enable. 0 = RDAC Resistor Tolerance Calibration enabled(Default) 1 = RDAC Resistor Tolerance Calibration enabled

Write contents of Serial Register Data to RDAC.

Read RDAC wiper setting from SDO output in the next frame.

Write Contents of Serial Register Data to Control Register

Read Control Register from SDO output in the next frame.

D0 = 0; Normal Mode D0 = 1; Device placed in powerdown

mode

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RDAC ARCHITECTURE

In order to achieve optimum cost performance, Analog Devices has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5293 employs a 3-stage segmentation approach as shown in Figure 7. The AD5293 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from V

of ±1% absolute resistance error over both the full supply and temperature ranges. determining the digitally programmed output resistance between the W terminal and B terminal is

where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register.

is the end-to-end resistance.

Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, R

is also calibrated to give a maximum of 1% absolute

resistance error. and decreases as the data loaded into the latch increases. The general equation for this operation is

where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register.

is the end-to-end resistance.

As a result, the general equation for

DR ×=

)( (1)

starts at the maximum resistance value

RWA

DR ×

024,1

)( (2)

024,1

ABWB

−

ABWA

Figure 7. AD5293 Simplified RDAC Circuit.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation - 1% Resistor Tolerance

The AD5293 operates in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating or tied to the W terminal as shown in Figure 8.

Figure 8. Rheostat Mode Configuration

The no mi na l r e si st a nc e be t we e n Te r mi na l A a n d Te rm i na l B, R

, is available in 20 kΩ, 50 kΩ, and 100 kΩ and has 1,024 tap

points accessed by the wiper terminal. The 10-bit data in the RDAC latch is decoded to select one of the 1,024 possible wiper settings. The AD5293 contains an internal ±1% resistor tolerance calibration feature which can be disabled or enabled, enabled by default, by programming bit C2 of the control register (Table 8). The digitally programmed output resistance between the W terminal and the A terminal, R terminal and B terminal, R

, is calibrated to give a maximum

and the W

In the zero-scale condition, a finite total wiper resistance of TBD Ω is present. Regardless of which setting the part is operating in, care should be taken to limit the current between the A terminal to B terminal, W terminal to A terminal, and W terminal to B terminal, to the maximum continuous current of ±3 mA(20KΩ) or ±2 mA(50KΩ and 100 KΩ) or pulse current of TBD mA. Otherwise, degradation, or possible destruction of the internal switch contact, can occur.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at wiper to B and wiper to A proportional to the input voltage at A to B as shown in Figure 9. Unlike the polarity of V GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity.

Figure 9. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground produces an output voltage at the Wiper W to Terminal B

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AD5293 Preliminary Technical Data

www.BDTIC.com/ADI

ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B, divided by the 1,024 positions of the potentiometer divider. The general equation defining the output voltage at V

with respect

to ground for any valid input voltage applied to Terminal A and Terminal B is

−

024,1

BAW

(3)

DV ×

)(

+×=

024,1

In voltage divider mode, to optimize wiper position update rate, it is recommended to disable the internal ±1% resistor tolerance calibration feature by programming bit C2 of the control register (able 9).

Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors R

and RWB and not the

absolute values. Therefore, the temperature drift reduces to 5 ppm/°C.

EXT_CAP CAPACITOR

A 1µF capacitor to GND must be connected to the EXT_CAP pin (Figure 10) on power-up and throughout the operation of the AD5293.

02816-B-041

Figure 11. Maximum Terminal Voltages Set by V

and V

The ground pin of the AD5293 device is primarily used as a digital ground reference. To minimize the digital ground bounce, the AD5293 ground terminal should be joined remotely to the common ground. The digital input control signals to the AD5293 must be referenced to the device ground pin (GND), and satisfy the logic level defined in the Specifications section.

Power-Up Sequence

Because there are diodes to limit the voltage compliance at Terminals A, B, and W (Figure 11), it is important to power V

first before applying any voltage to Terminals A, B,

DD/VSS

and W. Otherwise, the diode is forward-biased such that V

are powered unintentionally. The ideal power-up

DD/VSS

sequence is GND, V and V

. The order of powering VA, VB, VW, and digital inputs is

not important as long as they are powered after V V

LOGIC

DD/VSS

, V

, digital inputs, and VA, VB,

LOGIC

DD/VSS

and

Figure 10. Hardware setup for EXT_CAP pin

TERMINAL VOLTAGE OPERATING RANGE

The AD5293’s positive VDD and negative VSS power supplies define the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on Terminals A, B, and W that exceed V forward-biased diodes (see Figure 11).

or VSS are clamped by the internal

Regardless of the power-up sequence and the ramp rates of the power supplies, once V

is powered, the power-on preset

LOGIC

activates, which restores midscale to the RDAC register.

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Preliminary Technical Data AD5293

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

Figure 12. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD5293ABRUZ20 20 1,024 −40°C to +105°C 14-Lead TSSOP RU-14 AD5293ABRUZ50 50 1,024 −40°C to +105°C 14-Lead TSSOP RU-14

AD5293ABRUZ100 100 1,024 −40°C to +105°C 14-Lead TSSOP RU-14

(kΩ)

Resolution Temperature

Range

Package

Description

Package

Option

PR07675-0-7/08(PrA)

Rev. PrA | Page 15 of 15

ANALOG DEVICES AD5293 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual