ANALOG DEVICES AD5293 Service Manual

Single Channel, 1024-Position, 1% R-Tol, Digital

www.BDTIC.com/ADI

Potentiometer

Preliminary Technical Data

FEATURES

Single-channel, 1024-position resolution
20 kΩ, 50 kΩ and 100 kΩ nominal resistance
Calibrated 1% Nominal Resistor Tolerance
Rheostat mode temperature coefficient: 35 ppm/°C
Voltage divider temperature coefficient: 5 ppm/°C
+21V to +30V single-supply operation
±10.5V to ±15V dual-supply operation
SPI® compatible serial interface
Wiper setting readback

APPLICATIONS

Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage to current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

GENERAL DESCRIPTION

The AD5293 is a single-channel, 1,024-position digital
potentiometer
error. The AD5293 performs the same electronic adjustment
function as a mechanical potentiometer with enhanced
resolution, solid state reliability, and superior low temperature
coefficient performance. This device is capable of operating at
high-voltages; supporting both dual supply ±10.5 to ±15V and
single supply operation +21V to +30V.

The AD5293 offers guaranteed industry leading low resistor
tolerance errors of ±1% with a nominal temperature coefficient
of 35 ppm/ºC. The low resistor tolerance feature simplifies
open-loop applications as well as precision calibration and
tolerance matching applications.

1

with less than 1% end-to-end Resistor Tolerance

AD5293

FUNCTIONAL BLOCK DIAGRAM

Figure 1. 14ld TSSOP

The AD5293 is available in a compact 14ld TSSOP package. The
part is guaranteed to operate over the extended industrial
temperature range of −40°C to +105°C.

1

The terms digital potentiometer and RDAC are used interchangeably.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2008 Analog Devices, Inc. All rights reserved.

AD5293 Preliminary Technical Data

www.BDTIC.com/ADI

TABLE OF CONTENTS

REVISION HISTORY

Revision: Preliminary Version

Rev.PrA | Page 2 of 15

Preliminary Technical Data AD5293

www.BDTIC.com/ADI

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS – 20KΩ VERSION

VDD = 21V to 30V, VSS = 0V; VDD = 10.5V to 16.5V, VSS = -10.5V to -16.5V; V
unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS— RHEOSTAT MODE

Resolution N 10 Bits
Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB
Resistor Integral Nonlinearity2 R-INL R
R-INL R

= 20KΩ, |V

AB

= 20KΩ, |V

AB

Nominal Resistor Tolerance3 ∆RAB/RAB −1 0.5 +1 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW TBD TBD Ω

DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE

Resolution N 10 Bits
Differential Nonlinearity4 DNL −1 +1 LSB
Integral Nonlinearity4 INL −1 +1 LSB
Voltage Divider Temperature

(∆V

)/∆T × 106 Code = half-scale 5 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

Code = full scale −6 0 LSB

WFSE

Code = zero scale 0 TBD LSB

WZSE

RESISTOR TERMINALS

Terminal Voltage Range5 V
Capacitance6 A, B C

V

A, B, W

f = 1 MHz, measured to GND,

A, B

Code = half-scale

Capacitance6 W CW f = 1 MHz, measured to GND,

Code = half-scale

Common-Mode Leakage Current6 ICM V

= VB = VW 0.001 50 nA

A

DIGITAL INPUTS JEDEC compliant

Input Logic High VIH V
V

V

IH

Input Logic Low VIL V
Input Current IIL V
Input Capacitance6 C

5 pF

IL

= 4.5V to 5.5 V 2.0 V

LOGIC

= 2.7V to 3.6 V 1.8 V

LOGIC

= 2.7V to 5.5 V 0.8 V

LOGIC

= 0 V or V

IN

DIGITAL OUTPUTS(SDO and RDY)

Output High Voltage VOH R

Output Low Voltage VOL R

PULL_UP

PULL_UP

Three state Leakage Current -1 1 µA
Output Capacitance6 COL 5 pF

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 21 30 V

SS

Dual-Supply Power Range VDD/VSS ±10.5 ±16.5 V
Positive Supply Current IDD V
Negative Supply Current ISS V
Logic Supply Range V
Logic Supply Current I
I
Memory Read Current

6,7

2.7 5.5 V

LOGIC

V

LOGIC

V

LOGIC

I

LOGIC_FUSE_READ

VIH = 5 V or VIL = GND TBD mA

/ VSS = ±16.5 V TBD TBD µA

DD

/VSS = ±16.5 V TBD TBD µA

DD

= 5 V; VIH = 5 V or VIL = GND TBD TBD µA

LOGIC

= 3 V; VIH = 3 V or VIL = GND TBD TBD µA

LOGIC

= 2.7V to 5.5V, VA = VDD, VB = VSS , −40°C < TA < +105°C,

LOGIC

− V

| = 26V to 30V −1.5 +1.5 LSB

DD

SS

− V

| = 21V to 26V −2 +2 LSB

DD

SS

VDD V

SS

50 pF

40 pF

±1 µA

LOGIC

= 2.2kΩ to V

LOGIC

V

LOGIC

V

-

0.4

= 2.2kΩ to V

Gnd

LOGIC

V

+0.4V

Rev. PrA | Page 3 of 15

AD5293 Preliminary Technical Data

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ1 Max Unit

Power Dissipation8 P
Power Supply Rejection Ratio6 PSSR ∆VDD/∆VSS = ±15 V ± 10% 0.0006 0.002 %/%

DYNAMIC CHARACTERISTICS

6, 9

Bandwidth BW −3 dB TBD kHz
Total Harmonic Distortion THDW V

VW Settling Time tS

Resistor Noise Density e

1

Typicals represent average readings at 25°C,VDD = 15 V, VSS = -15 V and V

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions.

3

±1% resistor tolerance code range; R

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0V. DNL specification limits of

±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.

6

Guaranteed by design and not subject to production test.

7

Different from operating current; supply current for fuse read lasts approximately TBDµs..

8

P

is calculated from (IDD × VDD) + (ISS × VSS) + (I

DISS

9

All dynamic characteristics use VDD = +15 V, VSS = −15 V and V

= 20KΩ: 250 to 1,023 for | VDD - VSS | = 26V to 30V and 383 to 1,023 for | VDD - VSS | = 21V to 26V

AB

V

DISS

= 5 V or VIL = GND TBD TBD µW

IH

= 1 V rms, VB = 0 V, f = 1 kHz

A

R

= 20 kΩ

AB

R

= 50 kΩ

AB

R

= 100 kΩ

AB

= 10 V, VB = 0 V,

V

A

±1 LSB error band,
R

= 20 kΩ

AB

R

= 50 kΩ

AB

R

= 100 kΩ

AB

R

N_WB

× V

LOGIC

).

= 5 V.

LOGIC

LOGIC

= 5 kΩ, TA = 25°C, TBD

WB

= 5 V.

LOGIC

-90

-99

-99

1

2.5
5

dB

µs

nV/√Hz

Rev. PrA | Page 4 of 15

Preliminary Technical Data AD5293

www.BDTIC.com/ADI

ELECTRICAL CHARACTERISTICS – 50KΩ AND 100KΩ VERSIONS

VDD = 21V to 30V, VSS = 0V; VDD = 10.5V to 16.5V, VSS = -10.5V to -16.5V; V
unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS— RHEOSTAT MODE

Resolution N 10 Bits
Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB
Resistor Integral Nonlinearity2 R-INL −1 +1 LSB
Nominal Resistor Tolerance3 ∆RAB/RAB −1 0.5 +1 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW TBD TBD Ω

DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE

Resolution N 10 Bits
Differential Nonlinearity4 DNL −1 +1 LSB
Integral Nonlinearity4 INL −1 +1 LSB
Voltage Divider Temperature

(∆V

)/∆T × 106 Code = half-scale 5 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

Code = full scale −6 0 LSB

WFSE

Code = zero scale 0 TBD LSB

WZSE

RESISTOR TERMINALS

Terminal Voltage Range5 V
Capacitance6 A, B C

V

A, B, W

f = 1 MHz, measured to GND,

A, B

Code = half-scale

Capacitance6 W CW f = 1 MHz, measured to GND,

Code = half-scale

Common-Mode Leakage Current6 ICM V

= VB = VW 0.001 50 nA

A

DIGITAL INPUTS JEDEC compliant

Input Logic High VIH V
V

V

IH

Input Logic Low VIL V
Input Current IIL V
Input Capacitance6 C

5 pF

IL

= 4.5V to 5.5 V 2.0 V

LOGIC

= 2.7V to 3.6 V 1.8 V

LOGIC

= 2.7V to 5.5 V 0.8 V

LOGIC

= 0 V or V

IN

DIGITAL OUTPUTS(SDO and RDY)

Output High Voltage VOH R

Output Low Voltage VOL R

PULL_UP

PULL_UP

Three state Leakage Current -1 1 µA
Output Capacitance6 COL 5 pF

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 21 30 V

SS

Dual-Supply Power Range VDD/VSS ±10.5 ±16.5 V
Positive Supply Current IDD V
Negative Supply Current ISS V
Logic Supply Range V
Logic Supply Current I
I
OTP Read Current

6,7

Power Dissipation8 P

2.7 5.5 V

LOGIC

V

LOGIC

V

LOGIC

I

LOGIC_FUSE_READ

V

DISS

VIH = 5 V or VIL = GND TBD mA

/ VSS = ±16.5 V TBD TBD µA

DD

/VSS = ±16.5 V TBD TBD µA

DD

= 5 V; VIH = 5 V or VIL = GND TBD TBD µA

LOGIC

= 3 V; VIH = 3 V or VIL = GND TBD TBD µA

LOGIC

= 5 V or VIL = GND TBD TBD µW

IH

Power Supply Rejection Ratio6 PSSR ∆VDD/∆VSS = ±15 V ± 10% 0.0006 0.002 %/%

= 2.7V to 5.5V, VA = VDD, VB = VSS , −40°C < TA < +105°C,

LOGIC

VDD V

SS

50 pF

40 pF

±1 µA

LOGIC

= 2.2kΩ to V

LOGIC

V

LOGIC

V

-

0.4

= 2.2kΩ to V

Gnd

LOGIC

V

+0.4V

Rev. PrA | Page 5 of 15