ANALOG DEVICES AD5282 Service Manual

Single/Dual, +15 V/±5 V, 256-Position,

A

S

A

www.BDTIC.com/ADI

I2C-Compatible Digital Potentiometer

FEATURES

AD5280: 1 channel AD5282: 2 channels 256 positions 5 V to 15 V single supply; ±5.5 V dual-supply operation Fixed terminal resistance: 20 kΩ, 50 kΩ, 200 kΩ Low temperature coefficient: 30 ppm/°C Power-on midscale preset Programmable reset Operating temperature: −40

2

I

C-compatible interface

APPLICATIONS

Multimedia, video, and audio Communications Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage source Programmable current source Line impedance matching

GENERAL DESCRIPTION

The AD5280/AD5282 are single-channel and dual-channel, 256-position, digitally controlled variable resistors (VRs) The devices perform the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. Each VR offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a 1% channel-to-channel matching tolerance. The nominal temperature coefficient of both parts is 30 parts per million/ degrees centigrade (ppm/°C). Another key feature is that the parts can operate up to +15 V or ±5 V.

Wiper position programming defaults to midscale at system

wer-on. When powered, the VR wiper position is programmed

po

2

by an I

C-compatible, 2-wire serial data interface. The AD5280/ AD5282 feature sleep mode programmability. This allows any level of preset in power-up and is an alternative to a costly EEPROM solution. Both parts have additional programmable

1

Assert shutdown and program the device during power-up, then deassert

the shutdown to achieve the desired preset level.

2

The terms digital potentiometer, VR, and RDAC are used interchangeably.

1

o

C to +85oC

2

.

AD5280/AD5282

logic outputs that enable users to drive digital loads, logic gates, LED drivers, and analog switches in their system.

The AD5280/AD5282 are available in thin, surface-mounted 14-lead TSSOP and 16-lead TSSOP. All parts are guaranteed to operate over the extended industrial temperature range of

−40°C to +85°C. For 3-wire SPI-compatible interface applications, see the

w.analog.com.

ww

SHDN

V

DD

V

SS

SCL

SDA

GND

AD5260/AD5262 product information on

FUNCTIONAL BLOCK DIAGRAMS

WB O1O

HDN

V

DD

V

L

V

SS

SCL

SDA

GND

L

RDAC REGISTER OUTPUT REG ISTER

ADDRESS

CODE

SERIAL INPUT REGISTER

AD0 AD1

Figure 1. AD5280

1W1B1

RDAC1 REGISTE R RDAC2 REGISTE R

ADDRESS

CODE

SERIAL INPUT REGISTER

AD0 AD1

A2W2B

8

Figure 2. AD5282

PWR ON

8

2

PWR ON

RESET

2

RESET

AD5280

OUTPUT

REGIS TER

AD5282

02929-070

O

1

02929-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5280/AD5282

www.BDTIC.com/ADI

REVISION HISTORY

8/07—Rev. A to Rev. B

Updated Operating Temperature Range Throughout...................1

hanges to the Features Section .......................................................1

C

Changes to the General Description Section..................................1

Changes to Table 2..............................................................................3

Added the Thermal Resistance Section...........................................5

Changes to the Ordering Guide......................................................26

11/05—Rev. 0 to Rev. A

Updated Format................................................................... Universal

Updated Outline Dimensions.........................................................26

Changes to Ordering Guide............................................................27

10/02—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD5280/AD5282

www.BDTIC.com/ADI

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = +15 V, VSS = 0 V or VDD = +5 V, VSS = −5 V; V

= 5 V, VA = +VDD, VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.

LOGIC

Table 1.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS–RHEOSTAT MODE

Resistor Differential NL Resistor Nonlinearity Nominal Resistor Tolerance Resistance Temperature

Coefficient

Wiper Resistance R

2

R-DNL RWB, VA = NC −1 ±1/4 +1 LSB R-INL RWB, VA = NC −1 ±1/4 +1 LSB

3

ΔR

T

AB

(∆RAB/RAB)/∆T x 10

I

W

DC CHARACTERISTICS–POTENTIOMETER DIVIDER MODE (specifications apply to all VRs)

Resolution N Integral Nonlinearity Differential Nonlinearity Voltage Divider Temperature

4

INL DNL (∆V

)/∆T x 106 Code = 0x80

W/VW

= 25°C −30

A

6

VAB = VDD, wiper = no connect

= VDD/R, VDD = 3 V or 5 V

W

30

60 150 Ω

8

−1 ±1/4 +1 LSB

−1 ±1/4 +1 LSB 5

Coefficient Full-Scale Error V Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range Capacitance A, B

Capacitance W

5

6

Common-Mode Leakage I Shutdown Current I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V Input Logic Low V Output Logic High (O1, O2) V Output Logic Low (O1, O2) V Input Current I Input Capacitance

6

POWER SUPPLIES

Logic Supply V Power Single-Supply Range V Power Dual-Supply Range V Logic Supply Current I Positive Supply Current I Negative Supply Current I Power Dissipation

7

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

6, 8 , 9

Bandwidth −3 dB BW_20K RAB = 20 kΩ, Code = 0x80

Code = 0xFF −2 −1 0 LSB

WFSE

Code = 0x00 0 +1 +2 LSB

WZSE

VA, VB, V CA, C

C

CM

SHDN

W

B

W

V

f = 5 MHz, measured to GND,

Code = 0x80

f = 1 MHz, measured to GND, Code = 0x80

= VB = V

A

W

SS

25

55

1

IH

IL

IH

IL

V

IL

C

IL

0.7 × VL 0

4.9

= 0 V or 5 V

IN

5

LOGI C

V

DD RANGE

DD/SS RANGE

LOGI C

DD

SS

P

DISS

V

= 0 V 4.5

SS

= 5 V

LOGI C

= 5 V or VIL = 0 V

IH

2.7

±4.5

VIH = 5 V or VIL = 0 V, VDD = +5 V, VSS = −5 V

0.1 1 μA

0.2 0.3 mW

0.002 0.01 %/%

310 150 35

BW_50K RAB = 50 kΩ, Code = 0x80 BW_200K RAB = 200 kΩ, Code = 0x80

1

Max Unit

+30 %

V

DD

5 μA

VL + 0.5 V

0.3 × VL V

0.4 V ±1 μA

VDD V

16.5 V ±5.5 V 60 μA

ppm/°C

Bits

ppm/°C

pF

nA

V

pF

kHz kHz kHz

Rev. B | Page 3 of 28

AD5280/AD5282

S

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ

Total Harmonic Distortion THD

VW Settling Time t Crosstalk CT

V

W

V

S

= 1 V rms, RAB = 20 kΩ

A

VB = 0 V dc, f = 1 kHz

= 5 V, VB = 5 V, ±1 LSB error band

A

= VDD, VB = 0 V, measure VW1 with

V

A

0.014

5 15

1

Max Unit

%

μs

nV-s adjacent RDAC making full-scale code change

Analog Crosstalk CTA

Measure V 10 kHz

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS (applies to all parts)

SCL Clock Frequency f t

Bus Free Time Between

BUF

Stop and Start

t

Hold Time (Repeated

HD:STA

Start)

t

Low Period of SCL Clock t3

LOW

t

High Period of SCL Clock t4

HIGH

t

Setup Time for Start

SU:STA

Condition

t

Data Hold Time t6

HD:DAT

t

Data Setup Time t7

SU:DAT

tF Fall Time of Both SDA and

SCL Signals

tR Rise Time of Both SDA and

SCL Signals

t

Setup Time for STOP

SU:STO

Condition

1

Typicals represent average readings at 25°C, VDD = +5 V, VSS = −5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

8

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

9

All dynamic characteristics use VDD = 5 V.

10

See timing diagram (Figure 3) for location of measured values.

11

Standard I2C mode operation is guaranteed by design.

R

N_WB

SCL

t

1

t

2

t5

t8

t9

t10

= 20 kΩ, f = 1 kHz

WB

6, 10 , 11

After this period, the first clock pulse is generated

with VW2 = 5 V p-p @ f =

W1

0

1.3

0.6

1.3

0.6

0

100

0.6

−62

18

dB

nV/√Hz

400 kHz

μs

0.9 μs ns

300 ns

μs

t

8

t

6

9

2

SCL

t

DA

t

1

PS S

t

2

3

t

9

t

8

t

4

Figure 3. Detailed Timing Diagram

Rev. B | Page 4 of 28

t

7

t

5

t

10

02929-042

P

AD5280/AD5282

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

VDD to GND −0.3 V to +16.5 V VSS to GND 0 V to −7 V VDD to VSS 16.5 V VA, VB, VW to GND VSS to V AX to BX, AX to WX, BX to W

Intermittent Continuous ±5 mA

V

to GND 0 V to 7 V

LOGI C

Output Voltage to GND 0 V to 7 V Operating Temperature Range −40°C to +85°C Maximum Junction Temperature (T Storage Temperature Range −65°C to +150°C Reflow Soldering

Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec

3

Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.

3

X

) 150°C

JMAX

±20 mA

DD

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Package power dissipation = (T

JMAX

− TA)/ θ

JA .

Table 3. Thermal Resistance

Package Type θJA Unit

TSSOP-14 206 °C/W TSSOP-16 150 °C/W

ESD CAUTION

Rev. B | Page 5 of 28

AD5280/AD5282

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

SHDN

SCL

SDA

1

A

2

W

3

B

AD5280

TOP VIEW

4

DD

5

6

7

14

O

1

13

V

L

12

O

2

11

V

SS

10

GND

9

AD1

8

AD0

Figure 4. AD5280 Pin Configuration

Table 4. AD5280 Pin Function Descriptions

Pin No. Mnemonic Description

1 A Resistor Terminal A. 2 W Wiper Terminal W. 3 B Resistor Terminal B. 4 VDD

Positive Power Supply. Specified for operation from 5 V to 15 V (sum of |V + |V

| ≤ 15 V).

SS

5

Active Low, Asynchronous Connection

SHDN

of Wiper W to Terminal B and Open Circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to V

if not used. Can also be used as a

L

programmable preset in power-up. 6 SCL Serial Clock Input. 7 SDA Serial Data Input/Output. 8 AD0

Programmable Address Bit 0 for

ultiple Package Decoding. Bit AD0

M

and Bit AD1 provide four possible

addresses. 9 AD1

Programmable Address Bit 1 for

ultiple Package Decoding. Bit AD0

M

and Bit AD1 provide four possible

addresses. 10 GND Common Ground. 11 VSS

Negative Power Supply. Specified for

operation from 0 V to −5 V (sum of |V

+ |V

| ≤ 15 V).

SS

12 O2 Logic Output Terminal O2. 13 VL

Logic Supply Voltage. Needs to be less

than or equal to V

and at the same

DD

voltage as the digital logic controlling

the AD5280. 14 O1 Logic Output Terminal O1.

1

O

1

2

A

1

3

W

1

AD5282

4

B

1

TOP VIEW

5

V

DD

6

SHDN

7

02929-002

SCL

SDA

8

16

A

2

15

W

2

14

B

2

13

V

L

12

V

SS

11

GND

10

AD1

9

AD0

02929-003

Figure 5. AD5282 Pin Configuration

Table 5. AD5282 Pin Function Descriptions

Pin No. Mnemonic Description

1 O1 Logic Output Terminal O1. 2 A1 Resistor Terminal A1. 3 W1 Wiper Terminal W1. 4 B1 Resistor Terminal B1.

|

DD

5 VDD

6

SHDN

Positive Power Supply. Specified for operation from 5 V to 15 V (sum of |V + |V

| ≤ 15 V).

SS

DD

Active Low, Asynchronous Connection

|

of Wiper W to Terminal B and Open Circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to V

if not used. Can be also used as a

L

programmable preset in power-up. 7 SCL Serial Clock Input. 8 SDA 9 AD0

Serial Data Input/Output.

Programmable Address Bit 0 for

Multiple Package Decoding. Bit AD0

and Bit AD1 provide four possible

addresses. 10 AD1

Programmable Address Bit 1 for

Multiple Package Decoding. Bit AD0

and Bit AD1 provide four possible

addresses. 11 GND

|

DD

12 V

13 V

SS

L

Common Ground.

Negative Power Supply. Specified for

operation from 0 V to −5 V (sum of |V

+ |V

| ≤ 15 V).

SS

Logic Supply Voltage. Needs to be less

than or equal to V

and at the same

DD

|

DD

voltage as the digital logic controlling

the AD5282. 14 B

Resistor Terminal B2.

2

15 W2 Wiper Terminal W2. 16 A2 Resistor Terminal A2.

Rev. B | Page 6 of 28

AD5280/AD5282

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

RHEOSTAT MO DE R-INL (LSB)

–0.6

–0.8

–1.0

0 32 96 160 22464 128 192 256

+5V

±5V

+15V

CODE (Decimal)

R

T

Figure 6. R-INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

RHEOSTAT MODE R-DNL (LSB)

–0.8

–0.5

0 32 96 160 22464 128 192 256

±5V +15V

+5V

CODE (Decimal)

R

T

Figure 7. R-DNL vs. Code vs. Supply Voltages

1.0

R

DD/VSS

AB

= ±5 V

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTI OMETER MO DE INL (LSB)

–0.8

–1.0

TA = +85°C

TA = –40°C

TA = +25°C

0 32 96 160 22464 128 192 256

CODE (Decimal)

Figure 8. INL vs. Code, V

AB

= 25°C

A

AB

= 25°C

A

= 20k

= 20k

02929-004

= 20k

02929-005

02929-006

0.5

0.4

0.3

0.2

TA = –40°C TA = +85°C

0.1

0

–0.1

–0.2

–0.3

POTENTI OMETER MO DE DNL (LSB)

–0.4

–0.5

0 32 96 160 22464 128 192 256

CODE (Decimal)

Figure 9. DNL vs. Code, V

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTI OMETER MO DE INL (LSB)

–0.8

–1.0

0 32 96 160 22464 128 192 256

±5V

+5V

CODE (Decimal)

DD/VSS

RAB = 20k

= ±5 V

RAB = 20k T

+15V

Figure 10. INL vs. Code vs. Supply Voltages

0.5

+15V

RAB = 20k T

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENTI OMETER MO DE INL (LSB)

–0.4

–0.5

±5V

0 32 96 160 22464 128 192 256

+5V

CODE (Decimal)

Figure 11. DNL vs. Code vs. Supply Voltages

T

= 25°C

A

= 25°C

A

= +25°C

A

02929-007

02929-008

02929-009

Rev. B | Page 7 of 28

AD5280/AD5282

www.BDTIC.com/ADI

1.0

AVG +3

0.5

0

INL (LSB)

–0.5

–1.0

0 5 10 15 20

2.0

1.5

1.0

0.5

0

R-INL (LSB)

–0.5

–1.0

–1.5

AVG

AVG –3 

Figure 12. INL Over Supply Voltage

AVG +3

AVG

AVG –3 

|VDD– VSS| (V)

RAB = 20k T

= 25°C

A

RAB = 20k T

= 25°C

A

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

ZERO-SCALE ERROR (LSB)

0.4

0.2

02929-010

0

–40 0–20 20 40 60 80 100

VDD/VSS= +5V/0V

VDD/VSS= ±5V

VDD/VSS= +15V/0V

TEMPERATURE (°C)

RAB = 20k

02929-013

Figure 15. Zero-Scale Error

1000

100

|SS@VDD/VSS= +15V/0V

SUPPLY CURRENT (nA)

10

SS

/I

DD

I

|SS@VDD/VSS= ±5V

RAB = 20k V

|DD@VDD/VSS= ±5V

LOGIC

V

IH

V

IL

= +5V

= 0V

= +5V

–2.0

0 5 10 15 20

|VDD– VSS| (V)

Figure 13. R-INL Over Supply Voltage

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

FULL-SCALE ERROR (LSB)

–1.6

–1.8

–2.0

–40 0–20 20 40 60 80 100

VDD/VSS= +15V/0V

VDD/VSS= ±5V

VDD/VSS= +5V/0V

TEMPERATURE (°C)

RAB = 20k

Figure 14. Full-Scale Error

02929-011

1

–40 –7 26 59 85

TEMPERATURE (°C)

02929-014

Figure 16. Supply Current vs. Temperature

26.0

25.5

25.0

(µA)

24.5

LOGIC

I

24.0

23.5

02929-012

23.0 –40 –7 26 59 85

Figure 17. V

TEMPERATURE ( °C)

Supply Current vs. Temperature

LOGIC

RAB = 20k

VDD/VSS= +15V/0V

VDD/VSS= ±5V

02929-015

Rev. B | Page 8 of 28

AD5280/AD5282

A

www.BDTIC.com/ADI

1000

VDD/VSS= 5V/0V V

LOGIC

(µA)

100

LOGIC

I

VDD/VSS= 5V/0V V

= 3V

LOGIC

10

01234

Figure 18. V

700

600

500

400

300

200

T MODE TEMPCO (ppm/°C)

100

0

RHEOST

–100

–200

0 32 64 19296 128 224 256

Supply Current vs. Digital Input Voltage

LOGIC

20k

50k

200k

Figure 19. Rheostat Mode Tempco ΔR

120

100

80

60

40

20

0

–20

POTENTI OMETER MO DE TEMPCO (ppm/° C)

–40

0 32 64 19296 128 224 256

20k

50k

200k

Figure 20. Potentiometer Mode Tempco ΔV

(V)

V

IH

CODE (Decimal)

WB

CODE (Decimal)

= ±5 V

V

DD/VSS

/ΔT vs. Code, VDD/VSS = ±5 V

WB

RAB = 20k T

= 25°C

A

= 5V

TA = 25°C

/ΔT vs. Code,

02929-016

5

02929-017

02929-018

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0 10k 100k 1M

80H

40H

20H

10H

08H

04H

02H

01H

FREQUENCY (Hz)

TA = 25°C V V

Figure 21. Gain vs. Frequency vs. Code, R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0 10k 100k 1M

80H

40H

20H

10H

08H

04H

02H

01H

FREQUENCY (Hz)

TA = 25°C V V

Figure 22. Gain vs. Frequency vs. Code, R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0 10k 100k 1M

80H

40H

20H

10H

08H

04H

02H

01H

FREQUENCY (Hz)

TA = 25°C V V

Figure 23. Gain vs. Frequency vs. Code, R

= 50mV rms

A

= ±5V

DD/VSS

= 20 kΩ

AB

= 50mV rms

A

= ±5

DD/VSS

= 50 kΩ

AB

= 50mV rms

A

= ±5V

DD/VSS

= 200 kΩ

AB

02929-019

02929-020

02929-021

Rev. B | Page 9 of 28

ANALOG DEVICES AD5282 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS