Analog Devices AD5280 2 Datasheet

15 V, I2C Compatible

a

256-Position Digital Potentiometers

FEATURES
256 Position
AD5280: 1-Channel
AD5282: 2-Channel (Independently Programmable)
Potentiometer Replacement
20 k, 50 k, 200 k
Low Temperature Coefficient 30 ppm/°C
Internal Power-On Midscale Preset
5 V to 15 V Single-Supply; 5.5 V Dual-Supply Operation

2

C Compatible Interface

I

APPLICATIONS
Multimedia, Video, and Audio
Communications
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage Source
Programmable Current Source
Line Impedance Matching

GENERAL DESCRIPTION

The AD5280/AD5282 provides a single-/dual-channel, 256-position
digitally controlled variable resistor (VR) device.

1

These devices
perform the same electronic adjustment function as a potenti­ometer, trimmer, or variable resistor. Each VR offers a completely
programmable value of resistance between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a 1% chan­nel-to-channel matching tolerance. Nominal temperature
coefficient of both parts is 30 ppm/°C. Another key feature of
these parts is that they can operate up to +15 V or ±5 V.

Wiper position programming defaults to midscale at system
power-on. Once powered, the VR wiper position is programmed

2

by an I

C compatible 2-wire serial data interface. Both parts
have additional programmable logic outputs that enable users to
drive digital loads, logic gates, LED drivers, and analog switches
in their system.

The AD5280/AD5282 are available in thin surface-mount
14-lead and 16-lead TSSOP packages. All parts are guaranteed
to operate over the extended industrial temperature range
of –40°C to +85°C. For 3-wire SPI compatible interface appli-
cations, see AD5260/AD5262 products.

SHDN

V

V

SCL

SDA

GND

AD5280/AD5282

*

FUNCTIONAL BLOCK DIAGRAMS

AW B O

SHDN

V

DD

V

SS

V

L

SCL

SDA

GND

DD

SS

V

L

ADDRESS

DECODE

RDAC REGISTER

ADDRESS

DECODE

SERIAL INPUT REGISTER

AD0

AD1

A1W1B

RDAC1 REGISTER

SERIAL INPUT REGISTER

AD0

AD1

OUTPUT REGISTER

A2W2B

1

RDAC2 REGISTER

8

1

8

2

O

PWR ON

RESET

AD5280

PWR ON

RESET

2

O

1

OUTPUT

REGISTER

AD5282

*

Patent Pending.

NOTE

1

The terms digital potentiometer, VR, and RDAC are used interchangeably.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD5280/AD5282–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS 20 k, 50 k, 200 k VERSION

(VDD = +15 V, VSS = 0 V or VDD = +5 V, VSS = –5 V; V

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS–RHEOSTAT MODE Specifications apply to all VRs

Resistor Differential NL
Resistor Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient R
Wiper Resistance R

2

2

3

R-DNL RWB, VA = NC –1 ± 1/4 +1 LSB
R-INL RWB, VA = NC –1 ± 1/4 +1 LSB
⌬R

AB

/⌬TV

AB

W

DC CHARACTERISTICS–POTENTIOMETER DIVIDER MODE Specifications apply to all VRs

Resolution N 8 Bits
Integral Nonlinearity
Differential Nonlinearity
Voltage Divider Temperature ⌬V

4

4

INL –1 ± 1/4 +1 LSB
DNL –1 ± 1/4 +1 LSB

W

Coefficient

Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance

5

6

A, B C

Capacitance6 WC

Common-Mode Leakage I
Shutdown Current I

WFSE

WZSE

V

A,B,W

A,B

W

CM

SHDN

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Output Logic High (SDO) V
Output Logic Low (SDO) V
Input Current I
Input Capacitance

6

IH

IL

IH

IL

IH

IL

IL

C

IL

POWER SUPPLIES

Logic Supply V
Power Single-Supply Range V
Power Dual-Supply Range V
Logic Supply Current I
Positive Supply Current I
Negative Supply Current I
Power Dissipation

7

LOGIC

DD RANGE

DD/SS RANGE

LOGIC

DD

SS

P

DISS

Power Supply Sensitivity PSS 0.002 0.01 %/%

DYNAMIC CHARACTERISTICS

6, 8, 9

Bandwidth –3 dB BW_20K RAB = 20 kΩ, Code = 80

BW_50K R
BW_200K R

Total Harmonic Distortion THD

Settling Time t

V

W

S

Crosstalk CT V

Analog Crosstalk CTA Measure V

Resistor Noise Voltage e

N_WB

= 5 V, VA = +VDD, VB = 0 V; –40C < TA < +85C, unless otherwise noted.)

LOGIC

TA = 25°C –30 +30 %

= VDD, Wiper = No Connect 30 ppm/°C

AB

IW = VDD /R, VDD = 3 V or 5 V 60 150 Ω

/⌬TCode = 80

Code = FF
Code = 00

H

H

H

–2 –1 0 LSB
0+1+2LSB

V

SS

5 ppm/°C

f = 5 MHz, measured to 25 pF
GND, Code = 80

H

f = 1 MHz, measured to 55 pF
GND, Code = 80
VA = VB = V

H

W

1nA

2.4 V

V

= 3 V, VSS = 0 2.1 V

LOGIC

V

= 3 V, VSS = 0 0.6 V

LOGIC

4.9 V

VIN = 0 V or 5 V ±1 µA

5pF

2.7 5.5 V

VSS = 0 V 5 15 V

±4.5 ±5.5 V

V

= 5 V 60 µA

LOGIC

VIH = 5 V or VIL = 0 V 0.1 1 µA

0.1 1 µA

VIH = 5 V or VIL = 0 V, VDD = +5 V, 0.2 0.3 mW
V

= –5 V

SS

= 50 kΩ, Code = 80

AB

= 200 kΩ, Code = 80

AB

W

VA = 1 V rms, RAB = 20 kΩ 0.014 %
V

= 0 V DC, f = 1 kHz

B

H

H

H

310 kHz
150 kHz
35 kHz

VA = 5 V, VB = 5 V, 5 µs
±1 LSB error band

= VDD, VB = 0 V, Measure 15 nV-s

A

VW1 with Adjacent RDAC
Making Full-Scale Code Change

with VW2 = 5 V p-p –62 dB

W1

@ f = 10 kHz
RWB = 20 kΩ, f = 1 kHz 18 nV/√Hz

1

Max Unit

V

5 µA

0.8 V

0.4 V

DD

V

REV. 0–2–

AD5280/AD5282

Parameter Symbol Conditions Min Typ

INTERFACE TIMING CHARACTERISTICS Applies to all parts
SCL Clock Frequency f

Bus Free Time between STOP and START t

t

BUF

Hold Time (Repeated START) t

t

HD:STA

SCL

1

2

6, 10

1.3 µs

After this period, the first 0.6 µs

1

Max Unit

400 kHz

clock pulse is generated

Low Period of SCL Clock t

t

LOW

High Period of SCL Clock t

t

HIGH

t

Setup Time for START Condition t

SU:STA

Data Hold Time t

t

HD:DAT

Data Setup Time t

t

SU:DAT

tF Fall Time of Both SDA and SCL Signals t

Rise Time of Both SDA and SCL Signals t

t

R

t

Setup Time for STOP Condition t

SU:STO

NOTES

1

Typicals represent average readings at 25°C, VDD = +5 V, VSS = –5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, Wiper (VW) = No connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

P

is calculated from (IDD ⫻ VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

8

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.

9

All dynamic characteristics use VDD = 5 V.

10

See timing diagram for location of measured values.

Specifications subject to change without notice.

3

4

5

6

7

8

9

10

1.3 µs

0.6 50 µs

0.6 µs

0.9 µs

100 ns

300 ns
300 ns

0.6 µs

REV. 0

–3–

AD5280/AD5282

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V

SS

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V

V

DD

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

A

AX – BX, AX – WX, BX – W

X

Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V

V

LOGIC

Output Voltage to GND . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Thermal Resistance

3

␪JA,

TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W

TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W

1

Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature

RU-14, RU-16 (Vapor Phase, 60 sec) . . . . . . . . . . . . 215°C

RU-14, RU-16 (Infrared, 15 sec) . . . . . . . . . . . . . . . . 220°C

DD

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating; functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

2

Maximum terminal current is bound by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.

3

Package Power Dissipation (TJ MAX – TA)/␪

JA

ORDERING GUIDE

Number of R

AB

Package Package Parts Per Branding

Model Channels (k) Temp Description Option Container Information*

AD5280BRU20 1 20 –40°C to +85°CTSSOP-14 RU-14 96 AD5280B20
AD5280BRU20-REEL7 1 20 –40°C to +85°CTSSOP-14 RU-14 1000 AD5280B20
AD5280BRU50 1 50 –40°C to +85°CTSSOP-14 RU-14 96 AD5280B50
AD5280BRU50-REEL7 1 50 –40°C to +85°CTSSOP-14 RU-14 1000 AD5280B50
AD5280BRU200 1 200 –40°C to +85°CTSSOP-14 RU-14 96 AD5280B200
AD5280BRU200-REEL7 1 200 –40°C to +85°CTSSOP-14 RU-14 1000 AD5280B200
AD5282BRU20 2 20 –40°C to +85°CTSSOP-16 RU-16 96 AD5282B20
AD5282BRU20-REEL7 2 20 –40°C to +85°CTSSOP-16 RU-16 1000 AD5282B20
AD5282BRU50 2 50 –40°C to +85°CTSSOP-16 RU-16 96 AD5282B50
AD5282BRU50-REEL7 2 50 –40°C to +85°CTSSOP-16 RU-16 1000 AD5282B50
AD5282BRU200 2 200 –40°C to +85°CTSSOP-16 RU-16 96 AD5282B200
AD5282BRU200-REEL7 2 200 –40°C to +85°CTSSOP-16 RU-16 1000 AD5282B200

The AD5280/AD5282 die size is 75 mm ⫻ 120 mm, 9,000 sq. mm. Contains 3077 transistors.
*Line 1 contains model number, Line 2 contains ADI logo followed by the end-to-end resistance value, and line 3 contains date code YYWW.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5280/AD5282 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0–4–

PIN CONFIGURATION

S

S

AD5280/AD5282

AD5280 PIN CONFIGURATION

A

V

HDN

SCL

SDA

DD

1

2

W

3

B

4

5

6

7

AD5280

TOP VIEW

(Not to Scale)

14

O

1

13

V

L

12

O

2

11

V

SS

10

GND

9

AD1

8

AD0

AD5280 PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1A Resistor Terminal A
2W Wiper Terminal W
3B Resistor Terminal B
4V

DD

Positive Power Supply. Specified for operation
from 5 V to 15 V (Sum of |V

| + |VSS| ≤ 15 V).

DD

5 SHDN Active Low, Asynchronous Connection of the

Wiper W to Terminal B and Open Circuit
of Terminal A. RDAC Register contents
unchanged. SHDN should tie to V

if not used.

L

6 SCL Serial Clock Input
7 SDA Serial Data Input/Output
8AD0 Programmable Address Bit 0 for Multiple

Package Decoding. Bits AD0 and AD1 provide
four possible addresses.

9AD1 Programmable Address Bit 1 for Multiple

Package Decoding. Bits AD0 and AD1 provide

four possible addresses.
10 GND Common Ground
11 V

12 O
13 V

SS

2

L

Negative Power Supply. Specified for operation

from 0 V to –5 V (Sum of |V

Logic Output Terminal O

| + |VSS| ≤ 15 V).

DD

2

Logic Supply Voltage. Needs to be the same

voltage as the digital logic controlling the

AD5280.
14 O

1

Logic Output Terminal O

1

AD5282 PIN CONFIGURATION

W

V

HDN

SCL

SDA

O

A

B

DD

1

1

2

1

3

1

4

1

5

(Not to Scale)

6

7

8

AD5282

TOP VIEW

16

A

2

15

W

2

14

B

2

V

13

L

V

12

SS

11

GND

10

AD1

9

AD0

AD5282 PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1O

1

2A

1

3W

1

4B

1

5V

DD

Logic Output Terminal O
Resistor Terminal A
Wiper Terminal W
Resistor Terminal B

1

1

1

1

Positive Power Supply. Specified for operation
from 5 V to 15 V (Sum of |V

| + |VSS|≤ 15 V).

DD

6 SHDN Active Low, Asynchronous Connection of the

Wiper W to Terminal B and Open Circuit of
Terminal A. RDAC Register contents
unchanged. SHDN should tie to V

if not used.

L

7 SCL Serial Clock Input
8 SDA Serial Data Input/Output
9 AD0 Programmable Address Bit 0 for Multiple

Package Decoding. Bits AD0 and AD1 provide
four possible addresses.

10 AD1 Programmable Address Bit 1 for Multiple

Package Decoding. Bits AD0 and AD1 provide

four possible addresses.
11 GND Common Ground
12 V

13 V

SS

L

Negative Power Supply. Specified for operation

from 0 V to –5 V (Sum of |V

| + |VSS| ≤ 15 V).

DD

Logic Supply Voltage. Needs to be the same

voltage as the digital logic controlling the

AD5282.
14 B
15 W
16 A

2

2

2

Resistor Terminal B

Wiper Terminal W

2

Resistor Terminal A

2

2

REV. 0

–5–

AD5280/AD5282

–Typical Performance Characteristics

1

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

RHEOSTAT MODE INL – LSB

–0.8

–1

0 32 160 256

+5V

ⴞ5V

64 96 128 192 224

CODE – Decimal

+15V

RAB = 20k⍀

= 25ⴗC

T

A

TPC 1. R-INL vs. Code vs.
Supply Voltages

0.5

0.4

0.3

0.2

TA = –40ⴗC

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL – LSB

–0.4

–0.5

0 32 160 256

TA = +125ⴗC

64 96 128 192 224

CODE – Decimal

RAB = 20k⍀

TA = +85ⴗC

TA = +25ⴗC

TPC 4. DNL vs. Code, VDD/VSS = ±5 V

0.5

0.4

0.3

0.2

ⴞ5V

0.1

0

–0.1

–0.2

–0.3

RHEOSTAT MODE DNL – LSB

–0.8

–0.5

0 32 160 256

+15V

64 96 128 192 224

CODE – Decimal

+5V

RAB = 20k⍀

= 25ⴗC

T

A

TPC 2. R-DNL vs. Code vs.
Supply Voltages

1

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTIOMETER MODE INL – LSB

–0.8

–1

0 32 160 256

ⴞ5V

64 96 128 192 224

CODE – Decimal

+5V

RAB = 20k⍀
TA = 25ⴗC

+15V

TPC 5. INL vs. Code vs. Supply
Voltages

1

0.8

0.6
TA = +85ⴗC

0.4

0.2

0

–0.2

TA = –40ⴗC

–0.4

–0.6

POTENTIOMETER MODE INL – LSB

–0.8

–1

0 32 160 256

TA = +125ⴗC

TA = +25ⴗC

64 96 128 192 224

CODE – Decimal

RAB = 20k⍀

TPC 3. INL vs. Code, VDD/VSS = ±5 V

0.5

0.4

0.3

0.2

ⴞ5V

0.1

0

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL – LSB

–0.4

–0.5

0 32 160 256

+5V

64 96 128 192 224

CODE – Decimal

RAB = 20k⍀

= 25ⴗC

T

A

+15V

TPC 6. DNL vs. Code vs.
Supply Voltages

1.0

Avg + 3␴

0.5

0

INL – LSB

–0.5

–1.0

0 20

Avg

Avg – 3␴

51015

|VDD – VSS| – V

RAB = 20k⍀

= 25ⴗC

T

A

TPC 7. INL Over Supply Voltage

2.0

1.5

1.0

0.5

0

RINL – LSB

–0.5

–1.0

–1.5

–2.0

0 20

Avg + 3␴

Avg

Avg – 3␴

51015

|VDD – VSS| – V

RAB = 20k⍀
T

= 25ⴗC

A

TPC 8. RINL Over Supply Voltage

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

FULL-SCALE ERROR – LSB

–1.8

–2.0

–40 100

VDD/VSS = 15V/0V

VDD/VSS = ⴞ5V

200–20

TEMPERATURE – ⴗC

RAB = 20k⍀

VDD/VSS = 5V/0V

40 60 80

TPC 9. Full-Scale Error

REV. 0–6–