ANALOG DEVICES AD5270, AD5271 Service Manual
1024-/256-Position, 1% Resistor Tolerance Error,
SPI Interface and 50-TP Memory Digital Rheostat
FEATURES
Single-channel, 1024-/256-position resolution
20 kΩ, 50 kΩ, 100 kΩ nominal resistance
Maximum ±1% nominal resistor tolerance error
50-times programmable (50-TP) wiper memory
Rheostat mode temperature coefficient: 5 ppm/°C
2.7 V to 5.5 V single-supply operation
±2.5 V to ±2.75 V dual-supply operation for ac or bipolar
operations
SPI-compatible interface
Wiper setting readback
Power on refreshed from 50-TP memory
Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package
Compact MSOP, 10-lead, 3 mm × 4.9 mm × 1.1 mm package
APPLICATIONS
Mechanical rheostat replacements
Op-amp: variable gain control
Instrumentation: gain, offset adjustment
Programmable voltage to current conversions
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration
SCLK
SYNC
DIN
SDO
AD5270/AD5271
FUNCTIONAL BLOCK DIAGRAM
V
DD
POWER-ON
RESET
SERIAL
INTERFACE
V
SS
AD5270/AD5271
RDAC
REGISTER
10/8
50-TP
MEMORY
BLOCK
EXT_CAP GND
Figure 1.
A
W
08077-001
GENERAL DESCRIPTION
The AD5270/AD52711 are single-channel, 1024-/256-position
digital rheostats that combine industry leading variable resistor
performance with nonvolatile memory (NVM) in a compact
package.
The AD5270/AD5271 ensure less than 1% end-to-end resistor
tolerance error and offer 50-times programmable (50-TP) memory.
The guaranteed industry leading low resistor tolerance error
feature simplifies open-loop applications as well as precision
calibration and tolerance matching applications.
1
Protected by U.S.Patent Number 7688240...;
The AD5270/AD5271 device wiper settings are controllable
through the SPI digital interface. Unlimited adjustments are
allowed before programming the resistance value into the
50-TP memory. The AD5270/AD5271 do not require any
external voltage supply to facilitate fuse blow and there are
50 opportunities for permanent programming. During 50-TP
activation, a permanent blow fuse command freezes the resistance
position (analogous to placing epoxy on a mechanical trimmer).
The AD5270/AD5271 are available in a 3 mm × 3 mm, 10-lead
LFCSP package and in a 10-lead MSOP package. The parts are
guaranteed to operate over the extended industrial temperature
range of −40°C to +125°C.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
AD5270/AD5271
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—AD5270 .......................................... 3
Electrical Characteristics—AD5271 .......................................... 5
Interface Timing Specifications.................................................. 7
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Test Circuits..................................................................................... 17
Theory of Operation ...................................................................... 18
Serial Data Interface................................................................... 18
Shift Register............................................................................... 18
RDAC Register............................................................................ 18
50-TP Memory Block ................................................................ 18
Write Protection ......................................................................... 18
RDAC and 50-TP Read Operation .......................................... 19
Shut-Down Mode....................................................................... 20
Resistor Performance Mode...................................................... 20
Reset ............................................................................................. 20
SDO Pin and Daisy-Chain Operation..................................... 21
RDAC Architecture.................................................................... 21
Programming the Variable Resistor......................................... 22
EXT_CAP Capacitor.................................................................. 22
Terminal Voltage Operating Range ......................................... 22
Power-Up Sequence ................................................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
12/10—Rev. D to Rev. E
Changes to SDO Pin Description................................................. 10
Changes to SDO Pin and Daisy-Chain Operation Section....... 21
11/10—Rev. C to Rev. D
Changes to Figure 25...................................................................... 14
9/10—Rev. B to Rev. C
Changes to Figure 3 Caption........................................................... 7
Changes to Figure 4 Caption........................................................... 8
Deleted Daisy-Chain Operation Section, Added SDO Pin and
Daisy-Chain Operation Section ................................................... 21
5/10—Rev. A to Rev. B
Added LFCSP Throughout.............................................................. 1
Changed OTP to 50-TP Throughout............................................. 1
Changes to Product Title, Features, and General Description... 1
Changes to Table 1.............................................................................3
Added Table 3; Renumbered Sequentially .....................................4
Changes to Table 4.............................................................................5
Added Table 6 ....................................................................................6
Changes to Table 8 and Table 9 .......................................................9
Added Figure 6 and changes to Table 10 ..................................... 10
Replaced Typical Performance Characteristics Section ............ 11
Changes to Figure 44...................................................................... 21
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide.......................................................... 24
3/10—Rev. 0 to Rev. A
Changes to Product Title and General Description.....................1
Changes to Theory of Operation Section...................................14
10/09—Revision 0: Initial Version
Rev. E | Page 2 of 24
AD5270/AD5271
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5270
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution 10 Bits
Resistor Integral Nonlinearity
R
R
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
R-Perf Mode4
Normal Mode ±15 %
Resistance Temperature Coefficient
Wiper Resistance Code = zero scale 35 70 Ω
RESISTOR TERMINALS
Terminal Voltage Range
Capacitance5 A
Capacitance5 W
Common-Mode Leakage Current5
DIGITAL INPUTS
Input Logic5
High V
Low V
Input Current IIN ±1 μA
Input Capacitance5
DIGITAL OUTPUT
Output Voltage5
High VOH R
Low VOL R
V
V
Tristate Leakage Current −1 +1 μA
Output Capacitance5
POWER SUPPLIES
Single-Supply Power Range VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range ±2.5 ±2.75 V
Supply Current
Positive IDD 1 μA
Negative ISS −1 μA
50-TP Store Current
Positive I
Negative I
OTP Read Current
5, 9
Positive I
Negative I
5, 8
2, 3
R-INL RAW = 20 kΩ, |VDD − VSS| = 3.0 V to 5.5 V −1 +1 LSB
= 20 kΩ, |VDD − VSS| = 2.7 V to 3.0 V −1 +1.5 LSB
AW
= 50 kΩ, 100 kΩ −1 +1 LSB
AW
−1 +1 LSB
−1 ±0.5 +1 %
V
SS
V
DD
90 pF
5, 7
R-DNL
5, 6
Code = full scale 5 ppm/°C
V
See
Table 2 and Table 3
f = 1 MHz, measured to GND, code =
half scale
f = 1 MHz, measured to GND, code =
40 pF
half scale
V
= VW 50 nA
A
2.0 V
INH
0.8 V
INL
5 pF
C
IN
= 2.2 kΩ to VDD V
PULL_UP
= 2.2 kΩ to VDD
PULL_UP
= 2.7 V to 5.5 V, VSS = 0 V 0.4 V
DD
= 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V 0.6 V
DD
− 0.1 V
DD
5 pF
DD_OTP_STORE
SS_OTP_STORE
4 mA
−4 mA
DD_OTP_READ
SS_OTP_READ
500 μA
−500 μA
Rev. E | Page 3 of 24
AD5270/AD5271
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
Power Dissipation10 V
Power Supply Rejection Ratio5
PSRR ΔV
R
R
R
DYNAMIC CHARACTERISTICS
5, 11
Bandwidth −3 dB, RAW = 10 kΩ, Terminal W,
R
R
R
Total Harmonic Distortion VA = 1 V rms, f = 1 kHz,
R
R
R
Resistor Noise Density Code = half scale, TA = 25°C nV/√Hz
R
R
R
1
Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3
The maximum current in each code is defined by IAW = (VDD − 1)/RAW.
4
The terms resistor performance mode and R-Perf mode are used interchangeably. See the Resistor Performance Mode section.
5
Guaranteed by design and not subject to production test.
6
See Figure 25 for more details.
7
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar
signal adjustment.
8
Different from operating current, the supply current for the fuse program lasts approximately 55 ms.
9
Different from operating current, the supply current for the fuse read lasts approximately 500 ns.
10
P
is calculated from (IDD × VDD) + (ISS × VSS).
DISS
11
All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.
= VDD or VIL = GND 5.5 μW
IH
/ΔVSS = ±5 V ± 10% dB
DD
= 20 kΩ −66 −55
AW
= 50 kΩ −75 −67
AW
= 100 kΩ −78 −70
AW
kHz
see
Figure 42
= 20 kΩ 300
AW
= 50 kΩ 120
AW
= 100 kΩ 60
AW
dB
code = half scale
= 20 kΩ −90
AW
= 50 kΩ −88
AW
= 100 kΩ −85
AW
= 20 kΩ 50
AW
= 50 kΩ 25
AW
= 100 kΩ 32
AW
Table 2. AD5270—20 kΩ Resistor Performance Mode Code Range
Resistor Tolerance Per Code |VDD − VSS| = 4.5 V to 5.5 V |VDD − VSS| = 2.7 V to 4.5 V
R-TOLERANCE
1% R-Tolerance From 0x078 to 0x3FF From 0x0BE to 0x3FF
2% R-Tolerance From 0x037 to 0x3FF From 0x055 to 0x3FF
3% R-Tolerance From 0x028 to 0x3FF From 0x037 to 0x3FF
Table 3. AD5270—50 kΩ and 100 kΩ Resistor Performance Mode Code Range
Resistor Tolerance Per Code RAW = 50 kΩ RAW = 100 kΩ
R-TOLERANCE
1% R-Tolerance From 0x078 to 0x3FF From 0x04B to 0x3FF
2% R-Tolerance From 0x055 to 0x3FF From 0x032 to 0x3FF
3% R-Tolerance From 0x032 to 0x3FF From 0x019 to 0x3FF
Rev. E | Page 4 of 24
AD5270/AD5271
ELECTRICAL CHARACTERISTICS—AD5271
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution 8 Bits
Resistor Integral Nonlinearity
Resistor Differential Nonlinearity2 R-DNL
Nominal Resistor Tolerance
R-Perf Mode4 See Table 5 and Table 6 −1 ±0.5 +1 %
Normal Mode ±15 %
Resistance Temperature Coefficient
Wiper Resistance Code = zero scale 35 70 Ω
RESISTOR TERMINALS
Terminal Voltage Range
Capacitance5 A
Capacitance5 W
Common-Mode Leakage Current5 V
DIGITAL INPUTS
Input Logic5
High V
Low5 V
Input Current IIN ±1 μA
Input Capacitance5 C
DIGITAL OUTPUT
Output Voltage5
High VOH R
Low VOL R
V
V
Tristate Leakage Current −1 +1 μA
Output Capacitance5 5 pF
POWER SUPPLIES
Single-Supply Power Range VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range ±2.5 ±2.75 V
Supply Current
Positive IDD 1 μA
Negative ISS −1 μA
50-TP Store Current
Positive I
Negative I
OTP Read Current
5, 9
Positive I
Negative I
Power Dissipation10 V
Power Supply Rejection Ratio5 PSRR ΔVDD/ΔVSS = ±5 V ± 10% dB
R
R
R
2, 3
R-INL −1 +1 LSB
5, 6
Code = full scale 5 ppm/°C
5, 7
V
f = 1 MHz, measured to GND, code =
−1 +1 LSB
V
SS
V
DD
90 pF
half scale
f = 1 MHz, measured to GND, code =
40 pF
half scale
= VW 50 nA
A
2.0 V
INH
0.8 V
INL
5 pF
IN
= 2.2 kΩ to VDD V
PULL_UP
= 2.2 kΩ to VDD
PULL_UP
= 2.7 V to 5.5 V, VSS = 0 V 0.4 V
DD
= 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V 0.6 V
DD
5, 8
DD_OTP_STORE
SS_OTP_STORE
4 mA
−4 mA
− 0.1 V
DD
DD_OTP_READ
SS_OTP_READ
500 μA
−500 μA
= VDD or VIL = GND 5.5 μW
IH
= 20 kΩ −66 −55
AW
= 50 kΩ −75 −67
AW
= 100 kΩ −78 −70
AW
Rev. E | Page 5 of 24
AD5270/AD5271
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB, RAW = 10 kΩ, Terminal W, see Figure 42 kHz
R
R
R
Total Harmonic Distortion VA = 1 V rms, f = 1 kHz, code = half scale dB
R
R
R
Resistor Noise Density Code = half scale, TA = 25°C nV/√Hz
R
R
R
1
Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3
The maximum current in each code is defined by IAW = (VDD − 1)/RAW.
4
The terms resistor performance mode and R-Perf mode are used interchangeably. See the Resistor Performance Mode section.
5
Guaranteed by design and not subject to production test.
6
See Figure 25 for more details.
7
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar
signal adjustment.
8
Different from operating current, the supply current for the fuse program lasts approximately 55 ms.
9
Different from operating current, the supply current for the fuse read lasts approximately 500 ns.
10
P
is calculated from (IDD × VDD) + (ISS × VSS).
DISS
11
All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.
5, 11
= 20 kΩ 300
AW
= 50 kΩ 120
AW
= 100 kΩ 60
AW
= 20 kΩ −90
AW
= 50 kΩ −88
AW
= 100 kΩ −85
AW
= 20 kΩ 50
AW
= 50 kΩ 25
AW
= 100 kΩ 32
AW
Table 5. AD5271—20 kΩ Resistor Performance Mode Code Range
Resistor Tolerance per Code |VDD − VSS| = 4.5 V to 5.5 V |VDD − VSS| = 2.7 V to 4.5 V
R-TOLERANCE
1% R-Tolerance From 0x1E to 0xFF From 0x32 to 0xFF
2% R-Tolerance From 0x0F to 0xFF From 0x19 to 0xFF
3% R-Tolerance From 0x06 to 0xFF From 0x0E to 0xFF
Table 6. AD5271—50 kΩ and 100 kΩ Resistor Performance Mode Code Range
Resistor Tolerance per Code RAW = 50 kΩ RAW = 100 kΩ
R-TOLERANCE
1% R-Tolerance From 0x1E to 0xFF From 0x14 to 0xFF
2% R-Tolerance From 0x14 to 0xFF From 0x0F to 0xFF
3% R-Tolerance From 0x0A to 0xFF From 0x0A to 0xFF
Rev. E | Page 6 of 24
AD5270/AD5271
INTERFACE TIMING SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V; all specifications T
Table 7.
Parameter Limit1 Unit Test Conditions/Comments
2
t
20 ns min SCLK cycle time
1
t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 15 ns min
to SCLK falling edge setup time
SYNC
t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 1 ns min
3, 4
t
500 ns min
8
t9 15 ns min
5
t
450 ns max SCLK rising edge to SDO valid
10
t
RDAC_R-PERF
t
RDAC_NORMAL
t
MEMORY_READ
t
MEMORY_PROGRAM
t
RESET
t
POWER-UP
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 50 MHz.
3
Refer to t
4
Refer to t
5
R
6
Maximum time after VDD − VSS is equal to 2.5 V.
2 μs max RDAC register write command execute time
600 ns max RDAC register write command execute time
6 μs max Memory readback execute time
350 ms max Memory program time
0.6 ms max Reset 50-TP restore time
6
2 ms max Power-on 50-TP restore time
and t
RDAC_R-PER
MEMORY_READ
= 2.2 kΩ to VDD with a capacitance load of 168 pF.
PULL_UP
RDAC_NORMAL
and
for RDAC register write operations.
t
MEMORY_PROGRAM
for memory commands operations.
SCLK falling edge to SYNC
Minimum SYNC
rising edge to next SCLK fall ignored
SYNC
high time
Shift Register and Timing Diagrams
DB9 (MSB) DB0 (LSB)
to T
MIN
MAX
rising edge
, unless otherwise noted.
SCLK
SYNC
DIN
SDO
C0C1
C3
00
C2
CONTROL BI TS
D9
D7 D6 D5 D4 D3
D8
DATA BITS
Figure 2. Shift Register Content
t
4
t
8
t
2
t
3
0 0 C3 C2 D7 D6 D5 D2 D1 D0
t
1
Figure 3. Write Timing Diagram (CPOL = 0, CPHA = 1)
Rev. E | Page 7 of 24
t
5
D2 D1
t
6
D0
08077-002
t
7
t
9
08077-003
AD5270/AD5271
SCLK
SYNC
t
9
DIN
SDO
00 00C3 C3
X X C3 D1 D0
Figure 4. Read Timing Diagram (CPOL = 0, CPHA = 1)
D1 D0D0 D0
t
10
08077-004
Rev. E | Page 8 of 24
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