Xilinx Virtex-5 FPGA ML561 User Manual

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Virtex-5 FPGA ML561

Memory Interfaces

Development Board

User Guide

UG199 (v1.2.1) June 15, 2009

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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

© 2007–2009 Xilinx, Inc. All rights reserved.

XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI EXPRESS is a registered trademark of PCI-SIG. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

 

 

 

02/12/07

1.0

Initial Xilinx release.

 

 

 

08/09/07

1.1

Revised Read and Write Strobe in Table 5-4, page 49. Added Chapter 7, “ML561

 

 

Hardware-Simulation Correlation.”

 

 

 

04/19/08

1.2

Revised Figure 3-11, page 37 and Table 3-19, page 38. Corrected FPGA driver for Read

 

 

Data and Read Strobe in Table 5-4, page 49. Updated Data and Strobe entries in Table 5-5,

 

 

page 49. Updated manufacturers and links in Appendix B, “Bill of Materials.”

 

 

 

06/15/09

1.2.1

Clarified VIH(max) voltage in “Terminology.”

 

 

 

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Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 1: Introduction

About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit . . . . . . . . . . . . . . . . 11 Virtex-5 FPGA ML561 Memory Interfaces Development Board. . . . . . . . . . . . . . . 12

Chapter 2: Getting Started

Documentation and Reference Design CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Initial Board Check Before Applying Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Applying Power to the Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 3: Hardware Description

Hardware Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DDR400 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DDR2 DIMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DDR2 SDRAM Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

QDRII SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

RLDRAM II Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Memory Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DDR400 and DDR2 Component Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DDR2 SDRAM DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

QDRII and RLDRAM II Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

RS-232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

200 MHz LVPECL Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SMA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

33 MHz Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

33 MHz System ACE Controller Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

GTP Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

User I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

General-Purpose Headers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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Seven-Segment Displays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Light Emitting Diodes (LEDs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power On or Off Slide Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Soft Touch Probe Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power Measurement Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Liquid Crystal Display Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Board Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Chapter 4: Electrical Requirements

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

FPGA Internal Power Budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Chapter 5: Signal Integrity Recommendations

Termination and Transmission Line Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Chapter 6: Configuration

Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

JTAG Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Parallel IV Cable Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

System ACE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Chapter 7: ML561 Hardware-Simulation Correlation

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Signal Integrity Correlation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DDR2 Component Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DDR2 Component Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 DDR2 DIMM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DDR2 DIMM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 QDRII Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 QDRII Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Summary and Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

How to Generate a User-Specific FPGA IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . 93

Appendix A: FPGA Pinouts

FPGA #1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

FPGA #2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

FPGA #3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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Appendix B: Bill of Materials

Appendix C: LCD Interface

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Display Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Hardware Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Peripheral Device KS0713 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Controller – Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Controller – LCD Panel Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Controller – Power Supply Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Operation Example of the 64128EFCBC-3LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Read/Write Characteristics (6800 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 LCD Panel Used in Full Graphics Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 LCD Panel Used in Character Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Array Connector Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

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Preface

About This Guide

This user guide describes the Virtex®-5 FPGA ML561 Memory Interfaces Development Board. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/virtex5.

Guide Contents

This manual contains the following chapters:

Chapter 1, “Introduction”

Chapter 2, “Getting Started”

Chapter 3, “Hardware Description”

Chapter 4, “Electrical Requirements”

Chapter 5, “Signal Integrity Recommendations”

Chapter 6, “Configuration”

Chapter 7, “ML561 Hardware-Simulation Correlation”

Appendix A, “FPGA Pinouts”

Appendix B, “Bill of Materials”

Appendix C, “LCD Interface”

Additional Documentation

The following documents are also available for download at

http://www.xilinx.com/virtex5.

Virtex-5 Family Overview

The features and product selection of the Virtex-5 family are outlined in this overview.

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and Switching Characteristic specifications for the Virtex-5 family.

Virtex-5 FPGA User Guide

Chapters in this guide cover the following topics:

-Clocking Resources

-Clock Management Technology (CMT)

-Phase-Locked Loops (PLLs)

-Block RAM

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-Configurable Logic Blocks (CLBs)

-SelectIO™ Resources

-SelectIO Logic Resources

-Advanced SelectIO Logic Resources

Virtex-5 FPGA RocketIO GTP Transceiver User Guide

This guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXT and SXT platforms.

Virtex-5 FPGA RocketIO GTX Transceiver User Guide

This guide describes the RocketIO GTX transceivers available in the Virtex-5 FXT platform.

Virtex-5 FPGA Embedded Processor Block for PowerPC® 440 Designs

This reference guide is a description of the embedded processor block available in the Virtex-5 FXT platform.

Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide

This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in the Virtex-5 LXT, SXT, and FXT platforms.

Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs

This guide describes the integrated Endpoint blocks in the Virtex-5 LXT, SXT, and FXT platforms used for PCI Express® designs.

Virtex-5 FPGA XtremeDSP Design Considerations User Guide

This guide describes the XtremeDSP™ slice and includes reference designs for using the DSP48E.

Virtex-5 FPGA Configuration Guide

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and JTAG interfaces.

Virtex-5 FPGA System Monitor User Guide

The System Monitor functionality available in all the Virtex-5 devices is outlined in this guide.

Virtex-5 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

Virtex-5 FPGA PCB Designer’s Guide

This guide provides information on PCB design for Virtex-5 devices, with a focus on strategies for making design decisions at the PCB and interface level.

Additional Support Resources

To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support.

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Conventions

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

This document uses the following typographical conventions. An example illustrates each convention.

Convention

Meaning or Use

Example

 

 

 

 

References to other documents

See the Virtex-5 Configuration Guide

 

for more information.

Italic font

 

 

 

Emphasis in text

The address (F) is asserted after

 

 

clock event 2.

 

 

 

 

 

Underlined Text

Indicates a link to a web page.

http://www.xilinx.com/virtex5

 

 

 

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

 

 

See the section “Additional

 

Cross-reference link to a location

Documentation” for details.

Blue text

Refer to “Clock Management

in the current document

 

Technology (CMT)” in

 

 

 

 

Chapter 2 for details.

 

 

 

Red text

Cross-reference link to a location

See Figure 5 in the Virtex-5 FPGA

in another document

Data Sheet

 

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to http://www.xilinx.com

for the latest documentation.

 

 

 

 

 

Terminology

This section defines terms used in Chapter 7, “ML561 Hardware-Simulation Correlation,” of this document.

DVW is the data valid window opening measured by the VIH and VIL masks. The Data Valid Window (DVW) smaller of the two values are listed as absolute time as well as in terms of the percentage

of UI (Unit Interval), or bit time.

The ultimate goal of a design is to ascertain quality of signal at the receiver I/O Buffer (IOB). This measurement can only be simulated. When the hardware measurements are correlated with the simulation at the probe point, the extra probe capacitance is removed from the IBIS schematics, and the simulation is repeated at two extreme

Extrapolation corners (slow-weak and fast-strong). Removal of probe capacitance is important to represent the actual hardware. If the SI characteristics of these simulations are proved to be within the acceptable range with sufficient margin, then the performance requirements for data signal interface of the corresponding memory operation at the target clock frequency are proved to have been met.

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Hardware Measurements

Inter-Symbol Interference (ISI)

Noise Margin

Overshoot / Undershoot

Margin

Simulation Correlation

VIH(ac)-min

VIH(dc)-min

VIL(ac)-max

VIL(dc)-max

These measurements are the actual real-time measurements of an eye diagram and a segment of the test pattern (PRBS6) waveform captured on ML561 hardware at the designated probe point using an Agilent scope.

As the frequency of operation increases, the signal delay is affected by the data pattern that precedes the current data bit. This is called the inter-symbol interference (ISI) effect. All testing is performed with a pseudo-random bitstream (PRBS) of order 6, that is, PRBS6. ISI is the jitter represented by the eye at all four voltage thresholds. The worst of the following two sum values are listed in this table:

Sum of ISI at VIH(ac)-min and VIH(dc)-min

Sum of ISI at VIL(ac)-max and VIL(dc)-max

This is the noise margin available at the receiver. Measurements are taken at the AC voltage levels as the minimum vertical opening of the eye in the vicinity of the center of the bit period. Ideally, the input voltage needs to remain above the DC voltage specifications. However, by considering the AC voltage specifications for the nominal voltage level for VREF, these measurements are more conservative values that also include the effects of VREF variations.

VIH margin: Difference between the top of the eye opening and VIH(ac)-min

VIL margin: Difference between VIL(ac)-max and the bottom of the eye opening

These measurements are performed in stand-alone fashion for the signal under test. Thus no consideration of crosstalk or Simultaneously Switching Output (SSO) effects are accounted for.

Overshoot margin is the difference between the maximum allowable VIH per JEDEC specification and the maximum amplitude of the measured eye. Similarly, undershoot margin is the difference between the minimum amplitude of the measured eye and the minimum allowable VIL value per JEDEC specification. For both SSTL18 and 1.8V HSTL specifications:

VIH(max) < (VDDQ + 300 mV) = (1.8 + 0.3)V = 2.1V

VIL(min) > -300 mV = 0.3V

Note: VIH(max) must not exceed 1.9V for all Micron Parts.

The BoardSim utility of the HyperLynx simulator is used to extract the IBIS schematics of the same signal net for which hardware measurements are made. To replicate the hardware measurement probe set up at the probe point, a 0.5 pF probe capacitance is added based on Agilent probe loading specifications to the extracted IBIS schematics of the memory signal. For the FPGA devices soldered on the ML561 board under test, the process corner (slow, typical, or fast) is not known. Thus simulation is performed for all three corners (slow-weak, typical, and fast-strong), and the results of the case that best fits with hardware measurement is selected for tabulation.

This term is the minimum input level at which the receiver must recognize input logic High.

When the input signal reaches VIH(ac)-min, the receiver continues to interpret the input as a logic High as long as the signal remains above this voltage. (This parameter is basically the hysteresis for a logic ‘1’.)

This term is the maximum input level at which the receiver must recognize input logic Low.

When the input signal reaches VIL(ac)-max, the receiver continues to interpret the input as a logic Low as long as the signal remains below this voltage. (This parameter is basically the hysteresis for logic ‘0’.)

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Chapter 1

Introduction

This chapter introduces the Virtex®-5 FPGA ML561 reference design. It contains the following sections:

“About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit”

“Virtex-5 FPGA ML561 Memory Interfaces Development Board”

About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit

The Virtex-5 FPGA ML561 Memory Interfaces Tool Kit provides a complete development platform to interface with external memory devices for designing and verifying applications based on the Virtex-5 LXT FPGA platform. This kit allows designers to implement high-speed applications with extreme flexibility using IP cores and customized modules. The Virtex-5 LXT FPGA, with its column-based architecture, makes it possible to develop highly flexible memory interface applications.

The Virtex-5 FPGA ML561 Memory Interfaces Tool Kit includes the following:

Virtex-5 FPGA ML561 Memory Interfaces Development Board (XC5VLX50T-FFG1136 FPGA)

5V/6.5 A DC power supply

Country-specific power supply line cord

RS-232 serial cable, DB9-F to DB9-F

Documentation and reference design CD-ROM

Optional items that also support development efforts include:

Xilinx® ISE® software

JTAG cable

Xilinx Parallel IV cable

For assistance with any of these items, contact your local Xilinx distributor or visit the Xilinx online store at www.xilinx.com.

The heart of the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit is the Virtex-5 FPGA ML561 Development Board. This manual provides comprehensive information on Rev A3 and later revisions of this board.

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Virtex-5 FPGA ML561 Memory Interfaces Development Board

A high-level functional block diagram of the Virtex-5 FPGA ML561 Memory Interfaces Development Board is shown in Figure 1-1.

External Interfaces:

System ACE Controller,

USB, RS-232, LCD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSTL18/SSTL2

 

 

 

 

 

 

 

 

 

 

 

 

SSTL18

 

 

 

 

 

 

 

 

 

 

 

 

HSTL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA #1

 

 

 

 

 

 

 

 

 

 

 

 

FPGA #2

 

 

 

 

 

 

 

 

 

 

 

FPGA #3

 

 

 

 

XC5VLX50T/

 

 

 

 

 

 

 

 

 

 

XC5VLX50T/

 

 

 

 

 

 

 

 

 

 

XC5VLX50T/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FFG1136

 

 

 

 

 

 

 

 

 

 

 

 

FFG1136

 

 

 

 

 

 

 

 

 

 

FFG1136

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

72

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

32

 

 

 

 

 

 

 

72

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

72

 

72

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR2 SDRAM

 

DDR400 SDRAM

 

 

 

 

 

DDR2 DIMM

 

 

 

DDR2 DIMM

 

 

DDR2 DIMM

 

DDR2 DIMM

 

DDR2 DIMM

 

 

 

 

 

RLDRAM II

(CIO)

 

 

 

QDRII SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WIDE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEEP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG191_c1_01_020807

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1-1: Virtex-5 FPGA ML561 Development Board Block Diagram

The Virtex-5 FPGA ML561 Development Board includes the following major functional blocks:

Three XC5VLX50T-FFG1136 FPGAs (see DS100, Virtex-5 Family Overview)

DDR400 components: 128 MB (32M x 32 bits) at 200 MHz clock speed. See XAPP851,

DDR SDRAM Controller Using Virtex-5 FPGA Devices.

DDR2 DIMM: Five PC2-5300 DIMM sockets for up to 2 GB (128M x 144 bits). See XAPP858, High-Performance DDR2 SDRAM Interface in Virtex-5 Devices.

DDR2-667 components: 64 MB (16M x 32 bits) at 333 MHz clock speed

QDRII memory: 16 MB (2M x 72 bits) at up to 300 MHz clock speed. See XAPP853,

QDR II SRAM Interface for Virtex-5 Devices.

RLDRAM II memory: 64 MB (16M x 36 bits) at up to 300 MHz clock speed. See XAPP852, RLDRAM II Memory Interface for Virtex-5 FPGAs.

One DB9-M RS-232 port and one USB 2.0 port

A System ACE™ CompactFlash (CF) Configuration Controller that allows storing and downloading of up to eight FPGA configuration image files

On-board power regulators with ±5% output margin test capabilities

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Virtex-5 FPGA ML561 Memory Interfaces Development Board

Figure 1-2 shows the Virtex-5 FPGA ML561 Development Board and indicates the locations of the resident memory devices.

32-bit DDR400

SDRAM

144 bits wide

DDR2 SDRAM

DIMM

32-bit DDR2 SDRAM

72 bits wide, up to 4 deep

72-bit QDRII SRAM

36-bit RLDRAM II

UG199_c1_02_050106

Figure 1-2: Virtex-5 FPGA ML561 Development Board

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Chapter 1: Introduction

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Chapter 2

Getting Started

This chapter describes the items needed to configure the Virtex-5 FPGA ML561 Memory Interfaces Development Board. The Virtex-5 FPGA ML561 Development Board is tested at the factory after assembly and should be received in working condition. It is set up to load a bitstream from the CompactFlash card at socket J27 through the System ACE controller (U45).

This chapter contains the following sections:

“Documentation and Reference Design CD”

“Initial Board Check Before Applying Power”

“Applying Power to the Board”

Documentation and Reference Design CD

The CD included in the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit contains the design files for the Virtex-5 FPGA ML561 Development Board, including schematics, board layout, and reference design files. Open the ReadMe.rtf file on the CD to review the list of contents.

Initial Board Check Before Applying Power

Perform these steps before applying board power:

1.Set up the Configuration Mode jumpers (P27, P46, and P112) for JTAG configuration.

See “Configuration Modes” on page 51 for all available modes for the Virtex-5 FPGA ML561 Development Board.

2.Confirm that the JTAG chain jumpers P38, P44, and P109 are connecting pins 1 to 2 and pins 3 to 4. This way, all three devices are in the chain. Otherwise, the ISE iMPACT software will not find all three devices to configure. For more information see “JTAG Chain” on page 52.

3.Make sure that no inhibit jumpers are present on any of the power supply regulator modules. For more information, see “Voltage Regulators” on page 34.

4.The Virtex-5 FPGA ML561 Development Board has a 200 MHz on-board oscillator, which provides a copy of a differential LVPECL clock to each of the three FPGAs through a differential clock buffer (ICS853006). There is also a connection to a pair of SMA connectors (J19, J20) to provide a differential LVDS clock from an off-board signal generator. Another differential clock buffer (ICS853006) provides a copy of this clock to each of the three FPGAs. These clocks are available after configuration for the design to use for various system clocks.

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Chapter 2: Getting Started

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5.Insert the CompactFlash card included in the kit into socket J27 on the Virtex-5 FPGA ML561 Development Board. To select the startup file, check that SW8 is set to position 0.

Applying Power to the Board

The Virtex-5 FPGA ML561 Development Board is now ready to power on. The Virtex-5 FPGA ML561 Development Board is shipped with a country-specific AC line cord for the universal input 5V desktop power supply. Follow these steps to power up the Virtex-5 FPGA ML561 Development Board:

1.Confirm that the ON-OFF switch, SW5, is in the OFF position.

2.Plug the 5V desktop power supply into the 5V DC input barrel jack J28 on the Virtex-5 FPGA ML561 Development Board. Plug the desktop power supply AC line cord into an electrical outlet supplying the appropriate voltage.

3.Turn SW5 to the ON position. The power indicators for all regulator modules should come on, indicating output from the regulators. The System ACE status LED D37 comes on when the System ACE controller (U45) extracts the BIT configuration file from the CompactFlash card to the FPGA. If no CompactFlash card is installed in the card socket J27 on the Virtex-5 FPGA ML561 Development Board, the red System ACE error LED D38 flashes.

4.If a CompactFlash card is not installed in socket J27, a JTAG cable must be used to configure the FPGAs. To use a Parallel IV cable or other JTAG pod, download the FPGA configuration bitstream into each FPGA. After the DONE LED (D28) comes on, the FPGAs are configured and ready to use.

5.Push the reset button SW4.

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Chapter 3

Hardware Description

This chapter describes the major hardware blocks on the Virtex-5 FPGA ML561 Development Board and provides useful design consideration. It contains the following sections:

“Hardware Overview”

“Memory Details”

“External Interfaces”

“Power Regulation”

“Board Design Considerations”

Hardware Overview

The ML561 Development/Evaluation system reference design is implemented with three XC5VLX50T-FFG1136 devices from the Virtex-5 FPGA family to demonstrate high-speed external memory application interfaces. The memory technologies supported by the Virtex-5 FPGA ML561 Development Board are DDR2 SDRAM, DDR400 SDRAM, QDRII SRAM, and RLDRAM II SDRAM.

Figure 3-1 provides a view of all the major components on ML561 board. It shows the placement of the three Virtex-5 FPGAs, and the position of the associated major interfaces for each FPGA.

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Chapter 3: Hardware Description

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SSTL18

 

 

 

 

 

 

 

SSTL2 M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MGT Connections

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA #1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPY

 

SSTL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LEDs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VTT & VREF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIMM5

 

 

DIMM4

 

DIMM3

 

DIMM2

 

DIMM1

 

 

 

 

FPGA #2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA #1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA #1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LEDs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test Header 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA #2

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LEDs

 

 

Test Header 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MGT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR2

 

 

 

DDR2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TL18SS M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AVC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VTT & VREF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Config1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SSTL18

 

 

 

 

 

 

 

CPLL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Config2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VVTTR

 

 

 

AVTTX

 

AVTRX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12V Banana

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clocks &

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FBD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

SEG2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jacks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

 

 

 

 

ON

 

 

 

 

 

 

 

 

 

 

External

 

 

 

Buffers

 

 

 

 

 

 

 

DIP2

 

 

 

VCCINT

 

 

 

 

 

 

SSTL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RS-232

 

 

 

OFF

 

 

 

 

 

 

 

 

 

HSTL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7SEG1

Driver

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12V Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RLDRAM II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QDRII

 

 

 

VCCAUX /

 

 

Serial Header

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jack

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA #3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCO

 

 

 

 

 

 

 

 

 

RESET

 

 

5V Banana

 

 

 

 

 

 

 

 

 

12V -> 5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QDRII

 

 

 

 

HSTL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RLDRAM II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jacks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VTT & VREF

 

 

 

System ACE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test Header 3

 

 

 

 

 

ON

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Test Header

 

 

 

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA #3 LEDs

 

 

 

 

 

Config3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5V Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jack

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HSTL

 

 

 

7SEG3 DIP3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pwr Measure Header

 

 

 

LCD Connector

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PROG

 

 

 

 

JTAG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG199_c3_01_050106

Figure 3-1: ML561 XC5VLX50T-FFG1136 Board Placement Diagram

FPGA

The ML561 uses three Virtex-5 XC5VLX50T-FFG1136 devices, each in a 1136-pin,

35 mm x 35 mm BGA package. Figure 1-1, page 12 shows the memory devices associated with the three FPGAs. Refer to Appendix A, “FPGA Pinouts,” for a complete pinout of all Virtex-5 devices on the board. Refer to Appendix B, “Bill of Materials,” for a list of major components on the Virtex-5 FPGA ML561 Development Board, including their reference designators and links to their corresponding data sheets.

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Virtex-5 FPGA ML561 User Guide

 

 

UG199 (v1.2.1) June 15, 2009

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Hardware Overview

Memories

Table 3-1 lists the types of memories that the ML561 board supports.

Table 3-1: Summary of ML561 Memory Interfaces

Memory Type

Maximum Speed

Data Rate

Data Width

I/O Standard

Data/Strobe

Ratios

 

 

 

 

 

 

 

 

 

 

 

DDR400 SDRAM

200 MHz

400 Mbps

32

SSTL2

8:1

 

 

 

 

 

 

DDR2 DIMM

333 MHz

667 Mbps

144

SSTL18

8:1

 

 

 

 

 

 

DDR2 SDRAM

333 MHz

667 Mbps

32

SSTL18

8:1

 

 

 

 

 

 

QDRII SRAM

300 MHz

1.2 Gbps

72

HSTL18

18:1, 36:1

 

 

 

 

 

 

RLDRAM II

300 MHz

600 Mbps

36

HSTL18

9:1, 18:1

 

 

 

 

 

 

When a larger data/strobe ratio is implemented, for example, a x36 QDRII device, the smaller configurations can also be demonstrated by programming the FPGA for a smaller data width, such as a 9:1 data/strobe ratio for the QDRII device.

DDR400 SDRAM Components

The Virtex-5 FPGA ML561 Development Board has two 200 MHz Micron MT46V32M16BN-5B (16-bit) DDR400 SDRAM components that provide a 32-bit interface. Each 16-bit device is packaged in a 60-ball FBGA package, with a common address and control bus and separate clocks and DQS/DQ signals.

DDR2 DIMM

The Virtex-5 FPGA ML561 Development Board contains five PC-5300 240-pin DIMM sockets for a maximum data width of 144 bits or a maximum depth of four DIMMs. The sockets are arranged in a row leading away from the FPGA so they can share common address and control signals. DIMM1 through DIMM4 share DQ/DQS signals to form a deep 72-bit memory interface, while DIMM5 has separate DQ/DQS signals.

For the deep DDR2 interface, the sockets are to be populated starting at socket DIMM4. Table 3-2 illustrates how the sockets should be populated based on the interface wanted.

Table 3-2: Populating DDR2 DIMM Sockets

DIMM Interface

DIMM Sockets

Interface Width

Populated

 

 

 

 

 

One Deep

5 or 4

72-bit

 

 

 

Two Deep

4 and 3

72-bit

 

 

 

Three Deep

4, 3, and 2

72-bit

 

 

 

Four Deep

4, 3, 2, and 1

72-bit

 

 

 

Two Wide

5 and 4

144-bit

 

 

 

Populating the DIMMs in this order is necessary due to the placement of the termination on the signals being shared. More detail on termination is given in “Board Design Considerations,” page 36.

Virtex-5 FPGA ML561 User Guide

www.xilinx.com

19

UG199 (v1.2.1) June 15, 2009

Chapter 3: Hardware Description

R

Wide

Deep

DIMM5 (XP1)

 

DIMM4 (XP2)

 

DIMM3 (XP3)

 

DIMM2 (XP4)

 

DIMM1 (XP5)

 

 

 

 

 

 

 

 

 

DQ and DQS

BY0-BY7, CB0_7

DQ and DQS

BY8-BY15, CB8_15

Address and Commands

DIMM1 Control

DIMM2 Control

DIMM3 Control

DIMM4 Control

DIMM5 Control

UG199_c3_02_050106

Figure 3-2: DDR2 Deep and Wide DIMM Sockets

DDR2 SDRAM Components

The ML561 board contains two 333 MHz Micron MT47H32M16CC-3 (16-bit) DDR2 SDRAM components that provide a 32-bit interface to FPGA #1. Each 16-bit device is packaged in an 84-ball FBGA package, with a common address and control bus and separate clocks and DQS/DQ signals.

QDRII SRAM

The ML561 board contains a 300 MHz QDRII SRAM interface with a 72-bit Read interface and a 72-bit Write interface using two Samsung K7R643684M-FC30 components (x36). They are packaged in a 165-ball FBGA package with a body size of 15 x 17 mm. These two components share the same address/control signals but have separate clock and data signals.

RLDRAM II Devices

The ML561 contains a 300 MHz 36-bit RLDRAM II interface using two Micron MT49H16M18BM-25 devices (x18) packaged in a 144-ball PBGA package. They share a common address and control bus but have separate clocks and DQS/DQ signals.

20

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Virtex-5 FPGA ML561 User Guide

 

 

UG199 (v1.2.1) June 15, 2009

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Memory Details

Memory Details

DDR400 and DDR2 Component Memories

The FPGA #1 device on the Virtex-5 FPGA ML561 Development Board is connected to DDR and DDR2 component memories, as shown in Figure 3-3.

Figure 3-3 summarizes the distribution of DDR and DDR2 discrete component interface signals among the different banks of the FPGA #1 device.

BANK 25 (40)

BANK 6 (20)

 

BANK 21 (40)

BANK 4 (20)

BANK 22 (40)

 

Global Clock Inputs

 

BANK 17 (40)

BANK 2 (20)

BANK 18 (40)

 

Voltage Control

 

BANK 13 (40)

 

 

DDR Components

 

 

DQ 0, 1, 2

(Configuration)

 

BANK 11 (40)

BANK 0

BANK 12 (40)

DDR Components

 

USB Controls

DQ 3 & Controls

 

 

BANK 15 (40)

BANK 1 (20)

 

DDR2 Component

DDR2 Component

 

DQ 0, 1

Address

 

BANK 19 (40)

BANK 3 (20)

BANK 20 (40)

DDR2 Component

DDR2 Component

RS232

DQ 2, 3

Controls

Inter-FPGA MII Links

BANK 23 (40)

BANK 5 (20)

 

GTP I/O

BANK 126

BANK 122

BANK 118

BANK 114

BANK 112

BANK 116

BANK 120

BANK 124

UG199_c3_03_050106

Figure 3-3: FPGA #1 Banks for DDR400 and DDR2 Component (Top View)

Virtex-5 FPGA ML561 User Guide

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21

UG199 (v1.2.1) June 15, 2009

Chapter 3: Hardware Description

Table 3-3 describes all signals associated with DDR400 Component memories.

R

Table 3-3: DDR400 Component Signal Summary

Board Signal Name(s)

Bits

Description

 

 

 

DDR1_A[13:0]

14

DDR400 Component Address

 

 

 

DDR1_CK[2:1]_[P,N]

4

DDR400 Component Differential Clock

 

 

 

DDR1_[RAS,CAS,WE]_N, DDR1_CKE,

12

DDR400 Component Control Signals

DDR1_BA[1:0], DDR1_BY[0_1,2_3]_CS_N,

 

 

DDR1_DM_BY[3:0]

 

 

 

 

 

DDR1_DQ_BY0_B[7:0], DDR1_DQS_BY0_P

9

DDR400 Data and Strobe: Byte 0

 

 

 

DDR1_DQ_BY1_B[7:0], DDR1_DQS_BY1_P

9

DDR400 Data and Strobe: Byte 1

 

 

 

DDR1_DQ_BY2_B[7:0], DDR1_DQS_BY2_P

9

DDR400 Data and Strobe: Byte 2

 

 

 

DDR1_DQ_BY3_B[7:0], DDR1_DQS_BY3_P

9

DDR400 Data and Strobe: Byte 3

 

 

 

Notes:

1. DDR1_CKE signal has a weak 4.7KΩ pull-down resistor to meet the memory power-up requirements.

Table 3-4 describes all signals associated with DDR2 Component memories. For a complete list of FPGA #1 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”

Table 3-4: DDR2 Component Signal Summary

Board Signal Name(s)

Bits

Description

 

 

 

DDR2_A[12:0]

13

DDR2 Component Address

 

 

 

DDR2_CK[1:0]_[P,N]

4

DDR2 Component Differential

 

 

Clock

 

 

 

DDR2_ODT[1:0], DDR2_[RAS,CAS,WE]_N,

14

DDR2 Component Control Signals

DDR2_CKE, DDR2_BA[1:0], DDR2_CS[1:0]_N,

 

 

DDR2_DM_BY[3:0]

 

 

 

 

 

DDR2_DQ_BY0_B[7:0], DDR2_DQS_BY0_[P,N]

10

DDR2 Data and Strobe: Byte 0

 

 

 

DDR2_DQ_BY1_B[7:0], DDR2_DQS_BY1_[P,N]

10

DDR2 Data and Strobe: Byte 1

 

 

 

DDR2_DQ_BY2_B[7:0], DDR2_DQS_BY2_[P,N]

10

DDR2 Data and Strobe: Byte 2

 

 

 

DDR2_DQ_BY3_B[7:0], DDR2_DQS_BY3_[P,N]

10

DDR2 Data and Strobe: Byte 3

 

 

 

Notes:

1.DDR2_CKE and DDR2_ODT[1:0] signals have a weak 4.7KΩ pull-down resistor to meet the memory power-up requirements.

XAPP851, DDR SDRAM Controller Using Virtex-5 FPGA Devices, XAPP858, HighPerformance DDR2 SDRAM Interface in Virtex-5 Devices, and the corresponding demos are included on the CD shipped with the ML561 Tool Kit. For a complete list of FPGA #1 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”

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Memory Details

DDR2 SDRAM DIMM

The FPGA #2 device on the Virtex-5 FPGA ML561 Development Board is connected to DDR2 memories. The DDR2 memory interface includes a 144-bit wide DIMM connection to up to five 240-pin DDR2 DIMM sockets.

For the 144-bit wide DIMM datapath, the data bytes are spread across multiple banks of the FPGA #2 device. Figure 3-4 summarizes the distribution of DDR2 DIMM interface signals among the different banks of the FPGA #2 device.

BANK 124

TX 0, 1

BANK 120

RX 0, 1

BANK 116

GTP CLK

BANK 112

BANK 114

BANK 118

BANK 122

BANK 126

 

BANK 5 (20)

BANK 23 (40)

BANK 20 (40)

BANK 3 (20)

BANK 19 (40)

DDR2 DIMM

General I/O

DDR2 DIMM

DQ 8, 9, 10

 

Controls & DIMM1 Cntl

 

BANK 1 (20)

BANK 15 (40)

 

General I/O

DDR2 DIMM

 

 

DQ 0, 1, 2

BANK 12 (40)

 

BANK 11 (40)

DDR2 DIMM

 

DDR2 DIMM

DQ 11, 12, CB8_15

(Configuration)

DQ 6, 3 CB0_7

 

BANK 0

BANK 13 (40)

 

 

DDR2 DIMM

 

 

DQ 5, 7, 4

BANK 18 (40)

BANK 2 (20)

BANK 17 (40)

DDR2 DIMM

Inter-FPGA MII Links

DDR2 DIMM

DQ 14, 15, 13

 

Common Controls

BANK 22 (40)

BANK 4 (20)

BANK 21 (40)

DDR2 DIMM

Global Clock Inputs

DDR2 DIMM

DIMM 4 & 5 Cntl

 

DIMM 1, 2, 3 Cntl

 

BANK 6 (20)

BANK 25 (40)

 

 

UG199_c3_04_050106

Figure 3-4: FPGA #2 Banks for DDR2 DIMM (SSTL18) Interfaces (Top View)

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Table 3-5 describes all the signals associated with DDR2 DIMM component memories. For the Deep DIMM interface to four DIMMs, the individual dedicated control signals are listed at the bottom of Table 3-5.

Table 3-5: DDR2 DIMM Signal Summary

Board Signal Name(s)

Bits

Description

 

 

 

DDR2_DIMM_A[15:0]

16

DDR2 DIMM Address

 

 

 

DDR2_DIMM[5:1]_CK[2:0]_[P,N]

30

DDR2 DIMM Differential Clocks: Three copies per

 

 

DIMM

 

 

 

DDR2_DIMM_[RAS,CAS,WE,RESET]_N,

37

DDR2 DIMM Common Control Signals

DDR2_DIMM[5:1]_CKE[1:0], DDR2_DIMM_BA[2:0],

 

 

DDR2_DIMM[5:1]_CS[1:0]_N,

 

 

DDR2_DIMM[5:1]_ODT[1:0]

 

 

 

 

 

DDR2_DIMM[1:5]_CS[1:0]_N,

20

DDR2 DIMM Dedicated Control Signals

DDR2_DIMM[1:5]_CKE[1:0],

 

 

DDR2_DIMM[1:5]_ODT[1:0]

 

 

 

 

 

DDR2_DIMM_LB_BK[11,13,15]_[IN,OUT]

6

Deep DIMMs (DIMM1 through DIMM4) Loopback

 

 

Signals

 

 

 

DDR2_DIMM_LB_BK[12,18,20]

3

Wide DIMM (DIMM5) Loopback Signals (Total of six

 

 

FPGA pins)

 

 

 

DDR2_DIMM[1:5]_CNTL_PAR,

20

Miscellaneous Place Holder Signals to the Five

DDR2_DIMM[1:5]_CNTL_PAR_ERR,

 

DIMMs

DDR2_DIMM[1:5]_NC_019, DDR2_DIMM[1:5]_NC_102

 

 

 

 

 

DDR2_DIMM_DQ_BY[0:15]_B[7:0],

176

DDR2 DIMM Data, Strobes, and Data Mask: Bytes 0

DDR2_DIMM_DQS_BY[0:15]_L_[P,N],

 

through 15

DDR2_DIMM_DM_BY[0:15]

 

 

 

 

 

DDR2_DIMM_DQ_CB0_7_B[7:0],

11

DDR2 DIMM Data, Strobes, and Data Mask: Check

DDR2_DIMM_DQS_CB0_7_L_[P,N],

 

Byte 0

DDR2_DIMM_DM_CB0_7

 

 

 

 

 

DDR2_DIMM_DQ_CB8_15_B[7:0],

11

DDR2 DIMM Data, Strobes, and Data Mask: Check

DDR2_DIMM_DQS_CB8_15_L_[P,N],

 

Byte 1

DDR2_DIMM_DM_CB8_15

 

 

 

 

 

DDR2_DIMM[1:5]_SA[2:0]

15

Serial PROM Address

 

 

 

DDR2_DIMM_[SCL,SDA]"

2

Serial PROM interface CLK and Data

 

 

 

Notes:

1.DDR2_DIMM_CKE and DDR2_DIMM_ODT signals are connected to a 4.7KΩ pull-down resistor to meet the memory power-up requirements.

XAPP858, High-Performance DDR2 SDRAM Interface in Virtex-5 Devices and its corresponding demo are included on the CD shipped with the ML561 Tool Kit.

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Memory Details

QDRII and RLDRAM II Memories

Figure 3-5 summarizes the distribution of QDRII and RLDRAM II component interface signals among the different banks of the FPGA #3 device.

BANK 124

BANK 120

BANK 116

BANK 112

BANK 114

BANK 118

BANK 122

BANK 126

 

BANK 5 (20)

BANK 23 (40)

BANK 20 (40)

BANK 3 (20)

BANK 19 (40)

RLDII Data

General I/O

QDRII Data

DQ 0, 1 & D0

 

Q1, 3 & D1

 

BANK 1 (20)

BANK 15 (40)

 

System ACE Controls

QDRII Data

 

 

D7, 2, 3, 0

BANK 12 (40)

 

BANK 11 (40)

RLDII Data

 

QDRII Data

DQ 2, 3 & D1

(Configuration)

Q0, 2 & D6

 

BANK 0

BANK 13 (40)

 

 

 

 

QDRII Data

 

 

Q4, 5, 6

BANK 18 (40)

BANK 2 (20)

BANK 17 (40)

RLDII Data

Inter-FPGA MII Links

QDRII Data

D 2, 3

 

Q7 & D4, 5

BANK 22 (40)

BANK 4 (20)

BANK 21 (40)

RLDII Address

Global Clock Inputs

QDRII Address

and Control

 

and Control

 

BANK 6 (20)

BANK 25 (40)

 

 

UG199_c3_05_050106

Figure 3-5: FPGA #3 Banks for QDRII SRAM and RLDRAM II Interfaces (Top View)

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Table 3-6 describes all the signals associated with QDRII component memories.

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Table 3-6: QDRII Component Signal Summary

Board Signal Name(s)

Bits

Description

 

 

 

QDR2_SA[18:0]

19

QDRII Address

 

 

 

QDR2_CK_BY0_3_[P,N],

4

QDRII Differential Clock

QDR2_CK_BY4_7_[P,N]

 

 

 

 

 

QDR2_[R,W,DLL_OFF]_N

3

QDRII Control Signals

 

 

 

QDR2_D_BY[3:0]_B[8:0],

42

QDRII Write Data, Strobes, and Byte Write: Bytes 3:0

QDR2_K_BY0_3_[P,N],

 

 

QDR2_BW_BY[3:0]

 

 

 

 

 

QDR2_Q_BY[3:0]_B[8:0],

38

QDRII Read Data and Strobes: Bytes 3:0

QDR2_CQ_BY0_3_[P,N]

 

 

 

 

 

QDR2_D_BY[7:4]_B[8:0],

42

QDRII Write Data, Strobes, and Byte Write: Bytes 7:4

QDR2_K_BY4_7_[P,N],

 

 

QDR2_BW_BY[3:0]

 

 

 

 

 

QDR2_Q_BY[7:4]_B[8:0],

38

QDRII Read Data and Strobes: Bytes 7:4

QDR2_CQ_BY4_7_[P,N]

 

 

 

 

 

Notes:

1. QDR2_SA[18] is incorrectly labeled QDR2_NC_A3 in the ML561 schematics and layout file.

XAPP853: QDR II SRAM Interface for Virtex-5 Devices and its corresponding demo are included on the CD shipped with the ML561 Tool Kit.

For a complete list of FPGA #3 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.”

Table 3-7 describes all signals associated with RLDRAM II devices.

Table 3-7: RLDRAM II Component Signal Summary

Board Signal Name(s)

Bits

Description

 

 

 

RLD2_A[19:0], RLD2_BA[2:0]

23

RLDRAM II Address

 

 

 

RLD2_CK_BY0_1 _[P,N]

2

RLDRAM II Differential Clock

 

 

 

RLD2_CK_BY2_3 _[P,N]

2

RLDRAM II Differential Clock

 

 

 

RLD2_CS_BY[0_1,2_3]_N, RLD2_[REF,WE]_N,

8

RLDRAM II Control Signals

RLD2_DM_BY[0_1,2_3]_N, RLD2_QVLD_BY[0_1,2_3]

 

 

 

 

 

RLD2_DQ_BY[1:0]_B[8:0], RLD2_DK_BY0_1_[P,N],

24

RLDRAM II Data and Strobes: Bytes 1:0

RLD2_QK_BY[1:0]_[P,N]

 

 

 

 

 

RLD2_DQ_BY[3:2]_B[8:0], RLD2_DK_BY0_1_[P,N],

24

RLDRAM II Data and Strobes: Bytes 3:2

RLD2_QK_BY[3:2]_[P,N]

 

 

 

 

 

XAPP852, RLDRAM II Memory Interface for Virtex-5 FPGAs and its corresponding demo are included on the CD shipped with the ML561 Tool Kit.

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External Interfaces

External Interfaces

The external interfaces of the Virtex-5 FPGA ML561 Development Board are described in this section.

RS-232

The ML561 board provides an RS-232 serial interface using a Maxim MAX3316ECUP device. The maximum speed of this device is 460 Kbps.

Hooks are provided to connect and disconnect FPGAs to the RS-232 serial interface, by placing jumpers on headers based on the FPGA involved in the communication. Only one FPGA is allowed in the communication, and others must be disconnected before operation. The ML561 toolkit CD contains code to implement a UART core in one FPGA for interfacing with a host PC.

The RS-232 interface is accessible through a male DB-9 serial connector (P73).

Table 3-8: RS-232 Jumper Settings

To Connect FPGA # to

TX

RX

DB-9 (P73)

 

 

 

 

 

FPGA #1

P52 Pin 2 -> P52 Pin 1

P53 Pin 2 -> P53 Pin 1

 

 

 

FPGA #2

P52 Pin 2 -> P51 Pin 1

P53 Pin 2 -> P54 Pin 1

 

 

 

FPGA #3

P52 Pin 2 -> P52 Pin 3

P53 Pin 2 -> P53 Pin 3

 

 

 

USB

Full-speed (12 Mbps) USB functionality is proved using a Silicon Laboratories CP2102-GM USB to RS-232 Bridge. RS-232 and USB signals are converted between one another so a RS-232 core needs to be implemented in the FPGA for communication. A level translator is used to convert between the 2.5V I/O of the FPGA and the 3.3V I/O the CP2102 uses.

Hooks are provided to connect and disconnect FPGAs to the USB connection, by placing jumpers on headers based on the FPGA involved in the communication. Only one FPGA is allowed in the communication, and others must be disconnected before operation.

The USB interface is accessible through a female ‘A’ USB connector (J29).

Table 3-9: USB Jumper Settings

To Connect FPGA # to DB-9

TX

RX

(J29)

 

 

 

 

 

FPGA #1

P36 Pin 2 -> P36 Pin 1

P22 Pin2 -> P22 Pin 1

 

 

 

FPGA #2

P36 Pin 2 -> P35 Pin 1

P22 Pin2 -> P23 Pin 1

 

 

 

FPGA #3

P36 Pin 2 -> P36 Pin 3

P22 Pin2 -> P22 Pin 3

 

 

 

Clocks

The ML561 board contains a 200 MHz LVPECL clock oscillator and connectors for external clock inputs for use as system clocks (J19 and J20). The GTP transceivers use their own clock source that can be provided through SMA connectors on the board (J16 and J21).

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200 MHz LVPECL Clock

The 200 MHz LVPECL clock source is an Epson EG-2121CA200M-PCHS oscillator (Y1) with a differential output. The oscillator runs at 200 MHz ± 100 PPM with an operating voltage of 2.5V ±5%. This output is fed into an ICS853006 LVPECL buffer for generating a separate differential copy for each FPGA as well as a test point (P59).

Table 3-10: FPGA 200 MHz IDELAY Reference Clock Source

FPGA #

Signal Name

 

 

1

DIRECT_CLK_TO_FPGA1_P

 

 

1

DIRECT_CLK_TO_FPGA1_N

 

 

2

DIRECT_CLK_TO_FPGA2_P

 

 

2

DIRECT_CLK_TO_FPGA2_N

 

 

3

DIRECT_CLK_TO_FPGA3_P

 

 

3

DIRECT_CLK_TO_FPGA3_N

 

 

SMA Clock

Two SMA connectors are provided for the input of an off-board differential clock (J19 and J20). A differential clock buffer (ICS853006) is used on the board (U17 and U18) to generate four LVPECL copies of the differential clock signal, one for each FPGA along with a probe point (P40) for testing. The traces from the buffer are routed as a differential pair to each FPGA where they are terminated with 100Ω differential termination.

Table 3-11: FPGA External Clock Sources

FPGA #

Signal Name

 

 

1

EXT_CLK_TO_FPGA1_P

 

 

1

EXT_CLK_TO_FPGA1_N

 

 

2

EXT_CLK_TO_FPGA2_P

 

 

2

EXT_CLK_TO_FPGA2_N

 

 

3

EXT_CLK_TO_FPGA3_P

 

 

3

EXT_CLK_TO_FPGA3_N

 

 

33 MHz Clock

A single-ended 33 MHz Epson SG-8002CA oscillator is provided on the board (Y2) for testing purposes. Four copies of this clock are generated using a clock buffer (ICS8304) on the board, one per FPGA along with a probe point for testing (P41).

The application using this clock source as an input to the PLL on the Virtex-5 device has not yet been fully verified.

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External Interfaces

Table 3-12: FPGA Slow Clock Sources

FPGA

Signal Name

 

 

1

FPGA1_LOW_FREQ_CLK

 

 

2

FPGA2_LOW_FREQ_CLK

 

 

3

FPGA3_LOW_FREQ_CLK

 

 

33 MHz System ACE Controller Oscillator

A single-ended 33 MHz Epson SG-8002CA oscillator is provided on the board (Y3) as a clock source for System ACE functionality.

GTP Clocks

Two SMA connectors are provided for the input of an off-board differential clock (J16 and J21). A differential clock buffer (ICS8543BG) is used on the board (U20) to generate four LVDS copies of the differential clock signal, two for FPGA #1, one for FPGA #2, and one for FPGA #3.

A header is used to select between a clock forwarded by the GTP or from the external clock source used to provide a clock to the FPGA logic.

User I/Os

This subsection describes the devices that connect to the User I/Os of the ML561 board. These I/Os are provided to ease hardware development using the ML561.

General-Purpose Headers

The 16-pin test headers are surface mounted, one per FPGA. Of the two bytes of test signals, traces are matched for signals within a byte.

Table 3-13: Test Headers

Header Signal Description

Location

Header Pin #

 

 

 

FPGA1_TEST_HDR_BY0_B[0:7]

P20 (TEST1)

Odd pins: 1, 3, 5, 7, 9, 11, 13, 15

 

 

 

FPGA1_TEST_HDR_BY1_B[0:7]

P20 (TEST1)

Even pins: 2, 4, 6, 8, 10, 12, 14, 16

 

 

 

FPGA2_TEST_HDR_BY0_B[0:7]

P21 (TEST2)

Odd pins: 1, 3, 5, 7, 9, 11, 13, 15

 

 

 

FPGA2_TEST_HDR_BY1_B[0:7]

P21 (TEST2)

Even pins: 2, 4, 6, 8, 10, 12, 14, 16

 

 

 

FPGA3_TEST_HDR_BY0_B[0:7]

P93 (TEST3)

Odd pins: 1, 3, 5, 7, 9, 11, 13, 15

 

 

 

FPGA3_TEST_HDR_BY1_B[0:7]

P93 (TEST3)

Even pins: 2, 4, 6, 8, 10, 12, 14, 16

 

 

 

DIP Switch

One four-position DIP switch per FPGA (for a total of three) is available to externally pull up or pull down a signal on the FPGA. This can be used to manually set values used by the design running on the FPGA.

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Seven-Segment Displays

One seven-segment display per FPGA (for a total of three) is available for use. The red Stanley-Electric NAR131SB displays are active Low, using seven inputs to display a character or number plus another input for a decimal point.

7SEG_0_N

 

 

 

7SEG_5_N

 

7SEG_1_N

7SEG_6_N

7SEG_4_N

 

 

 

 

 

7SEG_2_N

 

 

 

 

 

 

 

 

 

 

 

 

7SEG_3_N

 

 

7SEG_DP_N

 

 

 

 

 

 

UG199_c3_06_050106

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3-6: Seven-Segment Display Signal Mapping

Light Emitting Diodes (LEDs)

Each FPGA is able to control four active-high green LEDs. The green is used to distinguish the User LEDs from the blue system LEDs on the Virtex-5 FPGA ML561 Development Board.

Pushbuttons

The ML561 board contains two momentary pushbuttons. Their functions and locations are described in Table 3-14.

Table 3-14: User Pushbuttons

Button

Description

Pin Connection

 

 

 

SW7

PROG_B: Configure FPGA

System ACE Controller: Pin 33

 

 

 

SW4

RESET_N: Reset the FPGA designs

FPGA #1: AH14

 

 

FPGA #2: AH14

 

 

FPGA #3: AH14

 

 

 

The Reset signal goes to a buffer (U32) that provides a separate copy of Reset to each

FPGA.

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External Interfaces

Power On or Off Slide Switch

The power on or off slide switch is a DPST slide switch used to apply input power to the board. While the board contains two such switches, the 5V switch is primarily used to supply 5V power to the board, whereas the 12V switch is available for testing only.

Soft Touch Probe Points

Soft Touch E5396A Probeless connection points are provided for monitoring FPGA #2 and FPGA #3 test signals with a compatible Agilent logic analyzer. FPGA #2 uses separate test signals for soft touch pins, while FPGA #3 shares the general-purpose test header signals with soft touch pins due to lack of available I/O pins.

Power Measurement Header

The ML561 comes with a 3M Pak 100 power measurement header to enable easy measurement of the power being consumed by the devices on the ML561. Each power regulator uses an Isotek Kelvin current sense resistor (SMV-R010-0.5) in the path from the output of the regulator to the power plane. The power can be computed by measuring the voltage drop across each of these resistors.

+5V or +12V

MARGIN+

MARGIN-

RKELVIN = 10 mΩ

 

 

VCCXXPR

VCCX

To FPGA or

 

VIN

VOUT

 

 

 

Other Device

 

Voltage

 

1KΩ

 

 

 

Regulator

 

VCCXX Mon

To

 

 

 

 

VCCXX Sense-

 

RSET

 

 

Monitor

 

 

 

VCCXX Sense+

Cable

 

 

 

 

 

 

 

 

 

 

UG199_c3_07_050106

Figure 3-7: Virtex-5 FPGA ML561 Development Board Power Measurement System

Table 3-15: Power Measurement Header Pins (P102)

 

 

Header Signal

Power Header Pin #

 

 

 

 

 

 

 

 

VCC1V0_SENSE+

1

 

 

 

 

 

 

 

 

VCC1V0_SENSE-

2

 

 

 

 

 

 

 

 

VCC1V0_MON

3

 

 

 

 

 

 

 

 

VCC2V5_SENSE+

5

 

 

 

 

 

 

 

 

VCC2V5_SENSE-

6

 

 

 

 

 

 

 

 

VCC2V5_MON

7

 

 

 

 

 

 

 

 

VCC3V3_SENSE+

9

 

 

 

 

 

 

 

 

VCC3V3_SENSE-

10

 

 

 

 

 

 

 

 

VCC3V3_MON

11

 

 

 

 

 

 

 

 

 

 

 

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Table 3-15: Power Measurement Header Pins (P102) (Continued)

Header Signal

Power Header Pin #

 

 

VCC1V8_SENSE+

13

 

 

VCC1V8_SENSE-

14

 

 

VCC1V8_MON

15

 

 

VCC1V5_SENSE+

17

 

 

VCC1V5_SENSE-

18

 

 

VCC1V5_MON

19

 

 

VCC2V6_SENSE+

21

 

 

VCC2V6_SENSE-

22

 

 

VCC2V6_MON

23

 

 

VCC5_SENSE+

25

 

 

VCC5_SENSE-

26

 

 

VCC5_MON

24

 

 

VCC5

20

 

 

GND

4

 

 

GND

8

 

 

GND

12

 

 

GND

16

 

 

Liquid Crystal Display Connector

R

Previous memory boards such as the ML461 had a DisplaytechQ 64128E-FC-BC-3LP 64x128 LCD panel. This display was removed from the ML561, but the connection is still available for use with embedded systems if the user connects the display to connector (P104). The LCD panel needs to hang off the edge of the board as shown in Figure 3-8.

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Power Regulation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RS232

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

 

 

 

 

 

HSTL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7SEG1

Driver

 

 

 

 

 

 

 

 

 

SPY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QDRII

 

 

 

 

 

 

 

 

 

Serial Header

 

12V Input

 

 

 

 

 

 

 

 

RLDRAM II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCAUX /

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jack

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCCO

 

 

 

 

 

RESET

 

 

5V Banana

 

 

 

 

 

 

12V -> 5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QDRII

 

 

 

 

 

HSTL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RLDRAM II

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jacks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VTT & VREF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

System ACE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test Header 3

 

 

 

 

 

ON

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Test Header

 

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA3 LEDs

 

 

 

Config3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5V Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jack

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HSTL

 

7

SEG3 DIP3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pwr Measure Header

 

 

LCD Connector

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PROG

 

 

 

JTAG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LCD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG199_c3_08_050106

Figure 3-8: LCD Panel Connector for Possible LCD Support

The product specification at http://www.displaytech.com.hk/pdf/graphic/64128e%20series-v10.PDF provides more information. Appendix C, “LCD Interface,” describes the LCD operation in detail.

Power Regulation

This section describes the devices that supply power to the Virtex-5 FPGA ML561 Development Board. For electrical requirements and power consumption, see Chapter 4, “Electrical Requirements.”

Power Distribution

The ML561 board uses +5V to drive numerous voltage regulators. Figure 3-9 shows a general overview of the power distribution system.

+5V

 

 

 

 

 

 

 

 

Board Power

 

 

 

 

 

 

 

 

To Devices

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slide

 

3.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MGT

 

 

 

 

Switch

 

 

 

 

 

 

 

 

 

 

MGT Power

 

 

 

 

 

 

 

Power

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+12V

 

 

 

12V -> 5V

 

 

 

 

FPGA Power

 

 

 

 

 

 

 

 

To All FPGAs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slide

 

 

 

 

 

VCCINT or VCCAUX/VCCO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPGA Power

 

 

 

 

 

 

 

 

To FPGAs

 

 

 

 

 

 

 

 

 

SSTL18, HSTL, or SSTL2

 

 

 

 

 

 

 

 

To Memories

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Power

 

 

 

 

 

 

 

 

VTT

 

 

 

 

 

 

 

 

 

SSTL18, HSTL, or SSTL2

 

 

 

 

 

VTT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF

 

 

UG199_c3_09_050106

Figure 3-9: Virtex-5 FPGA ML561 Development Board Power Distribution System

The Virtex-5 FPGA ML561 Development Board is powered through the +5V input jack (J28) from the power supply included in the ML561 Tool Kit. Alternatively, the +5V can

Virtex-5 FPGA ML561 User Guide

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UG199 (v1.2.1) June 15, 2009

Chapter 3: Hardware Description

R

also be supplied from a bench supply using the two banana jacks: J25 (RED) for +5V and J24 (BLACK) for GND.

The Rev-A assembly of the Virtex-5 FPGA ML561 Development Board does not support the +12V input via jack J23 or via banana jacks J18 (RED) for +12V and J17 (BLACK) for GND.

The memory and FPGAs use separate power supplies for SSTL18, HSTL, and SSTL2, respectively. Thus the power being consumed can be easily measured for each using the power measurement header provided on the ML561.

Voltage Regulators

The +5V voltage source is supplied as input to nine on-board regulator modules. Six of those modules (TI PTH05010-WAZ) are used to generate the +1.0V, +2.5V, and +1.8V for SSTL18 at FPGA #1 and FPGA #2, +1.8V for HSTL18 at FPGA #3, +2.6V for SSTL2 at FPGA #1, and +3.3V voltages for the GTP power supplies, LEDs, etc. The remaining three modules (TI PTH05000-ADJ) are used to generate +1.8V for SSTL18 at the memories, +1.8V for HSTL at the memories, and +2.6V for SSTL2 at the memories.

An additional three bulk voltage regulators (Fairchild FN6555) are used to generate termination (VTT) and reference (VREF) voltages each for the SSTL2, SSTL18, and HSTL power levels. By design, these voltage levels are half of the input reference voltage being supplied by the memory power supplies.

The TI PTH05010-WAZ and TI PTH05000-ADJ regulator modules require a fixed 5V input. The output is adjustable over a range of 0.9V to 3.6V by changing the resistor tied between pin 4 and GND. The difference between these two modules is that the PTH05010-WAZ output voltage can be margined up to+ 5% of the nominal value by driving pin 10 to GND (or digital Low), or margined down to -5% of the nominal value by driving pin 9 Low. The PTH05010-WAZ also has a tracking feature that can be used to track another voltage source.

TRACK

VMARGIN_DN_xxxx_N

VMARGIN_UP_xxxx_N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

9

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

GND

MRGNUP MRGNDN TRACK

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PTH05010

 

 

 

 

 

 

 

 

 

 

 

 

 

5V

 

 

 

 

 

 

 

 

2

VIN

 

 

 

 

 

 

 

 

 

Voltage Regulator

VOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INHIBIT VO_ADJ VO_SENSE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

4

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+

 

 

 

CIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+

 

 

COUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Inhibit

RSET

 

 

 

 

 

 

 

 

 

 

 

330 μF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

470 μF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(optional)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Jumper

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG199_c3_10_050106

Figure 3-10: PTH05010 Voltage Regulator

There are two ways to apply the digital controls to the margin input pins of the PTH05010: either from FPGA #1 or manually with jumpers.

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Power Regulation

The FPGA can drive VMARGIN_DN_xxxx_N and VMARGIN_UP_xxxx_N signals, where xxxx indicates one of the six main power regulators: SSTL2, HSTL, SSTL18, VCC1V0, VCC2V5, and VCC3V3.

Table 3-16: Manual Voltage Margining

VMARGIN_UP_N

VMARGIN_DN_N

Output Voltage

 

 

 

High

High

Nominal

 

 

 

High

Low

-5%

 

 

 

Low

High

+5%

 

 

 

Low

Low

Not Applicable

 

 

 

If both voltage-margining inputs to the power regulator are pulled Low, the output voltage is close to nominal but has the possibility of a slightly higher error in the output voltage. The power modules use a low-leakage open-drain control signal to control the voltage margining. In the FPGA, this can be approximated by using a control signal that drives the output Low when active and does not drive the signal at all when inactive (highimpedance output).

Three-pin headers are available for performing manual voltage margining, using jumpers to select between Nominal, -5%, and +5%. Table 3-17 shows the jumper settings.

Table 3-17: FPGA #1 Signals and On-Board Jumpers for Voltage Margining

Power Regulator

Signal Name

Jumper Setting

 

 

 

VCCINT (VR6)

VMARGIN_UP_VCC1V0_N

P48: 1 -> 2

 

VMARGIN_DN_VCC1V0_N

P48: 3 -> 2

 

 

 

SSTL18 (VR1)

VMARGIN_UP_SSTL18_N

P4: 1 -> 2

 

 

 

 

VMARGIN_DN_SSTL18_N

P4: 3 -> 2

 

 

 

SSTL2 (VR9)

VMARGIN_UP_SSTL2_N

P450 1 -> 2

 

 

 

 

VMARGIN_DN_SSTL2_N

P50: 3 -> 2

 

 

 

HSTL (VR10)

VMARGIN_UP_HSTL_N

P58: 1 -> 2

 

 

 

 

VMARGIN_DN_HSTL_N

P58: 3 -> 2

 

 

 

VCCAUX (VR12)

VMARGIN_UP_VCC2V5_N

P69: 1 -> 2

 

VMARGIN_DN_VCC2V5_N

P69: 3 -> 2

 

 

 

The TI PTH05010-WAZ and TI PTH05000-ADJ regulator outputs can be enabled or inhibited through the use of on-board two-pin jumpers. The inhibit jumpers use the following conventions:

Jumper OFF = Enabled

Jumper ON = Inhibited

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UG199 (v1.2.1) June 15, 2009

Chapter 3: Hardware Description

Table 3-18 summarizes the inhibit headers.

Table 3-18: Headers for Voltage Regulator Inhibition

Power Regulator

Inhibit Header

 

 

VCCINT (VR6)

P63

SSTL18 (VR1)

P11

 

 

SSTL18_M (VR4)

P32

 

 

SSTL2 (VR9)

P68

 

 

SSTL2_M (VR2)

P5

 

 

HSTL (VR10)

P74

 

 

HSTL_M (VR14)

P105

 

 

VCCAUX (VR12)

P79

VCC3V3 (VR13)

P101

 

 

Board Design Considerations

R

UG086, Memory Interface Generator (MIG) User Guide includes PCB implementation rules and guidelines to be followed for designing a board for a MIG reference design.

The Virtex-5 FPGA ML561 Development Board design allows implementation of DCI termination scheme at the FPGA for each of the memory interfaces on the board. A preliminary analysis of the Weighted Average Simultaneously Switching Outputs (WASSO) for all three Virtex-5 devices indicates that the SSO guidelines are met for the current pinout. The following factors helped to reduce the SSO noise as compared to the Virtex-4 FPGA ML461 board implementation:

SparseChevron pinout resulting in larger number of Power/GND pin pairs per bank

A revised higher SSO allowance per Power/GND pair for SparseChevron packages

Reduced thickness of the board (74 mils vs. 98 mils) resulting in reduced via inductance

External terminations at both the memory and FPGA are provided for data signals for most of the memory interfaces on the Virtex-5 FPGA ML561 Development Board layout. The external VTT termination is implemented with a single 50Ω termination to the VREF level. See Chapter 5, “Signal Integrity Recommendations,” for specific recommendations and guidelines for terminations.

These are VTT end terminations to the respective voltage levels for SSTL2, SSTL18, and HSTL signals. There are two topologies of end terminations for data signals:

1.Fly-by termination: The parallel termination is placed after the receiver pin.

2.Non-fly-by termination: The parallel termination is placed between the driver and the receiver along the trace as close to the receiver pin as possible. Also the stub from signal trace to the termination resistor is kept very short, within 0.1 inch.

For Read data, terminations at the FPGA have non-fly-by termination topology. These terminations can be selectively depopulated on the ML561 board when DCI termination is implemented inside FPGA for received data. Due to non-fly-by termination topology, the result is a minimal stub for the signal, thus preserving good signal integrity for read data.

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Board Design Considerations

For Write data and terminations at the memory, if the trace length from the receiver pin to the termination resistor can be guaranteed to be within 0.3 inches, then the fly-by termination scheme is implemented. Otherwise, the non-fly-by termination topology is implemented for Write data at the memory end.

The physical dimensions of the raw PCB are 12.75 inches x 11.75 inches. With the overhangs due to edge connectors, the actual size of the fully assembled board is approximately 13 inches x 12 inches, with 1.5 inches height allowance for the DIMM modules. This 14-layer board has 6 signal layers, 4 GND layers, and 4 power planes and uses Polyclad 370HR material for lead-free assembly. Figure 3-11 shows a stack-up diagram of the ML561 Revision A PCB.

Refer to UG203, Virtex-5 PCB Designer’s Guide for more information on the PCB design using Virtex-5 devices.

 

 

 

 

 

 

 

 

1.0 oz, TOP, Z0 = 50Ω, width = 6 mils

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.8 mils, Er = 4.4

 

 

 

 

 

 

 

 

1.0 oz, 02_GND1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 mils, Er = 4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.5 oz, 03_INR1, Z0 = 50Ω, width = 4.5 mils

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.3 mils, Er = 4.4

 

 

 

 

 

 

 

 

1.0 oz, 04_PWR1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8 mils, Er = 4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.5 oz, 05_INR2, Z0 = 50Ω, width = 4.5 mils

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.2 mils, Er = 4.4

 

 

 

 

 

 

 

 

1.0 oz, 06_GND2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 mils, Er = 4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.0 oz, 07_PWR2

 

 

 

 

 

 

 

 

73.90 ±7 mils

 

 

 

3.3 mils, Er = 4.4

 

 

 

 

 

 

 

 

1.0 oz, 08_PWR3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 mils, Er = 4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.0 oz, 09_GND3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.2 mils, Er = 4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.5 oz, 10_INR5, Z0 = 50Ω, width = 4.5 mils

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8 mils, Er = 4.4

 

 

 

 

 

 

 

 

1.0 oz, 11_PWR4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.3 mils, Er = 4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.5 oz, 12_INR6, Z0 = 50Ω, width = 4.5 mils

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 mils, Er = 4.4

 

 

 

 

 

 

 

 

1.0 oz, 13_GND4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.8 mils, Er = 4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.0 oz, BOTTOM, Z0 = 50Ω, width = 6 mils

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG199_c3_11_102407

 

 

 

Figure 3-11:

ML561 Revision A PCB Stack-Up

Virtex-5 FPGA ML561 User Guide

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37

UG199 (v1.2.1) June 15, 2009

Chapter 3: Hardware Description

R

Table 3-19 shows the details of the dielectric material and construction for each layer and the controlled impedance values for the signal layers.

Table 3-19: ML561 Revision A PCB Controlled Impedance

 

Layer

 

 

Cu

Substrate

 

Test

Z0

 

Seq #

Type

Usage

Weight

Thickness

Er

Width

Comment

Name

(ohms)

 

 

 

 

(oz.)

(mils)

 

(mils)

 

 

1

TOP

Metal

Signal

1.0

 

<Auto>

6

50 ±5

Microstrip Signal Top

 

 

 

 

 

 

 

 

 

 

2

 

Dielectric

Substrate

 

3.8

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

3

02_GND1

Metal

Plane

1.0

 

<Auto>

 

 

Ground Plane #1

 

 

 

 

 

 

 

 

 

 

4

 

Dielectric

Substrate

 

4

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

5

03_INR1

Metal

Signal

0.5

 

<Auto>

4.5

50 ±5

Stripline Signal - Inner #1

 

 

 

 

 

 

 

 

 

 

6

 

Dielectric

Substrate

 

5.3

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

7

04_PWR1

Metal

Plane

1.0

 

<Auto>

 

 

Split Power Plane #1

 

 

 

 

 

 

 

 

 

 

8

 

Dielectric

Substrate

 

8

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

9

05_INR2

Metal

Signal

0.5

 

<Auto>

4.5

50 ±5

Stripline Signal - Inner #2

 

 

 

 

 

 

 

 

 

 

10

 

Dielectric

Substrate

 

3.2

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

11

06_GND2

Metal

Plane

1.0

 

<Auto>

 

 

Ground Plane #2

 

 

 

 

 

 

 

 

 

 

12

 

Dielectric

Substrate

 

3

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

13

07_PWR2

Metal

Plane

1.0

 

<Auto>

 

 

Split Power Plane #2

 

 

 

 

 

 

 

 

 

 

14

 

Dielectric

Substrate

 

3.3

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

15

08_PWR3

Metal

Plane

1.0

 

<Auto>

 

 

Split Power Plane #3

 

 

 

 

 

 

 

 

 

 

16

 

Dielectric

Substrate

 

3

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

17

09_GND3

Metal

Plane

1.0

 

<Auto>

 

 

Ground Plane #3

 

 

 

 

 

 

 

 

 

 

18

 

Dielectric

Substrate

 

3.2

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

19

10_INR5

Metal

Signal

0.5

 

<Auto>

4.5

50 ±5

Stripline Signal - Inner #3

 

 

 

 

 

 

 

 

 

 

20

 

Dielectric

Substrate

 

8

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

21

11_PWR4

Metal

Plane

1.0

 

<Auto>

 

 

Split Power Plane #4

 

 

 

 

 

 

 

 

 

 

22

 

Dielectric

Substrate

 

5.3

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

23

12_INR6

Metal

Signal

0.5

 

<Auto>

4.5

50 ±5

Stripline Signal - Inner #4

 

 

 

 

 

 

 

 

 

 

24

 

Dielectric

Substrate

 

4

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

25

13_GND4

Metal

Plane

1.0

 

<Auto>

 

 

Ground Plane #4

 

 

 

 

 

 

 

 

 

 

26

 

Dielectric

Substrate

 

3.8

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

27

BOTTOM

Metal

Signal

1.0

 

<Auto>

6

50 ±5

Microstrip Signal Bottom

 

 

 

 

 

 

 

 

 

 

38

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Virtex-5 FPGA ML561 User Guide

 

 

UG199 (v1.2.1) June 15, 2009

R

Chapter 4

Electrical Requirements

This chapter provides the electrical requirements for the Virtex-5 FPGA ML561

Development Board. It contains the following sections:

“Power Consumption”

“FPGA Internal Power Budget”

Power Consumption

Table 4-1 lists the operating voltages, maximum currents, and power consumption used by the ML561 board devices. The Virtex-5 FPGA ML561 Development Board has provisions for two power inputs: a 5V power supply and a 12V power supply. The maximum rating of a commercially available 5V power supply is limited to 8A, or a 40W maximum capacity. This power supply is similar to the 5V brick used for previous memory tool kits, for example, ML461. This tool kit expects the Virtex-5 FPGA ML561 Development Board to exercise only one external memory interface at a time. In this case, the total power consumption of the board stays within the 40W limit.

As shown in Table 4-1, if all three FPGA devices and their associated memory devices are activated simultaneously, then the total power consumption is approximately 57W, which exceeds the 40W capacity of the 5V power brick. So an alternate 12V power input jack (J23) is provided on the Virtex-5 FPGA ML561 Development Board to hook up a 12V power brick, for example, CUI DTS120500U with a 60W capacity. The 12V is converted to 5V using the TI PTH12010WAS power module (VR11), which can supply up to 12A of current at 5V, or a 60W capacity.

Virtex-5 FPGA ML561 User Guide

www.xilinx.com

39

UG199 (v1.2.1) June 15, 2009

Chapter 4: Electrical Requirements

Table 4-1: ML561 Power Consumption

R

Device Description

Quantity

Voltage (V)

Current

Power

Source

(mA)

(W)

 

 

 

 

 

 

Total Available Power

 

 

 

 

 

 

 

 

 

 

 

5V Power Supply

1

5.0

8000

40.0

Bellus Power SPD-050-5

 

 

 

 

 

 

12V Power Supply

1

12.0

5000

60.0

CUI DTS120500U

 

 

 

 

 

 

Power Consumed

 

 

 

 

 

 

 

 

 

 

 

DDR400 Component Interface

 

 

 

 

 

 

 

 

 

 

 

XC5VLX50T-FFG1136:

1

1.0, 2.5, 2.6

1887

3.7

Xilinx Power Estimator

FPGA #1 (DDR400)

 

 

 

 

 

 

 

 

 

 

 

 

DDR x16 Memory

2

2.6

210

1.1

Micron DDR Component Data Sheet

 

 

 

 

 

 

DDR Comp VTT Termination

60

1.2

16

1.2

All signals. ±608 mV swing around VTT

DDR2 Component Interface

 

 

 

 

 

 

 

 

 

 

 

XC5VLX50T-FFG1136:

1

1.0, 1.8[S],

1991

3.1

Xilinx Power Estimator

FPGA #1 (DDR2)

2.5

 

 

 

 

 

 

 

 

 

 

 

DDR2 x16 Memory

2

1.8

250

0.9

Micron DDR2 Component Data Sheet

 

 

 

 

 

 

DDR2 Comp VTT Termination

25

1.2

16

0.5

Addr/Cntl: ± 603 mV swing around VTT

DDR2 DIMM Interface

 

 

 

 

 

 

 

 

 

 

 

XC5VLX50T-FFG1136:

1

1.0, 1.8[S],

6420

10.2

Xilinx Power Estimator

FPGA #2 (DDR2)

 

2.5

 

 

 

DDR2 DIMM

2

1.8

1755

6.3

Micron DDR2 DIMM Data Sheet

 

 

 

 

 

 

DDR2 DIMM VTT Termination

160

1.2

16

3.1

All signals: ± 603 mV swing around VTT

QDRII Memory Interface

 

 

 

 

 

 

 

 

 

 

 

XC5VLX50T-FFG1136:

1

1.0, 1.8[H],

3917

6.3

Xilinx Power Estimator

FPGA #3 (QDRII)

1.8[S], 2.5

 

 

 

 

 

 

 

 

 

 

 

QDRII Memory [H]

2

1.8

950

3.4

Samsung QDRII Data Sheet

 

 

 

 

 

 

QDRII VTT Termination

175

1.0

16

2.8

All signals. ± 500 mV swing around VTT

RLDRAM II Memory Interface

 

 

 

 

 

 

 

 

 

 

 

XC5VLX50T-FFG1136:

1

1.0, 1.8[H],

3069

4.5

Xilinx Power Estimator

FPGA #3 (RLDRAM II)

2.5

 

 

 

 

 

 

 

 

 

 

 

RLDRAM II Memory

2

1.8

920

3.3

Micron RLDRAM II Data Sheet

 

 

 

 

 

 

RLDRAM II VTT Termination

60

1.0

16

1.0

All signals. ± 500 mV swing around VTT

Miscellaneous Circuit

 

 

 

 

 

 

 

 

 

 

 

Clock Buffer

1

3.3

23

0.1

ICS8304 Data Sheet

 

 

 

 

 

 

Differential Clock Buffer

2

3.3

115

0.8

ICS853006 Data Sheet

 

 

 

 

 

 

System ACE Controller

1

3.3

200

0.7

DS080, System ACE CompactFlash Solution

 

 

 

 

 

 

200 MHz Oscillator

1

2.5

30

0.1

Epson EG2121CA Data Sheet

 

 

 

 

 

 

33 MHz Oscillator

2

3.3

45

0.3

Epson SG-8002CA Data Sheet

 

 

 

 

 

 

Total Power Consumed

 

 

 

53.2

 

 

 

 

 

 

 

40

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Virtex-5 FPGA ML561 User Guide

 

 

UG199 (v1.2.1) June 15, 2009

R

Power Consumption

Table 4-1: ML561 Power Consumption (Continued)

Device Description

Quantity

Voltage (V)

Current

Power

Source

(mA)

(W)

 

 

 

 

 

 

Power Modules Capacity

 

 

 

 

 

 

 

 

 

 

 

VCCINT Power Plane (1.0V)

1

1.00

15000

15.0

TI PTH05010 15A Module Data Sheet

HSTL FPGA Power Plane (1.8V)

1

1.80

15000

27.0

 

 

 

 

 

 

 

HSTL Memory Power Plane (1.8V)

1

1.80

6000

10.8

TI PTH05000 6A Module Data Sheet

 

 

 

 

 

 

HSTL _VREF Power Plane (0.9V)

1

0.90

3000

2.7

Fairchild FN6555 Data Sheet

 

 

 

 

 

 

SSTL18 FPGA Power Plane (1.8V)

1

1.80

15000

27.0

TI PTH05010 15A Module Data Sheet

 

 

 

 

 

 

SSTL18 Memory Power Plane (1.8V)

1

1.80

6000

10.8

TI PTH05000 6A Module Data Sheet

 

 

 

 

 

 

SSTL18 _VREF Power Plane (0.9V)

1

0.90

3000

2.7

Fairchild FN6555 Data Sheet

 

 

 

 

 

 

SSTL2 FPGA Power Plane (2.6V)

1

2.60

15000

39.0

TI PTH05010 15A Module Data Sheet

 

 

 

 

 

 

SSTL2 Memory Power Plane (2.6V)

1

2.60

6000

15.6

TI PTH05000 6A Module Data Sheet

 

 

 

 

 

 

SSTL2 _VREF Power Plane (1.3V)

1

1.30

3000

3.9

Fairchild FN6555 Data Sheet

 

 

 

 

 

 

2.5V Power Plane

1

2.50

15000

37.5

TI PTH05010 15A Module Data Sheet

 

 

 

 

 

 

3.3V Power Plane

1

3.30

15000

49.5

 

 

 

 

 

 

 

12V-to-5V Converter

1

5.00

12000

60.0

TI PTH12010 12A Module Data Sheet

 

 

 

 

 

 

Notes:

1.[S] = 1.8V power for SSTL18 plane.

2.[H] = 1.8V power for HSTL18 plane.

Virtex-5 FPGA ML561 User Guide

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41

UG199 (v1.2.1) June 15, 2009

Chapter 4: Electrical Requirements

R

Table 4-2 lists the 12 different power planes on the Virtex-5 FPGA ML561 Development Board. For the SSTL2, SSTL18, and HSTL power, separate power modules are implemented for VCCO to FPGA, and VDD to memory, allowing for ease of power measurement for the FPGAs. The power modules for VCCO inputs are implemented with TI PTH05010 modules, which have provisions for ± 5% voltage margining pins.

Table 4-2: Power Planes

Voltage Regulator Module (VRM) Part

Power Plane

VRM REFDES

Stack-Up

Layer

 

 

 

 

 

 

 

 

VCCINT Power Plane (1.0V)

VR6

Layer 4

 

SSTL18 FPGA Power Plane (1.8V)

VR1

Layer 7

 

 

 

 

TI PTH05010 15A Modules

HSTL FPGA Power Plane (1.8V)

VR10

Layer 8

 

 

 

VCCAUX Power Plane (2.5V)

VR12

Layer 11

 

 

SSTL2 FPGA Power Plane (2.6V)

VR9

Layer 8

 

 

 

 

 

TTL Power Plane (3.3V)

VR13

Layer 11

 

 

 

 

 

SSTL18 Memory Power Plane (1.8V)

VR4

Layer 7

 

 

 

 

TI PTH05000 6A Modules

HSTL Memory Power Plane (1.8V)

VR14

Layer 8

 

 

 

 

 

SSTL2 Memory Power Plane (2.6V)

VR2

Layer 8

 

 

 

 

 

SSTL18_VREF Power Plane (0.9V)

U14

Layer 8

 

 

 

 

SSTL18_VTT Power Plane (0.9V)

Layer 8

 

 

 

 

 

 

Fairchild FN6555 3A Bus Term Regulators

HSTL_VREF Power Plane (0.9V)

U42

Layer 7

(Separate outputs for VTT and VREF)

 

 

HSTL_VTT Power Plane (0.9V)

Layer 7

 

 

 

 

 

 

SSTL2_VREF Power Plane (1.3V)

U2

Layer 7

 

 

 

 

SSTL2_VTT Power Plane (1.3V)

Layer 7

 

 

 

 

 

 

Each of the three Fairchild FN6555 Bus Terminator Regulators has two voltage outputs:

one each for VREF and VTT. The FN6555 regulator is a push-pull device rated at ± 3A for the VTT output and 3 mA for the VREF output.

Because the VREF voltage is used by the FPGA and memory devices only as reference, the power supply does not source any real current. Thus the 3 mA capacity for the VREF output is considered sufficient.

The VTT voltage is guaranteed to within ± 20 mV of the VREF output by the FN6555 regulator. The minimum driver output voltage swing around VREF is specified for the

SSTL18, SSTL2, and HSTL I/O standards as:

SSTL2: ± 608 mV

SSTL18: ± 603 mV

HSTL: ± 500 mV (for HSTL18)

For a given memory interface, the maximum number of single-ended (non-differential) signals that might need to be pulled up or down at a time for QDRII is 144 data bits and approximately 30 address and control signals. The differential pair signals offset for the sink and source of current. With a continuous current capacity of 3A for the FN6555 regulator, the regulator can supply up to (3000 / 175) = 17 mA of current per signal. The maximum drive strength for a driver is specified at 16 mA. For a 50Ω VTT termination, this

42

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Virtex-5 FPGA ML561 User Guide

 

 

UG199 (v1.2.1) June 15, 2009

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