Xilinx UG129 User Manual

PicoBlaze 8-bit Embedded Microcontroller User Guide

for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs

UG129 (v1.1.2) June 24, 2008

Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate

on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reser ves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT cc THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2004-2008 Xilinx, Inc. All rights reser ved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM Corp. and used under license. PCI, PCI-X, and PCI EXPRESS are registered trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document...

Version Revision

05/20/04 1.0 Initial Xilinx release.

06/10/04 1.1 Various minor corrections, updates, and enhancements throughout.

11/21/05 1.1.1 Minor updates.

06/24/08 1.1.2 Corrected typo in example for “LOAD sX, Operand — Load Register sX with Operand”.

Updated trademarks and links.

PicoBlaze 8-bit Embedded Microcontroller www.xilinx.com UG129 (v1.1.2) June 24, 2008

Limitations

Limited Warranty and Disclaimer

These designs are provided to you “as-is”. Xilinx and its licensors make and you receive no warranties or conditions, express, implied, statutory or otherwise, and Xilinx specifically disclaims any implied warranties of merchantability, non-infringement, or fitness for a particular purpose. Xilinx does not warrant that the functions contained in these designs will meet your requirements, or that the operation of these designs will be uninterrupted or error free, or that defects in the Designs will be corrected. Furthermore, Xilinx does not warrant or make any representations regarding use or the results of the use of the designs in terms of correctness, accuracy, reliability, or otherwise.

Limitation of Liability

In no event will Xilinx or its licensors be liable for any loss of data, lost profits, cost or procurement of substitute goods or services, or for any special, incidental, consequential, or indirect damages arising from the use or operation of the designs or accompanying documentation, however caused and on any theory of liability. This limitation will apply even if Xilinx has been advised of the possibility of such damage. This limitation shall apply not-withstanding the failure of the essential purpose of any limited remedies herein.

Preface

Technical Support Limitations

This module is not supported by general Xilinx Technical support as an official Xilinx product. Please refer any issues initially to the provider of the module. The author will gratefully receive any issues or potential continued improvements of the PicoBlaze™ microcontroller.

Ken Chapman

Senior Staff Engineer

E-mail: picoblaze@xilinx.com

The author will also be pleased to hear from anyone using the PicoBlaze™ microcontroller with information about your application and how these macros have been useful.

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UG129 (v1.1.2) June 24, 2008

Acknowledgments

Xilinx thanks the following individuals for their contribution to the PicoBlaze microcontroller cause:

• Henk van Kampen, Mediatronix

Developer of the pBlazIDE graphical, integrated development environment.

• Prof. Dr.-Ing. Bernhard Lang, University of Applied Sciences, Osrabrueck, Germany

Concept of using VHDL simulation variables to display disassembled op-code instructions.

• Kris Chaplin, Xilinx Ltd.

JTAG-based program loader, update function.

Preface: Acknowledgments

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UG129 (v1.1.2) June 24, 2008

Guide Contents

About This Guide

The PicoBlaze™ embedded microcontroller is an efficient, cost-effective embedded processor core for Spartan describes the capabilities, features, and benefits of PicoBlaze hardware design and how to effectively use the PicoBlaze instruction set and tools to create software applications.

Guide Contents

This manual contains the following chapters:

• Chapter 1, “Introduction,” describes the features and functional blocks of the

• Chapter 2, “PicoBlaze Interface Signals,” defines the PicoBlaze signals.

• Chapter 3, “PicoBlaze Instruction Set,” summarizes the instruction set of the

• Chapter 4, “Interrupts,” describes how the PicoBlaze microcontroller uses interrupts.

• Chapter 5, “Scratchpad RAM,” describes the 64-byte scratchpad RAM.

• Chapter 6, “Input and Output Ports,” describes the input and output ports supported

• Chapter 7, “Instruction Storage Configurations,” provides several examples of

• Chapter 8, “Performance,”provides performance values for the PicoBlaze

• Chapter 10, “Using the PicoBlaze Microcontroller in an FPGA Design,” describes the

• Chapter 9, “PicoBlaze Development Tools,” describes the available development

• Chapter 11, “Assembler Directives,” describes the assembler directives that provide

• Chapter 12, “Simulating PicoBlaze Code,” describes the tools that simulate PicoBlaze

• Appendix A, “Related Materials and References,” provides additional resources

• Appendix B, “Example Program Templates,” provides example KCPSM3 and

• Appendix C, “PicoBlaze Instruction Set and Event Reference,” summarizes the

• Appendix D, “Instruction Codes,” provides the 18-bit instruction codes for all

• Appendix E, “Register and Scratchpad RAM Planning Worksheets,” provides

-3, Virtex®-II, and Virtex-II Pro FPGAs. This user guide

PicoBlaze microcontroller.

PicoBlaze microcontrollers.

by the PicoBlaze microcontroller.

instruction storage with the PicoBlaze microcontroller.

microcontroller.

design flow process with the PicoBlaze microcontroller.

tools.

advanced control.

code.

useful for the PicoBlaze microcontroller design.

pBlazIDE code templates for use in application programs.

PicoBlaze instructions and events in alphabetical order.

PicoBlaze instructions.

worksheets to use for the PicoBlaze microcontroller design.

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Preface: About This Guide

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UG129 (v1.1.2) June 24, 2008

Preface: Limitations

Limited Warranty and Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Limitation of Liability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Technical Support Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Preface: Acknowledgments

²: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 1: Introduction

PicoBlaze Microcontroller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PicoBlaze Microcontroller Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1,024-Instruction Program Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

64-Byte Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program Counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Program Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CALL/RETURN Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Why the PicoBlaze Microcontroller? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Why Use a Microcontroller within an FPGA? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chapter 2: PicoBlaze Interface Signals

Chapter 3: PicoBlaze Instruction Set

Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Processing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Logic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Bitwise AND, OR, XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Complement/Invert Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Invert or Toggle Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clear Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ADD and ADDCY Add Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SUB and SUBCY Subtract Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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Increment/Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Negate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

No Operation (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Setting and Clearing CARRY Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Clear CARRY Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Set CARRY Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Test and Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Shift. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Moving Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Program Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

JUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

CALL/RETURN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 4: Interrupts

Example Interrupt Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 5: Scratchpad RAM

Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Implementing a Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Stack Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

FIFO Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Chapter 6: Input and Output Ports

PORT_ID Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

INPUT Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Applications with Few Input Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

READ_STROBE Interaction with FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

OUTPUT Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Simple Output Structure for Few Output Destinations . . . . . . . . . . . . . . . . . . . . . . . . . 56

Pipelining for Maximum Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Repartitioning the Design for Maximum Performance . . . . . . . . . . . . . . . . . . . . . . . 60

Chapter 7: Instruction Storage Configurations

Standard Configuration – Single 1Kx18 Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . 61

Standard Configuration with UART or JTAG Programming Interface . . . . . . . . 62

Two PicoBlaze Microcontrollers Share a 1Kx18 Code Image. . . . . . . . . . . . . . . . . . 62

Two PicoBlaze Microcontrollers with Separate Code Images in a Block RAM 63

Distributed ROM Instead of Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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Chapter 8: Performance

Input Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Predicting Executing Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Chapter 9: PicoBlaze Development Tools

KCPSM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Assembly Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Input and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Mediatronix pBlazIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Configuring pBlazIDE for the PicoBlaze Microcontroller . . . . . . . . . . . . . . . . . . . . . . . 69

Importing KCPSM3 Code into pBlazIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Differences Between the KCPSM3 Assembler and pBlazIDE. . . . . . . . . . . . . . . . . 71

Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Chapter 10: Using the PicoBlaze Microcontroller in an FPGA Design

VHDL Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

KCPSM3 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Connecting the Program ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Black Box Instantiation of KCPSM3 using KCPSM3.ngc . . . . . . . . . . . . . . . . . . . . . 75

Generating the Program ROM using prog_rom.coe. . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Generating an ESC Schematic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Verilog Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Chapter 11: Assembler Directives

Locating Code at a Specific Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Naming or Aliasing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Defining Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Naming the Program ROM Output File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

KCPSM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

pBlazIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Defining I/O Ports (pBlazIDE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Input Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Custom Instruction Op-Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Chapter 12: Simulating PicoBlaze Code

Instruction Set Simulation with pBlazIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Simulator Control Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Using the pBlazIDE Instruction Set Simulator with KCPSM3 Programs . . . . . . . . . . 86

Simulating FPGA Interaction with the pBlazIDE Instruction Set Simulator . . . . . . . 86

Turbocharging Simulation using FPGAs! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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Appendix A: Related Materials and References

Appendix B: Example Program Templates

KCPSM3 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

pBlazIDE Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Appendix C: PicoBlaze Instruction Set and Event Reference

ADD sX, Operand —Add Operand to Register sX. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

ADDCY sX, Operand —Add Operand to Register sX with Carry . . . . . . . . . . . . . 94

AND sX, Operand — Logical Bitwise AND Register sX with Operand. . . . . . . . 95

CALL [Condition,] Address — Call Subroutine at Specified Address. . . . . . . . . 96

COMPARE sX, Operand — Compare Operand with Register sX. . . . . . . . . . . . . . 98

DISABLE INTERRUPT — Disable External Interrupt Input. . . . . . . . . . . . . . . . . . 99

ENABLE INTERRUPT — Enable External Interrupt Input . . . . . . . . . . . . . . . . . . . 99

FETCH sX, Operand — Read Scratchpad RAM Location to Register sX . . . . . . 100

INPUT sX, Operand — Set PORT_ID to Operand, Read value on IN_PORT. 101

INTERRUPT Event, When Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

JUMP [Condition,] Address — Jump to Specified Address . . . . . . . . . . . . . . . . . . 103

LOAD sX, Operand — Load Register sX with Operand. . . . . . . . . . . . . . . . . . . . . . 104

OR sX, Operand — Logical Bitwise OR Register sX with Operand . . . . . . . . . . 105

OUTPUT sX, Operand — Write Register sX Value to OUT_PORT. . . . . . . . . . . 106

RESET Event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

RETURN [Condition] — Return from Subroutine Call . . . . . . . . . . . . . . . . . . . . . . 108

RETURNI [ENABLE/DISABLE] — Return from Interrupt Service Routine . . 109

RL sX — Rotate Left Register sX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

RR sX — Rotate Right Register sX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

SL[ 0 | 1 | X | A ] sX — Shift Left Register sX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

SR[ 0 | 1 | X | A ] sX — Shift Right Register sX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

STORE sX, Operand — Write Register sX Value to Scratchpad RAM . . . . . . . . 114

SUB sX, Operand —Subtract Operand from Register sX. . . . . . . . . . . . . . . . . . . . . 115

SUBCY sX, Operand —Subtract Operand from Register sX with Borrow . . . . 116

TEST sX, Operand — Test Bit Location in Register sX, Generate Odd Parity . 118

XOR sX, Operand — Logical Bitwise XOR Register sX with Operand. . . . . . . . 120

Appendix D: Instruction Codes

Appendix E: Register and Scratchpad RAM Planning Worksheets

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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Introduction

Chapter 1

The PicoBlaze™ microcontroller is a compact, capable, and cost-effective fully embedded 8-bit RISC microcontroller core optimized for the Spartan FPGA families. The PicoBlaze microcontroller provides cost-efficient microcontrollerbased control and simple data processing.

The PicoBlaze microcontroller is optimized for efficiency and low deployment cost. It occupies just 96 FPGA slices, or only 12.5% of an XC3S50 FPGA and a miniscule 0.3% of an XC3S5000 FPGA. In typical implementations, a single FPGA block RAM stores up to 1024 program instructions, which are automatically loaded during FPGA configuration. Even with such resource efficiency, the PicoBlaze microcontroller performs a respectable 44 to 100 million instructions per second (MIPS) depending on the target FPGA family and speed grade.

The PicoBlaze microcontroller core is totally embedded within the target FPGA and requires no external resources. The PicoBlaze microcontroller is extremely flexible. The basic functionality is easily extended and enhanced by connecting additional FPGA logic to the microcontroller’s input and output ports.

The PicoBlaze microcontroller provides abundant, flexible I/O at much lower cost than off-the-shelf controllers. Similarly, the PicoBlaze peripheral set can be customized to meet the specific features, function, and cost requirements of the target application. Because the PicoBlaze microcontroller is delivered as synthesizable VHDL source code, the core is future-proof and can be migrated to future FPGA architectures, effectively eliminating product obsolescence fears. Being integrated within the FPGA, the PicoBlaze microcontroller reduces board space, design cost, and inventory.

The PicoBlaze FPC is supported by a suite of development tools including an assembler, a graphical integrated development environment (IDE), a graphical instruction set simulator, and VHDL source code and simulation models. Similarly, the PicoBlaze microcontroller is also supported in the Xilinx System Generator development environment.

-3, Virtex®-II, and Virtex-II Pro

The various PicoBlaze code examples throughout this application note are written for the Xilinx KCPSM3 assembler. The Mediatronix pBlazIDE assembler has a code import function that reads the KCPSM3 syntax.

PicoBlaze Microcontroller Features

As shown in the block diagram in Figure 1-1, the PicoBlaze microcontroller supports the following features:

• 16 byte-wide general-purpose data registers

• 1K instructions of programmable on-chip program store, automatically loaded during

FPGA configuration

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Chapter 1: Introduction

s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 sA sB

sC sD sE sF

Zero

Carry

OUT_PORT

PORT_ID

IN_PORT

64-Byte

Scratchpad RAM

Instruction

Decoder

1Kx18

Instruction

PROM

INTERRUPT

16 Byte-Wide Registers

ALU

Operand 1

Operand 2

Enable

Flags

Constants

UG129_c1_01_051204

Program Counter

(PC)

31x10

CALL/RETURN

Stack

• Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags

• 64-byte internal scratchpad RAM

• 256 input and 256 output ports for easy expansion and enhancement

• Automatic 31-location CALL/RETURN stack

• Predictable performance, always two clock cycles per instruction, up to 200 MHz or

100 MIPS in a Virtex-II Pro FPGA

• Fast interrupt response; worst-case 5 clock cycles

• Optimized for Xilinx Spartan-3, Virtex-II, and Virtex-II Pro FPGA architectures—just

96 slices and 0.5 to 1 block RAM

• Assembler, instruction-set simulator support

Figure 1-1: PicoBlaze Embedded Microcontroller Block Diagram

PicoBlaze Microcontroller Functional Blocks

General-Purpose Registers

The PicoBlaze microcontroller includes 16 byte-wide general-purpose registers, designated as registers s0 through sF. For better program clarity, registers can be renamed using an assembler directive. All register operations are completely interchangeable; no registers are reserved for special tasks or have priority over any other register. There is no dedicated accumulator; each result is computed in a specified register.

1,024-Instruction Program Store

The PicoBlaze microcontroller executes up to 1,024 instructions from memory within the FPGA, typically from a single block RAM. Each PicoBlaze instruction is 18 bits wide. The instructions are compiled within the FPGA design and automatically loaded during the FPGA configuration process.

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PicoBlaze Microcontroller Functional Blocks

Other memory organizations are possible to accommodate more PicoBlaze controllers within a single FPGA or to enable interactive code updates without recompiling the FPGA design. See Chapter 7, “Instruction Storage Configurations,” for more information.

Arithmetic Logic Unit (ALU)

The byte-wide Arithmetic Logic Unit (ALU) performs all microcontroller calculations, including:

• basic arithmetic operations such as addition and subtraction

• bitwise logic operations such as AND, OR, and XOR

• arithmetic compare and bitwise test operations

• comprehensive shift and rotate operations

All operations are performed using an operand provided by any specified register (sX). The result is returned to the same specified register (sX). If an instruction requires a second operand, then the second operand is either a second register (sY) or an 8-bit immediate constant (kk).

Flags

ALU operations affect the ZERO and CARRY flags. The ZERO flag indicates when the result of the last operation resulted in zero. The CARRY flag indicates various conditions, depending on the last instruction executed.

The INTERRUPT_ENABLE flag enables the INTERRUPT input.

64-Byte Scratchpad RAM

The PicoBlaze microcontroller provides an internal general-purpose 64-byte scratchpad RAM, directly or indirectly addressable from the register file using the STORE and FETCH instructions.

The STORE instruction writes the contents of any of the 16 registers to any of the 64 RAM locations. The complementary FETCH instruction reads any of the 64 memory locations into any of the 16 registers. This allows a much greater number of variables to be held within the boundary of the processor and tends to reserve all of the I/O space for real inputs and output signals.

The six-bit scratchpad RAM address is specified either directly (ss) with an immediate constant, or indirectly using the contents of any of the 16 registers (sY). Only the lower six bits of the address are used; the address should not exceed the 00 - 3F range of the available memory.

Input/Output

The Input/Output ports extend the PicoBlaze microcontroller’s capabilities and allow the microcontroller to connect to a custom peripheral set or to other FPGA logic. The PicoBlaze microcontroller supports up to 256 input ports and 256 output ports or a combination of input/output ports. The PORT_ID output provides the port address. During an INPUT operation, the PicoBlaze microcontroller reads data from the IN_PORT port to a specified register, sX. During an OUTPUT operation, the PicoBlaze microcontroller writes the contents of a specified register, sX, to the OUT_PORT port.

See Chapter 6, “Input and Output Ports,” for more information.

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Program Counter (PC)

The Program Counter (PC) points to the next instruction to be executed. By default, the PC automatically increments to the next instruction location when executing an instruction. Only the JUMP, CALL, RETURN, and RETURNI instructions and the Interrupt and Reset Events modify the default behavior. The PC cannot be directly modified by the application code; computed jump instructions are not supported.

The 10-bit PC supports a maximum code space of 1,024 instructions (000 to 3FF hex). If the PC reaches the top of the memory at 3FF hex, it rolls over to location 000.

Program Flow Control

The default execution sequence of the program can be modified using conditional and non-conditional program flow control instructions.

The JUMP instructions specify an absolute address anywhere in the 1,024-instruction program space.

CALL and RETURN instructions provide subroutine facilities for commonly used sections of code. A CALL instruction specifies the absolute start address of a subroutine, while the return address is automatically preserved on the CALL/RETURN stack.

Chapter 1: Introduction

If the interrupt input is enabled, an Interrupt Event also preserves the address of the preempted instruction on the CALL/RETURN stack while the PC is loaded with the interrupt vector, 3FF hex. Use the RETURNI instruction instead of the RETURN instruction to return from the interrupt service routine (ISR).

CALL/RETURN Stack

The CALL/RETURN hardware stack stores up to 31 instruction addresses, enabling nested CALL sequences up to 31 levels deep. Since the stack is also used during an interrupt operation, at least one of these levels should be reserved when interrupts are enabled.

The stack is implemented as a separate cyclic buffer. When the stack is full, it overwrites the oldest value. Consequently, there are no instructions to control the stack or the stack pointer. No program memory is required for the stack.

Interrupts

The PicoBlaze microcontroller has an optional INTERRUPT input, allowing the PicoBlaze microcontroller to handle asynchronous external events. In this context, “asynchronous” relates to interrupts occuring at any time during an instruction cycle. However, recommended design practice is to synchronize all inputs to the PicoBlaze controller using the clock input.

The PicoBlaze microcontroller responds to interrupts quickly in just five clock cycles.

See Chapter 4, “Interrupts,” for more information.

Reset

The PicoBlaze microcontroller is automatically reset immediately after the FPGA configuration process completes. After configuration, the RESET input forces the processor into the initial state. The PC is reset to address 0, the flags are cleared, interrupts are disabled, and the CALL/RETURN stack is reset.

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Why the PicoBlaze Microcontroller?

The data registers and scratchpad RAM are not affected by Reset.

See “RESET Event” in Appendix C for more information.

Why the PicoBlaze Microcontroller?

There are literally dozens of 8-bit microcontroller architectures and instruction sets. Modern FPGAs can efficiently implement practically any 8-bit microcontroller, and available FPGA soft cores support popular instruction sets such as the PIC, 8051, AVR, 6502, 8080, and Z80 microcontrollers. Why use the PicoBlaze microcontroller instead of a more popular instruction set?

The PicoBlaze microcontroller is specifically designed and optimized for the Spartan-3, Virtex-II, and Virtex-II Pro FPGA architectures. Its compact yet capable architecture consumes considerably less FPGA resources than comparable 8-bit microcontroller architectures within an FPGA. Furthermore, the PicoBlaze microcontroller is provided as a free, source-level VHDL file with royalty-free re-use within Xilinx FPGAs.

Some standalone microcontroller variants have a notorious reputation for becoming obsolete. Because it is delivered as VHDL source, the PicoBlaze microcontroller is immune to product obsolescence as the microcontroller can be retargeted to future generations of Xilinx FPGAs, exploiting future cost reductions and feature enhancements. Furthermore, the PicoBlaze microcontroller is expandable and extendable.

Before the advent of the PicoBlaze and MicroBlaze™ embedded processors, the microcontroller resided externally to the FPGA, limiting the connectivity to other FPGA functions and restricting overall interface performance. By contrast, the PicoBlaze microcontroller is fully embedded in the FPGA with flexible, extensive on-chip connectivity to other FPGA resources. Signals remain within the FPGA, improving overall performance. The PicoBlaze microcontroller reduces system cost because it is a single-chip solution, integrated within the FPGA and sometimes only occupying leftover FPGA resources.

The PicoBlaze microcontroller is resource efficient. Consequently, complex applications are sometimes best portioned across multiple PicoBlaze microcontrollers with each controller implementing a particular function, for example, keyboard and display control, or system management.

Why Use a Microcontroller within an FPGA?

Microcontrollers and FPGAs both successfully implement practically any digital logic function. However, each has unique advantages in cost, performance, and ease of use. Microcontrollers are well suited to control applications, especially with widely changing requirements. The FPGA resources required to implement the microcontroller are relatively constant. The same FPGA logic is re-used by the various microcontroller instructions, conserving resources. The program memory requirements grow with increasing complexity.

Programming control sequences or state machines in assembly code is often easier than creating similar structures in FPGA logic.

Microcontrollers are typically limited by performance. Each instruction executes sequentially. As an application increases in complexity, the number of instructions required to implement the application grows and system performance decreases accordingly. By contrast, performance in an FPGA is more flexible. For example, an algorithm can be implemented sequentially or completely in parallel, depending on the

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Chapter 1: Introduction

performance requirements. A completely parallel implementation is faster but consumes more FPGA resources.

A microcontroller embedded within the FPGA provides the best of both worlds. The microcontroller implements non-timing crucial complex control functions while timingcritical or data path functions are best implemented using FPGA logic. For example, a microcontroller cannot respond to events much faster than a few microseconds. The FPGA logic can respond to multiple, simultaneous events in just a few to tens of nanoseconds. Conversely, a microcontroller is cost-effective and simple for performing format or protocol conversions.

Table 1-1: PicoBlaze Microcontroller Embedded within an FPGA Provides the Optimal Balance between Microcontroller and FPGA Solutions

PicoBlaze Microcontroller FPGA Logic

Strengths

Weaknesses

• Easy to program, excellent for control and state machine applications

• Resource requirements remain constant with increasing complexity

• Re-uses logic resources, excellent for lower-performance functions

• Executes sequentially

• Performance degrades with increasing

complexity

• Program memory requirements increase with increasing complexity

• Slower response to simultaneous inputs

• Significantly higher performance

• Excellent at parallel operations

• Sequential vs. parallel implementation

trade-offs optimize performance or cost

• Fast response to multiple, simultaneous inputs

• Control and state machine applications more difficult to program

• Logic resources grow with increasing complexity

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PicoBlaze Interface Signals

INTERRUPT_ACK

WRITE_STROBE

READ_STROBE

PORT_ID[7:0]

OUT_PORT[7:0]IN_PORT[7:0]

INTERRUPT

RESET

CLK

PicoBlaze Microcontroller

UG129_c2_01_052004

The top-level interface signals to the PicoBlaze™ microcontroller appear in Figure 2-1 and are described in Table 2 -1 . Figure 7-1 provides additional detail on the internal structure of the PicoBlaze controller.

Chapter 2

Table 2-1: PicoBlaze Interface Signal Descriptions

IN_PORT[7:0] Input Input Data Port: Present valid input data on this port during an INPUT

INTERRUPT Input Interrupt Input: If the INTERRUPT_ENABLE flag is set by the application

RESET Input Reset Input: To reset the PicoBlaze microcontroller and to generate a RESET

CLK Input Clock Input: The frequency may range from DC to the maximum operating

OUT_PORT[7:0] Output Output Data Port: Output data appears on this port for two CLK cycles during

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Figure 2-1: PicoBlaze Interface Connections

Signal Direction Description

instruction. The data is captured on the rising edge of CLK.

code, generate an INTERRUPT Event by asserting this input High for at least two CLK cycles. If the INTERRUPT_ENABLE flag is cleared, this input is ignored.

Event, assert this input High for at least one CLK cycle. A Reset Event is automatically generated immediately following FPGA configuration.

frequency reported by the Xilinx ISE synchronous elements are clocked from the rising clock edge. There are no clock duty-cycle requirements beyond the minimum pulse width requirements of the FPGA.

an OUTPUT instruction. Capture output data within the FPGA at the rising CLK edge when WRITE_STROBE is High.

development software. All PicoBlaze

Chapter 2: PicoBlaze Interface Signals

Table 2-1: PicoBlaze Interface Signal Descriptions (Continued)

Signal Direction Description

PORT_ID[7:0] Output Port Address: The I/O port address appears on this port for two CLK cycles

during an INPUT or OUTPUT instruction.

READ_STROBE Output Read Strobe: When asserted High, this signal indicates that input data on the

IN_PORT[7:0] port was captured to the specified data register during an INPUT instruction. This signal is asserted on the second CLK cycle of the twocycle INPUT instruction. This signal is typically used to acknowledge read operations from FIFOs.

WRITE_STROBE Output Write Strobe: When asserted High, this signal validates the output data on the

OUT_PORT[7:0] port during an OUTPUT instruction. This signal is asserted on the second CLK cycle of the two-cycle OUTPUT instruction. Capture output data within the FPGA on the rising CLK edge when WRITE_STROBE is High.

INTERRUPT_ACK Output Interrupt Acknowledge: When asserted High, this signal acknowledges that

an INTERRUPT Event occurred. This signal is asserted during the second CLK cycle of the two-cycle INTERRUPT Event. This signal is optionally used to clear the source of the INTERRUPT input.

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Chapter 3

PicoBlaze Instruction Set

Ta bl e 3 -1 summarizes the entire PicoBlaze™ processor instruction set, which appears

alphabetically. Instructions are listed using the KCPSM3 syntax. If different, the pBlazIDE syntax appears in parentheses. Each instruction includes an overview description, a functional description, and how the ZERO and CARRY flags are affected. For more details on each instruction, see Appendix C, “PicoBlaze Instruction Set and Event Reference.”

Table 3-1: PicoBlaze Instruction Set (alphabetical listing)

Instruction Description Function ZERO CARRY

ADD sX, kk Add register sX with literal kk sX Å sX + kk ? ?

ADD sX, sY Add register sX with register sY sX Å sX + sY ? ?

ADDCY sX, kk (ADDC)

ADDCY sX, sY (ADDC)

AND sX, kk Bitwise AND register sX with literal kk sX Å sX AND kk ? 0

AND sX, sY Bitwise AND register sX with register sY sX Å sX AND sY ? 0

CALL aaa Unconditionally call subroutine at aaa TOS Å PC

CALL C, aaa If CARRY flag set, call subroutine at aaa If CARRY=1, {TOS Å PC,

CALL NC, aaa If CARRY flag not set, call subroutine at

CALL NZ, aaa If ZERO flag not set, call subroutine at aaa If ZERO=0, {TOS Å PC,

CALL Z, aaa If ZERO flag set, call subroutine at aaa If ZERO=1, {TOS Å PC,

COMPARE sX, kk (COMP)

COMPARE sX, sY (COMP)

Add register sX with literal kk with CARRY bit

Add register sX with register sY with CARRY bit

aaa

Compare register sX with literal kk. Set CARRY and ZERO flags as appropriate. Registers are unaffected.

Compare register sX with register sY. Set CARRY and ZERO flags as appropriate. Registers are unaffected.

sX Å sX + kk + CARRY ? ?

sX Å sX + sY + CARRY ? ?

PC Å aaa

PC Å aaa}

If CARRY=0, {TOS Å PC, PC Å aaa}

PC Å aaa}

If sX=kk, ZERO Å 1

If sX<kk, CARRY Å

If sX=sY, ZERO Å 1

If sX<sY, CARRY Å 1

DISABLE INTERRUPT (DINT)

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Disable interrupt input INTERRUPT_ENABLE Å 0--

Table 3-1: PicoBlaze Instruction Set (alphabetical listing)

Instruction Description Function ZERO CARRY

Chapter 3: PicoBlaze Instruction Set

ENABLE INTERRUPT

Enable interrupt input INTERRUPT_ENABLE Å 1--

(EINT)

Interrupt Event Asynchronous interrupt input. Preserve

flags and PC. Clear INTERRUPT_ENABLE flag. Jump to interrupt vector at address 3FF.

Preserved ZERO Å ZERO

Preserved CARRY Å CARRY

INTERRUPT_ENABLE Å 0

TOS Å PC

PC Å 3FF

FETCH sX, (sY) (FETCH sX, sY)

FETCH sX, ss Read scratchpad RAM location ss into

Read scratchpad RAM location pointed to by register sY into register sX

sX Å RAM[(sY)] - -

sX Å RAM[ss] - -

INPUT sX, (sY) (IN sX, sY)

INPUT sX, pp

(IN)

Read value on input port location pointed to by register sY into register sX

Read value on input port location pp into register sX

PORT_ID Å sY

sX Å IN_PORT

PORT_ID Å pp

sX Å IN_PORT

JUMP aaa Unconditionally jump to aaa PC Å aaa - -

JUMP C, aaa If CARRY flag set, jump to aaa If CARRY=1, PC Å aaa - -

JUMP NC, aaa If CARRY flag not set, jump to aaa If CARRY=0, PC Å aaa - -

JUMP NZ, aaa If ZERO flag not set, jump to aaa If ZERO=0, PC Å aaa - -

JUMP Z, aaa If ZERO flag set, jump to aaa If ZERO=1, PC Å aaa - -

LOAD sX, kk Load register sX with literal kk sX Å kk - -

LOAD sX, sY Load register sX with register sY sX Å sY - -

OR sX, kk Bitwise OR register sX with literal kk sX Å

sX OR kk ? 0

OR sX, sY Bitwise OR register sX with register sY sX Å sX OR sY ? 0

OUTPUT sX, (sY) (OUT sX, sY)

OUTPUT sX, pp (OUT sX, pp)

RETURN

Write register sX to output port location pointed to by register sY

Write register sX to output port location ppPORT_ID Å pp

PORT_ID Å sY

OUT_PORT Å sX

Unconditionally return from subroutine PC Å TOS+1 - -

(RET)

RETURN C

If CARRY flag set, return from subroutine If CARRY=1, PC Å TOS+1 - -

(RET C)

RETURN NC (RET NC)

RETURN NZ (RET NZ)

RETURN Z

If CARRY flag not set, return from

If CARRY=0, PC Å TOS+1 - -

subroutine

If ZERO flag not set, return from

If ZERO=0, PC Å TOS+1 - -

subroutine

If ZERO flag set, return from subroutine If ZERO=1, PC Å TOS+1 - -

(RET Z)

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Table 3-1: PicoBlaze Instruction Set (alphabetical listing)

Instruction Description Function ZERO CARRY

RETURNI DISABLE (RETI DISABLE)

Return from interrupt service routine. Interrupt remains disabled.

PC Å TOS

ZERO Å Preserved ZERO

CARRY Å Preserved CARRY

INTERRUPT_ENABLE Å 0

RETURNI ENABLE (RETI ENABLE)

Return from interrupt service routine. Re-enable interrupt.

PC Å TOS

ZERO Å Preserved ZERO

CARRY Å Preserved CARRY

INTERRUPT_ENABLE Å 1

RL sX Rotate register sX left sX Å {sX[6:0],sX[7]}

CARRY Å sX[7]

RR sX Rotate register sX right sX Å {sX[0],sX[7:1]}

CARRY Å sX[0]

SL0 sX Shift register sX left, zero fill sX Å {sX[6:0],0}

CARRY Å sX[7]

SL1 sX Shift register sX left, one fill sX Å {sX[6:0],1}

CARRY Å sX[7]

SLA sX Shift register sX left through all bits,

including CARRY

SLX sX Shift register sX left. Bit sX[0] is

unaffected.

sX Å {sX[6:0],CARRY}

CARRY Å sX[7]

sX Å {sX[6:0],sX[0]}

CARRY Å sX[7]

SR0 sX Shift register sX right, zero fill sX Å {0,sX[7:1]}

CARRY Å sX[0]

SR1 sX Shift register sX right, one fill sX Å {1,sX[7:1]}

CARRY Å sX[0]

SRA sX Shift register sX right through all bits,

including CARRY

SRX sX Arithmetic shift register sX right. Sign

extend sX. Bit sX[7] Is unaffected.

STORE sX, (sY) (STORE sX, sY)

Write register sX to scratchpad RAM location pointed to by register sY

STORE sX, ss Write register sX to scratchpad RAM

sX Å {CARRY,sX[7:1]}

CARRY Å sX[0]

sX Å {sX[7],sX[7:1]}

CARRY Å sX[0]

RAM[(sY)] Å sX - -

RAM[ss] Å sX - -

location ss

SUB sX, kk Subtract literal kk from register sX sX Å sX – kk ? ?

SUB sX, sY Subtract register sY from register sX sX Å sX – sY ? ?

SUBCY sX, kk (SUBC)

SUBCY sX, sY (SUBC)

Subtract literal kk from register sX with CARRY (borrow)

Subtract register sY from register sX with CARRY (borrow)

sX Å sX – kk - CARRY ? ?

sX Å sX – sY - CARRY ? ?

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UG129 (v1.1.2) June 24, 2008

Table 3-1: PicoBlaze Instruction Set (alphabetical listing)

Instruction Description Function ZERO CARRY

Chapter 3: PicoBlaze Instruction Set

TEST sX, kk Test bits in register sX against literal kk.

Update CARRY and ZERO flags. Registers are unaffected.

TEST sX, sY Test bits in register sX against register sX.

Update CARRY and ZERO flags. Registers are unaffected.

XOR sX, kk Bitwise XOR register sX with literal kk sX Å sX XOR kk ? 0

XOR sX, sY Bitwise XOR register sX with register sY sX Å sX XOR sY ? 0

sX = One of 16 possible register locations ranging from s0 through sF or specified as a literal

sY = One of 16 possible register locations ranging from s0 through sF or specified as a literal

aaa = 10-bit address, specified either as a literal or a three-digit hexadecimal value ranging from 000 to 3FF or a labeled

location

kk = 8-bit immediate constant, specified either as a literal or a two-digit hexadecimal value ranging from 00 to FF or

specified as a literal

pp = 8-bit port address, specified either as a literal or a two-digit hexadecimal value ranging from 00 to FF or specified

as a literal

ss = 6-bit scratchpad RAM address, specified either as a literal or a two-digit hexadecimal value ranging from 00 to 3F

or specified as a literal

If (sX AND kk) = 0, ZERO Å 1

CARRY Å odd parity of (sX AND kk)

If (sX AND sY) = 0, ZERO Å 1

CARRY Å odd parity of (sX AND kk)

RAM[n] = Contents of scratchpad RAM at location n

TOS = Value stored at Top Of Stack

Address Spaces

As shown in Tab le 3 -2 , the PicoBlaze microcontroller has five distinct address spaces. Specific instructions operate on each of the address spaces.

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UG129 (v1.1.2) June 24, 2008

Address Spaces

Table 3-2: PicoBlaze Address Spaces and Related Instructions

Address Space

Size

(Depth x Width)

Addressing

Modes

Instruction 1Kx18 Direct • JUMP

• CALL

• RETURN

• RETURNI

• INTERRUPT event

• RESET event

All others increment the PC to the next location

• AND

• OR

• XOR

• TEST (read only)

• ADD

• ADDCY

• SUB

• SUBCY

• COMPARE (read only)

• SR0

• SR1

• SRX

• SRA

• RR

• SL0

• SL1

• SLX

• SLA

• RL

• INPUT

• OUTPUT (read only)

• STORE (read only)

• FETCH

Instructions that Operate on

Address Space

Scratchpad RAM 64x8 Direct

Indirect

I/O 256x8 Direct

Indirect

• STORE

• FETCH

• INPUT

• OUTPUT

CALL/RETURN Stack 31x10 N/A • CALL

• Enabled INTERRUPT event

• RETURN

• RETURNI

• RESET event

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UG129 (v1.1.2) June 24, 2008

Processing Data

AND sX, sY AND sX, kk

7 6 5 4 3 2 1 0

Literal kk

UG129_c3_01_051204

All data processing instructions operate on any of the 16 general-purpose registers. Only the data processing instructions modify the ZERO or CARRY flags as appropriate for the instruction. The data processing instructions consists of the following types:

• Logic instructions

• Arithmetic instructions

• Test and Compare instructions

• Shift and Rotate instructions

Logic Instructions

The logic instructions perform a bitwise logical AND, OR, or XOR between two operands. The first operand is a register location. The second operand is either a register location or a literal constant. Besides performing pure AND, OR, and XOR operations, the logic instructions provide a means to:

• complement or invert a register

• clear a register

• set or clear specific bits within a register

Chapter 3: PicoBlaze Instruction Set

Bitwise AND, OR, XOR

All logic instructions are bitwise operations. The AND operation, illustrated in Figure 3-1, shows that corresponding bit locations in both operands are logically ANDed together and the result is placed back into register sX. If the resulting value in register sX is zero, then the ZERO flag is set. The CARRY flag is always cleared by a logic instruction.

Figure 3-1: Bitwise AND Instruction

The OR and XOR instructions are similar to the AND instruction illustrated in Figure 3-1 except that they perform an OR or XOR logical operation, respectively.

Arithmetic Instructions

The PicoBlaze microcontroller provides basic byte-wide addition and subtraction instructions. Combinations of instructions perform multi-byte arithmetic plus multiplication and division operations. If the end application requires significant arithmetic performance, consider using the 32-bit MicroBlaze RISC processor core for Xilinx FPGAs (see Reference 4).

ADD and ADDCY Add Instructions

The PicoBlaze microcontroller provides two add instructions, ADD and ADDCY, that compute the sum of two 8-bit operands, either without or with CARRY, respectively. The first operand is a register location. The second operand is either a register location or a literal constant. The resulting operation affects both the CARRY and ZERO flags. If the resulting sum is greater than 255, then the CARRY flag is set. If the resulting sum is either 0 or 256 (register sX is zero with CARRY set), then the ZERO flag is set.

The ADDCY instruction is an add operation with carry. If the CARRY flag is set, then ADDCY adds an additional one to the resulting sum.

The ADDCY instruction is commonly used in multi-byte addition. Figure 3-8 demonstrates a subroutine that adds two 16-bit integers and produces a 16-bit result. The upper byte of each 16-bit value is labeled as MSB for most-significant byte; the lower byte of each 16-bit value is labeled LSB for least-significant byte.

Figure 3-7: Clearing a Bit Location

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UG129 (v1.1.2) June 24, 2008

Processing Data

ADD16: NAMEREG s0, a_lsb ; rename register s0 as “a_lsb” NAMEREG s1, a_msb ; rename register s1 as “a_msb” NAMEREG s2, b_lsb ; rename register s2 as “b_lsb” NAMEREG s3, b_msb ; rename register s3 as “b_lsb”

ADD a_lsb, b_lsb ; add LSBs, keep result in a_lsb ADDCY a_msb, b_msb ; add MSBs, keep result in a_msb RETURN

SUB16: NAMEREG s0, a_lsb ; rename register s0 as “a_lsb” NAMEREG s1, a_msb ; rename register s1 as “a_msb” NAMEREG s2, b_lsb ; rename register s2 as “b_lsb” NAMEREG s3, b_msb ; rename register s3 as “b_lsb”

SUB a_lsb, b_lsb ; subtract LSBs, keep result in a_lsb SUBCY a_msb, b_msb ; subtract MSBs, keep result in a_msb RETURN

Figure 3-8: 16-Bit Addition Using ADD and ADDCY Instructions

Multiplication

The PicoBlaze microcontroller core does not have a dedicated hardware multiplier. However, the PicoBlaze microcontroller performs multiplication using the available arithmetic and shift instructions. Figure 3-14 demonstrates an 8-bit by 8-bit multiply routine that produces a 16-bit multiplier product in 50 to 57 instruction cycles, or 100 to 114

28 www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller

clock cycles. By contrast, the 8051 microcontroller performs the same multiplication in eight instruction cycles or 96 clock cycles on a the standard 12-cycle 8051.

Value

UG129 (v1.1.2) June 24, 2008

Processing Data

; Multiplier Routine (8-bit x 8-bit = 16-bit product) ; ================================================== ; Shift and add algorithm ;

mult_8x8: NAMEREG s0, multiplicand

; preserved

NAMEREG s1, multiplier ; preserved NAMEREG s2, bit_mask ; modified NAMEREG s3, result_msb ;

most-significant byte (MSB) of result,

; modified

NAMEREG s4, result_lsb ; least-significant byte (LSB) of result,

; modified

;

LOAD bit_mask, 01 ; start with least-significant bit (lsb) LOAD result_msb, 00 ; clear product MSB LOAD result_lsb, 00 ; clear product LSB (not required) ;

; loop through all bits in multiplier

mult_loop: TEST multiplier, bit_mask ; check if bit is set JUMP Z, no_add ; if bit is not set, skip addition ; ADD result_msb, multiplicand ; addition only occurs in MSB ; no_add: SRA result_msb ; shift MSB right, CARRY into bit 7,

; lsb into CARRY

SRA result_lsb ; shift LSB right,

; lsb from result_msb into bit 7 ; SL0 bit_mask ; shift bit_mask left to examine

; next bit in multiplier ; JUMP NZ, mult_loop ; if all bit examined, then bit_mask = 0,

; loop if not 0 RETURN ; multiplier result now available in

; result_msb and result_lsb

If reading this document in Adobe Acrobat, use the Select Text tool to select code snippets, then copy and paste the text into your text editor.

PicoBlaze 8-bit Embedded Microcontroller www.xilinx.com 29

UG129 (v1.1.2) June 24, 2008

If multiplication performance is important to the application, connect one of the FPGA’s 18x18 hardware multipliers the PicoBlaze I/O ports, as shown in Figure 3-15. The hardware multiplier computes the 16-bit result in less than one instruction cycle.

Figure 3-16 shows the routine required to multiply two 8-bit values using the hardware

multiplier. This same technique can be expanded to multiply two 16-bit values to produce a 32-bit result. This example also illustrates how to use FPGA logic attached to the PicoBlaze microcontroller to accelerate algorithms.

Figure 3-14: 8-bit by 8-bit Multiply Routine Produces a 16-bit Product

Chapter 3: PicoBlaze Instruction Set

IN_PORT[7:0] OUT_PORT[7:0]

PORT_ID[7:0]

READ_STROBE

WRITE_STROBE

PicoBlaze Microcontroller

[0]

A[7:0]

A[17:8]

B[7:0]

B[17:8]

P[7:0]

P[15:8]

18x18 Multiplier

SEL

UG129_c3_02_052004

; Multiplier Routine (8-bit x 8-bit = 16-bit product) ; =================================================== ; Connects to embedded 18x18 Hardware Multiplier via ports ;

mult_8x8io: NAMEREG s0, multiplicand ; preserved NAMEREG s1, multiplier ; preserved NAMEREG s3, result_msb ; most-significant byte (MSB) of result, modified NAMEREG s4, result_lsb ;

least-significant byte (LSB) of result, modified ; ; Define the port ID numbers as constants for better clarity

CONSTANT multiplier_lsb, 00 CONSTANT multiplier_msb, 01

; ;

Output multiplicand and multiplier to FPGA registers connected to the inputs of

; the embedded multiplier.

OUTPUT multiplicand, multiplier_lsb OUTPUT multiplier, multiplier_msb

; ; Input the resulting product from the embedded multiplier.

INPUT result_lsb, multiplier_lsb INPUT result_msb, multiplier_msb

; RETURN ; multiplier result now available in result_msb

; and result_lsb

Figure 3-15: 8-bit by 8-bit Hardware Multiplier Using the FPGA’s 18x18 Multipliers

30 www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller

Division

The PicoBlaze microcontroller core does not have a dedicated hardware divider. However, the PicoBlaze microcontroller performs division using the available arithmetic and shift instructions. Figure 3-17 demonstrates a subroutine that divides an unsigned 8-bit number by another unsigned 8-bit number to produce an 8-bit quotient and an 8-bit remainder in 60 to 74 instruction cycles, or 120 to 144 clock cycles.

Figure 3-16: 8-bit by 8-bit Multiply Routine Using Hardware Multiplier

UG129 (v1.1.2) June 24, 2008

+ 94 hidden pages

Xilinx UG129 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Limitations

Limited Warranty and Disclaimer

Limitation of Liability

Technical Support Limitations

Acknowledgments

Guide Contents

About This Guide

Table of Contents

Introduction

PicoBlaze Microcontroller Features

PicoBlaze Microcontroller Functional Blocks

General-Purpose Registers

1,024-Instruction Program Store

Arithmetic Logic Unit (ALU)

Flags

64-Byte Scratchpad RAM

Input/Output

Program Counter (PC)

Program Flow Control

CALL/RETURN Stack

Interrupts

Reset

Why the PicoBlaze Microcontroller?

Why Use a Microcontroller within an FPGA?

PicoBlaze Interface Signals

PicoBlaze Instruction Set

Address Spaces

Processing Data

Logic Instructions

Arithmetic Instructions

Multiplication

Division