Xilinx UG078 User Manual
Virtex-4 LX/SX
Prototype Platform
User Guide
UG078 (v1.2) May 24, 2006
P/N 0402226-06
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Revision History
The following table shows the revision history for this document.
Date Version Revision
08/30/04 1.0 Initial Xilinx release.
10/20/04 1.0.1 Minor corrections to text and figures.
06/09/05 1.0.2 Modified title from Virtex-4 Prototype Platform to Virtex-4 LX/SX Prototype Platform.
Updated figure titles and Table 8, Table 9, and Table 10.
06/27/05 1.0.3 Corrected clock names in Table 6 (pin W9) and Table 7 (pins H17, AJ17, and AK19).
05/05/06 1.1 Corrected title of Table 7.
05/24/06 1.2 Updated title of Table 5 and Table 7.
Added revision number to P/N on title page.
Virtex-4 LX/SX Prototype Platform www.xilinx.com UG078 (v1.2) May 24, 2006
Table of Contents
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Virtex-4 LX/SX Prototype Platform
Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CD-ROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1. Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. Power Supply Jacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Configuration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. JTAG Termination Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6a. Upstream System ACE Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6b. Downstream System ACE Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6c. Upstream Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6d. Downstream Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Prototyping Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8. VCCO-Enable Supply Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9. VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10. Oscillator Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11. Differential Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
12. DUT Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
13. Pin Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
14. User LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
15. PROGRAM Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
16. RESET Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
17. DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
18. INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
19. Platform Flash ISPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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About This Guide
This user guide describes the features and operation of the Virtex™-4 prototype platform
and describes how to configure chains of FPGAs and serial PROMs.
Guide Contents
This manual contains one chapter:
• “Virtex-4 LX/SX Prototype Platform”
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature/index.htm.
Preface
Conventions
Typographical
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
This document uses the following conventions. An example illustrates each convention.
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Messages, prompts, and
Courier font
Courier bold
Helvetica bold
program files that the system
displays
Literal commands that you enter
in a syntactical statement
Commands that you select from
a menu
Keyboard shortcuts Ctrl+C
speed grade: - 100
ngdbuild design_name
File → Open
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Preface: About This Guide
Italic font
Square brackets [ ]
Convention Meaning or Use Example
Variables in a syntax statement
for which you must supply
ngdbuild design_name
values
See the Development System
References to other manuals
Reference Guide for more
information.
If a wire is drawn so that it
Emphasis in text
overlaps the pin of a symbol, the
two nets are not connected.
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
ngdbuild [option_name]
design_name
required.
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Braces { }
Vertical bar |
Vertical ellipsis
Horizontal ellipsis . . .
Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Blue text
Red text
A list of items from which you
must choose one or more
Separates items in a list of
choices
lowpwr ={on|off}
lowpwr ={on|off}
IOB #1: Name = QOUT’
.
.
Repetitive material that has
been omitted
.
Repetitive material that has
been omitted
IOB #2: Name = CLKIN’
.
.
.
allow block block_name
loc1 loc2 ... locn;
See the section “Additional
Cross-reference link to a location
in the current document
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Cross-reference link to a location
in another document
See Figure 2-5 in the Virtex-II
Handbook.
Blue, underlined text
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Hyperlink to a website (URL)
Go to http://www.xilinx.com
for the latest speed files.
UG078 (v1.2) May 24, 2006
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Virtex-4 LX/SX Prototype Platform
Package Contents
• Xilinx Virtex™-4 prototype platform board
• User guide
• Device vacuum tool
• Headers for test points
• CD-ROM
• One low-voltage, 14-pin, dual-inline package (DIP) crystal oscillator
CD-ROM Contents
• User guide in PDF format
• Example designs
♦ These designs include the Verilog source code, user constraints files (*.ucf),
documentation in PDF, and a readme.txt file
• Bitstream files (*.bit) for each part type supported by the board (Bitstream synthesized
using Xilinx tools)
• Full schematics of the board in both PDF format and ViewDraw schematic format
• PC board layout in Pads PCB format
• Gerber files in *.pho and *.pdf for the PC board (There are many free or shareware
Gerber file viewers available on the Web for viewing and printing these files)
Introduction
The Virtex-4 prototype platform and demonstration boards allow designers to investigate
and experiment with the features of Virtex-4 series FPGAs. This user guide describes the
features and operation of the Virtex-4 prototype platform, including how to configure
chains of FPGAs and serial PROMs.
Note:
and are not intended for A/C characterization or high-speed I/O evaluation.
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Prototype platforms are intended strictly for evaluating the functionality of Virtex-4 features
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