Xilinx System Generator V2.1 Reference Manual

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Xilinx System Generator v2.1

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Introduction

Xilinx Blockset Overview

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System Generator Software Features

Using the Xilinx Software

Auxiliary Files

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User Guide Xilinx Blockset

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Xilinx System Generator v2.1 Reference Guide

About This Manual

This document is a reference guide for system designers who are unfamiliar with the System Generator v2.1 and the Xilinx Blockset.

Manual Contents

This guide covers the following topics:

• Chapter 1, Introduction, gives a high-level overview of the System Generator and

its uses.

• Chapter 2, Xilinx Blockset Overview, describes the Xilinx Blockset: how to

instantiate a Xilinx block within your Simulink model, how to conﬁgure it through its block parameters dialog box, the common options that can be used in several of the blocks, and the nature of the signals used in the System Generator software.

• Chapter 3,Xilinx Blocks, describes the details of each block, including options, and use of Xilinx LogiCOREs. This chapter also tells where to ﬁnd descriptions of the cores on your computer.

• Chapter 4, System Generator Software Features, describes the System Generator software and gives tips for using it to create efﬁcient hardware designs.

• Chapter 5, Using the Xilinx Software, tells, step-by-step, how to use System Generator as a front-end to the Xilinx Foundation 4.1i ISE software, from VHDL to bitstream generation.

• Chapter 6, Auxiliary Files, contains instructions for accessing System Generator demo designs, as well as a list of Perl scripts that are delivered with the System Generator software. The demo designs show examples of designs using Xilinx blocks. The scripts are used by the System Generator to create auxiliary project ﬁles, but can also be used as stand-alone tools.

2 Xilinx Development System

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some additional resources.

Resource Description/URL

IP Center Information on Xilinx LogiCOREs and IP solutions.

http://www.xilinx.com/ipcenter/

This page contains a link to the Xilinx Xtreme DSP solutions page.

Technical Tips Latest news, design tips, and patch information for the Xilinx design environment.

http://support.xilinx.com/xlnx/xil_tt_home.jsp

Tutorials Tutorials covering Xilinx ISE 4.1i design ﬂows, from design entry to veriﬁcation and

debugging.

http://support.xilinx.com/support/techsup/tutorials/ tutorials4.htm

Documentation Xilinx Software Manuals online.

http://toolbox.xilinx.com/docsan/xilinx4/

Software Updates

The MathWorks

Periodic software service packs, IP updates, and information is available online.

http://support.xilinx.com/support/software/install_info.htm

MATLAB , Simulink , DSP design, and other company information.

http://www.mathworks.com

Xilinx System Generator v2.1 Reference Guide

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following conventions are used for all System Generator documents.

• Courier font (a ﬁxed-width font) indicates messages, prompts, menu pick items, and dialog box entries that the system displays.

speed grade: - 100

• Courier bold indicates literal commands that you enter in a command-line prompt or dialog box. However, triangular braces “<>” in Courier bold are not literal.

>> cd <your $MATLAB home directory>

• Italic font denotes the following items.

♦ Introduction of words being used with a context-speciﬁc deﬁnition

The System Generator provides bit true and cycle true modeling.

♦ References to other manuals or sections in this manual

See the Development System Reference Guide for more information.

♦ Emphasis in text

If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

4 Xilinx Development System

Contents

Chapter 1 Introduction

Industry and Product Overview .................................................................................8

System Generator .....................................................................................................9

System Level Modeling with System Generator .......................................................9

The System Generator Design Flow .........................................................................10

Arithmetic Data Types ..............................................................................................12

Hardware Handshaking ............................................................................................13

Multirate Systems ................................................................................................13

Bit-True and Cycle-True Modeling ............................................................................14

Automatic Testbench Generation ........................................................................14

Chapter 2 Xilinx Blockset Overview

What is a Xilinx Block? .............................................................................................15

Instantiating Xilinx Blocks within a Simulink Model ...................................................16

The Block Parameters Dialog Box ............................................................................16

The Nature of Signals in the Xilinx Blockset .............................................................16

Use of Xilinx Smart-IP Cores by the System Generator ...........................................18

Licensed Cores ....................................................................................................18

Xilinx LogiCORE Versions ...................................................................................19

Common Options in Block Parameters Dialog Box ..................................................19

Arithmetic Type ....................................................................................................20

Implement with Xilinx Smart-IP Core (if possible) ...............................................20

Generate Core .....................................................................................................20

Latency ................................................................................................................20

Precision ..............................................................................................................21

Number of Bits .....................................................................................................21

Overflow and Quantization ..................................................................................21

Override with Doubles .........................................................................................21

Sample Period .....................................................................................................22

Chapter 3 Xilinx Blocks

Basic Elements .........................................................................................................23

System Generator ...............................................................................................23

Addressable Shift Register ..................................................................................26

Black Box .............................................................................................................28

Xilinx System Generator v2.1 Reference Guide

Concat .................................................................................................................30

Constant ..............................................................................................................31

Convert ................................................................................................................31

Counter ................................................................................................................32

Delay ...................................................................................................................35

Down Sample ......................................................................................................36

Get Valid Bit .........................................................................................................37

Mux ......................................................................................................................38

Parallel to Serial ..................................................................................................39

Register ...............................................................................................................40

Reinterpret ...........................................................................................................42

Serial to Parallel ..................................................................................................43

Set Valid Bit .........................................................................................................45

Slice .....................................................................................................................45

Sync .....................................................................................................................47

Up Sample ...........................................................................................................50

Communication .........................................................................................................52

Convolutional Encoder ........................................................................................52

Depuncture ..........................................................................................................54

Interleaver Deinterleaver .....................................................................................55

Puncture ..............................................................................................................58

RS Decoder .........................................................................................................59

RS Encoder .........................................................................................................63

Viterbi Decoder ....................................................................................................68

DSP ..........................................................................................................................70

CIC ......................................................................................................................70

DDS .....................................................................................................................73

FFT ......................................................................................................................75

FIR .......................................................................................................................79

Math ..........................................................................................................................81

Accumulator .........................................................................................................81

AddSub ................................................................................................................83

CMult ...................................................................................................................84

Inverter ................................................................................................................85

Logical .................................................................................................................86

Mult ......................................................................................................................88

Negate .................................................................................................................90

Relational .............................................................................................................90

Scale ....................................................................................................................92

Shift .....................................................................................................................92

SineCosine ..........................................................................................................93

Threshold .............................................................................................................95

MATLAB I/O ..............................................................................................................96

Gateway Blocks ...................................................................................................96

Enabled Subsystems ...........................................................................................96

Gateway In ...........................................................................................................97

6 Xilinx Development System

Gateway Out.........................................................................................................99

Quantization Error Blocks ....................................................................................101

Display .................................................................................................................101

Memory .....................................................................................................................102

Dual Port RAM .....................................................................................................102

FIFO ....................................................................................................................106

ROM ....................................................................................................................107

Single Port RAM ..................................................................................................110

State Machine ...........................................................................................................114

Mealy State Machine ...........................................................................................114

Moore State Machine ..........................................................................................116

Registered Mealy State Machine .........................................................................119

Registered Moore State Machine ........................................................................123

Chapter 4 System Generator Software Features

Using the System Generator installer .......................................................................127

Uninstalling previous System Generator directories ............................................127

Installed System Generator directory ..................................................................128

Using Black Boxes ....................................................................................................128

Example model ....................................................................................................128

Black Box window ................................................................................................129

Use of mixed language projects ...............................................................................130

Incorporating mixed language black boxes .........................................................130

Tips for creating a high performance design ............................................................132

Using the System Generator Constraints Files..........................................................133

System Clock Period............................................................................................133

Multicycle Path Constraints..................................................................................133

IOB Timing and Placement Constraints ...............................................................134

Example for showing constraints use...................................................................134

Important Issues...................................................................................................136

Files automatically created by System Generator ....................................................137

Chapter 5 Using the Xilinx Software

Xilinx ISE 4.1i Project Navigator ...............................................................................139

Opening a System Generator project ..................................................................139

Customizing your System Generator project .......................................................139

Implementing your design ...................................................................................140

Simulating using ModelSim within the Project Navigator ....................................141

Using an EDIF software flow ....................................................................................143

Simulation .................................................................................................................143

Compiling your IP ................................................................................................143

Associating ModelSim with ISE 4.1i Project Navigator ........................................144

Xilinx software tools resources .................................................................................145

Chapter 6 Auxiliary Files

Demonstration designs..............................................................................................146

Perl scripts.................................................................................................................147

Xilinx System Generator v2.1 Reference Guide

Introduction

This chapter describes the basic concepts and tools of the System Generator v2.1. This chapter contains the following sections.

• Industry and Product Overview

• System Generator

• System Level Modeling with System Generator

• The System Generator Design Flow

• Arithmetic Data Types

• Hardware Handshaking

Chapter 1

• Bit-true and Cycle-true Modeling

Industry and Product Overview

In recent years, ﬁeld-programmable gate arrays (FPGAs) have become key components in implementing high performance digital signal processing (DSP) systems, especially in the areas of digital communications, networking, video, and imaging. The logic fabric of today's FPGAs consists not only of look-up tables, registers, multiplexers, distributed and block memory, but also dedicated circuitry for fast adders, multipliers, and I/O processing (e.g., giga-bit I/O). The memory bandwidth of a modern FPGA far exceeds that of a microprocessor or DSP processor running at clock rates two to ten times that of the FPGA. Coupled with a capability for implementing highly parallel arithmetic architectures, this makes the FPGA ideally suited for creating high-performance custom data path processors for tasks such as digital ﬁltering, fast Fourier transforms, and forward error correction.

For example, all major telecommunication providers have adopted FPGAs for highperformance DSP out of necessity. A third-generation (3G) wireless base station typically contains FPGAs and ASICs in addition to microprocessors and digital signal processors (DSPs). The processors and DSPs, even when running at GHz clock rates, are increasingly used for relatively low MIPs packet level processing, with the chip and symbol rate processing being implemented in the FPGAs and ASICs. The ﬂuidity of emerging standards often makes FPGAs, which can be reprogrammed in the ﬁeld, better suited than ASICs.

Despite these characteristics, broader acceptance of FPGAs in the DSP community has historically been hampered by several factors. First, there is a general lack of familiarity with hardware design and especially, FPGAs. DSP engineers conversant with programming in C or assembly language are often unfamiliar with digital design using hardware description languages (HDLs) such as VHDL or Verilog. Furthermore, although VHDL provides many high level abstractions and language

8 Xilinx Development System

constructs for simulation, its synthesizable subset is far too restrictive for system design.

System Generator is a software tool for modeling and designing FPGA-based DSP systems in Simulink. The tool presents a high level abstract view of a DSP system, yet nevertheless automatically maps the system to a faithful hardware implementation. What is most signiﬁcant is that System Generator provides these services without substantially compromising either the quality of the abstract view or the performance of the hardware implementation.

System Generator

Simulink provides a powerful high level modeling environment for DSP systems, and consequently is widely used for algorithm development and veriﬁcation. System Generator maintains an abstraction level very much in keeping with the traditional Simulink blocksets, but at the same time automatically translates designs into hardware implementations that are faithful, synthesizable, and efﬁcient.

The implementation is faithful in that the system model and hardware implementation are bit-identical and cycle-identical at sample times deﬁned in Simulink. The implementation is made efﬁcient through the instantiation of intellectual property (IP) blocks that provide a range of functionality from arithmetic operations to complex DSP functions. These IP blocks have been carefully designed to run at high speed and to be area efﬁcient. In System Generator, the capabilities of IP blocks have been extended transparently and automatically to ﬁt gracefully into a system level framework. For example, although the underlying IP blocks operate on unsigned integers, System Generator allows signed and unsigned ﬁxed point numbers to be used, including saturation arithmetic and rounding. User-deﬁned IP blocks can be incorporated into a System Generator model as black boxes which will be embedded by the tool into the HDL implementation of the design.

Introduction

System Level Modeling with System Generator

The creation of a DSP design begins with a mathematical description of the operations needed and concludes with a hardware realization of the algorithm. The hardware implementation is rarely faithful to the original functional description --instead it is faithful enough. The challenge is to make the hardware area and speed efﬁcient while still producing acceptable results.

In a typical design ﬂow --a ﬂow supported by System Generator-- the following steps occur:

1. Describe the algorithm in mathematical terms,

2. Realize the algorithm in the design environment, initially using double precision,

3. Trim double precision arithmetic down to ﬁxed point,

4. Translate the design into efﬁcient hardware. Step 4 is error prone because it can be difﬁcult to guarantee the hardware implements

the design faithfully. System Generator eliminates this concern by automatically generating a faithful hardware implementation.

Step 3 is error prone because an efﬁcient hardware implementation uses just enough ﬁxed point precision to give correct results. System Generator does not automate this step, which typically involves subtle trade off analysis, but it does provide tools to make the process tractable. You might wonder why it is not possible to eliminate Step

System Generator 9

Xilinx System Generator v2.1 Reference Guide

3 and simply use ﬂoating point operations in hardware. The answer is that most operations have a sufﬁciently small dynamic range that a ﬁxed point representation is acceptable, and the hardware realization of ﬁxed point is considerably cheaper.

The System Generator Design Flow

Simulink provides a graphical environment for creating and modeling dynamical systems. System Generator consists of a Simulink library called the Xilinx Blockset, and software to translate a Simulink model into a hardware realization of the model. System Generator maps system parameters deﬁned in Simulink (e.g. as mask variables in Xilinx Blockset blocks), into entities and architectures, ports, signals, and attributes in a hardware realization. In addition, System Generator automatically produces command ﬁles for FPGA synthesis, HDL simulation, and implementation tools, so that the user can work entirely in graphical environments in going from system speciﬁcation to hardware realization.

10 Xilinx Development System

The System Generator design ﬂow is shown in the following ﬁgure.

Introduction

Library

(including

Xilinx Blockset)

Simulation

including S-functions

Synthesis

ENTITY mult IS GENERIC(w: PORT(a,b:IN PORT(y:OUT END ENTITY ...

VHDL

Input

MATLAB Environment

System Model

1–

System Generator

Code Generation Software

- map to IP libraries

- control signals

- VHDL design

- HDL testbench

- constraints

- simulation scripts, project ﬁles

Core Parameters

Output

Simulink

Simulation Data

Xilinx

DesignTools

Environment

Synthesis Compiler

EDIF

FPGA

Place & Route

Bit stream

EDIF + Timing

CORE

Generator

Test Vectors

Logic

Simulator

Pass/Fail

Figure 1-1: System Generator design ﬂow diagram

The Xilinx Blockset is accessible in the Simulink library browser, and elements can be freely combined with other Simulink elements. Only those subsystems denoted as Xilinx black boxes, and blocks and subsystems consisting of blocks from the Xilinx Blockset are translated by System Generator into a hardware realization. The generation process is controlled from the System Generator block found in the Xilinx Blockset Basic Elements library. The System Generator parameterization GUI allows the user to choose the target FPGA device, target system clock period, and other implementation options.

System Generator translates the Simulink model into a hardware realization by mapping Xilinx Blockset elements into IP library modules, inferring control signals and circuitry from system parameters (e.g. sample periods), and converting the

The System Generator Design Flow 11

Xilinx System Generator v2.1 Reference Guide

Simulink hierarchy into a hierarchical VHDL netlist. In addition, System Generator creates the necessary command ﬁles to create the IP block netlists using CORE Generator, invokes CORE Generator, and creates project and script ﬁles for HDL simulation, synthesis, technology mapping, placement, routing, and bit stream generation. To ensure efﬁcient compilation of multi-rate systems, System Generator creates constraint ﬁles for the physical implementation tools. System Generator also creates an HDL test bench for the generated realization, including test vectors computed during Simulink simulation.

Arithmetic Data Types

System Generator provides the three arithmetic data types that are of greatest use in DSP: double precision ﬂoating point, and signed and unsigned ﬁxed point numbers. Floating point data cannot be converted into hardware, but is supported for simulation and modeling.

The set of signed arbitrary precision ﬁxed point numbers has nice mathematical properties, allowing for operations that are much cleaner than those on familiar ﬂoating point representations. Operations on ﬂoating point numbers entail implicit rounding on the result, and consequently, desirable algebraic characteristics such as associativity and distributivity are lost. Both are retained for arbitrary precision ﬁxed point numbers.

System Generator allows the quantization of the design to be addressed as an issue separate from the implementation of the mathematical algorithm. The transition from double precision to ﬁxed point can be done selectively. In practice this means the designer gets the design working using double precision, then converts to ﬁxed point incrementally. At all times, these three representations can be freely intermingled without any changes to the signal ﬂow graph. This mixing is possible because library building blocks are polymorphic, changing their internal behavior based on the types of their inputs.

There is another beneﬁt from this scheme in which quantization events are broken out as separate design parameters. At every point and stage of the design, the designer can specify how both the overﬂow and the rounding issues are to be addressed. For cases of overﬂow, the designer can choose whether or not saturation should be applied, and do so in consideration of the hardware cost versus the beneﬁt to the system design. Saturation is a more faithful reﬂection of the underlying mathematics, but more expensive in hardware; wrapping is inexpensive but less faithful. It is also possible to trap overﬂow events in the system level simulation, which can be a useful debugging mechanism in the design of subsystem that are intended never to result in overﬂow.

Likewise, when quantizing at the least signiﬁcant bit, the designer can choose whether the value should be truncated (with no hardware cost) or rounded under some particular rule (possibly improving the system design, but with added cost in hardware).

In System Generator, many operators support full precision outputs, which means that the output precision is always sufﬁcient to carry out the operation without loss information. Combined with the data type propagation rules supported in Simulink, this allows great convenience when designing an algorithm. Naturally, any operator that increases the output width of its inputs (e.g. an adder) cannot feed back on itself with full precision.

The designer speciﬁes the translation to ﬁxed precision at key points in the design (in particular, at gateways from the outside world and in feedback loops), and System

12 Xilinx Development System

Generator then propagates signal types and precisions as appropriate. The automatically chosen type is the least expensive that preserves full precision. Translations from signed to unsigned and vice versa are automatic as well.

System Generator also allows designs to contain elements that cannot be realized in hardware, but assist development and debugging. Examples of such elements are signal sources, scopes, and machinery that tracks the divergence between ﬁxed point and double precision calculations. System Generator automatically discards such elements when asked to translate to hardware.

Hardware Handshaking

In Simulink, time evolution is deﬁned by sample rates for each block in the system. There are propagation rules along signals so that not every block need set an explicit sample period. This is extremely ﬂexible, but has implications for modeling hardware. Sequential circuits are clocked, and a key aspect of designing, especially multirate systems, is the interplay between clock and clock enable signals. Although abstracted, a bit and cycle true simulation must have mechanisms for deﬁning and controlling clocked behavior in the system model.

Every signal has a ﬁxed point value as deﬁned in the previous section. In addition, it carries an implicit boolean valid bit that can be used to achieve hardware handshakes between blocks. For example, upon startup, a pipeline may deﬁne its output invalid until it has ﬂushed its pipe. By inspecting the valid bits of its inputs, a block can determine how to process its input data.

Introduction

Multirate Systems

Multirate systems can be implemented in System Generator by using sample rate conversion blocks for up-sampling and down-sampling. The necessary control logic is automatically generated when the design is netlisted. Before netlisting, the sample rates in the system are normalized to integer values; in hardware, the system clock period corresponds to the GCD of the integer sample periods. Clock enables are used to activate the hardware blocks at the appropriate moment in time with respect to the system clock.

Consider for example, the multirate system model shown in the ﬁgure below, which consists of I/O registers, an up-sampler, an anti-aliasing ﬁlter, and a down-sampler. The input signal is up-sampled by a factor of two, and subsequently down-sampled by a factor of three, giving an overall sample rate conversion by a factor of 2/3. The ST blocks in the system model extract the sample period from a Simulink signal, which can then be displayed. In the example, the input sample period is one. In the generated hardware implementation shown below the system model, each element is driven by the system clock, with its respective clock enable driven according to its sample period in the original system model.

Figure 1-2: Example of a multirate system model

Hardware Handshaking 13

Xilinx System Generator v2.1 Reference Guide

Bit-True and Cycle-True Modeling

System Generator produces a hardware implementation that is bit and cycle true to the system level simulation. We deﬁne the term bit and cycle true at the boundaries of the design. The boundaries of a design in System Generator are speciﬁed by the presence of Gateway In and Gateway Out blocks. These form interfaces between data representation within System Generator and data types that can be examined and manipulated in the standard Simulink environment. The gateways are translated into ports in the implemented hardware design. The Gateway In blocks become input ports to the design and the Gateway Out blocks become output ports.

In the Simulink simulation, Gateway in and Out blocks have data samples ﬂowing through at regular sample periods. The values ﬂowing in provide the stimuli, and those ﬂowing out represent the response. In the generated hardware, if an identical stimulus sequence is presented at the input ports (at clock events corresponding to the input sample periods), then identical output sequences will be observed (here at clock events corresponding to Simulink output events). The values presented to the hardware input ports and produced by the output ports are bit vectors interpreted as representing the ﬁxed point values of the Simulink simulation. This correspondence between Simulink and hardware results is guaranteed to hold regardless of the particular input stimulus to the design or the positioning or number of Gateway Out blocks.

Automatic Testbench Generation

For a black box instantiation, the design must provide both a Simulink model and an implementation. System Generator cannot automatically provide the veriﬁcation that the two representationsof the black box match. Toassist the designer in verifying that the system model simulated in Simulink mirrors the generated hardware circuit, a VHDL test bench is automatically created during HDL code generation.

Test bench input stimuli are recorded by Gateway In blocks during Simulink simulation. These blocks quantize double precision input date into a ﬁxed point representation. The ﬁxed point values are saved to a data ﬁle and then used as input stimuli during VHDL simulation.

Gateway Out blocks convert the ﬁxed point representation into Simulink ﬂoating point and deﬁne the output data ports of the HDL design. The signal connected to the input of a Gateway In block is sampled at a given sample rate and is used as expected data in the HDL simulation.

During HDL code generation, each Gateway In block is translated to a VHDL component which reads the input stimuli. Gateway Out blocks are translated to components that compare the VHDL results to the expected results. The comparisons are performed at the blocks' sample rates. Only values which are tagged as valid by the valid bit are compared.

The ﬁxed point data type in Simulink is represented using a std_logic_vector in VHDL. The position of the binary point, size of the container, and treatment of sign are supplied to the VHDL as generic parameters. To ease the interpretation of ﬁxed point types in VHDL, the Gateway In and Out blocks convert the std_logic_vector into a real number representation by using the generic parameter information. A sequence of real numbers can then be viewed as an analog waveform in an HDL simulator.

14 Xilinx Development System

Xilinx Blockset Overview

This chapter gives an overview of the Xilinx Blockset, including background information on underlying blockset implementation, which will help you understand how each block can be used to create and simulate your designs.

This chapter contains the following sections.

• What is a Xilinx Block?

• Instantiating Xilinx Blocks Within a Simulink Model

• The Block Parameters Dialog Box

• The Nature of Signals in the Xilinx Blockset

Xilinx Blockset Overview

Chapter 2

• Use of Xilinx Smart-IP Cores by the System Generator

• Common Options in Xilinx Block Parameters Dialog Box

What is a Xilinx Block?

The Xilinx Blockset is a Simulink library, accessible from the Simulink library browser. It consists of building blocks that can be instantiated within a Simulink model and, like other Simulink blocksets, blocks can be combined to form subsystems and arbitrary hierarchies. The Xilinx Gateway blocks (from the Xilinx Blockset’s MATLAB I/O library) are used to interface between the Xilinx Blockset ﬁxed point data type and other Simulink blocks.

Every Xilinx Block can be conﬁgured using a block parameters dialog box, with few exceptions even during simulation. Many blocks share common parameters, which are described later in this chapter. Most also have parameters speciﬁc to the function computed.

The System Generator is able to generate an FPGA implementation consisting of RTF VHDL and Xilinx Smart-IP Cores from a Simulink subsystem built from the Xilinx Blockset. The overall design, including test environment, may consist of arbitrary Simulink blocks. However, the

What is a Xilinx Block? 15

Xilinx System Generator v2.1 Reference Guide

portion of a Simulink model to be implemented in an FPGA must be built exclusively of Xilinx blocks, with the exception of subsystems denoted as black boxes.

Instantiating Xilinx Blocks within a Simulink Model

Xilinx blocks can be dragged (from the Simulink library browser, or from an expanded sheet showing the blocks in the library) and dropped onto a Simulink model sheet. Double-clicking on a block icon will open its block parameters dialog box and allow customization of that instance of the block. It is also possible to build user libraries of customized blocks and subsystems. Refer to the manual: Using Simulink from The MathWorks.

The Xilinx blocks operate on ﬁxed point data, using an arbitrary precision arithmetic type. The Gateway blocks found in the Xilinx MATLAB I/O library comprise the interface between Xilinx blocks and other Simulink blocks, and enable Xilinx blocks to be freely instantiated within a Simulink model. Of course, the only blocks that System Generator will convert to hardware are those from the Xilinx Blockset.

The Block Parameters Dialog Box

Most Xilinx blocks have parameters that can be conﬁgured. The typical block has a dialog box with several common parameters (common to most blocks in the blockset) and some speciﬁc parameters (speciﬁc to the particular block only). Double-clicking on any block icon on a sheet will open its block parameters dialog box. Details of the use of each block’s parameters dialog can be found elsewhere in this document.

Each parameters dialog contains four buttons: OK, Cancel, Help, and Apply. Apply applies your conﬁguration changes to the block, leaving the box still visible on your screen. Help launches HTML help information for the block. Cancel closes the box without saving any changes, and OK applies your conﬁguration changes and closes the box.

Figure 2-1: Buttons common to each block parameters dialog box

The Nature of Signals in the Xilinx Blockset

The fundamental scalar signal type in Simulink is double precision ﬂoating point. In contrast, for bit and cycle true simulation of hardware, System Generator signals are representedin an arbitrary precision ﬁxed point arithmetic type. The Xilinx Gateway In block converts double precision values into ﬁxed point, and the Gateway Out block converts ﬁxed point values back into double precision ﬂoating point.

Some blocks produce full precision values by default, which is to say their output signal has sufﬁcient precision to represent the output without rounding error or overﬂow. Some blocks also support the option of deﬁning the output precision to be a speciﬁc arithmetic type (e.g., 16-bit signed data with 8 bits of fraction), with quantization options of rounding or truncation, and with overﬂow options of saturation or truncation.

16 Xilinx Development System

Xilinx Blockset Overview

As an example, the ﬁgures shown below depict the Xilinx Negate block parameters dialog box with full and user deﬁned precision. Note in the latter case the additional options for selecting quantization and overﬂow behavior.

Figure 2-2: User-Deﬁned Precision Options (available if selected instead of full precision)

Valid and Invalid Data

In the Xilinx Blockset portion of a Simulink model, every data sample is accompanied by a handshake validation signal. In the corresponding hardware, every data-carrying bus has a companion net that carries a valid or invalid status indicator. This is a commonly used handshaking mechanism. There are different circumstances under which the status indicator may be set to invalid. For example, invalid data might mean that a pipeline has not yet ﬁlled up, or it may denote bursty outputs, as with an FFT. Blocks in the Xilinx Blockset can use this valid bit signal to determine what to do with the input data. Some of the Xilinx blocks, for example, the storage blocks and the FFT, use the valid bit to determine when to store input data.

Port Data Types

Selecting the Port Data Types option (under the Format menu in the Simulink window) shows the data type and precision of a signal. An example port data type string is Fix_11_9, which indicates that the signal is a signed 11-bit number with the binary point 9 bits from the right side. Similarly, an unsigned signal is indicated by the UFix_ preﬁx.

The Nature of Signals in the Xilinx Blockset 17

Xilinx System Generator v2.1 Reference Guide

Use of Xilinx Smart-IP Cores by the System Generator

To increase hardware performance, most System Generator blocks are implemented using Xilinx Smart-IP (Intellectual Property) LogiCOREs. These are hand crafted modules that make optimal use of FPGA resources to maximize performance. Some System Generator blocks map onto multiple LogiCOREs, for example, the 1024-point FFT, maps onto Dual Port Memory blocks as well as the FFT core itself.

Some Xilinx blocks also can be implemented as synthesizable VHDL modules, hence the LogiCORE is an option. When such a block cannot be implemented as a LogiCORE, System Generator automatically maps the block onto the synthesizable module. For example, the Xilinx Negate block generates a LogiCORE if you specify input of up to 256 bits, but for more than 256 bits the block is realized in synthesizable VHDL.

Many Xilinx blocks have implementations only as LogiCOREs. The reason for this is circuit performance. Because they are handcrafted for FPGA implementation, LogiCOREs have predictable performance in all design contexts. For example, the Xilinx FIR Filter block can be implemented only as the Distributed Arithmetic FIR Filter LogiCORE.

During algorithm exploration in Simulink and System Generator, it is common to iterate through block customization, Simulink simulation, and code generation. When you incorporate Black Box functionality, you can also add HDL simulation to this ﬂow. To speed this design cycle, it is possible to instruct System Generator to not invoke Xilinx CORE Generator to re-generate LogiCOREs that have already been generated and have not changed. This can be done on individual blocks by the Generate Core checkbox control, or globally using the System Generator block parameters dialog box.

Licensed Cores

The System Generator targets a suite of new ready-to-use licensed LogiCORE algorithms for forward error correction (FEC), which are critical for detecting and correcting errors in wired and wireless communication systems during transmission of data to optimize the use of available bandwidth. The new algorithms include ReedSolomon Encoder/ Decoder, a Viterbi Decoder, and an Interleaver/De-interleaver. These cores may be used for communication applications such as broadcast equipment, wireless LAN, cable modems, xDSL, satellite communications, microwave networks, and digital TV.

The System Generator allows you to build and simulate your FEC designs in Simulink using the Xilinx Blockset Communication library. System Generator creates a VHDL design and testbench that allows you to do a VHDL simulation of the FEC cores. Free evaluation versions of the FEC cores provide the behavioral models needed for VHDL simulation. The System Generator will allow you to generate the licensed core using the Xilinx CORE Generator after you have purchased and installed the FEC cores. Licensing information, as well as instructions for downloading the cores, can be found at the Xilinx IP Center: http://www.xilinx.com/ipcenter/fec_index.htm.

18 Xilinx Development System

Xilinx LogiCORE Versions

The Xilinx LogiCORE blocks (indicating the version numbers being supported by the System Generator) used in Xilinx System Generator v2.1 are listed below.

Xilinx Block Xilinx LogiCORE Version

Accumulator ACCUMULATOR V5.0 Addressable Shift

Register Adder/Subtractor ADDSUB V5.0 CIC CIC V1.0 Counter BINARY_COUNTER V5.0 Constant Multiplier MULT_GEN V4.0 Convolutional

Encoder DDS DDS V4.0 Dual Port Ram MEM_DP_BLOCK V3.2 FIFO SYNC_FIFO V3.0 FFT FFT and MEM_DP_BLOCK V1.0 (Virtex, Spartan-II),

FIR Filter DA_FIR V6.0 Interleaver/

Deinterleaver Inverter GATE_BUS V5.0 Logical GATE_BUS V5.0 Multiplier (mult) MULT_GEN V4.0 Mutiplexer (mux) BUS_MUX V5.0 Negate TWOS_COMP V5.0 Relational COMPARE V5.0 RS Decoder RS_DECODER V2.0 RS Encoder RS_ENCODER V2.0 Sine Cosine SIN_COS V3.0 Single Port RAM MEM_SP_BLOCK and

State Machines MEM_SP_BLOCK and

ROM MEM_SP_BLOCK and

Viterbi Decoder VITERBI V1.0

RAM_SHIFT V5.0

CONVOLUTION V1.0

INTERLEAVER V1.1

DIST_MEM

Xilinx Blockset Overview

V2.0 (Virtex-II) V3.2 (MEM_DP_BLOCK)

V3.2(BRAM), V5.0 (dist.)

V3.2 (BRAM), V5.0 (dist.)

Common Options in Block Parameters Dialog Box

Each Xilinx block has several conﬁgurable parameters, seen in the block parameters dialog box. Many of these parameters are speciﬁc to that particular block. Those block

Common Options in Block Parameters Dialog Box 19

Xilinx System Generator v2.1 Reference Guide

speciﬁc parameters are described in the speciﬁc block documentation in the next chapter.

The remainder of the parameters in each block’s parameters dialog box are common to most blocks. These common parameters are described below.

Arithmetic Type

In the Type ﬁeld of the block parameters dialog box, you can choose unsigned or signed (two’s complement) as the datatype of the output signal.

Implement with Xilinx Smart-IP Core (if possible)

This checkbox (sometimes referred to as the Use Core checkbox) asks the software to instantiate a core in the generated VHDL. If you do not select this checkbox, the software will instead create synthesizable VHDL.

Selecting this option does not guarantee that a Xilinx LogiCORE will be used. If the parameters for your block are such that a core cannot be generated, synthesizable VHDL will be generated instead. The System Generator software determines this at code generation time.

Generate Core

Latency

When the Generate Core checkbox is selected, the Xilinx CORE Generator will be invoked during System Generator code generation. If Generate Core is not selected, a Xilinx LogiCORE will not be generated, and if the core doesn’t already exist in your project directory, subsequently running the Xilinx Implementation tools will produce an error.

If you select Implement with Xilinx Smart-IP Core but do not select Generate Core, you will be able to simulate your generated VHDL because (1) a core will be instantiated in the VHDL, and (2) the behavioral VHDL models will be available for a simulator to use. However, you will not be able to complete implementation into a Xilinx FPGA until you have also generated the core.

In some blocks, only the Generate Core option is available. If the Implement with Smart IP-Core option is not available, only a core implementation is available from the System Generator, but no synthesizable VHDL implementation.

Use Placement Information for Core

If Generate Core is selected,the generated core includes relative placement information. This generally results in a faster implementation. Because the placement is constrained by this information, it can sometimes hinder the place and route software.

Many elements in the Xilinx Blockset have a latency option. This deﬁnes the number of sample periods by which the block’s output is delayed. One sample period may correspond to multiple clock cycles in the corresponding FPGA implementation (for example, when the hardware is overclocked with respect to the Simulink model). System Generator v2.1 does not perform extensive pipelining; additional latency is usually implemented as a shift register on the output of the block.

20 Xilinx Development System

Precision

The fundamental computational mode in the Xilinx Blockset is arbitrary precision ﬁxed point arithmetic. Most blocks give you the option of choosing the precision, i.e. the number of bits and binary point position.

By default, the output of Xilinx blocks is full precision; that is, sufﬁcient precision to represent the result without error. Most blocks have a User-Deﬁned precision option that ﬁxes the number of total and fractional bits.

Number of Bits

When you have specify user-deﬁned precision, you will be asked to specify how many bits the output should have.

Binary Point

You will also be asked to specify how many bits are to the right of the binary point (i.e., the size of the fraction). The binary point position must be between zero and the number of bits in the number’s container.

Overﬂow and Quantization

Xilinx Blockset Overview

When user-deﬁned precision is selected, errors may result from overﬂow or quantization. Overﬂow occurs if a value lies outside the representable range. Quantization error occurs if the number of fractional bits is insufﬁcient to represent the fractional portion of a value.

The Xilinx ﬁxed point data type supports several options for user-deﬁned precision. In the case of overﬂow, the options are to saturate to the largest positive (or smallest negative) value, wrap the value (i.e., discard any signiﬁcant bits beyond the mostsigniﬁcant bit in the ﬁxed point number), or ﬂag an overﬂow as a Simulink error during simulation.

In the case of quantization, the options are to round to the nearest representable value or to the value farthest from zero if there are two equidistant nearest representable values, or to truncate the data (i.e., discard bits to the right of the least signiﬁcant bit).

It is important to realize that whatever option is selected, the generated HDL model and Simulink model will behave identically.

Override with Doubles

An Override with Doubles message appears on many Xilinx Blocks, with some variations. Variations are:

Override Computation with Doubles Override Constant with Double Override Output with Doubles Override Storage with Doubles

Most Simulink blocks use double precision ﬂoating point signals and arithmetic. However, when such a signal passes through Xilinx Gateway In block, it is converted to a ﬁxed point signal. Later, when passing through a Xilinx Gateway Out block, the signals are converted back into double precision ﬂoating point.

Common Options in Block Parameters Dialog Box 21

Xilinx System Generator v2.1 Reference Guide

In the Simulink environment, the Override with Doubles option allows you to simulate the entire design in double precision ﬂoating point.

This option is useful in selecting ﬁxed point widths or when debugging. If you detect unacceptable quahtization errors with ﬁxed point signals, you can choose to simulate your entire design, or only speciﬁc blocks, using double precision ﬂoating point signals and arithmetic operations. This option will help you discover which part of your design is responsible for the unacceptable quantization error.

You may choose Override with Doubles on a particular block. You may also choose this option for an entire sheet or an entire subsystem (the sheet plus underlying hierarchy) by instantiating a System Generator token on the sheet, and choosing Override with Doubles as one of the System Generator block’s conﬁgurable parameters.

When the output of one block with Override with Doubles set is connected to the input of another block where the option is also set, data samples are transmitted in double precision.

You can easily identify which blocks are currently set to Override with Doubles. When this option is set, affected Xilinx blocks are displayed in gray rather than the normal blue or yellow.

Sample Period

Data streams are processed at a speciﬁc sample rate as they ﬂow through Simulink. Typically, each block detects the input sample rate and produces the correct sample rate on its output. Xilinx blocks Up Sample and Down Sample provide a means to increase or decrease sample rates.

Use Explicit Sample Period

If you select Use Explicit Sample Period rather than the default, you may set the sample period required for all the block outputs. This is useful when implementing features such as feedback loops in your design. In a feedback loop, it is not possible for the System Generator to determine a default sample rate, because the loop makes an input sample rate depend on a yet-to-be-determined output sample rate. System Generator under these circumstances requires you to supply a hint to establish sample periods throughout a loop.

The following image (the Concat block’s parameters dialog box) shows the options with Use Explicit Sample Period selected.

Figure 2-3: Use Explicit Sample Period options (available if selected)

22 Xilinx Development System

Xilinx Blocks

This chapter describes each Xilinx block in detail. Xilinx blocks are grouped within six categories, also shown in the Simulink library browser. They are:

• Basic Elements

• Communication

• DSP

• Math

• MATLAB I/O

• Memory

Xilinx Blocks

Chapter 3

• State Machine

Basic Elements

The Xilinx Basic Elements library includes the standard building blocks for digital designs. Using these blocks, you may insert delay, change the sample rate, and introduce constants, counters, multiplexers, etc. The Basic Elements library also has two special blocks: the System Generator and the Black Box.

System Generator

Simulink simulation and code generation.

The System Generator is a special Xilinx block that invokes the tool’s code generation software.

By placing the System Generator token on your Simulink project sheet, you can generate HDL and Xilinx LogiCOREs for all the Xilinx blocks on that sheet and on any sheets beneath it in the hierarchy. The System Generator block parameters dialog box allows you to tailor your

Basic Elements 23

Xilinx System Generator v2.1 Reference Guide

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-1: System Generator block parameters dialog box

Parameters speciﬁc to the System Generator block are:

• Xilinx Product Family

Supported families currently are: Virtex, Virtex2, Spartan2, and VirtexE.

• Target Directory

Specify where the output ﬁles (VHDL, cores, and project ﬁles) will be written. It is suggested that you create a separate directory (away from your Simulink model ﬁles) to generate your ﬁles in order to keep your Xilinx project ﬁles and Simulink model ﬁles directories organized separately.

• System Clock Period

Enter the desired System Clock Period of your design in nanoseconds (ns). This information will be passed to the Xilinx software tools through the user constraints ﬁle (.ucf) that will be created by the System Generator. This value will be used as the global PERIOD constraint and multi-cycle paths will be constrained to a multiple of this value.

• Create Testbench

Checking the Create Testbench box instructs the tool to save test vectors to be used downstream, during behavioral simulation.

When the Create Testbench box is checked, a VHDL testbench wrapper ﬁle is created for your design. Data vectors (created during Simulink simulation) are also generated.

24 Xilinx Development System

Xilinx Blocks

The wrapper ﬁle is named to match the top level VHDL ﬁle generated for your project. For example, if your top level ﬁle is named design_project, the wrapper is called design_project_testbench.vhd. The top level of the project is taken to be the Simulink sheet from which you invoked the System Generator token.

In addition to the testbench VHDL ﬁle, test vectors (.dat ﬁles) are also generated. These vectors represent the inputs and expected outputs seen in Simulink simulation. The testbench (which uses these test vectors) can be run in a behavioral simulator such as ModelSim from Model Technology.It will report any discrepancies between the Simulink and VHDL simulations.

• Global Clock Enable and Global Clear

A global clock enable or clear clock signal can be added to the design by selecting these options. This may result in a large fanout signal thus degrading system performance. Use this option only if absolutely necessary.

• Override with Doubles

The System Generator token allows you to override ﬁxed point values with double precision values for your Simulink simulation. This is particularly useful during design and debugging. The Override with Doubles directive from a System Generator token is applied to all Xilinx blocks on the same sheet and recursively through all subsystems on the sheet. Additional System Generator tokens can be inserted into the subsystems to selectively mask this effect. For an explanation of the Override with Doubles behavior, see the Common Parameters section of the previous chapter.

• Generate Cores

The Generate Cores pulldown menu on the System Generator token gives three ways to determine for which blocks the Xilinx LogiCOREs should be generated. They are:

♦ According to Block Masks: Each block that uses a Xilinx LogiCORE has

a Generate Core checkbox on its parameters dialog box. When According to Block Masks is selected on the System Generator dialog, a core is generated for each block whose Generate Core box is checked.

♦ Everywhere Available: When Everywhere Available is selected,

cores are generated without regard to the settings of Generate Core checkboxes on individual blocks.

♦ Not Needed - Already Generated: When Not Needed - Already

Generated is selected, no cores are generated. This is useful in the early stages of design development because it saves the time that would otherwise be used in unnecessary calls to the Xilinx CORE Generator. When, in the later stages, you plan to run the design through the Xilinx Implementation tools, you must remember to regenerate your design with According to Block Masks or Everywhere Available selected so that your cores are up to date.

• Generate button

Finally, clicking the Generate button invokes the code generation software, and your Simulink design is converted to VHDL and Xilinx LogiCOREs. Note that the Cancel button is active during code generation. If you want to cancel the code generation phase while it is running, you may do so by selecting Cancel during code generation.

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Xilinx System Generator v2.1 Reference Guide

Addressable Shift Register

The Xilinx Addressable Shift Register block is a variable-length shift register (or delay chain). This block differs from the Xilinx Delay block in that the amount of latency experienced by data from input to block output is variable and depends on the address value.

Data presented to the block will traverse the entire delay chain. The output of the block is not necessarily the output of the last register in the chain, however. Instead, the output of the block is taken from the register pointed to by the address presented on the addr port.

Block Interface

The block interface (inputs and outputs as seen on the Addressable Shift Register icon) are as follows:

Input signals:

d data input addr address en enable signal

Output signals:

q data output

In Simulink, the addr port is given priority over the data (d) port, i.e. on each successive cycle, the addressed data value is read from the register before the shift operation occurs. This order is needed in the Simulink software model to guarantee one clock cycle of latency between the data port and the ﬁrst register of the delay chain. (If the shift operation were to come ﬁrst, followed by the read, then there would be no delay, and the hardware would be incorrect.)

26 Xilinx Development System

Xilinx Blocks

Block Parameters Dialog Box

The Addressable Shift Register Block Parameters Dialog Box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-2: Addressable Shift Register block parameters dialog box

Parameters speciﬁc to the Addressable Shift Register block are:

• Infer Maximum Latency (depth) using Address Port Width: you can

choose to allow the block to automatically determine the depth or maximum latency of the shift-register based on the bit-width of the address port.

• Maximum Latency (depth): In the case thaqt the maximum latency is not

inferred (previous option), the maximum latency can be set explicitly.It must be a positive integer.

• Allow Additional Hardware in Certain Rate-Change Cases: several

rate-change conditions require the use of extra hardware beyond that used by the IP core to make it compliant with the Simulink simulation output. A rate-change condition will be detected if the address and data rates differ and the address port is running at a non-system rate. Choosing this parameter allows additonal hardware to be used in these cases.

• Use Enable Port: when checked, the optional enable port is activated. Other parameters used by this block are explained in the Common Parameters section

of the previous chapter.

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE Ram-based Shift Register V5.0. When the Generate Core parameter is checked, the Use Placement Information parameter provides the option of generating the core as a Relationally Placed Macro (RPM) or as unplaced logic.

The core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\ram_shift.pdf

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Xilinx System Generator v2.1 Reference Guide

Black Box

The Xilinx Black Box token enables you to instantiate your own specialized functions in your model, and subsequently into a generated design. Like the System Generator token, the Black Box token can be placed in any Simulink subsystem, identifying the subsystem as a black box. If you choose to include functionality in your Simulink model that

does not exist in the current blockset, any Simulink subsystem can be treated as a black box. You may want to build a model out of non-Xilinx blocks for an HDL representation of functionality that you want to turn into a Simulink model.

To create a black box in the System Generator, you must supply both a Simulink model and a corresponding HDL ﬁle.

Incorporating mixed language black boxes

System Generator creates VHDL for the Xilinx blocks in your design. But if you include a black box that is written in Verilog HDL, System Generator will produce a mixed language project.

A VHDL black box and a Verilog black box share the same interface, as is seen below in the description of the block parameters. You must specify the VHDL/Verilog design unit name, and specify types, names, and values of generics or parameters. You must also specify how many clocks the black box has and how these clocks should be associated with ports.

In addition, you must specify whether you are inserting a VHDL black box or a Verilog black box by choosing the appropriate language in the HDL Language option on the Black Box block parameter dialog. System Generator will generate a corresponding wrapper in the chosen language.

Block Parameters Dialog Box

The Black Box block parameters dialog box encapsulates the design information necessary for the compiler to create the correct instantiation interfaces. This black box support allows you to abstract commonly used control signals and ports, and then

28 Xilinx Development System

Xilinx Blocks

infer them in the generated VHDL. The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-3: Black Box block parameters dialog box

Parameters speciﬁed as cell arrays (generic or parameter names, types, and values) permit several methods for entering data. You can specify your data directly in the dialog box as shown. You may also specify the cell arrays as MATLAB expressions. This is useful if you have many elements in your cell arrays. Generic types can be any VHDL type. Parameter types can be any Verilog type.

The black box block parameters dialog box allows you to specify multiple clocks on a black box. To handle more than one clock, the System Generator must be told how fast each clock should run. To specify a clock’s speed, you must associate the clock to a port on the black box; the frequency of the clock is then the frequency of the signal passing through the port. System Generator allows more than one port to be associated to a clock, but all associated ports must have the same frequency.

Note - Constant inputs match any paired frequency. For example, a black box with two ports (a fast input and a slow output) should have

clocks called fast_clk and slow_clk with frequencies that match those of the

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Xilinx System Generator v2.1 Reference Guide

input and output ports respectively. To conﬁgure the black box, enter the parameters in the black box block parameters dialog box as shown in the ﬁgure below.

Figure 3-4: Customizing Clocks in the Black Box block parameters dialog box

These settings indicate that the black box should have clocks named fast_clk and slow_clk. The fast_clk should have the same frequency as the samples presented

to input port #1, and the slow_clk should have the same frequency as output port #1.

Concat

The Xilinx Concat block performs a concatenation of two bit vectors represented by unsigned integer numbers, i.e. two unsigned numbers with binary points at position zero.

The Xilinx Reinterpret block provides capabilities that can extend the functionality of the Concat block.

Block Interface

The block has two input ports and one output port. The two input ports are labeled hi and low. The number input to the hi port will occupy the most signiﬁcant bits of the output and the number that is input to the low port will occupy the least signiﬁcant bits of the output.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-5: Concat block parameters dialog box

Parameters used by this block are explained in the Common Parameters section of the previous chapter.

The Concat block does not use a Xilinx LogiCORE.

30 Xilinx Development System

Constant

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Xilinx Blocks

The Xilinx Constant block generates a constant. This block is similar to the Simulink constant block, but can be used to drive the inputs on Xilinx blocks.

Convert

Figure 3-6: Constant block parameters dialog box

Parameters speciﬁc to the block are:

• Constant Value: speciﬁes the value of the constant. When changed, the new

constant value of the block will appear on the block icon.

• Sampled Constant: allows a sample period to be associated with the constant

ouput and inherited by blocks that the constant block drives. (This is useful mainly because the blocks eventually target hardware and the sample periods of Simulink are used to establish hardware clock periods.)

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The Constant block does not use a Xilinx LogiCORE.

The Xilinx Convert block converts each input sample to a number of a desired arithmetic type. For example, a number can be converted to a signed (two’s complement) or unsigned value.

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Xilinx System Generator v2.1 Reference Guide

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-7: Convert block parameters dialog box

All the parameters of the Convert block are parameters common to other blocks. Please refer to the Common Parameters section in the previous chapter for details.

Parameters deﬁning the desired output type are:

• Output Arithmetic Type

• Number of Bits

• Binary Point

Parameters deﬁning the quantization effect and the overﬂow effect are:

• Quantization Behavior

• Overflow Behavior

The Convert block does not use a Xilinx LogiCORE.

Counter

The output for an up counter is calculated as follows:

The Xilinx Counter block implements an up or down counter. It can be conﬁgured to step between the starting and ending values, provided the increment evenly divides the difference between the starting and ending values. The counter output and increment values can be ﬁxed point numbers in addition to integers.

The down counter calculation replaces addition by subtraction.

32 Xilinx Development System

Xilinx Blocks

The block can be conﬁgured as a free running up or down counter by selecting the Provide Reset Pin option on the block parameters dialog box. In this case, the block has a reset input port in addition to its output port.

The output for a free running up counter is calculated as follows:

Here N denotes the number of bits in the counter. The down counter calculations replace addition by subtraction.

The free running up or down counter can be conﬁgured to load the

output of the counter with a value on the input din port by selecting the

Provide Load Pin option on the block parameters dialog box.

In this case, the block has three (rst, Load, din) input ports in addition to its output port.

The output for a free running up counter with load capability is calculated as follows:

Here N denotes the number of bits in the counter. The down counter calculations replace addition by subtraction.

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Xilinx System Generator v2.1 Reference Guide

Block Parameters Dialog Box

The Counter block parameters dialog box is invoked by double-clicking the block icon.

Figure 3-8: Counter block parameters dialog box

Parameters speciﬁc to the block are:

• Number of Bits: speciﬁes the number of bits in the counter.

• Binary Point Position: speciﬁes the location of the binary point.

• Arithmetic Type: speciﬁes the block ouput to be either Signed or Unsigned.

• Start Count at: speciﬁes the starting and reset value. The default is zero.

• Count to Value: speciﬁes the ending value, the number at which the counter

resets. A value of Inf denotes the largest representable output in the speciﬁed precision. This cannot be the same as the start count.

• Count By Value: speciﬁes the increment, which must evenly divide the

difference between the extreme values.

• Count Direction: speciﬁes the direction of the count (Up or Down).

• Provide Reset Pin: when checked, the block operates as a free running

counter with explicit reset port. In this case, there is no Count to Value setting.

• Provide Load Pin: when checked, the block operates as a free running load

counter with explicit load and din port. The load capability is available only for free running counter.

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

34 Xilinx Development System

Delay

Xilinx Blocks

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE: Binary Counter V5.0. The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\binary_counter.pdf

The Xilinx Delay block is a delay line (also called a shift register) of conﬁgurable length, allowing you to add latency to your design. Data presented at the input will appear at the output after a user speciﬁed number of sample periods.

The Delay block differs from the Register in that the Register allows only latency of 1, and contains an Initial Value parameter. The Delay block supports a user speciﬁed latency, but no initial value, other than zeroes.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-9: Delay block parameters dialog box

Parameters speciﬁc to this block are:

• Initialize with Zeros: The block’s internal registers are set to zero if this

option is selected, otherwise the output will be NaN (Not a Number) until the registers are ﬂushed. For example, if the Delay block has a latency of 5 and this option is selected, the ﬁrst ﬁve output values will be zeros. If this option is not selected, the ﬁrst ﬁve output values will be NaN.

• Latency: You may set the amount of latency in the Latency ﬁeld. Other parameters used by this block are explained in the Common Parameters section

of the previous chapter. The Delay block does not use a Xilinx LogiCORE, but is efﬁciently mapped to utilize

the SRL16 feature of Xilinx devices.

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Xilinx System Generator v2.1 Reference Guide

Down Sample

The Xilinx Down Sample block reduces the sample rate at the point

where the block is placed in your design. The input signal is under-

sampled so that every nth input sample is presented at the output and

held.

Output sample period is the input sample period.

In Simulink, a block changes its output right after it is enabled. In hardware, a register does not change until the clock enable is sampled, i.e. one clock cycle later. To make the hardware cycle-true to the Simulink model, the down sample block is implemented with the following circuit in hardware:

Figure 3-10: Hardware implementation of down sample block

The clock enable connected to this circuit is the same one that is distributed to the blocks connected to its output. The timing diagram shown below demonstrates the circuit's behavior. It is important to notice that this circuit has a combinatorial path from din to dout. Whenever possible put a register or delay block after a down sample block.

ki,

where kis the sampling rate and iis

Figure 3-11: Down sample circuit behavior

36 Xilinx Development System

Xilinx Blocks

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-12: Down sample block parameters dialog box

Parameters speciﬁc to the block are:

• Sampling Rate: must be an integer greater or equal to 2. This is the ratio of the

output sample period to the input, and is essentially a sample rate divider. For example, a ratio of 2 indicates a 2:1 division of the input sample rate. If a noninteger ratio is desired, the Up Sample block can be used in combination with the Down Sample block.

• Zero Initial Output (otherwise NaN): NaN means Not a Number. This

option lets you choose what the ﬁrst value of the new sample (before it has valid data) will be. By selecting Zero Initial Output, you can validate the ﬁrst sample with valid data of zero. Otherwise, an invalid data (NaN) will be the block’s ﬁrst output.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The Down Sample block does not use a Xilinx LogiCORE.

Get Valid Bit

status indicator. Under different circumstances the status indicator may be set to invalid. For example, a pipeline might not yet have ﬁlled, or outputs might be bursty, as with an FFT. This block simply reports the valid status of the samples presented to it.

There are no parameters for this block.

The Xilinx Get Valid Bit element sets its output to 1 when its input is a valid data value. The output is set to 0 otherwise.

In the Xilinx Blockset, every data sample that ﬂows through the model is accompanied by a handshake validation signal. In the corresponding hardware, every data-carrying bus has a companion net that carries a

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Mux

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

The Xilinx Mux block implements a multiplexer. The block has one select input (type unsigned) and a user-

conﬁgurable number of data bus inputs, ranging from 2 to

32.

Figure 3-13: Mux block parameters dialog box

Parameters speciﬁc to the block are:

• Number of Inputs: speciﬁes the number of data bus inputs, from 2 to 32.

• Use Placement Information for Core: when checked, the generated core

includes relative placement information. This usually results in a faster implementation. The resulting ﬂoorplan is a single column with two bits per slice. With this placement, large multiplexers may not ﬁt into small Xilinx devices. When unchecked, the core is generated as unplaced logic.

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

The block uses the Xilinx LogiCORE Bus Multiplexer V5.0. When the Generate Core parameter is checked, the Use Placement Information for Core parameter provides the option of generating the core as a Relationally Placed Macro (RPM) or as unplaced logic.

The Core datasheet can be found on your local disk at:

38 Xilinx Development System

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\bus_mux.pdf

Parallel to Serial

The following waveform illustrates the block’s behavior:

Xilinx Blocks

The Parallel to Serial block takes an input word and splits it into N time

multiplexed output words where N equals the number of input bits/

number of output bits. The order of the output is either least signiﬁcant

bit ﬁrst or most signiﬁcant bit ﬁrst.

Figure 3-14: Example of Parallel to Serial behavior

This example illustrates the case where the input width is 4, output width is 2, word size is 1 bit, and the block is conﬁgured to output the least signiﬁcant partial word ﬁrst.

Block Interface

The Parallel to Serial block has one input and one output port. The input port can be any size. The output port size is indicated on the block parameters dialog box.

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Block Parameters Dialog Box

Figure 3-15: Parallel to Serial block parameters dialog box

Parameters speciﬁc to the block are:

• Output Order: Most signiﬁcant word ﬁrst or least signiﬁcant word ﬁrst. Word

• Output Arithmetic Type: unsigned or signed

• Number of Input Bits: Input width. Must match size of input port.

• Number of Output Bits: Output width. Must divide Number of Input

• Binary Point: Output binary point location.

An error is reported when the number of output bits does not evenly divide the number of input bits.

The minimum latency of this block is 1. Other parameters used by this block are explained in the Common Parameters section

of the previous chapter. The Parallel to Serial block does not use a Xilinx LogiCORE.

size is determined by the size of the input port.

Bits evenly.

The Xilinx Register block models a D ﬂip ﬂop-based register, having latency of one sample period.

40 Xilinx Development System

Xilinx Blocks

Block Interface

The block has one input port for the data and an optional input reset port. The initial output value is speciﬁed by the user in the block parameters dialog box (below). Data presented at the input will appear at the output after one sample period. Upon reset, the register assumes the initial value speciﬁed in the parameters dialog box.

The Register block differs from the Xilinx Delay block by providing an optional reset port and a user speciﬁable initial value.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-16: Register block parameters dialog box

Parameters speciﬁc to the block are:

• Initial Value: speciﬁes the initial value in the register.

• Quantization (of Initital Value): speciﬁes desired quantization effect;

one on Round or Truncate.

• Overflow Effect (of Initital Value): speciﬁes desired overﬂow effect;

Wrap, Saturate, or Flag as Error.

• Register Only Valid Data: when checked, only valid values are registered.

Extra logic is added when this option is selected, thus decreasing system performance.

• Use Reset Port: when checked, the optional reset port is activated.

• Use Enable Port: when checked, the optional clock enable port is activated.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The Register block is implemented as a synthesizable VHDL module. It does not use a Xilinx LogiCORE.

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Reinterpret

The Reinterpret block forces its output to a new type without any regard for retaining the numerical value represented by the input. The binary representation is passed through unchanged, so in hardware this block consumes no resources. The number of bits in the output will always be the same as the number of bits in the input.

The block allows for unsigned data to be reinterpreted as signed data, or, conversely, for signed data to be reinterpreted as unsigned. It also allows for the reinterpretation of the data’s scaling, through the repositioning of the binary point within the data. The Xilinx Scale block provides an analagous capability.

An example of this block’s use is as follows: if the input type is 6 bits wide and signed, with 2 fractional bits and the output type is forced to be unsigned with 0 fractional bits, then an input of -2.0 (1110.00 in binary, two’s complement) would be translated into an output of 56 (111000 in binary).

This block can be particularly useful in applications that combine it with the Xilinx Slice block or the Xilinx Concat block. To illustrate the block’s use, consider the following scenario:

Given two signals, one carrying signed data and the other carrying two unsigned bits (a UFix_2_0), we want to design a system that concatenates the two bits from the second signal onto the tail (least signiﬁcant bits) of the signed signal.

We can do so using two Reinterpret blocks and one Concat block. The ﬁrst Reinterpret block is used to force the signed input signal to be treated as an unsigned value with its binary point at zero. The result is then fed through the Concat block along with the other signal’s UFix_2_0. The Concat operation is then followed by a second Reinterpret that forces the output of the Concat block back into a signed interpretation with the binary point appropriately repositioned.

Though three blocks are required in this construction, the hardware implementation will be realized as simply a bus concatenation, which has no cost in hardware.

42 Xilinx Development System

Block Parameters Dialog box

Figure 3-17: Reinterpret block parameters dialog box

Xilinx Blocks

Parameters speciﬁc to the block are:

• Force Arithmetic Type: When checked, the Output Arithmetic Type

parameter can be set and the output type will be forced to the arithmetic type chosen according to the setting of the Output Arithmetic Type parameter. When unchecked, the arithmetic type of the output will be unchanged from the arithmetic type of the input.

• Force Binary Point Position: When checked, the Output Binary Point

parameter can be set and the binary point position of the output will be forced to the position supplied in the Output Binary Point parameter.When unchecked, the arithmetic type of the output will be unchanged from the arithmetic type of the input.

• Output Arithmetic Type: The arithemetic type (unsigned or signed, 2’s

complement) to which the output is to be forced.

• Output Binary Point: The position to which the output’s binary point is to be

forced. The supplied value must be an integer between zero and the number of bits in the input (inclusive).

This block does not use any hardware resources. The block does not use a Xilinx LogiCORE.

Serial to Parallel

The Serial to Parallel block takes a series of inputs of any size and creates a single output of a speciﬁed multiple of that size. The input series can be ordered either with the most signiﬁcant word ﬁrst or the least signiﬁcant word ﬁrst.

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The following waveform illustrates the block’s behavior:

Figure 3-18: Example of Serial to Parallel behavior

This example illustrates the case where the input width is 1, output width is 4, word size is 1 bit, and the block is conﬁgured for most signiﬁcant word ﬁrst.

Block Interface

The Serial to Parallel block has one input and one output port. The input port can be any size. The output port size is indicated on the block parameters dialog box.

Block Parameters Dialog Box

Figure 3-19: Serial to Parallel block parameters dialog box

Parameters speciﬁc to the block are:

• Input Order: Most Signiﬁcant Word First or Least Signiﬁcant Word First

• Output Arithmetic Type: Unsigned or Signed

• Number of Input Bits: Input width. Must match size of input port.

• Number of Output Bits: Output width which must be a multiple of the

number of input bits.

44 Xilinx Development System

• Binary Point: Output binary point location Other parameters used by this block are explained in the Common Parameters section

of the previous chapter. The Parallel to Serial block does not use a Xilinx LogiCORE. An error is reported when the number of output bits cannot be divided evenly by the

number of input bits. The minimum latency for this block is zero.

Set Valid Bit

hardware, every data-carrying bus has a companion net that carries a valid or invalid status indicator. This block provides some explicit control over this handshake mechanism.

Block Parameters Dialog Box

Xilinx Blocks

The Xilinx Set Valid Bit block ﬂags input data as invalid when the signal on the valid bit input port is zero. This block only sets data invalid; it cannot change input data to valid.

In the Xilinx Blockset, every data sample that ﬂows through the model is accompanied by a handshake validation signal. In the corresponding

Slice

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-20: Set Valid Bit block parameters dialog box

The Xilinx Slice block allows you to slice off a sequence of bits from your

input data and create a new data value. This value is presented as the

output from the block. The output data type is unsigned with its binary

point at zero.

The block provides several mechanisms by which the sequence of bits can be speciﬁed. If the input type is known at the time of parameterization, the various mechanisms do not offer any gain in functionality. If, however,a Slice block is used in a design where the input data width or binary point position are subject to change, the variety of mechanisms becomes useful. The block can be conﬁgured, for example, always to extract only the top bit of the input, or only the integral bits, or

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only the ﬁrst three fractional bits. The following diagram illustrates how to extract all but the top 16 and bottom 8 bits of the input.

Figure 3-21: Slice block operation

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

46 Xilinx Development System

Xilinx Blocks

Figure 3-22: Slice block parameters dialog box showing different options

Parameters speciﬁc to the block are:

Sync

• Specify Range As: (Two Bit Locations | Upper Bit Location + Width |Lower

Bit Location + Width). Allows the user to specify either the bit locations of both end-points of the slice or one end-point along with number of bits to be taken in the slice.

• Width of Slice (Number of Bits): speciﬁes the number of bits to extract.

• Top bit of slice Offset by: speciﬁes the offset for the ending bit position

from the LSB, MSB or binary point.

• Bottom bit of slice Offset by: speciﬁes the offset for the ending bit

position from the LSB, MSB or binary point.

• Relative To: speciﬁes the bit slice position relative to the Most Signiﬁcant Bit

(MSB), Least Signiﬁcant Bit (LSB), or Binary point of the top or the bottom of the slice. Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The Slice block does not use a Xilinx LogiCORE.

The Xilinx Sync Block synchronizes two to four channels of data so that their ﬁrst valid data samples appear aligned in time with the outputs. The input of each channel is passed through a delay line and then presented at the output port for that channel. The lengths of the delay lines embedded in this block, however, are adaptively chosen at the

start of simulation so that the ﬁrst valid input samples are aligned. Thus, no data appears on any channel until a ﬁrst valid sample has been received into each channel.

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The following diagram illustrates the operation of this block.

Figure 3-23: Sync block use

This diagram shows a two-channel Xilinx Sync Block connected to two signal sources, with one producing a sawtooth wave and the other a sine wave. The sawtooth generator is able to produce its output much more quickly than the sine generator. This scenario could reﬂect, for example, a CORDIC-based sine generator with many pipeline stages for hardware efﬁciency and a simple counter-based sawtooth generator.

The rest of the diagram shows the connections of both the inputs and outputs of the Sync block to a four-channel scope. The waveforms presented by that scope are shown in the ﬁgure below. Note that the input waveforms are not aligned, with the ﬁrst valid sine wave samples signiﬁcantly lagging the sawtooth wave. In the third and fourth scope windows, the output signals can be seen to have been aligned.

Figure 3-24: Output of diagram showing Sync block use

48 Xilinx Development System

Xilinx Blocks

It is instructive to note that the following model produces behavior identical to the one with the Sync block. This one, though, requires the designer to examine the two upstream pipelined sources and to insert the correct delay line length to balance the two pipelines. Moreover, should a pipeline stage be either added to or removed from the sine wave generator, the pipeline balancing delay line would have to be re-tuned. The Xilinx Sync block allows such balancing operations to be automated.

Figure 3-25: Design with delay rather than Sync block

The Sync block can be conﬁgured to have up to four channels and to add latency to all channels beyond the minimum required.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking on the block icon in your Simulink model. The dialog box is illustrated below.

Figure 3-26: Sync block parameters dialog box

Parameters speciﬁc to the block are:

• Number of channels: Speciﬁes the number of channels to process, hence the

number of input and output ports. The number of channels can be 2, 3, or 4.

• Latency (minimum per channel): Speciﬁes the smallest amount of delay

that will be added to any channel. Latency will also be the amount of latency

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Xilinx System Generator v2.1 Reference Guide

added to the channel that is last to present a valid input sample. Note that if this parameter is zero, the block has a feed-through path; otherwise, it does not.

Other parameters used by this block are described in the Common Parameters section of a previous chapter in this manual.

The Xilinx Sync block does not use a Xilinx LogiCORE.

Up Sample

The Xilinx Up Sample block increases the sample rate at the point where the block is placed in your design. The input signal is oversampled so that every nth input sample is presented at the output, or presented once with (n-1) zeroes interspersed.

The output sample period is i/k, where i is the input sample period

and k the sampling rate. In Simulink, a block changes its output right after it is enabled. In hardware, a

register does not change until the clock enable is sampled, i.e. one clock cycle later. To make the hardware cycle-true to the Simulink model, the up sample block is implemented with the circuit shown below. The portion of the circuit within the dashed line is always present. The additional mux used for zero padding is removed if the Copy Samples option is selected on the block parameters dialog box.

Figure 3-27: Up sample block hardware implementation

The clock enable connected to this circuit is the same one that is distributed to the blocks connected to its input. The timing diagram shown below demonstrates the circuit's behavior. It is important to notice that this circuit has a combinatorial path

50 Xilinx Development System

Xilinx Blocks

from din to dout. Whenever possible, put a register or delay block after an up sample block.

Figure 3-28: Example of up sample block behavior with zero padding

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-29: Up Sample block parameters dialog box

Parameters speciﬁc to the block are:

• Sampling Rate: must be an integer with a value of 2 or greater.This is the ratio

of the output sample period to the input, and is essentially a sample rate multiplier. For example, a ratio of 2 indicates a doubling of the input sample rate. If a non-integer ratio is desired, the Up Sample block can be used in combination with the Down Sample block.

• Copy Samples: allows you to choose what to do with the additional samples

produced by the increased clock rate. By selecting Copy Samples, the same sample will be duplicated (copied) during the extra sample times. If this checkbox is not selected, the additional samples are zero.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The Up Sample block does not use a Xilinx LogiCORE.

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Communication

The blocks in the Communication library implement functions used in digital communications systems, including convolutional and block channel coding, interleaving, and utility functions.

Convolutional Encoder

data, as shown in the ﬁgure below. The length of the shift register, and the code's constraint length, is equal to the length of the convolution codes that characterize the encoder, speciﬁed in the block’s parameters dialog box. These convolution codes specify which bits in the data window contribute to the modulo-two sum at the encoder output. Resetting the block will clear the contents of the shift register to all zeros. The encoder rate is the ratio of input bits to output bits, so a rate 1/2 encoder outputs two bits for each input bit. Similarly, a rate 1/3 encoder outputs three bits for each input bit.

The Xilinx Convolutional Encoder block implements an encoder for convolutional codes. Commonly used in tandem with a Viterbi decoder block, this block can be used to implement forward error correction (FEC) circuitry for digital communication systems.

Data is encoded using a linear feed forward shift register to compute modulo-two sums over a sliding window of input

Figure 3-30: Constraint length 9 convolutional encoder

Block Interface

The block has two input and one output ports. The input ports, din and rst, are limited to type UFix1_0. The size of the output port, dout, is determined by the output rate. The port will be either type UFix2_0 or UFix3_0.

52 Xilinx Development System

Block Parameters Dialog Box

The following ﬁgure shows the block parameters dialog box.

Xilinx Blocks

Figure 3-31: Convolutional encoder block parameters dialog box

Parameters speciﬁc to the block are:

• Output Rate: 2 or 3. Number of output bits generated per input bit. A rate 1/2

encoder will have an output rate of 2.

• Convolution Code 1: Used to generate least signiﬁcant bit of the output.

Length of convolution code must be between 3 and 9 (inclusive).

• Convolution Code 2: Used to generate bit 2 of the output. Length of

convolution code must be between 3 and 9 (inclusive).

• Convolution Code 3: Used to generate bit 3 of the output. Length of

convolution code must be between 3 and 9 (inclusive).

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

The Convolutional Encoder block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLABI/O library documentation) explanation for more details.

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE: Convolutional Encoder v1.0. The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\convolution_v1_0 \doc\convolution.pdf

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Depuncture

The Xilinx Depuncture block allows you to insert arbitrary symbol into your input data at the location speciﬁed by the depuncture code and creates a new value. This value is presented as output from the block.

The Xilinx depuncture block accepts data of type UFixN_0 where N equals the length of insert string x (the number of ones in the depuncture code) and produces output data of type UFixK_0 where K equals the length of insert string x (the length of the depuncture code ).

The Xilinx Depuncture block can be used to decode a range of punctured convolution codes. The following diagram illustrates an application of this block to implement soft decision Viterbi decoding of punctured convolution codes.

Figure 3-32: Example of Depuncture block use

The previous diagram shows a matched ﬁlter block connected to a serial to parallel block. The serial to parallel block concatenates two continuous soft inputs and presents it as a 6-bit word to the depuncture block. The depuncture block inserts the symbol '100' after the 3-bits from the MSB for code 0 ( [1 0 1] ) and 6-bits from the MSB for code 1 ( [1 1 0] ) to form a 9-bit word. The output of the depuncture block is serialized as soft decision 3-bit input words for the Viterbi decoder which decodes the punctured convolutional code and outputs the decoded data.

54 Xilinx Development System

Xilinx Blocks

Block Parameters Dialog Box

The Xilinx depuncture block can be conﬁgured using its Block Parameters dialog box.

Figure 3-33: Depuncture block parameters dialog box

Parameters speciﬁc to the Xilinx Puncture block are:

• Depuncture Code: speciﬁes the depuncture pattern for inserting the string to

the input.

• Insert Symbol: speciﬁes the binary word to be inserted in the depuncture

code.

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

The Depuncture block does not use a Xilinx LogiCORE.

Interleaver Deinterleaver

The Xilinx Interleaver/Deinterleaver block implements an interleaver or a deinterleaver. An interleaver is a device that rearranges the ordering of a sequence of symbols in a one-to-one deterministic manner. Associated with any interleaver is a deinterleaver, a device that restores the reordered sequence.

When the block is in interleaver mode, the input data sampled on the din port shall be multiplexed into and out of B shift registers

onto the dout port using two (synchronized) commutator arms, as illustrated in the ﬁgure below.Bis the number of branches as entered in the block’s parameters dialog. Branch 0 shall have a shift register of zero length. Branch 1 shall have a shift register of lengthL. Branch 2 shall have a shift register of length2L. Branch ( constant entered as an array with a length of one.

B-1

) shall have a shift register of length

(B-1)L.L

is the branch length

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Figure 3-34: Forney convolutional interleaver with a constant difference between consecutive branches

When the block is in deinterleaver mode, the input data sampled on the DIN port is multiplexed into and out of B shift registers onto the DOUT port using two (synchronized) commutator arms. Branch 0 will have a shift register of length (B-1)*L. Branch (B-1) shall have a shift register length of zero.

Figure 3-35: Forney convolutional deinterleaver with a constant difference between consecutive branches

56 Xilinx Development System

Xilinx Blocks

When the branch lengths are speciﬁed as an array, the block operates the same in either interleaver or deinterleaver mode because the array fully deﬁnes the length of all the branches. The array must have length B, matching the number of branches.

The reset pin (rst) will set the commutator arms to branch 0, but will not clear the branches of data.

Block Interface

The Interleaver/Deinterleaver block has two input and one output ports. The input port, din, must be between 1 and 256 (inclusive) bits. The reset port, rst, must be of type UFix1_0. The size of the output port, dout, is the same as the input port, din.

Block Parameters Dialog Box

Figure 3-36: Interleaver/Deinterleaver block parameters dialog box

Parameters speciﬁc to the block are:

• Mode: Interleaver or Deinterleaver

• Number of Branches: 1 to 256 (inclusive)

• Length of Branches: 1 to MAX (inclusive). MAX depends on the number of

branches and size of core input. Branch length must be an array of either length one or number of branches. If the array size is one, the value is used as a constant difference between consecutive branches. Otherwise, each branch has a unique length.

• Memory Type: Automatically chosen, block RAM or distributed RAM Other parameters used by this block are described in the Common Parameters section

of the previous chapter.

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE: Interleaver/Deinterleaver v1.1.

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The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\sid_v1_1\doc\sid .pdf

This is a licensed core, available for purchase on the Xilinx web site at:

http://www.xilinx.com/ipcenter/interleaver

Puncture

The Xilinx Puncture block allows you to remove arbitrary bits speciﬁed as a puncture code from your input data and create a new value. This value is presented as the output from the block. The Xilinx puncture

block accepts data of type UFixN_0 (where N is equal to the length of the puncture code) and outputs data of type UFixK_0 (where K is equal to the number of ones in the puncture code).

The Xilinx Puncture block can be used to implement a range of punctured convolution codes. The following diagram illustrates an application of this block.

Figure 3-37: Example of a Puncture block application

The preceding diagram shows a 1/2 rate Convolutional Encoder block connected to a binary input signal source. The slice blocks separate the convolution code output over the two branches. The output of the slice block is connected to a Serial to Parallel block which concatenates the output of the convolution code to form a 3-bit word. The puncture block removes the center bit for code 0 ( [1 0 1] ) and LSB bit for code 1 ( [1 1 0 ] ) to produce a 2-bit punctured output which is again serialized to be connected to the I and Q channel for baseband shaping.

58 Xilinx Development System

Xilinx Blocks

Block Parameters Dialog Box

The Xilinx puncture block can be conﬁgured using its Block Parameters dialog box.

Figure 3-38: Puncture block parameters dialog box

Parameters speciﬁc to the Xilinx Puncture block are:

• Puncture Code: speciﬁes the puncture pattern for removing the bits from the

input.

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

The Puncture block does not use a Xilinx LogiCORE.

RS Decoder

n is the total number of symbols in a code block and k is the number of information or data symbols. See the RS Encoder block documentation for more details. A ReedSolomon decoder can correct up to t symbols that contain errors in a codeword, where 2t = n-k.

The RS decoder can correct up to t errors or up to 2t erasures. An erasure occurs when the position of an erred symbol is known. Erasure information is generally supplied by the demodulator in a digital communication system, i.e. the demodulator ﬂags received symbols that are likely to contain errors. When a codeword is decoded, there are three possible outcomes:

1. If 2p + r < 2t (p errors, r erasures) the original transmitted code word will always be recovered

RS (Reed-Solomon) codes are block-based error correcting codes with a wide range of applications in digital communications and storage. The Xilinx RS Decoder core handles both full length and shortened systematic codes. The Reed-Solomon decoder takes a block of digital data and processes each block and attempts to correct errors and recover the original data.

A Reed-Solomon code is speciﬁed as RS(n,k) with s-bit symbols. Reed-Solomon codes are usually referred to as (n,k) codes, where

2. The decoder will detect that it cannot recover the original code word and will indicate a failure in decoding.

3. The decoder will mis-decode and recover an incorrect code word without any indication.

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The probability of each of the three outcomes depends on the particular ReedSolomon code and the nature of the communications channel. The Simulink blocksets provide excellent capabilities for modeling communication channels and ascertaining these probabilities.

Block Interface

The Xilinx RS Decoder Block has two input (din, rst) and four output (dout, info, fail, err_cnt) ports. The RS Decoder block also has two optional input ports (start, erase) and one optional output port (erase_cnt).

Figure 3-39: Reed-Solomon Decoder icons, including optional ports

The port descriptions are:

• din: carries the codeword to be decoded. The din signal must be a UFixS_0

where S is equal to the symbol width (3 to 12).

• rst: carries the reset signal for the decoder. After the rst signal is asserted the

decoder initializes the next available input as the ﬁrst input codeword symbol. The rst signal must be a UFix1_0.

• start: when start is asserted for a particular sample period, the data on the din

port is taken as the ﬁrst input codeword. The start signal is ignored for (n-1) sample periods after the ﬁrst start signal is asserted. The decoder always needs the start signal to be asserted for one sample period to mark the beginning of a codeword. The start signal must be a UFix1_0.

• erase: when erase is asserted for a particular sample period, data input on the

din port is marked as an erasure to be corrected by the decoder. The erase signal must be a UFix1_0.

• dout: carries the decoded information symbols and the parity symbols of the

input codeword. The dout signal must have the same arithmetic type as the din input.

• info: info output is 1 when there are information symbols on the dout port and 0

when there are parity symbols on the dout port. The info signal is a UFix1_0.

• fail: supplied when the last symbol of a code block is output on dout. The

decoder sets fail 1 if it determines that there were more errors in the code block than it could correct. The fail signal is a UFix1_0.

• err_cnt: supplied when the last symbol of a code block is output on dout. The

err_cnt outputs the number of errors that were corrected by the decoder in the output code block. The err_cnt signal is a UFixN_0 (where N is equal to the number of binary bits required to represent n-k).

• erase_cnt: erase_cnt output is available only when the erasure decoding is

enabled. The erase_cnt output is set when the last symbol of a code block is output on dout. The erase_cnt output provides a count on the number of erasures that were ﬂagged for the output code block. The erase_cnt signal is a

UFixN_0 (where N is equal to the number of binary bits required to represent n).

60 Xilinx Development System

Xilinx Blocks

Block Parameters Dialog Box

The RS Decoder block can be conﬁgured using its Block Parameters dialog box.

Figure 3-40: Reed-Solomon Decoder block parameters dialog box

Parameters speciﬁc to the RS Decoder block are:

• Code Specification: speciﬁes the type of RS Decoder desired. The choices

are:

♦ Custom: allows you to set all the block parameters. ♦ ATSC: implements ATSC (Advanced Television Systems Committee) stan-

dard (207, 187) shortened RS code.

♦ CCSDS: implements CCSDS (Consultative Committee for Space Data

Systems) standard full length and shortened RS code.

♦ DVB: implements DVB (Digital Video Broadcasting) standard (204, 188)

shortened RS code.

♦ IESS-308 (126): implements IESS-308 (INTELSAT Earth Station Standard)

speciﬁcation (126, 112) shortened RS code.

♦ IESS-308 (194): implements IESS-308 speciﬁcation (194, 178) shortened RS

code.

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Xilinx System Generator v2.1 Reference Guide

♦ IESS-308 (208): implements IESS-308 speciﬁcation (208, 192) shortened RS

code.

♦ IESS-308 (219): implements IESS-308 speciﬁcation (219, 201) shortened RS

code.

♦ IESS-308 (225): implements IESS-308 speciﬁcation (225, 205) shortened RS

code.

• Symbol Width: speciﬁes the symbol width for the RS code. The RS decoder

supports symbol width from 3 to 12.

• n: speciﬁes the length of the RS code. The RS decoder supports code with length

from (2sw -1) to 3, where sw is symbol width.

• k: speciﬁes the number of information symbols in a RS code. The RS decoder

supports code with length from (n-2) to max((n-128), 1).

• Field Polynomial: speciﬁes the ﬁeld polynomial used to generate the Galois ﬁeld

for the code. It is entered as an binary array where the 1st element corresponds to the highest degree of the polynomial. A value of zero causes the default polynomial for the given symbol width to be selected. The speciﬁed polynomial should be a primitive polynomial for the given symbol width. The default polynomials for the speciﬁed symbol width are:

Symbol Width Default Polynomials Array Representation

3x 4x 5x 6x 7x 8x 9x

+ x + 1 [1 0 1 1]

+ x + 1 [1 0 0 1 1]

+ x2 + 1 [1 0 0 0 1 1]

+ x + 1 [1 0 0 0 0 1 1]

+ x3 + 1 [1 0 0 0 1 0 0 1]

+ x4 + x3 + x2 + 1 [1 0 0 0 1 1 1 0 1]

+ x4+ 1 [1 0 0 0 0 1 0 0 0 1] 10 x10 + x3 + 1 [1 0 0 0 0 0 0 1 0 0 1] 11 x11 + x2 + 1 [1 0 0 0 0 0 0 0 0 1 0 1] 12

x12 + x6 + x4 + x + 1

[1 0 0 0 0 0 1 0 1 0 0 1 1]

• Generator Start: speciﬁes the Galois ﬁeld logarithm of the ﬁrst root of the

generator polynomial g(x), i.e.:

nk–1–

gx() xa

∏

i 0=

hx GS i+()

–()

where

a = a primitive root of the Galois ﬁeld for the code

GS = Generator Start h = Scaling Factor. Normally,Generator_Start is 0 or 1; however,it can be any non-

negative integer between 0 and (216- 1).

62 Xilinx Development System

Xilinx Blocks

• Scaling Factor: Scaling factor for the generator polynomial root index.

Normally h is 1; however, it can be any positive integer between 1 and (216-1).

• Provide Start Pin: when checked, the block has optional start input pin.

• Enable Erasure Decoding: when checked, the block has optional pins erase

at the input and erase_cnt at the output.

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

The RS Decoder block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLAB I/O library documentation) explanation for more details.

Latency

The RS Decoder block always accepts continuous code blocks. The same RS Decoder core is sometimes overclocked using the core’s Clock Periods Per Symbol parameter.In a multirate system, the Clock Periods Per Symbol is set to the maximum of the rate of decoder block and the number of Clock Periods Per Symbol required to support continuous code blocks. The latency of the decoder in sample periods is dependent on the values of n,error correcting capacity of the code and Clock Periods Per Symbol set by the block. The latency of the RS decoder block is always equal to the latency returned by the RS Decoder core + 3.

Xilinx LogiCore

The RS Decoder block uses Xilinx LogiCORE: RS Decoder v2.0. The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\rs_decoder_v2_0\ doc\rs_decoder.pdf

This is a licensed core, available for purchase on the Xilinx web site at:

http://www.xilinx.com/ipcenter/reed_solomon

RS Encoder

Figure 3-41: Example of a system using Reed-Solomon codes

Reed-Solomon (RS) codes are block-based error correcting codes with a wide range of applications in digital communications and storage. Reed-Solomon codes are used to correct errors in many systems such as digital storage devices, wireless or mobile communications, digital video broadcasting, etc.

A typical system is shown below:

The Reed-Solomon encoder takes a block of digital data and adds extra, redundant bits. Errors may occur during transmission or storage for a number of reasons (noise or interference, scratches on a CD, etc.). The Reed-Solomon decoder processes each block and attempts to correct errors and recover the original data. The number and

Communication 63

Xilinx System Generator v2.1 Reference Guide

type of errors that can be corrected depends on the characteristics of the ReedSolomon code.

Reed-Solomon codes are a subset of BCH (Bose, Chaudhuri, and Hocquenghem) codes and are linear block codes. A Reed-Solomon code is speciﬁed as RS(n,k) with sbit symbols. Reed-Solomon codes are usually referred to as (n,k) codes, where n is the total number of symbols in a code block and k is the number of information or data symbols. Normally, n = 2 code is referred to as a shortened code. The RS Encoder core handles both full length and shortened codes.

The RS Encoder block generates systematic code blocks. This means that the encoder takes k data symbols of s bits each and adds parity symbols to make an n symbol codeword. There are (n-k) parity symbols of s bits each. The following diagram shows a typical Reed-Solomon codeword. This is known as a Systematic code because the data is left unchanged and the parity symbols are appended.

(sw)

-1, where sw is symbol width. If n is less than this, the

Figure 3-42: Example of a Reed Solomon codeword

A Reed-Solomon code is characterized by two polynomials: the ﬁeld polynomial and the generator polynomial. The ﬁeld polynomial deﬁnes the Galois ﬁeld, of which the symbols are members. The generator polynomial deﬁnes how the check symbols are generated. Both of these polynomials are usually deﬁned in the speciﬁcation for any particular Reed-Solomon code. The Reed-Solomon codeword is generated using the generator polynomial. All valid codewords are exactly divisible by the generator polynomial.

The general form of the generator polynomial is:

gx() xa

and the codeword is constructed using:

–()xa

i 1+

–()= xa

. . . .

i 2t+

–()

cx() gx()ix()⋅=

where

g(x) is the generator polynomial i(x) is the information block c(x) is a valid codeword x is referred to as the ﬁeld polynomial.

For example: Generator for RS(204,188) is:

gx() xa

64 Xilinx Development System

–()xa

–()= xa

. . . .

–()

Xilinx Blocks

Block Interface

The Xilinx RS Encoder block has two inputs (din, rst) and three output (dout, info and rfd) ports. The RS Encoder block also has optional start and bypass

input ports.

Figure 3-43: Reed-Solomon Encoder icons, including optional ports

The port descriptions are:

• din: carries the input information symbols of the RS code. The din signal must

be an UFixS_0 where S is equal to the symbol width (3 to 12).

• rst: carries the reset signal for the RS encoder. After the rst signal is asserted the

RS encoder initializes the next available input as the ﬁrst information symbol. The rst signal must be a UFix1_0.

• start: when start is asserted for a particular sample period, the data on the din

port is taken as the ﬁrst input information symbol. If start is asserted high for more than one sample period, the data at the last sample period is taken as the ﬁrst input information symbol. The start signal is ignored if bypass is asserted high for the same sample period. The start signal always resets the state of the code generator. The start signal must be a UFix1_0.

• bypass: when bypass is asserted for a particular sample period, the

corresponding data input on the din port is passed straight through to the dout port with a 4 (6 in case of CCSDS) sample period delay. The bypass signal has no effect on the state of the code generator. The bypass signal must be a UFix1_0.

• dout: carries the input information symbols and the parity symbols of the RS

code. The dout signal has the same arithmetic type as the din input.

• info: The info output is 1 when there is information symbols on the dout port.

The info output is also 1 when the bypass asserted input data appears at the dout port. The info signal is a UFix1_0.

• rfd: carries the ready for data signal for the RS encoder. This signal is 1 till the RS

encoder is accepting information symbols and 0 when the RS encoder is outputting parity symbols. The rfd signal is a UFix1_0.

Communication 65

Xilinx System Generator v2.1 Reference Guide

Block Parameters Dialog Box

The RS Encoder block can be conﬁgured using its Block Parameters dialog box.

Figure 3-44: Reed-Solomon Encoder block parameters dialog box

Parameters speciﬁc to the RS Encoder block are:

• Code Specification: speciﬁes the type of RS Encoder desired. The choices

are:

♦ Custom: allows you to set all the block parameters. ♦ ATSC: implements ATSC (Advanced Television Systems Committee) stan-

dard (207, 187) shortened RS code.

♦ CCSDS: implements CCSDS (Consultative Committee for Space Data

Systems) standard (255, 223) full length RS code.

♦ DVB: implements DVB (Digital Video Broadcasting) standard (204, 188)

shortened RS code.

♦ IESS-308 (126): implements IESS-308 (INTELSAT Earth Station Standard)

speciﬁcation (126, 112) shortened RS code.

♦ IESS-308 (194): implements IESS-308 speciﬁcation (194, 178) shortened RS

code.

♦ IESS-308 (208): implements IESS-308 speciﬁcation (208, 192) shortened RS

code.

♦ IESS-308 (219): implements IESS-308 speciﬁcation (219, 201) shortened RS

code.

66 Xilinx Development System

Xilinx Blocks

♦ IESS-308 (225): implements IESS-308 speciﬁcation (225, 205) shortened RS

code.

• Symbol Width: speciﬁes the symbol width for the RS code. The RS encoder

supports symbol width from 3 to 12.

• n: speciﬁes the length of the RS code. The RS encoder supports code with length

from (2sw - 1) to 3, where sw is symbol width.

• k: speciﬁes the number of information symbols in a RS code. The RS encoder

supports code with length from (n-2) to max((n-256), 1).

• Field Polynomial: speciﬁes the ﬁeld polynomial used to generate the Galois

ﬁeld for the code. It is entered as an binary array where the 1st element corresponds to the highest degree of the polynomial. A value of zero causes the default polynomial for the given symbol width to be selected. The speciﬁed polynomial should be a primitive polynomial for the given symbol width. The default polynomials for the speciﬁed symbol width are:

Symbol Width Default Polynomials Array Representation

3x 4x 5x 6x 7x 8x 9x

+ x + 1 [1 0 1 1]

+ x + 1 [1 0 0 1 1]

+ x2 + 1 [1 0 0 0 1 1]

+ x + 1 [1 0 0 0 0 1 1]

+ x3 + 1 [1 0 0 0 1 0 0 1]

+ x4 + x3 + x2 + 1 [1 0 0 0 1 1 1 0 1]

+ x4+ 1 [1 0 0 0 0 1 0 0 0 1] 10 x10 + x3 + 1 [1 0 0 0 0 0 0 1 0 0 1] 11 x11 + x2 + 1 [1 0 0 0 0 0 0 0 0 1 0 1] 12 x12 + x6 + x4 + x + 1 [1 0 0 0 0 0 1 0 1 0 0 1 1]

• Generator Start: speciﬁes the Galois ﬁeld logarithm of the ﬁrst root of the

generator polynomial g(x), i.e.:

nk–1–

gx() xa

∏

i 0=

hx GS i+()

–()

where

a = a primitive root of the Galois ﬁeld for the code

GS = Generator Start h = Scaling Factor. Normally,Generator_Start is 0 or 1; however,it can be any non-

negative integer between 0 and (216- 1).

• Scaling Factor: Scaling factor for the generator polynomial root index.

Normally h is 1; however, it can be any positive integer between 1 and (216- 1).

• Provide Reset Pin: when checked, the block has optional start and bypass

input pins.

Communication 67

Xilinx System Generator v2.1 Reference Guide

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

The RS Encoder block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLAB I/O library documentation) explanation for more details.

Latency

The RS Encoder has a 6 sample period latency for CCSDS code speciﬁcation and a 4 sample period latency for all other speciﬁcations.

Xilinx LogiCore

The RS Encoder block uses Xilinx LogiCORE RS Encoder v2.0. The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\rs_encoder_v2_0\ doc\rs_encoder.pdf

This is a licensed core, available for purchase on the Xilinx web site at:

http://www.xilinx.com/ipcenter/reed_solomon

Viterbi Decoder

length of the trace through the trellis is determined from the traceback length parameter.

The Viterbi Decoder has a lower error rate when given optimal convolution codes. On the Convolutional Encoder, the convolution codes are used to select which bits in the constraint register are XORed to generate the encoded output. The convolution codes must match those on the corresponding convolutional encoder. When using suboptimal codes, the opposite path has the same cost as the desired path in the Viterbi trellis and decoding errors will result. The following table provides a list of optimal codes. The constraint length is inferred from the length of the convolution code.

Constraint

length

3 111,101 111,111,101 4 111,1011 111,1011,1101

The Xilinx Viterbi Decoder block is used for decoding convolutionally encoded data. The ﬁrst step in decoding is to assess the cost of the incoming data against all possible data input combinations. Either the Hamming or Euclidean metric is used to determine the cost. The cost determines the distance to each state in the Viterbi trellis. The second and ﬁnal decoding step is to trace backwards through the trellis and determine the optimal path. The

Optimal convolution codes for

decoding 1/2 rate encoders

Optimal convolution codes for

decoding 1/3 rate encoders

5 11111,11011 11111,11011,10101 6 101111, 110101 101111, 110101,111001 7 1001111,1010111 1001111,1010111,1101101 8 11101111, 10011011 11101111, 10011011, 10101001

68 Xilinx Development System

Xilinx Blocks

Constraint

length

9 111101101, 110011011 111101101, 110011011, 100100111

Optimal convolution codes for

decoding 1/2 rate encoders

Optimal convolution codes for

decoding 1/3 rate encoders

Block Interface

The Viterbi Decoder has either two or three input ports and one output port. The decoder can have either two or three input ports depending on the conﬁgurable parameter indicating encoder output rate. Use of hard coding requires input data to be 1 bit wide. Soft coding requires the input data to be 3 to 8 bits (inclusive). Theoutput

port is of type UFix1_0. Note - This version of the ViterbiDecoder is not recommended for implementation of

punctured codes.

Block Parameters Dialog Box

Figure 3-45: Viterbi Decoder block parameters dialog box

Parameters speciﬁc to the Viterbi Decoder block are:

• Encoder Output Rate: 2 or 3. must match the output rate on the

Convolutional Encoder from which data is being decoded.

Communication 69

Xilinx System Generator v2.1 Reference Guide

• Traceback Length: Length of the traceback through the Viterbi trellis. Optimal

length is considered to be between 5 and 7 times the constraint length.

• Convolution Code 1: Used to decode data on input port din1. Length of

convolution code must be between 3 and 9 (inclusive).

• Convolution Code 2: Used to decode data on input port din2. Length of

convolution code must be between 3 and 9 (inclusive).

• Convolution Code 3: Used to decode data on input port din3. Length of

convolution code must be between 3 and 9 (inclusive). This parameter is only available for encoder output rate of 3.

• Coding: Hard or Soft. Hard coding uses the Hamming metric to calculate

the difference between the input and the branches in the Viterbi trellis. Hard coding requires the input data to be 1 bit wide. Soft coding uses the Euclidean metric to cost the incoming data against the branches of the Viterbi trellis. When using soft coding, the input port widths must be between 3 and 8 bits.

• Data Format: Signed Magnitude and Offset Binary (available for Soft Coding

only).

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

DSP

The Viterbi Decoder block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLAB I/O library documentation) explanation for more details.

Xilinx LogiCore

The Viterbi Decoder block uses Xilinx LogiCORE: Viterbi v1.0. The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\viterbi_v1_0\doc \viterbi.pdf

This is a licensed core, available for purchase on the Xilinx web site at:

http://www.xilinx.com/ipcenter/viterbi

This library contains blocks that implement Digital Signal Processing (DSP) speciﬁc functions.

CIC

Cascaded integrator-comb (CIC) ﬁlters are multirate ﬁlters used for realizing large sample rate changes in digital systems. Both decimation and interpolation structures are supported. CIC ﬁlters contain no multipliers; they consist only of adders, subtractors and registers. They are typically employed in applications that have a large excess sample rate; that is, the system sample rate is much larger than the bandwidth occupied by the signal. CIC ﬁlters are frequently used in digital downconverters and digital up-converters.

70 Xilinx Development System

Xilinx Blocks

Block Interface

The CIC Block has one input and one output port. The input port can be between 1 and 32 bits (inclusive).

The two basic building blocks of a CIC ﬁlter are the integrator and the comb. A single integrator is a single-pole IIR ﬁlter with a transfer function of:

H(z) = (1 – z-1) The integrator’s unity feedback coefﬁcient is y[n] = y[n-1] + x[n]. A single comb ﬁlter is an odd-symmetric FIR ﬁlter described by: y[n] = x[n] – x[n – RM] M is the differential delay selected in the block parameterization GUI, and R is the

selected integer rate change factor. The transfer function for a single comb stage is H(z) = 1 –z As seen in the two ﬁgures below, the CIC ﬁlter cascades N integrator sections together

with N comb sections. To keep the integrator and comb structures independent of rate change, a rate change block (i.e., an up-sampler or down-sampler) is inserted between the sections. In the interpolator, the up-sampler causes a rate increase by a factor of R by inserting R-1 zero-valued samples between consecutive samples of the comb section output. In the decimator, the down-sampler reduces the sample rate by a factor of R by taking subsamples of the output from the last integrator stage.

-1

-RM

Figure 3-46: Pipelined decimator and interpolator

DSP 71

Xilinx System Generator v2.1 Reference Guide

Block Parameters Dialog Box

The CIC Block can be conﬁgured using its Block Parameters dialog box:

Figure 3-47: CIC block parameters dialog box

Parameters speciﬁc to this block are:

• Filter Type: Interpolator or Decimator

• Number of Stages: 1 to 8 (inclusive)

• Sample Rate Change: 8 to 16384 (inclusive)

• Differential Delay: 1 or 2

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

The CIC block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLABI/O library documentation) explanation for more details.

Xilinx LogiCORE

The CIC block always uses the Xilinx LogiCORE: CIC v1.0. The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\cic_v1_0\doc\ C_CIC_V1_0.pdf

72 Xilinx Development System

DDS

Xilinx Blocks

The Xilinx DDS Block implements a direct digital synthesizer (DDS), also commonly called a numerically controlled oscillator (NCO). The block employs a look-up table scheme to generate real or complex valued sinusoids. An internal look-up table stores samples representing one period of a sinusoid. A digital integrator (accumulator) is then used to generate a suitable phase argument that is mapped by the look-up table into the desired output waveform.

To understand how to use the DDS block, it is necessary to understand how the block is implemented in hardware, as the block parameters are deﬁned in terms of the DDS implementation as a Xilinx LogiCORE. The ﬁgure below shows a high-level view of the core. The input phase increment ∆θ is registered and integrated in a phase accumulator. A phase offset is added to the high-precision phase angle computed by the accumulator, and the sum is quantized by truncation. The quantized value is then used to index into the Sine/Cosine Lookup Table, mapping phase-space into time. The phase increment ∆θ is deﬁned by the following relationship

The phase offset and phase increment can be deﬁned as constants or can be set dynamically through optional input ports (details not shown in the ﬁgure). When one or both are set dynamically, the block has a single data port, which is multiplexed between the Phase Increment and Phase Offset inputs, with the selection determined by the value on a select port of the block. If only one of the increment and offset is conﬁgurable, there is no select port. The data value is registered in the Phase Increment register or the Phase Offset register when the block’s write enable input is

1. When phase dithering is used, the dither sequence d(n) linearises the quantizer Q()

that is used to produce the sine/cosine LUT address. The additional logic resources required to implement the dither sequence generator are not signiﬁcant.

Figure 3-48: High-Level View of LogiCORE DDS Implementation

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Xilinx System Generator v2.1 Reference Guide

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-49: DDS block parameters dialog box

Parameters speciﬁc to the DDS block are:

• Function: speciﬁes the block output to be sine, cosine, or both.

• Negative Sine: when checked, the sine output is negated.

• Negative Cosine: when checked, the cosine output is negated.

• Output Width: number of bits in the output signal; value must be between 4

and 32 inclusive.

• Lookup Table Input Width: speciﬁes the number of address bits into the

Sin/Cos Lookup Table; value must be at least 3. It cannot exceed the lesser of the accumulator width and 16 (if block RAM is used), or 10 (if distributed RAM is used).

74 Xilinx Development System

Xilinx Blocks

• Phase Increment Type: speciﬁes ∆θ to be either constant or register. Choice

of register activates optional ports on the block.

• Phase Increment: speciﬁes value of phase increment constant, a multiple of 2π.

The number of bits is determined in one of two ways. If the increment type is Register, the number of bits is set to the width of the data port. If the increment type is Constant, the number of bits is inferred from the phase increment value.

• Accumulator Latency: speciﬁes the latency in the phase accumulator to be

zero or one.

• Accumulator Width: speciﬁes the phase accumulator width; value must be

between 3 and 32 inclusive.

• Phase Offset Type: speciﬁes phase offset to be Constant, Register, or None.

Choice of register activates optional ports on the block.

• Phase Offset: speciﬁes value of phase offset constant, as a multiple of 2π. The

number of bits is determined in one of two ways. If the offset type is Register,the number of bits is set to the width of the data port. If the offset type is Constant, the number of bits is inferred from the phase offset value.

• Memory Type: directs the block to be implemented either with distributed or

block RAM.

FFT

• Use Phase Dithering: when checked, a dither sequence is added to the result

of the phase accumulator.

• Pipeline the DDS: when checked, the implementation is fully pipelined. Other parameters used by this block are described in the Common Parameters section

of the previous chapter.

Xilinx LogiCORE

The DDS block always uses the Xilinx LogiCORE DDS v4.0. The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\dds_v4_0\doc\dds .pdf

The Xilinx FFT Block computes the Discrete Fourier Transform (DFT) using the radix-4 Cooley-Tukey algorithm, explained below:

the vector X(k) = [X(0), X(1), ..., X(N-1)], where the k-th element

DSP 75

The N-point DFT of a complex vector x(n) = [x(0), x(1), ..., x(N-1)], is

N 1–

Xk() xm()W

∑

m 0=

Xilinx System Generator v2.1 Reference Guide

for k=0, 1, ... , N-1, where

is a principal N-th root of unity. The FFT block accepts as input a stream of complex data represented as a pair of

Xilinx ﬁxed point data and computes successive DFTs of nonoverlapping frames of N data samples.

Block Interface

The block interface (inputs and outputs as seen on the FFT icon) are as follows:

Input signals:

xn_r real component of input data stream xi_r imaginary component of input data stream reset reset signal inv 0 for forward transform, 1 for inverse

Output signals:

Xk_r real component of output data stream Xk_i imaginary component of output data stream done active high on ﬁrst output sample in a frame rfd active high when block can accept input data

2π

------

i–()

Block Parameters Dialog Box

The FFT block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-50: FFT block parameters dialog box

Parameters speciﬁc to the FFT block are:

• Number of Sample Points: transform length, one of 16, 64, 256, or 1024.

76 Xilinx Development System

Xilinx Blocks

• Memory Usage: number of memory banks used to compute the transform, one of

Single, Double, Triple (not used for 16 point FFTs).

• Scale Output By: one of 1/N or 1/(2N).

• Overflow characteristic: block behavior when internal overﬂow occurs;

you may choose to invalidate the output (if checkbox is selected) or to stop the simulation in the event of an overﬂow (if checkbox is not selected).

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The FFT block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLABI/O library documentation) explanation for more details.

Block Timing

The timing diagram below illustrates the behavior of the FFT block. The diagram indicates the number of sample periods between the taking of input samples and the production of the output samples for a particular frame. (Note that the timing characteristics depend on the number of points in the FFT and the memory usage mode selected. For triple memory conﬁgurations, the timing numbers are speciﬁed in terms of the output data sample period.)

Figure 3-51: FFT Timing Diagram

DSP 77

Xilinx System Generator v2.1 Reference Guide

64-point

256-point

1024-point

Figure 3-52: FFT Timing Characteristics

For 16-point FFTs, the block is always in the "ready for data" state and output frames are delivered continuously.Thus, there are no stall periods (stall = stall_0 = 0), and the frame variable of the timing diagram defaults to 16 sample periods. There is, however, a pipeline delay (i.e., it takes some time for the ﬁrst output frame to appear) with frame_0 = 84 sample periods.

Single Memory Double Memory Triple Memory

stall_0 = 275

stall = 275

frame_0 = 277

frame = 339

stall_0 = 1074

stall = 1074

frame_0 = 1076

frame = 1330

stall_0 = 5170

stall = 5170

frame_0 = 5172

frame = 6194

stall_0 = 146

stall = 128

frame_0 = 276

frame = 192

stall_0 = 789

stall = 768

frame_0 = 1075

frame = 1024

stall_0 = 4117

stall = 4096

frame_0 = 5171

frame = 5120

stall_0 = 0

stall = 0

frame_0 = 406

frame = 192

stall_0 = 0

stall = 0

frame_0 = 1589

frame = 768

stall_0 = 0

stall = 0

frame_0 = 8246

frame = 4096

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE fft V1.0 (Virtex) or FFT V2.0 (Virtex-II). The number of points supported are N=16, 64, 256, or 1024. The 64, 256, and 1024 point FFTs contain external memories implemented with the LogiCORE Dual Port Block Memory V3.2. The number of memory blocks (either 1, 2, or 3) determines the timing characteristics and size of the implementation. The FFT LogiCOREs support only 16-bit data, although in simulation, the System Generator FFT block supports other data sizes.

The Core datasheets can be found on your local disk at: For Virtex:

%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft\doc\c_ff t1024_v1_0.pdf %XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft\doc\c_ff t16_v1_0.pdf %XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft\doc\c_ff t256_v1_0.pdf %XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft\doc\c_ff t64_v1_0.pdf

For Virtex-II:

%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft_v2_0\doc \vfft1024v2.pdf %XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft_v2_0\doc \vfft16v2.pdf %XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft_v2_0\doc \vfft256v2.pdf %XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\vfft_v2_0\doc \vfft64v2.pdf

78 Xilinx Development System

FIR

Xilinx Blocks

The Dual Port Block Memory LogiCORE datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemdp_v3_2\do c\dp_block_mem.pdf

The Xilinx FIR Filter Block implements a ﬁnite-impulse response (FIR) digital ﬁlter, or a bank of identical FIR ﬁlters (multichannel mode). An

N-tap ﬁlter is deﬁned by N ﬁlter coefﬁcients (or taps) h(0), h(1), ....,h(n-

1). Here each h(i) is a Xilinx ﬁxed point number. The ﬁlter block accepts a stream of Xilinx ﬁxed point data samples x(0),

x(1), ..., and at time n computes the output:

N 1–

yn() hi()xn i–()

∑

i 0=

Block Interface

The FIR block takes one to eight inputs, xi(n): i Xilinx Blockset signal ﬁxed point data samples.

The block produces the same number of output signals, yi(n): i Xilinx Blockset ﬁxed point samples.

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Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-53: FIR block parameters dialog box

Parameters speciﬁc to the block are:

• Coefficients: vector of ﬁlter coefﬁcients; note that these can be evaluated from

a MATLAB workspace variable and may in turn be computed by MATLAB. You can also refer to examples in the System Generator Tutorial.

• Coefficient Structure: Xilinx Smart-IP core preferred implementation

depends on the structure of the sequence of ﬁlter taps. You can choose one of these: inferred from coefﬁcients, none, symmetric, negative symmetric, half band, and interpolate ﬁr.

• Number of bits per coefficient: Xilinx ﬁxed point parameter.

• Binary point for coefficients: Xilinx ﬁxed point parameter.

• Coefficient arithmetic type: Xilinx ﬁxed point parameter.

• Number of Channels: One to eight, inclusive. For multi-channel ﬁlters,

polyphase behavior is not supported, i.e. the ﬁlter must be single rate. The core, which processes the channels serially, will be overclocked by the System Generator by a factor equaling the number of channels so as to provide the necessary throughput. To reduce control logic overhead, the block requires that the valid bits match on all inputs.

80 Xilinx Development System

Xilinx Blocks

• Polyphase behavior: Decimation, Interpolation, Single rate.

• Latency: specify input sample period latency.

• Hardware Over-Sampling Rate: Hardware clocks per sample. This affects

hardware implementation only, and has no effect on simulation. In multi-channel mode, this factor will multiply the implicit oversampling factor.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The FIR ﬁlter block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLAB I/O library documentation) explanation for more details.

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE Distributed Arithmetic FIR Filter V6.0. The Simulink model operates on a sample in/sample out basis, but the core has the

capability of using serial arithmetic by overclocking. Although this adds latency, it has the beneﬁt of reducing the hardware required for the ﬁlter. Refer to the core datasheet for more details of the ﬁlter modes and parameters.

The core datasheet can be found on your local disk at:

Math

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\da_fir_v6_0\doc\ da_fir.pdf

The Math section of the Xilinx Blockset contains mathematical functions.

Accumulator

The Xilinx Accumulator block implements an adder or subtractor based scaling accumulator. The block’s current input is accumulated with a scaled current stored value. The scale factor is a block parameter.

Block Interface

The block has an input b, a reset rst, and an output q. The output must have the same width as the input data. The output q is calculated as follows:

The output must have the same arithmetic type as the input. The block has latency of one sample period.

A subtractor based accumulator replaces addition of the current input subtraction. The output will have the same arithmetic type and binary point position as the input. The block always has a latency of one sample period.

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b(n)

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Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-54: Accumulator block parameters dialog box

Parameters speciﬁc to the block are:

• Number of Bits (output width): speciﬁes the output width which must

match the input width. If the data input does not match the output width, an error is reported.

• Overflow: speciﬁes behavior on internal overﬂow to be Wrap,Saturate, or ﬂag as

an Error.

• Operation: This is a list of two choices: add and subtract. This determines

whether the block is adder or subtractor based.

• Feedback Scaling: speciﬁes the feedback scale factor to be one of the

following: 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, or 1/256.

• Reset to input: when selected, the output of the accumulator is loaded by the

data on input port b whenever the accumulator is reset. When not selected, the output of the accumulator is reset to 0.

The type of the output is the same as that of the input. The block always has a latency of 1.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE Accumulator V5.0. The data width must be between 1 and 258, inclusive.

The Core datasheet can be found on your local disk at:

82 Xilinx Development System

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\accum.pdf

AddSub

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Xilinx Blocks

The Xilinx AddSub block implements an adder/subtractor. The operation can be ﬁxed (Add or Subtract) or changed dynamically under control of the sub mode signal.

Figure 3-55: AddSub block parameters dialog box

Parameters speciﬁc to the AddSub block are:

• Mode: speciﬁes the block operation to be Addition, Subtraction, or Addition/

Subtraction. When Addition/Subtraction is selected, the block operation is determined by the sub input port, which must be driven by a 1-bit unsigned signal. When the sub input is 1, the block performs subtraction. Otherwise, it performs addition.

• Implement with Xilinx Smart-IP Core: when checked, the System

Generator will implement the block as a LogiCORE. Otherwise, it is implemented as a synthesizable VHDL module.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

If the Implement with Xilinx Smart-IP Core checkbox is selected on the parameters dialog box, and if the output width is in the range of 1 to 256, the block

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uses the Xilinx LogiCORE Adder Subtractor V5.0. Otherwise, the block is implemented as a synthesizable VHDL module.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\addsub.pdf

CMult

The Xilinx CMult block implements a gain operator,with output equal to the product of its input by a constant value. This value can be a MATLAB expression that evaluates to a constant.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-56: CMult block parameters dialog box

Parameters speciﬁc to the CMult block are:

• Value of Constant: may be a constant or an expression. If the constant cannot

be expressed exactly in the speciﬁed ﬁxed point type, its value is rounded and

84 Xilinx Development System

Xilinx Blocks

saturated as needed. A positive value is implemented as an unsigned number, a negative value as signed.

• Number of Bits in Constant: speciﬁes the bit location of the binary point of

the constant, where bit zero is the least signiﬁcant bit.

• Multiplier Type: speciﬁes the implementation to be parallel or sequential.

• Memory Type: speciﬁes whether to use distributed RAM or block RAM.

• Require Maximum Pipelining: when checked, directs System Generator to

pipeline the LogiCORE implementation to the fullest extent possible.

• Hardware Over-Sampling Rate: speciﬁes the number of hardware cycles per

input sample; does not affect behavior in simulation, only the hardware implementation.

• Use Placement Information for Core: allows speciﬁcation of placement

layout shape that will be used when implementing the core in hardware

• Placement Style: speciﬁes the layout shape in which the multiplier core will

be placed in hardware. The Rectangular option will generate a rectangular placed core with loosely placed LUTs. Triangular packing will create a more compact shape, with denser placement of LUTs.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

Inverter

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE Multiply Generator V4.0. The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\mult_gen_v4_0\do c\mult_gen.pdf

The Xilinx Inverter block calculates the bitwise logical complement of a ﬁxed point number. The block can be implemented either as a Xilinx LogiCORE or as a synthesizable VHDL module.

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Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-57: Inverter block parameters dialog box

Logical

Parameters used by this block are explained in the Common Parameters section of the previous chapter of the Reference Guide.

Xilinx LogiCORE

The Inverter block uses the Xilinx LogiCORE Bus Gate V5.0 if the Implement with Xilinx Smart-IP Core parameter is checked and the input data width is between

1 and 64, inclusive. Otherwise, the block is implemented as a synthesizable VHDL module.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\bus_gate.pdf

The Xilinx Logical block performs a bit-wise logical operation on 2, 3, or 4 ﬁxed point numbers. Operands are aligned at their respective binary points, zero padded, and sign extended as necessary. The logical operation is performed and produced at the output port.

The block can be implemented either as a Xilinx LogiCORE or as a synthesizable VHDL module. If you build a tree of logical gates, it is typically better to choose the synthesizable implementation so that

logic optimization can be applied during synthesis and mapping.

86 Xilinx Development System

Xilinx Blocks

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-58: Logical block parameters dialog box

Parameters speciﬁc to the block are:

• Logical Function: speciﬁes one of the following bitwise logical operators:

AND, NAND, OR, NOR, XOR, XNOR.

• Number of Inputs: speciﬁes the number of inputs: either 2, 3, or 4.

• Align Binary point: speciﬁes that the block must align binary points

automatically. If not selected, all inputs must have the same binary point position.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

The Logical block uses the Xilinx LogiCORE Bus Gate V5.0 if the Implement with Xilinx Smart-IP Core parameter is checked and the input data width is between

1 and 64, inclusive. Otherwise, the block is implemented as a synthesizable VHDL module.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\bus_gate.pdf

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Mult

The Xilinx Mult block implements a multiplier. It computes the product of the data on its two input ports, producing the result on its output port. The block supports a size-performance tradeoff in its implementation. It can be implemented either as a parallel multiplier that operates on the full width data (faster and larger), or as a sequential multiplier that computes the result from smaller partial products (slower and smaller). Note that this choice affects the

hardware implementation only. The simulation behavior of the block is not affected.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-59: Mult block parameters dialog box - parallel type

88 Xilinx Development System

Xilinx Blocks

Figure 3-60: Mult block parameters dialog box - sequential type

Parameters speciﬁc to the Mult block are:

• Multiplier Type: directs the implementation to be either parallel or

sequential.

• Require Maximum Pipelining: directs the core to be pipelined to the fullest

extent possible.

• Use Dedicated High-Speed Multipliers: when checked, directs the core

to use embedded multipliers (available in Virtex-II only, and when the multiplier type is parallel).

• Hardware Over-Sampling Rate: speciﬁes the number of hardware cycles per

input sample; does not affect behavior in simulation, only the hardware implementation.

• Use Placement Information for Core: allows speciﬁcation of placement

layout shape that will be used when implementing the core in hardware

• Placement Style: speciﬁes the layout shape in which the multiplier core will

be placed in hardware. The Rectangular option will generate a rectangular placed core with loosely placed LUTs. Triangular packing will create a more compact shape, with denser placement of LUTs.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

The Mult block always uses Xilinx LogiCORE: Multiply Generator V4.0. The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\mult_gen_v4_0\do c\mult_gen.pdf

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Negate

The Xilinx Negate block computes the arithmetic negation (two’s complement) of its input.

The block can be implemented either as a Xilinx LogiCORE or as a synthesizable VHDL module.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-61: Negate block parameters dialog box

Parameters used by this block are explained in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

If the Implement with Xilinx Smart-IP Core checkbox is selected and the input width is between 1 and 256, inclusive, the block uses the Xilinx LogiCORE Twos Complementer V5.0. Otherwise, the block is implemented as a synthesizable VHDL module.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\twos_comp.pdf

Relational

The Xilinx Relational block implements a comparator. The supported comparisons are the following:

90 Xilinx Development System

Xilinx Blocks

♦ equal-to (a = b) ♦ not-equal-to (a != b) ♦ less-than (a < b) ♦ greater-than (a > b) ♦ less-than-or-equal-to (a <= b) ♦ greater-than-or-equal-to (a >= b)

The output of the block is a 1-bit unsigned number. It is 1 if the comparison is true and 0 if false.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-62: Relational block parameters dialog box

The only parameter speciﬁc to the Relational block is:

• Comparison Operation: speciﬁes the comparison operation computed by the

block.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

Xilinx LogiCORE

The block uses the Xilinx LogiCORE: Comparator V5.0 if the Implement with Xilinx Smart-IP Core checkbox is selected and the output widths to the block

are between 1 and 64, inclusive. Otherwise, the block is implemented as a synthesizable VHDL module.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do c\compare.pdf

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Scale

The Xilinx Scale block scales its input by a power of two. The power can be either positive or negative. The block has one input and one output. The scale operation has the effect of moving the binary point without changing the bits in the container.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Shift

Figure 3-63: Scale block parameters dialog box

The only parameter that is speciﬁc to the Scale block is Scale Factor. It can be a positive or negative integer. The output of the block is i2k, where i is the input value and k is the scale factor. The effect of scaling is to move the binary point, which in hardware has no cost (a shift, on the other hand, may add logic).

The other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The Scale block does not use a Xilinx LogiCORE.

The Xilinx Shift block performs a left or right shift on the input signal. The result will have the same ﬁxed point container as that of the input.

92 Xilinx Development System

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Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-64: Shift block parameters dialog box

Parameters speciﬁc to the Shift block are:

• Shift Direction: speciﬁes a direction, Left or Right. The Right shift moves the

input toward the least signiﬁcant bit within its container, with appropriate sign extension. Bits shifted out of the container are discarded. The Left shift moves the input toward the most signiﬁcant bit within its container with zero padding of the least signiﬁcant bits. Bits shifted out of the container are discarded.

• Number of Bits: speciﬁes how many bits are shifted. If the number is negative,

direction selected with Shift direction is reversed.

Other parameters used by this block are explained in the Common Parameters section of the previous chapter.

The Shift block does not use a Xilinx LogiCORE.

SineCosine

full period to reduce memory size). The input signal must be an unsigned integer.

The Xilinx Sine Cosine block computes sin(x) and/or cos(x). It stores a reference sinusoid in a read-only memory (ROM), whose depth is deﬁned by the width of the block’s single input port. An N-bit input address results in a logical ROM containing 2N equally spaced samples of one period (the implementation may actually store only a fraction of one

The block can produce a sine or cosine (or its negative) at one output port, or both sine and cosine (or their negatives) at two output ports, depending on customization parameters. Stepping through the memory produces sampled sinusoids on the block’s output port(s), with output frequency determined by the address increment.

Although the error is quite small for practical choices of output width, the implementation is unbalanced; that is, values are stored in the memory as two’s complement numbers having exactly one sign bit. Consequently,sample values of the

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fundamental sinusoid lie in the half-open interval [-1, 1]. If you need a balanced representation, one can be built using the Single Port RAM block with the appropriate initialization vector.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-65: SineCosine block parameters dialog box

Parameters speciﬁc to the SineCosine block are:

• Function: speciﬁes output to be sine, cosine, or both.

• Negative Sine: when selected, the sine output is negated.

• Negative Cosine: when selected, the cosine output is negated.

• Output Width: speciﬁes the number of bits in the output. The valid range is

from 4 to 32, inclusive. The output is stored as a two’s complement value with one integer sign bit. As a result, the range of values stored in the table lies in the halfopen interval [-1, 1].

• Memory Type: directs the block to be implemented either with Distributed or

Block RAM.

• Pipeline the Core: when selected, the implementation is fully pipelined. Other parameters used by this block are described in the Common Parameters section

of the previous chapter.

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE Sine/Cosine Look-Up Table V3.0. The input and output width determine whether the ROM stores a full or quarter wave. The distributed memory case stores a full wave for table depths less than or equal to

94 Xilinx Development System

Xilinx Blocks

64. This corresponds to one CLB per output bit. If the table depth is greater than 64, a quarter wave is stored, and additional logic is used to generate the remaining portions of the wave. Storing only the quarter wave for the large tables reduces the area needed. Block memory stores a full wave for all table depths and widths that can be implemented in a single block memory. Otherwise, values are stored as a quarter wave. Latency for the distributed ROM implementation is determined by the input width, whether or not the block is pipelined, and the given latency value.

The minimum pipeline for block ROM implementations is 1, thus the minimum latency is 1. The maximum latency for block ROM is also 1 except for the cases outlined in the table below.

Input Width Output Width

Greater than 10 Greater than 16 2 Equal to 10 Greater than 4 2 Greater than 9 Greater than 8 2

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\primary\com\xilinx\ip\sincos_v3_0\d oc\C_SIN_COS_V3_0.pdf

Threshold

Input Width

3-6 1-2 7-8 1-4

9-10 1-5

Block Latency Range using

Distributed ROM

Maximum Core

LatencyUsing Block

ROM

The Xilinx Threshold block tests the sign of the input number. If the input number is negative, the output of the block is -1; otherwise, the output is 1. The output is a signed ﬁxed point integer that is 2 bits long. The block has one input and one output.

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Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-66: Threshold block parameters dialog box

The block parameters do not control the output data type because the output is always a signed ﬁxed point integer that is 2 bits long.

All the parameters used by this block are explained in the Common Parameters section of the previous chapter.

MATLAB I/O

Gateway Blocks

The Threshold block does not use a Xilinx LogiCORE.

The MATLAB I/O section includes Xilinx Gateway blocks, the Enabled Subsystem gateway, blocks to report quantization error, and display blocks.

The Xilinx Gateway blocks have several functions:

• Convert data from double precision ﬂoating point to the System Generator ﬁxed

point type and vice versa during Simulink simulation.

• Deﬁne I/O ports for the top level of the HDL design generated by System

Generator. A Gateway In block deﬁnes a top level input port, and a Gateway Out block deﬁnes a top level output port.

• Deﬁne testbench stimuli and predicted output ﬁles when the System Generator

Create Testbench option is selected. In this case, during HDL code generation, Simulink simulation values are logged as logic vectors into a data ﬁle for each top level port deﬁned by a Gateway block. An HDL component is inserted in the top level testbench for each top level port which, during HDL simulation, reads the values from the ﬁle and compares them to the expected results.

• The name speciﬁed for the Gateway In or Gateway Out block is passed on as the

port name on the top level VHDL entity.

Enabled Subsystems

The System Generator infers clock circuitry in its hardware implementation from the sample periods deﬁned in the Simulink model for the Xilinx blocks. This circuitry includes clock (CLK), clock enable (CE), and clear (CLR) ports on registers and Xilinx

96 Xilinx Development System

Xilinx Blocks

LogiCOREs, as well as signals and control circuits to drive the clock network. Consequently, most System Generator blocks do not provide an explicit enable port. There are two exceptions> the Register block and the Addressable Shift Register block, which fundamentally require a CE port in order to target a high performance hardware implementation.

Simulink Enabled Subsystems can be used to enable blocks and subsystems. In order to support System Generator’s bit and cycle true modeling in Simulink, it is required that the enable port on an enabled subsystem be driven by the Enable Adapter block, found in the Xilinx blockset’s MATLAB I/O library.An example of this requirement is shown in the ﬁgure below.This shows an address generation model for a MAC-based FIR ﬁlter. The DownCount subsystem is stalled for a single sample period when the CoefCount counter value is equal to the number of ﬁlter taps (in this case, 96 taps).

Figure 3-67: Example of enabled subsystem

The following blocks cannot be placed in an enabled subsystem with System Generator v2.1. The blocks are: CIC, Convolutional Encoder, FIR, FFT, Gateway In, Gateway Out, RS Decoder, RS Encoder, and Viterbi Decoder.

Enable Adapter

Gateway In

When using an enabled subsystem that contains Xilinx blocks, the enable port must be driven by a Xilinx Enable Adapter block. This block is a required interface to any enabled subsystem that contains a System Generator block. The Enable Adapter block’s output port must drive the subsystem’s enable port.

The Xilinx Gateway In block is the input into the Xilinx FPGA part of your Simulink design. It converts Simulink double precision input to the System Generator ﬁxed point type, and deﬁnes an input port for the top level of the HDL design generated by System Generator.

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The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-68: Gateway In block parameters dialog box

Parameters speciﬁc to the Gateway In block are:

• IOB Timing Constraint: In hardware, a Gateway In is realized as a set of

input/output buffers (IOBs). There are three ways to constrain the timing on IOBs. They are

Attribute

None

is selected, no timing constraints for the IOBs are put in the user

None,Data Rate

, and

Data Rate, Set 'FAST'

constraint ﬁle (.ucf) produced by System Generator. This means the paths from the IOBs to synchronous elements are not constrained.

Data Rate

is selected, the IOBs are constrained at the data rate at which the IOBs operate. The rate is determined by the System Clock Period provided on the System Generator block and the sample rate of the Gateway relative to the other sample periods in the design. For example, the following OFFSET = IN constraints are generated for a Gateway In named 'Din' that is running at the system period of 10 ns:

# Offset in constraints

NET "Din<0>" OFFSET = IN : 10.0 : BEFORE "clk"; NET "Din<1>" OFFSET = IN : 10.0 : BEFORE "clk"; NET "Din<2>" OFFSET = IN : 10.0 : BEFORE "clk"; NET "Din_valid" OFFSET = IN : 10.0 : BEFORE "clk";

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It should be noted there is a valid bit that accompanies the data signal. It is constrained at the same rate. For more information concerning the valid bit, refer to the Hardware Handshaking section in Chapter 1 of this manual.

Data Rate, Set 'FAST' Attribute

constraints described above are produced. In addition, a FAST slew rate attribute is generated for each IOB. This reduces delay but increases noise and power consumption. For the previous example, the following additional attributes are added to the .ucf ﬁle

NET "Din<0>" FAST; NET "Din<1>" FAST; NET "Din<2>" FAST; NET "Din_valid" FAST;

• Specify IOB Location Constraints: Checking this option allows IOB

location constraints to be speciﬁed.

• IOB Pad Locations, e.g. {'Valid Bit', 'MSB', ...., 'LSB'}:

IOB pin locations can be speciﬁed as a cell array of strings in this edit box. The locations are package-speciﬁc. For the above example, if a Virtex-E 2000 in a FG680 package is used, the location constraints for the Din bus can be speciﬁed in the dialog box as {'A36', 'C36', 'B36', 'D35'}. This is translated into constraints in the .ucf ﬁle in the following way:

is selected, the OFFSET = IN

# Loc constraints

NET "Din<0>" LOC = "D35"; NET "Din<1>" LOC = "B36"; NET "Din<2>" LOC = "C35"; NET "Din_valid" LOC = "A36";

Other parameters used by this block are described in the Common Parameters section of the previous chapter.

The Gateway In block cannot be placed in an enabled subsystem in System Generator v2.1. See the Enabled Subsystems section (within the MATLAB I/O library documentation) explanation for more details.

Gateway Out

will be trimmed from the hardware representation.

The Xilinx Gateway Out block is output from the Xilinx FPGA part of your Simulink design. It converts System Generator ﬁxed point data to Simulink double precision. According to its conﬁguration, it can either deﬁne an output port for the top level of the HDL design generated by System Generator, or be used simply as a test point that

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The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.

Figure 3-69: Gateway Out block parameters dialog box

Parameters speciﬁc to the Gateway Out block are:

• IOB Timing Constraint: In hardware, a Gateway Out is realized as a set of

input/output buffers (IOBs). There are three ways to constrain the timing on IOBs. They are

Attribute

None,Data Rate

, and

Data Rate, Set 'FAST'

None

is selected, no timing constraints for the IOBs are put in the user constraint ﬁle (.ucf) produced by System Generator. This means the paths from the IOBs to synchronous elements are not constrained.

Data Rate

is selected, the IOBs are constrained at the data rate at which the IOBs operate. The rate is determined by System Clock Period provided on the System Generator block and the sample rate of the Gateway relative to the other sample periods in the design. For example, the following OFFSET = OUT constraints are generated for a Gateway Out named 'Dout' that is running at the system period of 10 ns:

# Offset out constraints

NET "Dout<0>" OFFSET = OUT : 10.0 : AFTER "clk"; NET "Dout<1>" OFFSET = OUT : 10.0 : AFTER "clk"; NET "Dout<2>" OFFSET = OUT : 10.0 : AFTER "clk"; NET "Dout_valid" OFFSET = OUT : 10.0 : AFTER "clk"; NET "Dout_valid" FAST;

Data Rate, Set 'FAST' Attribute

is selected, the OFFSET = OUT constraints described above are produced. In addition, a FAST slew rate attribute is generated for each IOB. This reduces delay but increases noise and power consumption. For the previous example, the following additional attributes are added to the .ucf ﬁle

NET "Dout<0>" FAST; NET "Dout<1>" FAST;

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