Xilinx® Spartan™-6 LX9
MicroBoard
User Guide
Revision D
Contents
1 Introduction ..................................................................................................................................................... 4
1.1 Description ............................................................................................................................................... 4
1.2 Board Features .......................................................................................................................................... 5
1.3 Reference Designs .................................................................................................................................... 6
1.4 Ordering Information ............................................................................................................................... 7
2 Functional Description .................................................................................................................................... 8
2.1 Xilinx Spartan-6 FPGA LX9 FPGA ........................................................................................................ 9
2.2 Clocks ..................................................................................................................................................... 11
2.2.1 Triple Output User programmable Texas Instruments CDCE913 clock ........................................ 11
2.2.2 Optional 66.6 MHz Maxim low-cost, fixed-frequency oscillator ................................................... 11
2.3 Memory .................................................................................................................................................. 12
2.3.1 32 Mb x 16 (64MB) Micron LPDDR Mobile SDRAM component ............................................... 13
2.3.2 128 Mb Micron Multi-I/O SPI Flash .............................................................................................. 15
2.4 Communication ...................................................................................................................................... 16
2.4.1 Universal Serial Bus (USB) 2.0, Full Speed USB-to-JTAG bridge via Atmel AT90USB162 /
ATMEGA162U2 AVR Microcontroller and TE Connectivity USB-A connector ....................................... 16
2.4.2 USB-UART..................................................................................................................................... 16
2.4.3 10/100 Ethernet PHY via Texas Instruments DP83848J PHY and TE Connectivity RJ45 connector
17
2.5 User I/O and Expansion Connectors ...................................................................................................... 19
2.5.1 Peripheral Module (PMOD) ........................................................................................................... 19
2.6 User Interfaces ........................................................................................................................................ 20
2.6.1 User LEDs ....................................................................................................................................... 20
2.6.2 Four configurable FPGA user DIP switches (TE Connectivity 1571983-4) .................................. 20
2.6.3 One configurable FPGA user push-button (TE Connectivity 8-1437565-0) .................................. 20
2.7 Power ...................................................................................................................................................... 21
2.7.1 Power Good LED ............................................................................................................................ 21
2.7.2 FPGA Decoupling ........................................................................................................................... 22
2.7.3 Power Results.................................................................................................................................. 23
2.8 Configuration ......................................................................................................................................... 24
2.8.1 Configuration Modes ...................................................................................................................... 24
2.8.2 Digilent On-board JTAG Boundary Scan Configuration ............................................................... 24
2.8.3 Multi-I/O SPI Flash Configuration ................................................................................................. 24
2.8.4 JTAG Chain .................................................................................................................................... 24
3 Test Design .................................................................................................................................................... 25
4 Acknowledgements ....................................................................................................................................... 26
5 Getting Help and Support .............................................................................................................................. 27
6 Revision History ............................................................................................................................................ 28
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Figures
Figure 1 – Spartan-6 FPGA LX9 MicroBoard Front .............................................................................................. 6
Figure 2 – Spartan-6 FPGA LX9 MicroBoard Back .............................................................................................. 6
Figure 3 – Spartan-6 FPGA LX9 MicroBoard Block Diagram .............................................................................. 8
Figure 4 – XC6SLX9 CSG324 I/O Allocation ................................................................................................ 10
Figure 5 – Spartan-6 FPGA LX9 MicroBoard Memory Interfaces ...................................................................... 12
Figure 6 – Spartan-6 FPGA LX9 LPDDR Mobile SDRAM Interface ................................................................. 13
Figure 7 – 10/100 Ethernet Interface .................................................................................................................... 17
Figure 8 – PMOD Connector Pinout .................................................................................................................... 19
Figure 9 – TPS65708 Connections ....................................................................................................................... 21
Figure 10 – Xilinx Ribbon Cable JTAG Connector ............................................................................................. 24
Tables
Table 1 – Ordering Information .............................................................................................................................. 7
Table 2 – CDCE913 Clocks .................................................................................................................................. 11
Table 3 – CDCE913 I2C ....................................................................................................................................... 11
Table 4 – 66 MHz Clock ....................................................................................................................................... 11
Table 5 – LPDDR Timing Parameters .................................................................................................................. 14
Table 6 – FPGA SPI Interface Pinout ................................................................................................................... 15
Table 7 – USB-JTAG Signals ............................................................................................................................... 16
Table 8 – USB-to-UART Pin Locations ............................................................................................................... 16
Table 9 – 10/100 Pin Assignments ....................................................................................................................... 18
Table 10 – Peripheral Module Connections – J4 .................................................................................................. 19
Table 11 – Peripheral Module Connections – J5 .................................................................................................. 19
Table 12 – LED Pin Assignments ......................................................................................................................... 20
Table 13 – FPGA Dip Switches ............................................................................................................................ 20
Table 14 – FPGA Push Button.............................................................................................................................. 20
Table 15 – S6LX9 MicroBoard Capacitors for XC6SLX9-CSG324 ................................................................... 22
Table 16 – S6LX9 Board Capacitor Quantities for XC6SLX9-CSG324 ............................................................. 22
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1 Introduction
The purpose of this manual is to describe the functionality and contents of the Avnet Spartan-6 FPGA LX9
MicroBoard from Avnet Electronics Marketing. This document includes instructions for operating the board,
descriptions of the hardware features, and explanations of the test code programmed into the on-board
programmable memory. For reference design documentation and example projects, see the Avnet Design
Resource Center (DRC).
DRC Home Page: www.em.avnet.com/drc
Spartan-6 FPGA LX9 MicroBoard Kit Home Page www.em.avnet.com/s6microboard
1.1 Description
The Spartan-6 FPGA LX9 MicroBoard provides a complete hardware environment for designers to accelerate
their time to market. The kit delivers a stable platform to develop and test designs targeted to the low-cost and
low-power Xilinx Spartan-6 FPGA. The installed Spartan-6 FPGA LX9 device offers a prototyping
environment to effectively demonstrate the enhanced benefits of low-cost Xilinx FPGA solutions. Reference
designs are included with the kit to exercise standard peripherals on the evaluation board for a quick start to
device familiarization.
The Spartan-6 FPGA LX9 MicroBoard kit contains the following individual pieces:
Avnet Spartan-6 FPGA LX9 MicroBoard
Type A male to Type A female USB Extension Cable
Type A to Micro-B USB Cable
Xilinx ISE® Design Suite WebPACK edition
License voucher for ChipScope™ Pro, XPS, and SDK (device-locked to XC6SLX9)
Welcome Letter
Getting Started Guide
Please note that this kit does NOT include a 10/100 Ethernet cable.
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1.2 Board Features
FPGA
o Xilinx Spartan-6 XC6SLX9-2CSG324C FPGA
Clocks
o Triple Output, user programmable, Texas Instruments CDCE913 clock
Pre-programmed during manufacturing
Spread-spectrum enabled
o Optional user installable Maxim DS1088LU-66+, low-cost, fixed-frequency oscillator
Memory
o 32 Mb x 16 (512 Mb) Micron LPDDR Mobile SDRAM component
o 128 Mb Micron Multi-I/O SPI Flash
Communication
o One USB 2.0, Full Speed USB-to- JTAG bridge via Atmel AT90USB162 / ATMEGA162U2,
Digilent JTAG firmware, and TE Connectivity USB-A connector
o One USB 2.0, Full Speed USB-to-UART bridge via Silicon Labs CP2102 and TE Connectivity
Micro-B connector
o One 10/100 Ethernet port via Texas Instruments DP83848J PHY and TE Connectivity RJ45
connector with Integrated Magnetics
User I/O and Expansion Connectors
o Two Digilent 12-pin, 0.245mm pitch, Peripheral Module (PMOD) headers support 3rd party
expansion modules
User Interfaces
o Four user LEDs
o Four configurable FPGA user DIP switches
o Two system push-button switches: one tied to user I/O and used for logical reset in the factory
test image, one hard-wired for FPGA program initialization
Power
o Texas Instruments TPS65708 PMU multi-channel regulator, with 5V input supplied by either
USB connection
Configuration
o Micron N25Q128 128Mb SPI Configuration Flash
o On-board USB Programming/Configuration based on the Digilent USB Full Speed JTAG design
utilizing the Atmel AT90USB162 / ATMEGA162U2
o Xilinx Compatible JTAG Cable
Test Files
o Files that are used to factory test the Spartan-6 FPGA LX9 MicroBoard are available and can be
found on the Avnet Electronics Marketing Design Resource Center (DRC) web site:
www.em.avnet.com/s6microboard
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1.3 Reference Designs
Reference designs that demonstrate some of the potential applications of the Spartan-6 FPGA LX9 MicroBoard
are available and can be found on the Avnet Electronics Marketing Design Resource Center (DRC) web site:
www.em.avnet.com/s6microboard. See the PDF document included with each reference design for a complete
description of the design and detailed instructions for running a demonstration on the development board.
Check the DRC periodically for updates and new designs. The Expanded Getting Started Guide, available for
download from the DRC, is the best place to start.
Figure 1 – Spartan-6 FPGA LX9 MicroBoard Front
Figure 2 – Spartan-6 FPGA LX9 MicroBoard Back
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1.4 Ordering Information
The following table lists the evaluation kit part numbers and available software options.
Table 1 – Ordering Information
Part Number Hardware
AES-S6MB-LX9-G Xilinx Spartan-6 FPGA LX9 MicroBoard
HW-USB-II-G Xilinx Platform Cable USB-II
210-299P-KIT Digilent HS3 JTAG Cable
EF-EDK-NL EDK Upgrade for ISE WebPack
EF-ISE-EMBD-NL ISE Embedded Edition
EF-ISE-SYSTEM-NL ISE System Edition
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2 Functional Description
A Xilinx Spartan-6 FPGA LX9 (XC6SLX9-2CSG324) FPGA is the primary component of the Avnet Spartan-6
FPGA LX9 MicroBoard. A 10/100 Ethernet port and two Full Speed USB interfaces provide means of offboard communication. On-board memory consists of a 256 Mbit x 16 LPDDR mobile SDRAM component and
a 128 Mbit Multi-I/O SPI Flash that may be used by the FPGA for configuration.
A high-level block diagram of the Spartan-6 FPGA LX9 MicroBoard is shown below followed by a brief
description of each sub-section.
Figure 3 – Spartan-6 FPGA LX9 MicroBoard Block Di agram
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2.1 Xilinx Spartan-6 FPGA LX9 FPGA
The Xilinx XC6SLX9-2CSG324C device designed onto the Spartan-6 FPGA LX9 MicroBoard is a member of
the logic-optimized Xilinx Spartan-6 LX FPGA family. This family is built on a mature 45 nm low-power
copper process technology that delivers the optimal balance of cost, power, and performance. The Spartan-6
LX family offers a new, more efficient, dual-register 6-input look-up table (LUT) logic and a rich selection of
built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices,
SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology,
advanced system-level power management modes, auto-detect configuration options, and enhanced IP security
with Device DNA protection. These features provide a low-cost programmable alternative to custom ASIC
products with unprecedented ease-of-use. Spartan-6 FPGAs offer the best solution for high-volume logic
designs, consumer-oriented DSP designs, and cost-sensitive embedded applications.
On the Avnet Spartan-6 FPGA LX9 MicroBoard, the FPGA provides four I/O banks. Banks 0, 1, and 2 VCCO
as well as the VCCAUX power rail are tied to 3.3V. This allows Bank 0 to interface to 3.3V user I/O, Bank 1 to
interface to 3.3V Ethernet I/O, and Bank 2 to interface to 3.3V configuration I/O. Bank 3 interfaces to the
LPDDR memory and is connected to a 1.8V power rail for low-power consumption memory designs. The
VCCINT power rail is connected to 1.2V.
The four I/O banks are described in
Figure 4 and detailed I/O pin usage is provided throughout this document.
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