Texas Instruments JM38510-37701BEA, JM38510-37701B2A, SN54ALS138AJ, SN54AS138J, SN74ALS138AD Datasheet
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SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDAS055E – APRIL 1982 – REVISED JUL Y 1996
D
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
D
Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
SN54ALS138A, SN54AS138 ...J PACKAGE
SN74ALS138A, SN74AS138 ...D OR N PACKAGE
G2A
G2B
G1
Y7
GND
(TOP VIEW)
A
1
B
2
C
3
4
5
6
7
8
16
15
14
13
12
11
10
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
9
The ′ALS138A and ′AS138 are 3-line to 8-line
decoders/demultiplexers designed for highperformance memory-decoding or data-routing
SN54ALS138A, SN54AS138 . . . FK PACKAGE
(TOP VIEW)
applications requiring very short propagation
delay times. In high-performance systems, these
devices can be used to minimize the effects of
system decoding. When employed with
high-speed memories with a fast enable circuit,
the delay times of the decoder and the enable time
of the memory are usually less than the typical
access time of the memory . The ef fective system
delay introduced by the Schottky-clamped system
decoder is negligible.
The conditions at the binary-select (A, B, and C)
inputs and the three enable (G1, G2A
, and G2B)
inputs select one of eight output lines. Two
BANC
3 2 1 20 19
C
4
NC
G1
5
6
7
8
910111213
Y7
G2A
G2B
NC – No internal connection
GND
NC
CC
V
Y6
Y0
18
17
16
15
14
Y5
Y1
Y2
NC
Y3
Y4
active-low and one active-high enable inputs
reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without
external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input
for demultiplexing applications.
The SN54ALS138A and SN54AS138 are characterized for operation over the full military temperature range
of –55°C to 125°C. The SN74ALS138A and SN74AS138 are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138
OUTPUTS
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDAS055E – APRIL 1982 – REVISED JUL Y 1996
FUNCTION TABLE
INPUTS
ENABLE SELECT
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HL LHHHHHHHHHHL
logic symbols (alternatives)
1
A
2
B
3
C
6
G1
4
G2A
5
G2B
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
BIN/OCT
1
2
4
&
EN
†
15
0
1
2
3
4
5
6
7
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
9
Y6
7
Y7
G1
G2A
G2B
1
A
2
B
3
C
6
4
5
DMUX
0
G
2
&
0
0
1
7
2
3
4
5
6
7
15
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
9
Y6
7
Y7
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
A
Select
Inputs
Enable
Inputs
G2A
G2B
G1
2
B
3
C
4
5
6
SN54ALS138A, SN54AS138, SN74ALS138A, SN74AS138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SDAS055E – APRIL 1982 – REVISED JUL Y 1996
15
Y0
14
Y1
13
Y2
12
11
10
Y3
Y4
Y5
9
Y6
7
Y7
Data
Outputs
Pin numbers shown are for the D, J, and N packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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