Texas Instruments DUAL-DIYAMP-EVM User Manual

User's Guide
SBOU193–July 2017
DUAL-DIYAMP-EVM
Contents
1 Introduction ................................................................................................................... 3
1.1 DUAL-DIYAMP-EVM Kit Contents................................................................................ 3
1.2 Features.............................................................................................................. 3
1.3 List of Circuits on EVM............................................................................................. 3
2 Hardware Setup.............................................................................................................. 3
2.1 EVM Circuit Locations.............................................................................................. 4
2.2 EVM Assembly Instructions ....................................................................................... 5
3 Schematic and PCB Layout ................................................................................................ 6
3.1 Schematic PCB Drawing........................................................................................... 6
3.2 Non-Inverting Amplifier............................................................................................. 7
3.3 Inverting Amplifier................................................................................................... 8
3.4 Difference Amplifier With Reference Buffer ................................................................... 10
3.5 Multiple Feedback Active Filter.................................................................................. 11
3.6 Sallen-Key Filter................................................................................................... 12
3.7 Riso With Dual-Feedback........................................................................................ 13
3.8 Two Op-Amp Instrumentation Amplifier ........................................................................ 14
3.9 Single-Ended Input to Differential Output ...................................................................... 16
3.10 Parallel Op Amps.................................................................................................. 17
3.11 Differential Input to Differential Output ......................................................................... 18
4 Connections................................................................................................................. 19
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4.1 Inputs and Outputs................................................................................................ 19
4.2 Power ............................................................................................................... 22
5 Bill of Materials and References ......................................................................................... 22
5.1 Bill of Materials .................................................................................................... 22
5.2 References......................................................................................................... 22
List of Figures
1 Circuit Configuration Location.............................................................................................. 4
2 Detach Desired Circuit Configuration ..................................................................................... 5
3 Detach Configuration With Attached IC and Passive Components................................................... 5
4 Terminal Strip (TS-132-G-AA) Broken Into 4-Pin Lengths ............................................................. 5
5 4-Pin Length Terminal Strips Inserted in DIP Socket................................................................... 5
6 Detached Board Configuration Position Over Terminal Pins .......................................................... 6
7 Fully-Assembled Circuit Configuration From DIYAMP-SOIC-EVM.................................................... 6
8 Silk Screen Schematic ...................................................................................................... 6
9 Non-Inverting Amplifier Schematic ........................................................................................ 7
10 Non-Inverting Amplifier Top Layer PCB Layout ......................................................................... 8
11 Inverting Amplifier Schematic .............................................................................................. 8
12 Inverting Amplifier Top Layer PCB Layout ............................................................................... 9
13 Difference Amplifier with Reference Buffer Schematic................................................................ 10
14 Difference Amplifier with Reference Buffer Top Layer PCB Layout ................................................. 11
15 Multiple Feedback Active Filter Schematic ............................................................................. 11
16 Multiple Feedback Active Filter Top Layer PCB Layout .............................................................. 12
17 Sallen-Key Active Filter Schematic ...................................................................................... 12
18 Sallen-Key Active Filter PCB Layout .................................................................................... 13
19 Riso With Dual-Feedback Schematic.................................................................................... 13
20 Riso With Dual-Feedback PCB Layout.................................................................................. 14
21 Two Op-Amp Instrumentation Amplifier Schematic.................................................................... 14
22 Two Op-Amp Instrumentation Amplifier Top Layer PCB Layout..................................................... 15
23 Single-Ended Input to Differential Output Schematic.................................................................. 16
24 Single-Ended Input to Differential Output Top Layer PCB Layout................................................... 16
25 Parallel Op Amp Schematic............................................................................................... 17
26 Parallel Op-Amp Top Layer PCB Layout................................................................................ 18
27 Differential Input to Differential Output Schematic..................................................................... 18
28 Differential Input to Differential Output Top Layer PCB Layout ...................................................... 19
29 SMA Vertical Connectors ................................................................................................. 19
30 SMA Horizontal Connectors .............................................................................................. 20
31 Wire Connections .......................................................................................................... 20
32 Through-Hole Test Points................................................................................................. 20
33 Input and Output Labeled as INA, INB and OUTA and OUTB....................................................... 21
34 Input and Output Labeled as Vin and Vout............................................................................. 21
35 Wire Alternative for Terminal Area ....................................................................................... 22
1 DUAL-DIYAMP-EVM Kit Contents ........................................................................................ 3
2 Circuit Configuration Location Legend.................................................................................... 4
3 MFB Filter Type Component Selection.................................................................................. 11
4 Sallen-Key Filter Component Type Selection .......................................................................... 12
5 DUAL-DIYAMP-EVM Bill of Materials ................................................................................... 22
2
DUAL-DIYAMP-EVM
List of Tables
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Trademarks
FilterPro is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
1 Introduction
The DUAL-DIYAMP-EVM is an EVM developed for dual package op amps to give users the ability to easily evaluate amplifier circuits. This “break apart” EVM has several popular op-amp configurations including amplifiers, filters, stability compensation, and other signal conditioning circuits that require two amplifiers. The EVM is designed for 0805 and 0603 package size surface mount components enabling easy prototyping. This board gives the user the ability to build anything from a simple amplifier to complex signal chains by combining different configurations.
1.1 DUAL-DIYAMP-EVM Kit Contents
Table 1 details the contents included in the DUAL-DIYAMP-EVM kit.
Table 1. DUAL-DIYAMP-EVM Kit Contents
Item Description Quantity
DUAL-DIYAMP-EVM PCB 1
Header Strip 100-mil (2.54 mm) spacing, 32 position, through hole 2
1.2 Features
The EVM has the following features:
Multiple circuit configurations
Breadboard compatible
Schematic provided in silk screen on the PCB
Multiple connector options for the input and output connections: SMA, test point, and wires.
Introduction
1.3 List of Circuits on EVM
The EVM has the following circuits:
Non-inverting amplifier
Inverting amplifier
Difference amplifier with reference buffer
Multiple feedback active filter
Sallen-Key filter
Riso with dual feedback
Two op amp instrumentation amplifier
Single-ended input to differential output
Parallel op amps
Differential input to differential output
2 Hardware Setup
Assembly of the DUAL-DIYAMP-EVM involves identifying and breaking out the desired circuit configuration from the EVM, soldering the components, header strip, and input and output connections. This section presents the details of these procedures.
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A A B B
C C D D
E E F F
G H
I
J
Hardware Setup
2.1 EVM Circuit Locations
Figure 1 and Table 2 map the location of each circuit configuration on the EVM. Figure 1 labels each
circuit configuration with a letter ranging from A to J. Table 2 matches the circuit configuration to a letter in
Figure 1 and also provides the name of each individual circuit written in silk screen on the EVM.
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Circuit Name Silk Screen Label Letter in Figure 1
Non-inverting amplifier Non-inverting Amplifier A Inverting amplifier Inverting Amplifier B
4
Difference amplifier with reference buffer Difference Amp C Multiple feedback filter MFB - Filter D Sallen-Key filter SK Filter E Riso with dual feedback Riso Dual Feedback F Two op amp instrumentation amplifier 2 Op Amp INA G Single-ended input to differential output SE to Diff H Parallel op amps Parallel Op Amps I Differential input to differential output Diff In Diff Out J
DUAL-DIYAMP-EVM
Figure 1. Circuit Configuration Location
Table 2. Circuit Configuration Location Legend
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2.2 EVM Assembly Instructions
This section has step-by-step instructions on how to assemble a circuit configuration from the EVM.
1. Choose the desired circuit configuration. See Section 2.1 for the location of each circuit configuration.
2. Gently flex the PCB panel at the score lines to separate the desired circuit configuration from the EVM.
Figure 2. Detach Desired Circuit Configuration
3. Solder device and surface mount passive components to the separated PCB.
Hardware Setup
Figure 3. Detach Configuration With Attached IC and Passive Components
4. Use long-nose pliers to break header strips, provided in the EVM kit, into 8-position lengths.
Figure 4. Terminal Strip (TS-132-G-AA) Broken Into 4-Pin Lengths
5. Insert header strips into a spare DIP socket as shown in Figure 5.
Figure 5. 4-Pin Length Terminal Strips Inserted in DIP Socket
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Schematic and PCB Layout
6. Position separated PCB over pins and solder the connections. Carefully remove from the DIP socket.
Figure 6. Detached Board Configuration Position Over Terminal Pins
7. Attach SMA connectors, test points, or wires to the inputs and outputs of the separated PCB.
Figure 7. Fully-Assembled Circuit Configuration From DIYAMP-SOIC-EVM
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3 Schematic and PCB Layout
This section provides the schematic and PCB layout of each circuit configuration provided on the EVM.
3.1 Schematic PCB Drawing
Each circuit board has the schematic of the circuit in silk screen located on the back of the PCB for easy reference. Figure 8 displays an example of a schematic on the back of the PCB.
Figure 8. Silk Screen Schematic
6
DUAL-DIYAMP-EVM
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c
1/4 2/6
1
2 R C
=
´ p ´ ´
f
1/4
2/ 5
R
OUTA / B 1 INA / B
R
æ ö
= +
ç ÷ è ø
+
±
C3/7
R2/5 R1/4
R3/6
C4/8
OUTA/B
INA/B
V+
C1
REFA/B
C2/6
C5
V-
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3.2 Non-Inverting Amplifier
Figure 9 displays the schematic for the non-inverting amplifier circuit configuration.
The non-inverting amplifier circuit configuration takes an input signal that is applied directly to the high impedance non-inverting input and outputs a signal that is the same polarity as the input signal. The feedback network for this topology is R1, R2, C2, and C3 for channel A and R4, R5, C6, and C7 for channel B.
There are multiple ways to configure the non-inverting amplifier circuit configuration. The following cases show the two primary use-case configurations for this circuit.
Case 1: Standard non-inverting circuit
This circuit can be configured into a standard non-inverting circuit by shorting C4/8 and C3/7 with a 0- resistor and leaving R3/6 unpopulated.
Equation 1 displays the transfer function of the non-inverting amplifier circuit configuration shown in Figure 9.
Schematic and PCB Layout
Figure 9. Non-Inverting Amplifier Schematic
where
C
C
R
is shorted with a 0-resistor
4/8
is shorted with a 0-resistor
3/7
is unpopulated (1)
3/6
Capacitor C2 for channel A and C6 for channel B provide the option to filter the output. The cutoff frequency of the filter can be calculated using Equation 2.
Case 2: AC-coupled, non-inverting amplifier configuration
This circuit board can be configured as an ac-coupled, non-inverting circuit by populating C4/8 and C3/7 with capacitors and populating R3/6 with resistors. Test points REFA for channel A and REFB for channel B are used to set the dc biasing of the circuit. The dc bias voltage is typically set to one half of the supply voltage of the amplifier.
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(2)
7
+
±
C4/7
R3/8 R2/7
R4/9
R5/10 C5/8
OUTA/B
INA/B
V+
C1
REFA/B
C3/6
R1/6
V-
C2
c
3/ 7 2/5
1
2 C R
=
´ p ´ ´
f
c
4/ 8 3 /6
1
2 C R
=
´ p ´ ´
f
Schematic and PCB Layout
Populating C4/8 with capacitors ac couples the input of the circuit. The corner frequency of the high-pass filter created by C4/8 and R3/6 is calculated in Equation 3:
Similarly, capacitor C3/7 creates a high-pass filter with R2/5. The corner frequency of the high-pass filter created by C3/7 and R2/5 is calculated in Equation 4.
Figure 10 displays the PCB layout of the top layer of the non-inverting amplifier circuit configuration.
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(3)
(4)
Figure 10. Non-Inverting Amplifier Top Layer PCB Layout
3.3 Inverting Amplifier
Figure 11 shows the schematic for the inverting amplifier circuit configuration.
The inverting amplifier configuration takes an input signal and outputs a signal that is the opposite polarity as the input signal. The benefit of this topology is that it avoids common mode limitations. The ratio of the resistors in the feedback network will determine the amount of gain the input signal will be amplified by.
The inverting amplifier circuit configuration provides the option to ac couple the input, filter the output, and bias the output of the amplifier to a desired value.
Figure 11. Inverting Amplifier Schematic
8
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c _REF
5/8 4/9 5/10
1
2 C R / /R
=
´ p ´ ´
f
c _OUT
3/ 6 2/7
1
2 C R
=
´ p ´ ´
f
c _highpass
4/7 3 /8
1
2 C R
=
´ p ´ ´
f
5/10
4/ 9 5 /10
R
OUTA / B REFA / B
R R
æ ö
=
ç ÷
+
è ø
5/10
2/ 7 2/7
3/ 8 4/9 5/10 3/ 8
R
R R
OUTA / B INA / B 1 REFA / B
R R R R
æ ö æ öæ ö
= - + +
ç ÷ ç ÷ç ÷
+
è ø è øè ø
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Equation 5 displays the dc transfer function of the inverting amplifier circuit configuration.
Capacitor C4 for channel A and C7 for channel B provide the option to ac couple the input of the circuit.
Equation 6 displays the dc transfer function of the ac-coupled inverting amplifier circuit configuration.
Equation 7 calculates the cut-off frequency of the high-pass filter.
Capacitors C3 and C6 provide the option to filter the output. Equation 8 calculates the cut-off frequency of the filter.
Capacitor C5 for channel A and C8 for channel B provide the option to filter noise introduced from the reference voltage, REFA/B. Equation 9 calculates the cutoff frequency of the filter.
where
C
is shorted with a 0-resistor (5)
4/7
where
The input is ac coupled with C
Schematic and PCB Layout
4/7
(6)
(7)
(8)
Figure 12 displays the PCB layout of the top layer of the inverting amplifier circuit configuration.
Figure 12. Inverting Amplifier Top Layer PCB Layout
(9)
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