Texas Instruments DS90LV012A, DS90LT012A Datasheet

DS90LT012A, DS90LV012A

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DS90LV012A /DS90LT012A 3V LVDS Single CMOS Differential Line Receiver

Check for Samples: DS90LT012A, DS90LV012A

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FEATURES

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• Compatible with ANSI TIA/EIA-644-A Standard

• >400 Mbps (200 MHz) switching rates

• 100 ps differential skew (typical)

• 3.5 ns maximum propagation delay

• Integrated line termination resistor (102Ω
typical)

• Single 3.3V power supply design (2.7V to 3.6V
range)

• Power down high impedance on LVDS inputs

• Accepts small swing (350 mV typical)
differential signal levels

• LVDS receiver inputs accept
LVDS/BLVDS/LVPECL inputs

• Supports open, short and terminated input fail­safe

• Pinout simplifies PCB layout

• Low Power Dissipation (10mW typical@ 3.3V
static)

• SOT-23 5-lead package

• Leadless WSON-8 package (3x3 mm body size)

• Electrically similar to the DS90LV018A

• Fabricated with advanced CMOS process
technology

• Industrial temperature operating range (−40°C
to +85°C)

SNLS141D –AUGUST 2002–REVISED APRIL 2013

DESCRIPTION

The DS90LV012A and DS90LT012A are single
CMOS differential line receivers designed for
applications requiring ultra low power dissipation, low
noise, and high data rates. The devices are designed
to support data rates in excess of 400 Mbps (200
MHz) utilizing Low Voltage Differential Swing (LVDS)
technology

The DS90LV012A and DS90LT012A accept low
voltage (350 mV typical) differential input signals and
translates them to 3V CMOS output levels. The
receivers also support open, shorted, and terminated
(100Ω) input fail-safe. The receiver output will be
HIGH for all fail-safe conditions. The DS90LV012A
has a pinout designed for easy PCB layout. The
DS90LT012A includes an input line termination
resistor for point-to-point applications.

The DS90LV012A and DS90LT012A, and companion
LVDS line driver provide a new alternative to high
power PECL/ECL devices for high speed interface
applications.

Connection Diagram

See Package Number DBV (R-PDSO-G5)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Figure 1. Top View

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DS90LT012A, DS90LV012A

SNLS141D –AUGUST 2002–REVISED APRIL 2013

Functional Diagram

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Figure 2. Top View

See Package Number NGK0008A

Figure 3. DS90LV012A

Figure 4. DS90LT012A

Truth Table

INPUTS OUTPUT

[IN+] − [IN−] TTL OUT

VID≥ 0V H

VID≤ −0.1V L

Full Fail-safe OPEN/SHORT or Terminated H

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings

Supply Voltage (VDD) −0.3V to +4V
Input Voltage (IN+, IN−) −0.3V to +3.9V
Output Voltage (TTL OUT) −0.3V to (VDD+ 0.3V)
Output Short Circuit Current −100mA
Maximum Package Power Dissipation @ +25°C

NGK Package 2.26 W
Derate NGK Package 18.1 mW/°C above +25°C
Thermal resistance (θJA) 55.3°C/W
DBV Package 902mW
Derate DBV Package 7.22 mW/°C above +25°C

Thermal resistance (θJA) 138.5°C/W
Storage Temperature Range −65°C to +150°C
Lead Temperature Range Soldering (4 sec.) +260°C
Maximum Junction Temperature +150°C
ESD Ratings

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply

that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.

(2) ESD Ratings:

(a) DS90LV012A:

(b) DS90LT012A:

(2)

(a) HBM (1.5 kΩ, 100 pF) ≥ 2kV
(b) EIAJ (0Ω, 200 pF) ≥ 900V
(c) CDM ≥ 2000V
(d) IEC direct (330Ω, 150 pF) ≥ 5kV

(a) HBM (1.5 kΩ, 100 pF) ≥ 2kV
(b) EIAJ (0Ω, 200 pF) ≥ 700V
(c) CDM ≥ 2000V
(d) IEC direct (330Ω, 150 pF) ≥ 7kV

(1)

SNLS141D –AUGUST 2002–REVISED APRIL 2013

Recommended Operating Conditions

Min Typ Max Units

Supply Voltage (VDD) +2.7 +3.3 +3.6 V

Operating Free Air Temperature (TA) −40 25 +85 °C

Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

unless otherwise specified (such as VID).

(2) All typicals are given for: VDD= +3.3V and TA= +25°C.

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(1) (2)

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Electrical Characteristics (continued)

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

Symbol Parameter Conditions Pin Min Typ Max Units

IN−
IN−

(3)

DD

= +0V
= +2.0V

V
V
V

Differential Input High Threshold VCMdependant on V

TH

Differential Input Low Threshold −100 −30 mV

TL

Common-Mode Voltage VDD= 2.7V, VID= 100mV 0.05 2.35 V

CM

VDD= 3.0V to 3.6V, VID= 100mV 0.05 VDD- 0.3V V

I

IN

Input Current (DS90LV012A) VIN= +2.8V VDD= 3.6V or 0V −10 ±1 +10 μA

VIN= 0V −10 ±1 +10 μA
VIN= +3.6V VDD= 0V −20 +20 μA

ΔI

Change in Magnitude of I

IN

IN

VIN= +2.8V VDD= 3.6V or 0V 4 μA
VIN= 0V 4 μA
VIN= +3.6V VDD= 0V 4 μA

I

R

C
V

IND

Differential Input Current V
(DS90LT012A) V
Integrated Termination Resistor

T

(DS90LT012A)
Input Capacitance IN+ = IN− = GND 3 pF

IN

Output High Voltage IOH= −0.4 mA, VID= +200 mV TTL OUT 2.4 3.1 V

OH

= +0.4V, V

IN+

= +2.4V, V

IN+

IOH= −0.4 mA, Inputs terminated 2.4 3.1 V

IOH= −0.4 mA, Inputs shorted 2.4 3.1 V
V
I

OS

V
I

DD

Output Low Voltage IOL= 2 mA, VID= −200 mV 0.3 0.5 V

OL

Output Short Circuit Current V
Input Clamp Voltage ICL= −18 mA −1.5 −0.7 V

CL

OUT

= 0V

(4)

No Load Supply Current Inputs Open V

(3) VDDis always higher than IN+ and IN− voltage. IN+ and IN− are allowed to have voltage range −0.05V to +2.35V when VDD= 2.7V and

|VID| / 2 to VDD− 0.3V when VDD= 3.0V to 3.6V. VIDis not allowed to be greater than 100 mV when VCM= 0.05V to 2.35V when VDD=

2.7V or when VCM= |VID| / 2 to VDD− 0.3V when VDD= 3.0V to 3.6V.

(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted

at a time, do not exceed maximum junction temperature specification.

(1) (2)

IN+, IN− −30 0 mV

3 3.9 4.4 mA

102 Ω

−15 −50 −100 mA

DD

5.4 9 mA

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SNLS141D –AUGUST 2002–REVISED APRIL 2013

Switching Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

t

PHLD

t

PLHD

t

SKD1

t

SKD3

t

SKD4

t

TLH

t

THL

f

MAX

(1) CLincludes probe and jig capacitance.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50Ω, trand tf(0% to 100%) ≤ 3 ns for IN±.
(3) t

(4) t
(5) t

(6) f

Differential Propagation Delay High to Low CL= 15 pF 1.0 1.8 3.5 ns
Differential Propagation Delay Low to High VID= 200 mV 1.0 1.7 3.5 ns
Differential Pulse Skew |t

PHLD

Differential Part to Part Skew
Differential Part to Part Skew

− t

(4)
(5)

PLHD

(3)

|

(Figure 5 and Figure 6) 0 100 400 ps

Rise Time 350 800 ps
Fall Time 175 800 ps
Maximum Operating Frequency

is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of

SKD1

the same channel.

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices

SKD3

at the same VDDand within 5°C of each other within the operating temperature range.

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices

SKD4

over the recommended operating temperature and voltage ranges, and across process distribution. t

(6)

differential propagation delay.

generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria:

MAX

60%/40% duty cycle, VOL(max 0.4V), VOH(min 2.4V), load = 15 pF (stray plus probes). The parameter is ensured by design. The limit
is based on the statistical analysis of the device over the PVT range by the transition times (t

(1) (2)

TLH

0 0.3 1.0 ns
0 0.4 1.5 ns

200 250 MHz

is defined as |Max − Min|

SKD4

and t

).

THL

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PARAMETER MEASUREMENT INFORMATION

Figure 5. Receiver Propagation Delay and Transition Time Test Circuit

Figure 6. Receiver Propagation Delay and Transition Time Waveforms

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TYPICAL APPLICATIONS

Balanced System

Figure 7. Point-to-Point Application (DS90LV012A)

Balanced System

Figure 8. Point-to-Point Application (DS90LT012A)

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