Texas Instruments DS125BR111EVM User Manual
DS125BR111EVM User's Guide
SMA Evaluation Kit
User's Guide
Literature Number: SNLU168A
August 2014–Revised August 2014
User's Guide
SNLU168A–August 2014–Revised August 2014
DS125BR111EVM User's Guide
SMA Evaluation Kit
The DS125BR111EVM – SMA evaluation kit provides a complete high bandwidth platform to evaluate the
10GbE, PCIe, and SAS/SATA signal conditioning features of the Texas Instruments DS125BR111
repeater/redriver. The DS125BR111EVM can be used for standard compliance testing, performance
evaluation, and initial system prototyping. The SMA edge launch connectors used for the
DS125BR111EVM will interface to multiple system connector types via commercially available breakout
cables, adaptors, and boards (not included). This flexible connectivity enables integrated system level
testing between TI repeaters and 3rd party ASIC/FPGA host boards.
Topic ........................................................................................................................... Page
1 Features ............................................................................................................. 3
2 Applications........................................................................................................ 3
3 Demo Kit Contents............................................................................................... 3
4 Ordering Information............................................................................................ 3
5 Evaluation Board ................................................................................................. 4
6 Setup.................................................................................................................. 4
7 Expected Results................................................................................................. 7
8 Schematic........................................................................................................... 8
9 Bill of Materials.................................................................................................. 10
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DS125BR111EVM User's Guide SMA Evaluation Kit SNLU168A–August 2014–Revised August 2014
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1 Features
• Two Channel Repeater up to 12 Gbps Rate
– DS125BR111: 1x Bidirectional Lane
• Low 65mW/channel Power Consumption, with Option to Power Down Unused Channels
• Advanced Signal Conditioning Features
– Linear Equalization (up to 10 dB @ 6 GHz)
– Linear output drive
– Output voltage range over 1200 mV
• Fully Programmable via Pin Selection or SMBus Interface
• Selectable Single Supply Operation
• 5 kV HBM ESD Rating
• 3.3 V LVCMOS Input Tolerant for SMBus Interface
• Flow–Thru Pinout Package: 24-Pin QFN (4 mm x 4 mm)
• Industrial –40 to 85°C Operating Temperature Range
2 Applications
• High-Speed Cables and Backplanes in Communication Systems
• PCIe, SAS I/II/III, SATA 3/6 Gbps (with OOB detection) and many others
Features
3 Demo Kit Contents
• DS125BR111EVM Board
4 Ordering Information
DS125BR111RTWR 1000
DS125BR111RTWT 250
Table 1. DS125BR111EVM Ordering Information
DEVICE QUANTITY
SMA Evaluation Kit: DS125BR111EVM
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Evaluation Board
5 Evaluation Board
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Figure 1. DS125BR111EVM Evaluation Board
6 Setup
The DS125BR111EVM – SMA evaluation kit can be used in three different modes:
1. Pin Control (provides access to selected signal integrity settings)
2. SMBus Mode (full access to signal integrity and control settings)
3. EEPROM Mode (full access to signal integrity and control settings)
The EEPROM mode is a convenient method of programming one or more DS125BRxxx devices on
system power-up when a SMBus master (microcontroller or similar) is unavailable in the design. It is
recommended to use a 1 MHz capable EEPROM. The EEPROM must be 8-kbits or smaller.
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DS125BR111EVM User's Guide SMA Evaluation Kit SNLU168A–August 2014–Revised August 2014
Copyright © 2014, Texas Instruments Incorporated
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HIGH
SIGNAL
RESISTOR
SIGNAL
LOW
4-LEVEL CONTROL
HIGH RESISTOR FLOAT LOW
PIN HEADER CONNECTION
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6.1 DS125BR111 Pin Control
Uses the external control pins on the DS125BR111 to configure the signal integrity and control settings of
the device. Due to the limited number of control pins, a limited bandwidth 4-level input scheme has been
implemented across the control pin interface. This allows for improved EQ and VOD control with fewer
physical pins.
The 4 levels are defined as:
1. Low: 1 KΩ to GND
2. Resistor: 20 KΩ to GND
3. Float: No External Connection
4. High: 1 KΩ to VDD
The EVM interfaces to this 4-level IO using the setup below. Only one shunt connection is required to
access any of the 4 levels. This methodology minimizes the risk of improper connections that could
damage the board or board power supply.
Setup
The DS125BR111EVM is quickly setup for use in pin control configuration. Jumpers listed below should
be installed on the EVM for pin control.
1. J4 – 3.3 V operation: Use the J1 and J3 connectors to supply 3.3 V power to the EVM. The EVM
power connections are designed to accommodate 1287-ST quick connect tabs or directly soldered to
power leads for connection to a lab power supply.
2. J18 – PWDN = LOW: Device is enabled.
3. J19 – ENSMB = LOW: PIN CONTROL configuration mode.
4. J22 – VDD_SEL = LOW: Uses DS125BR111 internal regulator to convert 3.3 V supply to proper
internal supply level of 2.5 V. Note: The 2.5 V level may be observed on the device VDD pins or the J2
connector.
5. VOD_SEL = 1: Recommended output amplitude settings for CH A and CH B in SAS/SATA and PCIe
applications.
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Figure 2. 4-Level IO Control on EVM
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