Texas Instruments DRV8846RGER Schematics

STEP/DIR

Step size

nFAULT

4 to 18 V

Controller

M

+ t

+ -

DRV8846

Stepper

Motor Driver

1 A

1 A

Decay Mode

1/32 µstep

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DRV8846 Dual H-Bridge Stepper Motor Driver

1 Features 3 Description

1

• PWM Microstepping Motor Driver
– Built-In Microstepping Indexer
– Up to 1/32 Microstepping
– Step/Direction Control

• Multiple Decay Modes
– Adaptive Decay
– Mixed Decay
– Slow Decay
– Fast Decay

• Configurable Off-Time PWM Chopping
– 10-, 20-, or 30-μs Off-Time

• Adaptive Blanking Time for Smooth Stepping

• 4- to 18-V Operating Supply Voltage Range

• 1-A Continuous/RMS Output Current per H-Bridge
(at 25°C)

• Low-Current Sleep Mode

• 3-Bit Torque DAC to Scale Motor Current

• Thermally Enhanced Surface Mount Package

• Protection Features
– VM Undervoltage Lockout (UVLO)
– Overcurrent Protection (OCP)
– Thermal Shutdown (TSD)
– Fault Condition Indication Pin (nFAULT)

2 Applications

• Printers

• Scanners

• Video Security Cameras

• Projectors

The DRV8846 provides a highly-integrated stepper
motor driver for cameras, printers, projectors, and
other automated equipment applications. The device
has two H-bridges and a microstepping indexer and
is intended to drive a bipolar stepper motor. The
output block of each H-bridge driver consists of N­channel and P-channel power MOSFETs configured
as full H-bridges to drive the motor windings. The
DRV8846 is capable of driving up to 1-A full scale
output current (with proper heatsinking and TA=
25°C).

A simple STEP/DIR interface allows easy interfacing
to controller circuits. Pins allow configuration of the
motor in full-step up to 1/32-step modes. Decay mode
is configurable so that adaptive decay, slow decay,
fast decay, and mixed decay can be used. The PWM
current chopping off-time can also be selected. A low­power sleep mode is provided which shuts down
internal circuitry to achieve very-low quiescent current
draw. This sleep mode can be set using a dedicated
nSLEEP pin.

Internal protection functions are provided for UVLO,
overcurrent protection, short circuit protection, and
overtemperature. Fault conditions are indicated via a
nFAULT pin.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

DRV8846 QFN (24) 4.00 × 4.00 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.

DRV8846

SLLSEK2 –JUNE 2014

(1)

4 Simplified Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRV8846

SLLSEK2 –JUNE 2014

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Simplified Schematic............................................. 1

5 Revision History..................................................... 2

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 Handling Ratings....................................................... 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements................................................ 7

7.7 Typical Characteristics.............................................. 8

8 Detailed Description .............................................. 9

8.1 Overview ................................................................... 9

5 Revision History

DATE REVISION NOTES

June 2014 * Initial release.

8.2 Functional Block Diagram....................................... 10

8.3 Feature Description................................................. 11

8.4 Device Functional Modes........................................ 22

9 Application and Implementation........................ 23

9.1 Application Information............................................ 23

9.2 Typical Application ................................................. 23

10 Power Supply Recommendations ..................... 26

11 Layout................................................................... 26

11.1 Layout Guidelines ................................................. 26

11.2 Layout Example .................................................... 26

12 Device and Documentation Support................. 27

12.1 Trademarks ........................................................... 27

12.2 Electrostatic Discharge Caution............................ 27

12.3 Glossary ................................................................ 27

13 Mechanical, Packaging, and Orderable

Information........................................................... 27

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1

2

3

4

5

6

18

17

16

15

14

13

24

23

22

21

20

19

7

8

9

10

11

12

AOUT1

AISEN

AOUT2

BOUT2

BISEN

BOUT1

GND

VINT

NC

VM

VREF

DIR

nFAULT

M0

M1

nENBL

STEP

ADEC

I0

I1

DEC0

nSLEEP

DEC1

GND

(PPAD)

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6 Pin Configuration and Functions

DRV8846

SLLSEK2 –JUNE 2014

RGE (VQFN) Package

24 Pins

(Top View)

Pin Functions

PIN

NAME NO.

ADEC 19 I Adaptive decay enable adaptive decay operation is enabled; must be set prior to coming out

AISEN 2 O Winding A sense
AOUT1 1

AOUT2 3
BISEN 5 O Winding B sense
BOUT1 6

BOUT2 4
DEC0 22 I
DEC1 24 I
DIR 13 I Direction input Logic level sets the direction of stepping; internal pulldown

GND 18, PPAD PWR Device ground
I0 20 I

I1 21 I
MO 8 I
M1 9 I
NC 16 — No connect Unused pin not connected internally

nENBL 11 I Enable driver output

nFAULT 7 OD Fault indication pin

nSLEEP 23 I Sleep mode input

STEP 12 I Step input
TOFF_SEL 10 I Decay mode off time set Sets the off-time during current chopping; tri-level pin

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I/O DESCRIPTION

Logic low sets decay modes by DEC0 and DEC1 pins; logic high –
of sleep; internal pulldown

Connect to current sense resistor for bridge A, or GND if current
regulation is not required

O Winding A output

Connect to current sense resistor for bridge B, or GND if current
regulation is not required

O Winding B output

Decay mode setting pins Sets the decay mode; see description section; tri-level pin

Both the GND pin and device PowerPAD™ must be connected to
ground

Torque DAC current scalar Scales the current from 100% to 12.5% in 12.5% steps; tri-level pin

Microstepping mode setting Controls step mode (full, half, up to 1/32-step) and single- or dual­pins edge clocking; tri-level pin

Logic low to enable device outputs and internal indexer; logic high to
disable; internal pulldown

Pulled logic low with fault condition; open-drain output requires
external pullup

Logic high to enable device; logic low to enter low-power sleep mode;
internal pulldown

A rising edge (or rising and falling depending on step mode) advances
the indexer one step; internal pulldown

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Pin Functions (continued)

PIN

NAME NO.

VINT 17 — Internal regulator Internal supply voltage; bypass to GND with 2.2-μF, 6.3-V capacitor
VM 15 PWR Power supply

VREF 14 I

I/O DESCRIPTION

Connect to motor power supply; bypass to GND with a 0.1- and 10-μF
(minimum) ceramic capacitor rated for VM

Full-scale current reference Voltage on this pin sets the full scale chopping current; short to VINT
input if not supplying an external reference voltage

Table 1. External Components

Component Pin 1 Pin 2 Recommended

C

VM

C

VM

C

VINT

R

nFAULT

R

AISEN

R

BISEN

(1) VCC is not a pin on the DRV8846, but a VCC supply voltage pullup is required for open-drain output nFAULT; nFAULT may be pulled

up to VINT through a resistor R

VM GND 10-µF (minimum) ceramic capacitor rated for VM
VM GND 0.1-µF ceramic capacitor rated for VM

VINT GND 6.3-V, 2.2-µF ceramic capacitor

(1)

VCC

nFAULT >5 kΩ
AISEN GND Sense resistor, see applications section for sizing
BISEN GND Sense resistor, see applications section for sizing

nFAULT

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature referenced with respect to GND (unless otherwise noted)

Power supply voltage (VM) –0.3 20 V
Power supply voltage ramp rate (VM) 0 2 V/µs
Internal regulator voltage (VINT) –0.3 3.6 V
Analog input pin voltage (VREF) –0.3 3.6 V
Control pin voltage (nENABLE, STEP, DIR, I0, I1, M0, M1, DEC0, DEC1, TOFF_SEL, nSLEEP,

nFAULT, ADEC)
Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) –0.3 VM + 0.6 V
Continuous shunt amplifier input pin voltage (AISEN, BISEN)

(2)

Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2, AISEN, BISEN) Internally limited A
T

Operating junction temperature –40 150 °C

J

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Transients of ±1 V for less than 25 ns are acceptable.

7.2 Handling Ratings

T

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Storage temperature range –65 150 °C

stg

(ESD)

Electrostatic
discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins

(1)

(1)

MIN MAX UNIT

–0.3 7.0 V

–0.6 0.6 V

MIN MAX UNIT

–4 4

(2)

–1.5 1.5

kV

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

VM Power supply voltage range
VREF Reference rms voltage range
ƒ

PWM

I

VINT

I

rms

T

A

(1) Note that R
(2) Operational at VREF between 0 to 1 V, but accuracy is degraded

Applied STEP signal 0 250 kHz
VINT external load current 1 mA
Motor rms current per H-bridge
Operating ambient temperature –40 85 °C

increases and maximum output current is reduced at VM supply voltages below 5 V

DS(ON)

(3) Power dissipation and thermal limits must be observed

(1)

(2)

(3)

4 18 V
1 3.3 V

0 1 A

7.4 Thermal Information

DRV8846

THERMAL METRIC

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 34
Junction-to-case (top) thermal resistance 36.9
Junction-to-board thermal resistance 12.5
Junction-to-top characterization parameter 0.4
Junction-to-board characterization parameter 12.5
Junction-to-case (bottom) thermal resistance 2.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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QFN UNIT

24 PINS

°C/W

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7.5 Electrical Characteristics

TA= 25°C, over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER SUPPLIES (VM, VINT)

VM VM operating voltage 4 18 V
I

VM

I

VMQ

t

SLEEP

t

WAKE

t

ON

VM operating supply current 3.5 4.5 5.5 mA
VM sleep mode supply current VM = 12 V, nSLEEP = 0, nENBL = 0 or 1 0.5 1.2 3 μA

Sleep time nSLEEP = 0 to sleep mode 1 ms
Wake time nSLEEP = 1 to output transition 1 ms
Power-on time VM > V

VINT VINT voltage VM > 4 V, I

LOGIC-LEVEL INPUTS (STEP, DIR, nENBL, nSLEEP, ADEC)

V

IL

V

IH

V

HYS

I

IL

I

IH

R

PD

t

DEG

t

PROP

Input logic low voltage 0 0.7 V
Input logic high voltage 1.6 5.5 V
Input logic hysteresis 100 mV
Input logic low current VIN = 0 V –1 1 μA
Input logic high current VIN = 5 V 1 30 μA

Pulldown resistance kΩ

Input deglitch time 200 ns
Propagation delay STEP edge to current change 600 ns

TRI-LEVEL INPUTS (I0, I1, M0, M1, DEC0, DEC1, TOFF_SEL)

V

IL

V

IZ

V

IH

V

HYS

I

IL

I

IH

R

PD

R

PU

Tri-level input logic low voltage 0 0.7 V
Tri-level input Hi-Z voltage 1.1 V
Tri-level input logic high voltage 1.6 5.5 V
Tri-level input hysteresis 100 mV
Tri-level input logic low current VIN= 0 V –30 –1 μA
Tri-level input logic high current VIN= 5 V 1 30 μA
Tri-level pulldown resistance To GND 170 kΩ
Tri-level pullup resistance To VINT 340 kΩ

CONTROL OUTPUTS (nFAULT)

V

OL

I

OH

Output logic low voltage IO= 5 mA 0.5 V
Output logic high leakage VO= 3.3 V –1 1 μA

MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)

R

DS(ON)

R

DS(ON)

I

OFF

t

RISE

t

FALL

t

DEAD

High-side FET on resistance Ω

Low-side FET on resistance Ω

Off-state leakage current VM = 5 V, TJ= 25°C –1 1 μA
Output rise time 60 ns
Output fall time 60 ns
Output dead time Internal dead time 200 ns

PWM CURRENT CONTROL (VREF, AISEN, BISEN)

I

REF

V

TRIP

A

ISENSE

Externally applied VREF input current VREF = 1 to 3.3 V 1 μA
xISEN trip voltage For 100% current step with VREF = 3.3 V 500 mV
Current sense amplifer gain Reference only 6.6 V/V

VM = 12 V, excluding winding current,
nSLEEP = 1, nENBL = 0 or 1

rising to output transition 1 ms

UVLO

= 0 A to 1 mA 3.13 3.3 3.47 V

OUT

nENBL, STEP, DIR, ADEC 200
nSLEEP 500

VM = 12 V, I = 0.5 A, TJ= 25°C 550
VM = 12 V, I = 0.5 A, TJ= 85°C

(1)

660
VM = 12 V, I = 0.5 A, TJ= 25°C 350
VM = 12 V, I = 0.5 A, TJ= 85°C

(1)

420

(1) Not tested in production; limits are based on characterization data
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STEP

2

3

1

4

5

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Electrical Characteristics (continued)

TA= 25°C, over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TOFF_SEL = GND 20

t

OFF

PROTECTION CIRCUITS

V

UVLO

I

OCP

t

OCP

t

RETRY

T

TSD

T

HYS

Current control constant off time TOFF_SEL = Hi-Z 10 μs

TOFF_SEL = VINT 30

VM undervoltage lockout V

VM falling; UVLO report 2.9
VM rising; UVLO recovery 3

Overcurrent protection trip level 2 A
Overcurrent deglitch time 2.8 μs
Overcurrent protection period 1.6 ms
Thermal shutdown temperature Die temperature T
Thermal shutdown hysteresis Die temperature T

J
J

150 160 180 °C

50 °C

7.6 Timing Requirements

TA= 25°C, over recommended operating conditions unless otherwise noted

NO. PARAMETER MIN MAX UNIT

1 ƒ
2 t
3 t
4 t
5 t

STEP
WH(STEP)
WL(STEP)
SU(STEP)
H(STEP)

Step frequency 250 kHz
Pulse duration, STEP high 1.9 μs
Pulse duration, STEP low 1.9 μs
Setup time, DIR or Mx to STEP rising 200 ns
Hold time, DIR or Mx to STEP rising 200 ns

DRV8846

Figure 1. Timing Diagram

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VM (V)

R

DSON

HS + LS (:)

0 5 10 15 20

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

D001

-40qC
25qC
85qC
125qC

TA (qC)

R

DSON

HS + LS (:)

-50 0 50 100 150

0.6

0.8

1

1.2

1.4

1.6

1.8

D004

4 V
12 V
18 V

VM (V)

I

VM

(mA)

0 5 10 15 20

2

2.5

3

3.5

4

4.5

5

5.5

D001

-40qC
25qC
85qC
125qC

VM (V)

I

VMQ

(PA)

0 5 10 15 20

0

0.5

1

1.5

2

2.5

3

3.5

D001

-40qC
25qC
85qC
125qC

DRV8846

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7.7 Typical Characteristics

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Figure 2. IVMvs VM Figure 3. I

Figure 4. R

vs VM Figure 5. R

DSON

VMQ

vs Temperature

DSON

vs VM

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8 Detailed Description

8.1 Overview

The DRV8846 is an integrated motor driver solution for bipolar stepper motors. The device integrates 2 H-bridges
that use NMOS low-side drivers and PMOS high-side drivers, current sense regulation circuitry, and a
microstepping indexer. The DRV8846 can be powered with a supply range between 4 to 18 V and is capable of
providing an output current to 1.4-A full scale or 1-A rms.

A simple STEP/DIR interface allows easy interfacing to the controller circuit. The internal indexer is able to
execute high-accuracy microstepping without requiring the processor to control the current level.

The PWM off-time, t
The DRV8846 has an adaptive decay feature that automatically adjusts the decay setting to minimize current

ripple while still reacting quickly to step changes. This feature allows the DRV8846 to quickly be integrated into a
system.

A torque DAC feature allows the controller to scale the output current without needing to scale the analog
reference voltage input VREF. The torque DAC is accessed using digital input pins. This allows the controller to
save power by decreasing the current consumption when not required.

A low-power sleep mode is included, which allows the system to save power when not driving the motor.

can be adjusted to 10, 20, or 30 μs.

OFF

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Over­Temp

AOUT1

GND

STEP

VM

Logic

AOUT2

VM

Gate

Drive

and

OCP

BOUT1

VM

BOUT2

VM

Gate

Drive

and

OCP

BISEN

AISEN

Step

Motor

ISEN

ISEN

DIR

M1

VM

VM

Internal Ref and

Regs

nFAULT

nSLEEP

nENBL

M0

10 µF

+

VM

I0

I1

PPAD

VINT

2.2 µF

VREF

DEC0

VREF

VREF

VINT

TOFF_SEL

DEC1

VINT

VINT

VINT

VINT

VINT

VINT

VINT

ADEC

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8.2 Functional Block Diagram

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xOUT1

xOUT2

VM

xISEN

Pre-

drive

VM

PWM

OCP

OCP

Optional

Step

Motor

SIN

DAC

5

+

±

DAC

3

I1

VREF

I0

A = 6.6

3­level
Input

buffer

To other
channel

From Indexer

Internal

reference

To other
channel

DIR

STEP

Indexer

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8.3 Feature Description

8.3.1 PWM Motor Drivers

DRV8846 contains two identical H-bridge motor drivers with current-control PWM circuitry. Figure 6 shows a
block diagram of the circuitry.

Figure 6. PWM Motor Driver Circuitry

8.3.2 Micro-Stepping Indexer

To allow a simple step and direction interface to control stepper motors, the DRV8846 contains a microstepping
indexer. The indexer controls the state of the H-bridges automatically. When the correct transition is applied at
the STEP input, the indexer moves to the next step, according to the direction set by the DIR pin. In 1/8, 1/16,
and 1/32 step modes, both the rising and falling edges of the STEP input may be used to advance the indexer,
depending on the M0 / M1 setting.

The nENBL pin disables the output stage in indexer mode. When nENBL = 0, the indexer inputs are still active
and respond to the STEP and DIR input pins; only the output stage is disabled.

The indexer logic in the DRV8846 allows a number of different stepping configurations. The M0 and M1 pins
configure the stepping format (see Table 2).

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