TEXAS INSTRUMENTS DRV8824 Technical data

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DRV8824

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SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

STEPPER MOTOR CONTROLLER IC

Check for Samples: DRV8824

FEATURES

• PWM Microstepping Motor Driver – Built-In Microstepping Indexer – Five-Bit Winding Current Control Allows Up

to 32 Current Levels

– Low MOSFET On-Resistance

• 1.6-A Maximum Drive Current at 24 V, 25°C

• Built-In 3.3-V Reference Output

• 8-V to 45-V Operating Supply Voltage Range

• Thermally Enhanced Surface Mount Package

DESCRIPTION

The DRV8824 provides an integrated motor driver solution for printers, scanners, and other automated equipment applications. The device has two H-bridge drivers and a microstepping indexer, and is intended to drive a bipolar stepper motor. The output driver block for each consists of N-channel power MOSFET’s configured as full H-bridges to drive the motor windings. The DRV8824 is capable of driving up to 1.6-A of output current (with proper heatsinking, at 24 V and 25°C).

A simple step/direction interface allows easy interfacing to controller circuits. Pins allow configuration of the motor in full-step up to 1/32-step modes. Decay mode is programmable.

Internal shutdown functions are provided for overcurrent protection, short circuit protection, undervoltage lockout and overtemperature.

The DRV8824 is available in a 28-pin HTSSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br).

APPLICATIONS

• Automatic Teller Machines

• Money Handling Machines

• Video Security Cameras

• Printers

• Scanners

• Office Automation Machines

• Gaming Machines

• Factory Automation

• Robotics

ORDERING INFORMATION

–40°C to 85°C PowerPAD™ (HTSSOP) - PWP Reel of 2000 DRV8824PWPR 8824

(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.

PACKAGE

(2)

(1)

ORDERABLE PART TOP-SIDE

NUMBER MARKING

Charge

Pump

Thermal

Shut down

AOUT1

AOUT2

BOUT1

BOUT2

GNDGND

0.1uF

0.01uF

Step

Motor

VMA

VMB

CP1

CP2

VCP

ISENA

ISENB

STEP

DIR

MODE1

MODE2

AVREF

HS Gate

Drive

Internal

Reference &

Regs

Int. VCC

Motor

Driver B

nFAULT

Indexer /

Control

Logic

nRESET

Motor

Driver A

nENBL

nSLEEP

V3P3OUT

3.3V

LS Gate

Drive

3.3V

BVREF

MODE0

nHOME

DECAY

DRV8824

SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

DEVICE INFORMATION

Functional Block Diagram

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Product Folder Link(s): DRV8824

DRV8824

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SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

Table 1. TERMINAL FUNCTIONS

NAME PIN I/O

POWER AND GROUND

GND 14, 28 - Device ground VMA 4 - Bridge A power supply VMB 11 - Bridge B power supply

V3P3OUT 15 O 3.3-V regulator output CP1 1 IO Charge pump flying capacitor

CP2 2 IO Charge pump flying capacitor VCP 3 IO High-side gate drive voltage

CONTROL

nENBL 21 I Enable input

nSLEEP 17 I Sleep mode input

STEP 22 I Step input DIR 20 I Direction input Level sets the direction of stepping

MODE0 24 I Microstep mode 0 MODE1 25 I Microstep mode 1 MODE2 26 I Microstep mode 2

DECAY 19 I Decay mode

nRESET 16 I Reset input AVREF 12 I Bridge A current set reference input Reference voltage for winding current set.

BVREF 13 I Bridge B current set reference input

NC 23 No connect Leave this pin unconnected.

STATUS

nHOME 27 OD Home position Logic low when at home state of step table nFAULT 18 OD Fault

OUTPUT

ISENA 6 IO Bridge A ground / Isense Connect to current sense resistor for bridge A. ISENB 9 IO Bridge B ground / Isense Connect to current sense resistor for bridge B. AOUT1 5 O Bridge A output 1 AOUT2 7 O Bridge A output 2 BOUT1 10 O Bridge B output 1 BOUT2 8 O Bridge B output 2

(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output

(1)

DESCRIPTION

Connect to motor supply (8 - 45 V). Both pins must be connected to same supply.

Bypass to GND with a 0.47-mF 6.3-V ceramic capacitor. Can be used to supply VREF.

Connect a 0.01-mF 50-V capacitor between CP1 and CP2.

Connect a 0.1-mF 16-V ceramic capacitor to VM.

Logic high to disable device outputs and indexer operation, logic low to enable

Logic high to enable device, logic low to enter low-power sleep mode

Rising edge causes the indexer to move one step

MODE0 - MODE2 set the step mode - full, 1/2, 1/4, 1/8/ 1/16, or 1/32 step

Low = slow decay, open = mixed decay, high = fast decay

Active-low reset input initializes the indexer logic and disables the H-bridge outputs

Normally AVREF and BVREF are connected to the same voltage. Can be connected to V3P3OUT. A 0.01-µF bypass capacitor to GND is recommended.

Logic low when in fault condition (overtemp, overcurrent)

Connect to bipolar stepper motor winding A. Positive current is AOUT1 → AOUT2

Connect to bipolar stepper motor winding B. Positive current is BOUT1 → BOUT2

EXTERNAL COMPONENTS

OR CONNECTIONS

Product Folder Link(s): DRV8824

DRV8824

SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VMx Power supply voltage range –0.3 to 47 V

Digital pin voltage range –0.5 to 7 V

VREF Input voltage –0.3 to 4 V

ISENSEx pin voltage –0.3 to 0.8 V Peak motor drive output current, t < 1 mS Internally limited A Continuous motor drive output current

ESD rating V

Continuous total power dissipation See Dissipation Ratings table

stg

Operating virtual junction temperature range –40 to 150 °C Operating ambient temperature range –40 to 85 °C Storage temperature range –60 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) Power dissipation and thermal limits must be observed.

(3)

HBD (human body model) 2000 CDM (charged device model) 500

(1) (2)

VALUE UNIT

1.6 A

DISSIPATION RATINGS (PRELIMINARY)

BOARD PACKAGE R

(1)

Low-K

(2)

Low-K High-K High-K

(3) (4)

PWP

qJA

67.5°C/W 14.8 mW/°C 1.85 W 1.18 W 0.96 W

39.5°C/W 25.3 mW/°C 3.16 W 2.02 W 1.64 W

33.5°C/W 29.8 mW/°C 3.73 W 2.38 W 1.94 W 28°C/W 35.7 mW/°C 4.46 W 2.85 W 2.32 W

(1) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper. (2) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with 25-cm22-oz copper on back

side.

(3) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and

solid 1-oz internal ground plane.

(4) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with 25-cm21-oz copper on back

side and solid 1-oz internal ground plane.

DERATING FACTOR

ABOVE TA= 25°C

Product Folder Link(s): DRV8824

TA< 25°C TA= 70°C TA= 85°C

DRV8824

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

V V I

V3P3

M REF

Motor power supply voltage range VREF input voltage

(2)

V3P3OUT load current 1 mA

(1) All VMpins must be connected to the same supply voltage. (2) Operational at VREF between 0 V and 1 V, but accuracy is degraded.

(1)

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER SUPPLIES

VMQ

UVLO

V3P3OUT REGULATOR

3P3

LOGIC-LEVEL INPUTS

HYS

nHOME, nFAULT OUTPUTS (OPEN-DRAIN OUTPUTS)

DECAY INPUT

H-BRIDGE FETS

DS(ON)

OFF

MOTOR DRIVER

PWM

BLANK

DEAD

PROTECTION CIRCUITS

OCP

TSD

VM operating supply current VM= 24 V, f

< 50 kHz 5 8 mA

PWM

VM sleep mode supply current VM= 24 V 10 20 mA VM undervoltage lockout voltage VMrising 7.8 8.2 V

V3P3OUT voltage IOUT = 0 to 1 mA 3.2 3.3 3.4 V

Input low voltage 0.6 0.7 V Input high voltage 2 5.25 V Input hysteresis 0.45 V Input low current VIN = 0 –20 20 mA Input high current VIN = 3.3 V 100 mA

Output low voltage IO= 5 mA 0.5 V Output high leakage current VO= 3.3 V 1 mA

Input low threshold voltage For slow decay mode 0.8 V Input high threshold voltage For fast decay mode 2 V Input current ±40 µA

HS FET on resistance Ω

LS FET on resistance Ω

VM= 24 V, IO= 1 A, TJ= 25°C 0.63 VM= 24 V, IO= 1 A, TJ= 85°C 0.76 0.90 VM= 24 V, IO= 1 A, TJ= 25°C 0.65 VM= 24 V, IO= 1 A, TJ= 85°C 0.78 0.90

Off-state leakage current –20 20 mA

Internal PWM frequency 37 50 63 kHz Current sense blanking time 3.75 ms Rise time VM= 24 V 100 360 ns Fall time VM= 24 V 80 250 ns Dead time 400 ns

Overcurrent protection trip level 1.8 5 A Thermal shutdown temperature Die temperature 150 160 180 °C

SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

MIN NOM MAX UNIT

8.2 45 V 1 3.5 V

Product Folder Link(s): DRV8824

DRV8824

SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT CONTROL

REF

TRIP

ΔI

TRIP

ISENSE

xVREF input current xVREF = 3.3 V –3 3 mA xISENSE trip voltage xVREF = 3.3 V, 100% current setting 635 660 685 mV

xVREF = 3.3 V , 5% current setting –25 25 xVREF = 3.3 V , 10% - 34% current

Current trip accuracy (relative to programmed value)

setting xVREF = 3.3 V, 38% - 67% current

setting xVREF = 3.3 V, 71% - 100% current

setting

Current sense amplifier gain Reference only 5 V/V

TIMING REQUIREMENTS

1 f 2 t 3 t 4 t 5 t 6 t 7 t

STEP WH(STEP) WL(STEP) SU(STEP) H(STEP) ENBL WAKE

Step frequency 250 kHz Pulse duration, STEP high 1.9 ms Pulse duration, STEP low 1.9 ms Setup time, command to STEP rising 200 ns Hold time, command to STEP rising 200 ns Enable time, nENBL active to STEP 200 ns Wakeup time, nSLEEP inactive to STEP 1 mS

–15 15

–10 10

–5 5

MIN MAX UNIT

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Figure 1. Timing Diagram

Product Folder Link(s): DRV8824

DRV8824

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SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

FUNCTIONAL DESCRIPTION

PWM Motor Drivers

The DRV8824 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the motor control circuitry is shown in Figure 2.

Figure 2. Motor Control Circuitry

Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor supply voltage.

Product Folder Link(s): DRV8824

I =

CHOP

REFX

5 · R

ISENSE

DRV8824

SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

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Current Regulation

The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle.

In stepping motors, current regulation is used to vary the current in the two windings in a semi-sinusoidal fashion to provide smooth motion.

The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input from the xVREF pins.

The full-scale (100%) chopping current is calculated in Equation 1.

(1)

Example:

If a 0.5-Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current will be

3.3 V / (5 x 0.5 Ω) = 1.32 A.

The reference voltage is scaled by an internal DAC that allows fractional stepping of a bipolar stepper motor, as described in the microstepping indexer section below.

Decay Mode

During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 3 as case 1. The current flow direction shown indicates positive current flow.

Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay.

In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 3 as case 2.

In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 3 as case 3.

Product Folder Link(s): DRV8824

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SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

Figure 3. Decay Mode

The DRV8824 supports fast decay, slow decay and a mixed decay mode. Slow, fast, or mixed decay mode is selected by the state of the DECAY pin - logic low selects slow decay, open selects mixed decay operation, and logic high sets fast decay mode.

Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow decay mode for the remainder of the fixed PWM period. This occurs only if the current through the winding is decreasing (per the indexer step table); if the current is increasing, then slow decay is used.

Blanking Time

After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 ms. Note that the blanking time also sets the minimum on time of the PWM.

Microstepping Indexer

Built-in indexer logic in the DRV8824 allows a number of different stepping configurations. The MODE0 - MODE2 pins are used to configure the stepping format as shown in Table 2.

Table 2. Stepping Format

MODE2 MODE1 MODE0 STEP MODE

0 0 0 Full step (2-phase excitation) with 71% current 0 0 1 1/2 step (1-2 phase excitation) 0 1 0 1/4 step (W1-2 phase excitation) 0 1 1 8 microsteps / step 1 0 0 16 microsteps / step 1 0 1 32 microsteps / step 1 1 0 32 microsteps / step 1 1 1 32 microsteps / step

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Table 3 shows the relative current and step directions for different settings of MODEx. At each rising edge of the

STEP input, the indexer travels to the next state in the table. The direction is shown with the DIR pin high; if the DIR pin is low the sequence is reversed. Positive current is defined as xOUT1 = positive with respect to xOUT2.

Note that if the step mode is changed while stepping, the indexer will advance to the next valid state for the new MODEx setting at the rising edge of STEP.

The home state is 45°. This state is entered at power-up or application of nRESET. This is shown in Table 3 by the shaded cells.

Table 3. Relative Current and Step Directions

1/32 STEP 1/16 STEP 1/8 STEP 1/4 STEP 1/2 STEP STEP CURRENT CURRENT

FULL WINDING WINDING

70% A B

1 1 1 1 1 100% 0% 0 2 100% 5% 3 3 2 100% 10% 6 4 99% 15% 8 5 3 2 98% 20% 11 6 97% 24% 14 7 4 96% 29% 17 8 94% 34% 20

9 5 3 2 92% 38% 23 10 90% 43% 25 11 6 88% 47% 28 12 86% 51% 31 13 7 4 83% 56% 34 14 80% 60% 37 15 8 77% 63% 39 16 74% 67% 42 17 9 5 3 2 1 71% 71% 45 18 67% 74% 48 19 10 63% 77% 51 20 60% 80% 53 21 11 6 56% 83% 56 22 51% 86% 59 23 12 47% 88% 62 24 43% 90% 65 25 13 7 4 38% 92% 68 26 34% 94% 70 27 14 29% 96% 73 28 24% 97% 76 29 15 8 20% 98% 79 30 15% 99% 82 31 16 10% 100% 84 32 5% 100% 87 33 17 9 5 3 0% 100% 90 34 –5% 100% 93 35 18 –10% 100% 96 36 –15% 99% 98 37 19 10 –20% 98% 101 38 –24% 97% 104

ELECTRICAL

ANGLE

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DRV8824

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SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

Table 3. Relative Current and Step Directions (continued)

1/32 STEP 1/16 STEP 1/8 STEP 1/4 STEP 1/2 STEP STEP CURRENT CURRENT

39 20 –29% 96% 107 40 –34% 94% 110 41 21 11 6 –38% 92% 113 42 –43% 90% 115 43 22 –47% 88% 118 44 –51% 86% 121 45 23 12 –56% 83% 124 46 –60% 80% 127 47 24 –63% 77% 129 48 –67% 74% 132 49 25 13 7 4 2 –71% 71% 135 50 –74% 67% 138 51 26 –77% 63% 141 52 –80% 60% 143 53 27 14 –83% 56% 146 54 –86% 51% 149 55 28 –88% 47% 152 56 –90% 43% 155 57 29 15 8 –92% 38% 158 58 –94% 34% 160 59 30 –96% 29% 163 60 –97% 24% 166 61 31 16 –98% 20% 169 62 –99% 15% 172 63 32 –100% 10% 174 64 –100% 5% 177 65 33 17 9 5 –100% 0% 180 66 –100% –5% 183 67 34 –100% –10% 186 68 –99% –15% 188 69 35 18 –98% –20% 191 70 –97% –24% 194 71 36 –96% –29% 197 72 –94% –34% 200 73 37 19 10 –92% –38% 203 74 –90% –43% 205 75 38 –88% –47% 208 76 –86% –51% 211 77 39 20 –83% –56% 214 78 –80% –60% 217 79 40 –77% –63% 219 80 –74% –67% 222 81 41 21 11 6 3 –71% –71% 225 82 –67% –74% 228 83 42 –63% –77% 231 84 –60% –80% 233

FULL WINDING WINDING

70% A B

ELECTRICAL

ANGLE

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DRV8824

SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

Table 3. Relative Current and Step Directions (continued)

FULL WINDING WINDING

1/32 STEP 1/16 STEP 1/8 STEP 1/4 STEP 1/2 STEP STEP CURRENT CURRENT

70% A B

85 43 22 –56% –83% 236 86 –51% –86% 239 87 44 –47% –88% 242 88 –43% –90% 245 89 45 23 12 –38% –92% 248 90 –34% –94% 250 91 46 –29% –96% 253 92 –24% –97% 256 93 47 24 –20% –98% 259 94 –15% –99% 262 95 48 –10% –100% 264 96 –5% –100% 267 97 49 25 13 7 0% –100% 270 98 5% –100% 273 99 50 10% –100% 276

100 15% –99% 278 101 51 26 20% –98% 281 102 24% –97% 284 103 52 29% –96% 287 104 34% –94% 290 105 53 27 14 38% –92% 293 106 43% –90% 295 107 54 47% –88% 298 108 51% –86% 301 109 55 28 56% –83% 304 110 60% –80% 307 111 56 63% –77% 309 112 67% –74% 312 113 57 29 15 8 4 71% –71% 315 114 74% –67% 318 115 58 77% –63% 321 116 80% –60% 323 117 59 30 83% –56% 326 118 86% –51% 329 119 60 88% –47% 332 120 90% –43% 335 121 61 31 16 92% –38% 338 122 94% –34% 340 123 62 96% –29% 343 124 97% –24% 346 125 63 32 98% –20% 349 126 99% –15% 352 127 64 100% –10% 354 128 100% –5% 357

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ELECTRICAL

ANGLE

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SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

nRESET, nENBLE and nSLEEP Operation

The nRESET pin, when driven active low, resets internal logic, and resets the step table to the home position. It also disables the H-bridge drivers. The STEP input is ignored while nRESET is active.

The nENBL pin is used to control the output drivers and enable/disable operation of the indexer. When nENBL is low, the output H-bridges are enabled, and rising edges on the STEP pin are recognized. When nENBL is high, the H-bridges are disabled, the outputs are in a high-impedance state, and the STEP input is ignored.

Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (approximately 1 ms) needs to pass before applying a STEP input, to allow the internal circuitry to stabilize.

Protection Circuits

The DRV8824 is fully protected against undervoltage, overcurrent and overtemperature events.

Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is removed and re-applied.

Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense circuitry used for PWM current control, and is independent of the I

resistor value or VREF voltage.

SENSE

Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level operation will automatically resume.

Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. Operation will resume when VMrises above the UVLO threshold.

Product Folder Link(s): DRV8824

P = R (I )

TOT DS(ON) OUT(RMS)

· ·

DRV8824

SLVSA06B –OCTOBER 2009–REVISED APRIL 2010

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THERMAL INFORMATION

Thermal Protection

The DRV8824 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level.

Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature.

Power Dissipation

Power dissipation in the DRV8824 is dominated by the power dissipated in the output FET resistance, or R Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.

where P current being applied to each winding. I

is the total power dissipation, R

TOT

DS(ON)

OUT(RMS)

is the resistance of each FET, and I

OUT(RMS)

is the RMS output

is equal to the approximately 0.7x the full-scale output current setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are conducting winding current for each winding (one high-side and one low-side).

The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking.

Note that R

increases with temperature, so as the device heats, the power dissipation increases. This must

DS(ON)

be taken into consideration when sizing the heatsink.

DS(ON)

(2)

Heatsinking

The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers.

For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com.

In general, the more copper area that can be provided, the more power can be dissipated. It can be seen that the heatsink effectiveness increases rapidly to about 20 cm2, then levels off somewhat for larger areas.

Product Folder Link(s): DRV8824

PACKAGE OPTION ADDENDUM

www.ti.com 16-Apr-2010

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

DRV8824PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

(3)

no Sb/Br)

DRV8824PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

DRV8824PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2010

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DRV8824PWPR HTSSOP PWP 28 2000 346.0 346.0 33.0

Pack Materials-Page 2

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TEXAS INSTRUMENTS DRV8824 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

APPLICATIONS

DEVICE INFORMATION

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS (PRELIMINARY)

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

TIMING REQUIREMENTS

FUNCTIONAL DESCRIPTION

PWM Motor Drivers

Current Regulation

Decay Mode

Blanking Time

Microstepping Indexer

nRESET, nENBLE and nSLEEP Operation

Protection Circuits

Overcurrent Protection (OCP)

Thermal Shutdown (TSD)

Undervoltage Lockout (UVLO)

THERMAL INFORMATION

Thermal Protection

Power Dissipation

Heatsinking