TEXAS INSTRUMENTS DRV8312, DRV8332 Technical data

GVDD

GVDD

PVDD

M

Controller

RESET_A

PWM_B

OC_ADJ

GND

GND_A

GND_B

OUT_B

PVDD_B

AGND

VREG

M3

M2

BST_B

NC

NC

GND

RESET_C

RESET_B

VDD

GVDD_C

OUT_C

PVDD_C

BST_C

GVDD_C

PWM_C

GND_C

M1 GND

GVDD_B

OTW

FAULT

PWM_A

GVDD_A

BST_A

PVDD_A

OUT_A

DRV8312
DRV8332

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Three Phase PWM Motor Driver

Check for Samples: DRV8312, DRV8332

1

FEATURES

• High-Efficiency Power Stage (up to 97%) with
Low R

• Operating Supply Voltage up to 50 V
(70 V Absolute Maximum)

• DRV8312 (power pad down): up to 3.5 A
Continuous Phase Current (6.5 A Peak)

• DRV8332 (power pad up): up to 8 A
Continuous Phase Current ( 13 A Peak)

• Independent Control of Three Phases

• PWM Operating Frequency up to 500 kHz

• Integrated Self-Protection Circuits Including
Undervoltage, Overtemperature, Overload, and
Short Circuit

• Programmable Cycle-by-Cycle Current Limit
Protection

• Independent Supply and Ground Pins for Each
Half Bridge

• Intelligent Gate Drive and Cross Conduction
Prevention

• No External Snubber or Schottky Diode is
Required

APPLICATIONS

• BLDC Motors

• Three Phase Permanent Magnet Synchronous
Motors

• Inverters

• Half Bridge Drivers

• Robotic Control Systems

MOSFETs (80 mΩ at TJ= 25°C)

DS(on)

SLES256 –MAY 2010

Because of the low R

of the power MOSFETs

DS(on)

and intelligent gate drive design, the efficiency of
these motor drivers can be up to 97%, which enables
the use of smaller power supplies and heatsinks, and
are good candidates for energy efficient applications.

The DRV8312/32 require two power supplies, one at
12 V for GVDD and VDD, and another up to 50 V for
PVDD. The DRV8312/32 can operate at up to
500-kHz switching frequency while still maintain
precise control and high efficiency. They also have an
innovative protection system safeguarding the device
against a wide range of fault conditions that could
damage the system. These safeguards are
short-circuit protection, overcurrent protection,
undervoltage protection, and two-stage thermal
protection. The DRV8312/32 have a current-limiting
circuit that prevents device shutdown during load
transients such as motor start-up. A programmable
overcurrent detector allows adjustable current limit
and protection level to meet different motor
requirements.

The DRV8312/32 have unique independent supply
and ground pins for each half bridge, which makes it
possible to provide current measurement through
external shunt resistor and support half bridge drivers
with different power supply voltage requirements.

Simplified Application Diagram

DESCRIPTION

The DRV8312/32 are high performance, integrated
three phase motor drivers with an advanced
protection system.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2010, Texas Instruments Incorporated

DRV8312
DRV8332

SLES256 –MAY 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range unless otherwise noted

VDD to GND –0.3 V to 13.2 V
GVDD_X to GND –0.3 V to 13.2 V
PVDD_X to GND_X
OUT_X to GND_X
BST_X to GND_X
Transient peak output current (per pin), pulse width limited by internal over-current protection circuit. 16 A
Transient peak output current for latch shut down (per pin) 20 A
VREG to AGND –0.3 V to 4.2 V
GND_X to GND –0.3 V to 0.3 V
GND to AGND –0.3 V to 0.3 V
PWM_X, RESET_X to GND –0.3 V to 4.2 V
OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V
FAULT, OTW to GND –0.3 V to 7 V
Maximum continuous sink current (FAULT, OTW) 9 mA
Maximum operating junction temperature range, T
Storage temperature, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.

(2)

(2)

(2)

J

STG

(1)

VALUE

–0.3 V to 70 V
–0.3 V to 70 V
–0.3 V to 80 V

-40°C to 150°C

–55°C to 150°C

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

PVDD_X Half bridge X (A, B, or C) DC supply voltage 0 50 52.5 V
GVDD_X Supply for logic regulators and gate-drive circuitry 10.8 12 13.2 V
VDD Digital regulator supply voltage 10.8 12 13.2 V
I

O_PULSE

I

O

F

SW

R

OCP_CBC

R

OCP_OCL

C

BST

T

ON_MIN

T

A

(1) Depending on power dissipation and heat-sinking, the DRV8312/32 can support ambient temperature in excess of 85°C. Refer to the

package heat dissipation ratings table and package power deratings table.

Pulsed peak current per output pin (could be limited by thermal) 15 A
Continuous current per output pin (DRV8332) 8 A
PWM switching frequency 500 kHz
OC programming resistor range in cycle-by-cycle current limit modes 22 200 kΩ
OC programming resistor range in OC latching shutdown modes 19 200 kΩ
Bootstrap capacitor range 33 220 nF
Minimum PWM pulse duration, low side 50 nS
Operating ambient temperature -40 85

(1)

°C

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DRV8332

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PACKAGE HEAT DISSIPATION RATINGS

PARAMETER DRV8312 DRV8332

R

, junction-to-case (power pad / heat slug)

qJC

thermal resistance

R

, junction-to-ambient thermal resistance 25 °C/W

qJA

Exposed power pad / heat slug area 34 mm

PACKAGE POWER DERATINGS (DRV8312)

PACKAGE POWER

TA= 25°C

RATING

44-PIN TSSOP (DDW) 5.0 W 40.0 mW/°C 3.2 W 2.6 W 1.0 W

(1) Based on EVM board layout

DERATING

FACTOR TA= 70°C POWER TA= 85°C POWER TA= 125°C POWER

ABOVE TA= RATING RATING RATING

25°C

1.1 °C/W 0.9 °C/W
This device is not intended to be used

without a heatsink. Therefore, R
specified. See the Thermal Information
section.

2

(1)

80 mm

2

MODE SELECTION PINS

MODE PINS

M3 M2 M1

1 0 0 1 3PH or 3 HB Three-phase or three half bridges with cycle-by-cycle current limit
1 0 1 1 3PH or 3 HB
0 x x Reserved

1 1 x Reserved

OUTPUT

CONFIGURATION

DESCRIPTION

Three-phase or three half bridges with OC latching shutdown (no
cycle-by-cycle current limit)

qJA

is not

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

GVDD_C

VDD

NC
NC

PWM_C

RESET_C

RESET_B

OC_ADJ

GND

AGND

VREG

M3

M2

M1

PWM_B

RESET_A

PWM_A

NC

FAULT

NC

OTW

GVDD_B

DRV8312

DDW Package

(Top View)

GVDD_C
BST_C

NC
PVDD_C
PVDD_C
OUT_C
GND_C
GND

GND

NC
NC
BST_B
PVDD_B
OUT_B
GND_B
GND_A
OUT_A
PVDD_A
PVDD_A

NC
BST_A
GVDD_A

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

1

2

3

4

5

6

7

8

9

11

10

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

26

27

25

24

23

22

21

20

19

GVDD_B

FAULT

RESET_A

RESET_C

PWM_B

PWM_C

RESET_B

OTW

GND

PWM_A

AGND

OC_ADJ

VREG

VDD

GVDD_C

M3

M2

M1

GVDD_A

BST_A

PVDD_A

OUT_A

GND_A

GND_B

OUT_B

PVDD_B

BST_B

NC

NC

GND

GND

GND_C

OUT_C

PVDD_C

BST_C

GVDD_C

DRV8332

DKD Package

(Top View)

DRV8312
DRV8332

SLES256 –MAY 2010

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DEVICE INFORMATION

Pin Assignment

Here are the pinouts for the DRV8312/32:

• DRV8312: 44-pin TSSOP power pad down DDW package. This package contains a thermal pad that is
located on the bottom side of the device for dissipating heat through PCB.

• DRV8332: 36-pin PSOP3 DKD package. This package contains a thick heat slug that is located on the top
side of the device for dissipating heat through heatsink.

Pin Functions

PIN

NAME DRV8312 DRV8332

FUNCTION

AGND 12 9 P Analog ground
BST_A 24 35 P High side bootstrap supply (BST), external capacitor to OUT_A required
BST_B 33 28 P High side bootstrap supply (BST), external capacitor to OUT_B required
BST_C 43 20 P High side bootstrap supply (BST), external capacitor to OUT_C required

GND 13, 36, 37 8 P Ground
GND_A 29 32 P Power ground for half-bridge A requires close decoupling capacitor to ground
GND_B 30 31 P Power ground for half-bridge B requires close decoupling capacitor to ground
GND_C 38 23 P Power ground for half-bridge C requires close decoupling capacitor to ground

GVDD_A 23 36 P Gate-drive voltage supply
GVDD_B 22 1 P Gate-drive voltage supply

GVDD_C 1, 44 18, 19 P Gate-drive voltage supply

M1 8 13 I Mode selection pin
M2 9 12 I Mode selection pin
M3 10 11 I Reserved mode selection pin, AGND connection is recommended
NC 3,4,19,20,25,34,35 26,27 - No connection pin. Ground connection is recommended

OC_ADJ 14 7 O Analog overcurrent programming pin, requires resistor to AGND

(1) I = input, O = output, P = power, T = thermal
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(1)

DESCRIPTION

DRV8312
DRV8332

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PIN

NAME DRV8312 DRV8332

OTW 21 2 O Overtemperature warning signal, open-drain, active-low. An internal pull-up resistor

OUT_A 28 33 O Output, half-bridge A
OUT_B 31 30 O Output, half-bridge B
OUT_C 39 22 O Output, half-bridge C

PVDD_A 26,27 34 P Power supply input for half-bridge A requires close decoupling capacitor to ground.
PVDD_B 32 29 P Power supply input for half-bridge B requires close decoupling capacitor to gound.
PVDD_C 40,41 21 P Power supply input for half-bridge C requires close decoupling capacitor to ground.

PWM_A 17 4 I Input signal for half-bridge A
PWM_B 15 6 I Input signal for half-bridge B

PWM_C 5 16 I Input signal for half-bridge C
RESET_A 16 5 I Reset signal for half-bridge A, active-low
RESET_B 7 15 I Reset signal for half-bridge B, active-low
RESET_C 6 15 I Reset signal for half-bridge C, active-low

FAULT 18 3 O Fault signal, open-drain, active-low. An internal pull-up resistor to VREG (3.3 V) is

VDD 2 17 P Power supply for digital voltage regulator requires capacitor to ground for

VREG 11 10 P Digital regulator supply filter pin requires 0.1-mF capacitor to AGND.

THERMAL PAD -- N/A T Solder the exposed thermal pad at the bottom of the DRV8312DDW package to the

HEAT SLUG N/A -- T Mount heatsink with thermal interface to the heat slug on the top of the

FUNCTION

(1)

to VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be
obtained by adding external pull-up resistor to 5 V

provided on output. Level compliance for 5-V logic can be obtained by adding
external pull-up resistor to 5 V

decoupling.

landing pad on the PCB. Connect the landing pad through vias to large ground
plate for better thermal dissipation.

DRV8332DKD package to improve thermal dissipation.

DESCRIPTION

SLES256 –MAY 2010

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Temp.
Sense

M1

M2

RESET_A

FAULT

OTW

AGND

OC_ADJ

VREG VREG

VDD

M3

Power

On

Reset

Under-

voltage

Protection

GND

PWM_C OUT_C

GND_C

PVDD_C

BST_C

Timing

Gate

Drive

PWM

Rcv.

Overload

Protection

I

sens e

GVDD_C

RESET_B

4

Protection

and

I/OLogic

PWM_B OUT_B

GND_B

PVDD_B

BST_B

Timing

Gate

Drive

Ctrl.

PWM

Rcv.

GVDD_B

PWM_A OUT_A

GND_A

PVDD_A

BST_A

Timing

Gate

Drive

Ctrl.

PWM

Rcv.

GVDD_A

Ctrl.

InternalPullup

ResistorstoVREG

4

RESET_C

DRV8312
DRV8332

SLES256 –MAY 2010

SYSTEM BLOCK DIAGRAM

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ELECTRICAL CHARACTERISTICS

TA= 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, fSw= 400 kHz, unless otherwise noted. All performance is in accordance
with recommended operating conditions unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Internal Voltage Regulator and Current Consumption

V

REG

I

VDD

I

GVDD_X

I

PVDD_X

Output Stage

R

DS(on)

V

F

t

R

t

F

t

PD_ON

t

PD_OFF

t

DT

I/O Protection

V

uvp,G

(1)

V

uvp,hyst

(1)

OTW
OTW

hyst

(1)

OTSD
OTE- OTE-OTW overtemperature detect temperature

OTW

differential

OTSD

HYST

I

OC

I

OCT

Static Digital Specifications

V

IH

V

IH

V

IL

l

lkg

OTW / FAULT

R

INT_PU

V

OH

V

OL

(1) Specified by design

Voltage regulator, only used as a reference node VDD = 12 V 2.95 3.3 3.65 V

VDD supply current

Gate supply current per half-bridge

Idle, reset mode 9 12 mA
Operating, 50% duty cycle 10.5
Reset mode 1.7 2.5 mA
Operating, 50% duty cycle 8

Half-bridge X (A, B, or C) idle current Reset mode 0.7 1 mA

MOSFET drain-to-source resistance, low side (LS) TJ= 25°C, GVDD = 12 V 80 mΩ
MOSFET drain-to-source resistance, high side (HS) TJ= 25°C, GVDD = 12 V 80 mΩ
Diode forward voltage drop TJ= 25°C - 125°C, IO= 5 A 1 V
Output rise time Resistive load, IO= 5 A 14 nS
Output fall time Resistive load, IO= 5 A 14 nS
Propagation delay when FET is on Resistive load, IO= 5 A 38 nS
Propagation delay when FET is off Resistive load, IO= 5 A 38 nS
Dead time between HS and LS FETs Resistive load, IO= 5 A 5.5 nS

Gate supply voltage GVDD_X undervoltage
protection threshold

Hysteresis for gate supply undervoltage event 0.8 V
Overtemperature warning 115 125 135 °C

(1)

Hysteresis temperature to reset OTW event 25 °C
Overtemperature shut down 150 °C

(1)

difference
Hysteresis temperature for FAULT to be released

(1)

following an OTSD event
Overcurrent limit protection Resistor—programmable, nominal, R

Overcurrent response time 250 ns

Time from application of short condition to Hi-Z of
affected FET(s)

= 27 kΩ 9.7 A

OCP

High-level input voltage PWM_A, PWM_B, PWM_C, M1, M2, M3 2 3.6 V
High-level input voltage RESET_A, RESET_B, RESET_C 2 3.6 V

Low-level input voltage 0.8 V

PWM_A, PWM_B, PWM_C, M1, M2, M3,
RESET_A, RESET_B, RESET_C

Input leakage current -100 100 mA

Internal pullup resistance, OTW to VREG, FAULT to
VREG

High-level output voltage V

Internal pullup resistor only 2.95 3.3 3.65
External pullup of 4.7 kΩ to 5 V 4.5 5

20 26 35 kΩ

Low-level output voltage IO= 4 mA 0.2 0.4 V

8.5 V

25 °C

25 °C

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1.10

0.96

1.00

0.98

1.02

1.04

GVDD – Gate Drive – V

Normalized R / (R at 12 V)

DS(on) DS(on)

11.010.08.0 10.59.58.5 9.0 11.5

1.06

1.08

12

T = 25°C

J

0

100

40

50

60

70

80

90

Efficiency – %

f – Switching Frequency – kHz

0 100 150 200 250 300 350 400 450 50050

10

20

30

Load = 5 A
PVDD = 50 V
T = 75°C

Full Bridge

C

1.6

0.4

0.6

0.8

1.0

T – Junction Temperature – C

J

o

Normalized R / (R at 25 C)

DS(on) DS(on)

o

8040 120–40 6020–20 0 100

1.2

1.4

140

GVDD = 12 V

–1

5

0

1

2

3

V – Voltage – V

I – Current – A

1.20.80 10.60.2 0.4

4

6

T = 25°C

J

DRV8312
DRV8332

SLES256 –MAY 2010

TYPICAL CHARACTERISTICS

EFFICIENCY NORMALIZED R

vs vs

SWITCHING FREQUENCY (DRV8332) GATE DRIVE

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DS(on)

Figure 1. Figure 2.

NORMALIZED R

DS(on)

vs DRAIN TO SOURCE DIODE FORWARD

JUNCTION TEMPERATURE ON CHARACTERISTICS

Figure 3. Figure 4.

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0

100

10

20

30

40

50

60

70

80

90

Output Duty Cycle – %

Input Duty Cycle – %

9060 1000 70402010 30 50 80

f = 500 kHz
T = 25°C

S

C

DRV8312
DRV8332

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SLES256 –MAY 2010

TYPICAL CHARACTERISTICS (continued)

OUTPUT DUTY CYCLE

vs

INPUT DUTY CYCLE

Figure 5.

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DRV8332

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THEORY OF OPERATION

POWER SUPPLIES

To facilitate system design, the DRV8312/32 need
only a 12-V supply in addition to H-Bridge power
supply (PVDD). An internal voltage regulator provides
suitable voltage levels for the digital and low-voltage
analog circuitry. Additionally, the high-side gate drive
requiring a floating voltage supply, which is
accommodated by built-in bootstrap circuitry requiring
external bootstrap capacitor.

To provide symmetrical electrical characteristics, the
PWM signal path, including gate drive and output
stage, is designed as identical, independent
half-bridges. For this reason, each half-bridge has a
separate gate drive supply (GVDD_X), a bootstrap
pin (BST_X), and a power-stage supply pin
(PVDD_X). Furthermore, an additional pin (VDD) is
provided as supply for all common circuits. Special
attention should be paid to place all decoupling
capacitors as close to their associated pins as
possible. In general, inductance between the power
supply pins and decoupling capacitors must be
avoided. Furthermore, decoupling capacitors need a
short ground path back to the device. SYSTEM POWER-UP/POWER-DOWN

For a properly functioning bootstrap circuit, a small ceramic capacitor (an X5R or better) must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the The DRV8312/32 do not require a power-up power-stage output is low, the bootstrap capacitor is sequence. The outputs of the H-bridges remain in a charged through an internal diode connected high impedance state until the gate-drive supply between the gate-drive power-supply pin (GVDD_X) voltage GVDD_X and VDD voltage are above the and the bootstrap pin. When the power-stage output undervoltage protection (UVP) voltage threshold (see is high, the bootstrap capacitor potential is shifted the Electrical Characteristics section of this data above the output potential and thus provides a sheet). Although not specifically required, holding suitable voltage supply for the high-side gate driver. RESET_A, RESET_B, and RESET_C in a low state In an application with PWM switching frequencies in while powering up the device is recommended. This the range from 10 kHz to 500 kHz, the use of 100-nF allows an internal circuit to charge the external ceramic capacitors (X5R or better), size 0603 or bootstrap capacitors by enabling a weak pulldown of 0805, is recommended for the bootstrap supply. the half-bridge output. These 100-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to Powering Down keep the high-side power stage FET fully turned on during the remaining part of the PWM cycle. In an application running at a switching frequency lower than 10 kHz, the bootstrap capacitor might need to be increased in value.

Special attention should be paid to the power-stage
power supply; this includes component selection,
PCB placement, and routing. As indicated, each
half-bridge has independent power-stage supply pin
(PVDD_X). For optimal electrical performance, EMI
compliance, and system reliability, it is important that
each PVDD_X pin is decoupled with a ceramic
capacitor (X5R or better) placed as close as possible
to each supply pin. It is recommended to follow the
PCB layout of the DRV8312/32 EVM board.

The 12-V supply should be from a low-noise,
low-output-impedance voltage regulator. Likewise, the
50-V power-stage supply is assumed to have low
output impedance and low noise. The power-supply
sequence is not critical as facilitated by the internal
power-on-reset circuit. Moreover, the DRV8312/32
are fully protected against erroneous power-stage
turn-on due to parasitic gate charging. Thus,
voltage-supply ramp rates (dv/dt) are non-critical
within the specified voltage range (see the
Recommended Operating Conditions section of this
data sheet).

SEQUENCE

Powering Up

The DRV8312/32 do not require a power-down
sequence. The device remains fully operational as
long as the gate-drive supply (GVDD_X) voltage and
VDD voltage are above the UVP voltage threshold
(see the Electrical Characteristics section of this data
sheet). Although not specifically required, it is a good
practice to hold RESET_A, RESET_B and RESET_C
low during power down to prevent any unknown state
during this transition.

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