Siemens SAB-C504-2R24M, SAB-C504-2R40M, SAB-C504-2RM, SAB-C504-L24M, SAB-C504-L40M Datasheet

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Data Sheet 05.96

Microcomputer Components

C504

8-Bit CMOS Microcontroller

C504 Revision History: Current Version: 05.96

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Edition 05.96

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8-Bit CMOS Microcontroller C504

Advance Information

• Fully compatible to standard 8051 microcontroller

• Up to 40 MHz operating frequency

• 16 K×8 ROM (C504-2R only, optional ROM protection)

• 256×8 RAM

• 256×8 XRAM

• Four 8-bit ports, (2 ports with mixed analog/digital I/O capability)

• Three 16-bit timers/counters (timer 2 with up/down counter feature)

• Capture/compare unit for PWM signal generation and signal capturing

- 3-channel, 16-bit capture/compare unit

- 1-channel, 10-bit compare unit

• Compare unit

• USART

• 10-bit A/D Converter with 8 multiplexed inputs

• Twelve interrupt sources with two priority levels

• On-chip emulation support logic (Enhanced Hooks Technology

)

• Programmable 15-bit Watchdog Timer

• Oscillator Watchdog

• Fast Power On Reset

• Power Saving Modes

• M-QFP-44 package

• Temperature ranges: SAB-C504 T

SAF-C504 TA : – 40 to 85°C SAH-C504 TA : – 40 to 110°C (max. operating frequency.: TBD) SAK-C504 TA : – 40 to 125°C (max. operating frequency.: 12 MHz)

: 0 to 70°C

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C504

The C504 with its capture compare unit (CCU) especially provides a functionality, which allows to use the microcontroller in motor control applications. Further, the C504 is functionally upward compatible with the SAB 80C52/C501 microcontroller and can replace it in existing applications. The C504-2R contains a non-volatile 16K×8 read-only program memory, a volatile on-chip 512×8 read/write data memory, four 8-bit wide ports, three 16-bit timers/counters, a 16-bit capture/ compare unit with compare timer, a 10-bit compare timer, a twelve source, two priority level interrupt structure, a serial port, versatile fail save mechanisms, on-chip emulation support logic, and a genuine 10-bit A/D converter. The C504-L is identical to the C504-2R, except that it lacks the program memory on chip. Therefore, the term C504 refers to all versions within this data sheet unless otherwise noted.

Ordering Information Type Ordering Code Package Description

(8-Bit CMOS microcontroller)

SAB-C504-LM Q67120-C1048 P-MQFP-44 for external memory (12 MHz) SAB-C504-L24M Q67120-C1049 P-MQFP-44 for external memory (24 MHz) SAB-C504-L40M Q67120-C1050 P-MQFP-44 for external memory (40 MHz) SAB-C504-2RM Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (12 MHz) SAB-C504-2R24M Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (24 MHz) SAB-C504-2R40M Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (40 MHz)

Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C504) and – 40 ˚C to

125 ˚C (SAK-C504) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer.

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C504

Figure 1 Logic Symbol

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C504

Figure 2 Pin Configuration (top view)

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Table 1 Pin Definitions and Functions

C504

Symbol Pin Number

(P-MQFP-44)

P1.0-P1.7 40-44,

1-3

I/O

Function

I/O Port 1

is an 8-bit bidirectional port. Port pins can be used for digital input/output. P1.0 - P1.3 can also be used as analog inputs of the A/D-converter. As secondary digital functions, port 1 contains the timer 2 pins and the capture/compare inputs/outputs. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. The functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / T2 Analog input channel 0 /

P1.1 / AN1 / T2EX Analog input channel 1 /

P1.2 / AN2 / CC0 Analog input channel 2 /

P1.3 / AN3 / COUT0 Analog input channel 3 /

P1.4 / CC1 Input/output of capture/compare

P1.5 / COUT1 Output of capture/compare

P1.6 / CC2 Input/output of capture/compare

P1.7 / COUT2 Output of capture/compare

input to counter 2

capture/reload trigger of timer 2 / up-down count

input/output of capture/compare channel 0

output of capture/compare channel 0

channel 1

channel 2

RESET 4 I RESET

A high level on this pin for one machine cycle while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC.

*) I = Input

O = Output

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Table 1 Pin Definitions and Functions (cont’d)

C504

Symbol Pin Number

(P-MQFP-44)

P3.0-P3.7 5, 7-13

I/O

Function

I/O Port 3

is an 8-bit bidirectional port. P3.0 (R×D) and P3.1 (T×D) operate as defined for the C501. P3.2 to P3.7 contain the external interrupt inputs, timer inputs, input and as an additional optinal function four of the analog inputs of the A/D-converter. Port 3 pins are assigned to be used as analog inputs via the bits of SFR P3ANA. P3.6/WR can be assigned as a third interrupt input. The functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data

P3.1 / TxD Transmitter data output (asynch.) or

P3.2 / AN4 / INT0 Analog input channel 4 / external

P3.3 / AN5 / INT1 Analog input channel 5 / external

P3.4 / AN6 / T0 Analog input channel 6 / timer 0

P3.5 / AN7 / T1 Analog input channel 7 / timer 1

P3.6 / WR / INT2 WR control output; latches the data

P3.7 / RD RD control output; enables the

input/output (synch.) of serial interface

clock output (synch.) of serial interface

interrupt 0 input / timer 0 gate control input

interrupt 1 input / timer 1 gate control input

counter input

byte from port 0 into the external data memory / external interrupt 2 input

external data memory

CTRAP 6 I CCU Trap Input

With CTRAP = low the compare outputs of the CAPCOM unit are switched to the logic level as defined in the COINI register (if they are enabled by the bits in SFR TRCON). CTRAP is an input pin with an internal pullup resistor. For power saving reasons, the signal source which drives the CTRAP input should be at high or floating level during power-down mode.

*) I = Input

O = Output

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Table 1 Pin Definitions and Functions (cont’d)

C504

Symbol Pin Number

(P-MQFP-44)

I/O *)

Function

XTAL2 14 – XTAL2

Output of the inverting oscillator amplifier.

XTAL1 15 – XTAL1

Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed.

P2.0-P2.7 18-25 I/O Port 2

is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register.

, in the DC characteris-tics) because

PSEN 26 O The Program Store Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periodes except during external data memory accesses. Remains high during internal program execution.

ALE 27 O The Address Latch Enable

output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periodes except during an external data memory access. When instructions are executed from internal ROM (

EA=1) the ALE generation can be disabled

by bit EALE in SFR SYSCON.

*) I = Input

O = Output

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Table 1 Pin Definitions and Functions (cont’d)

C504

Symbol Pin Number

(P-MQFP-44)

I/O *)

Function

COUT3 28 O 10-Bit compare channel output

This pin is used for the output signal of the 10-bit compare timer 2 unit. COUT3 can be disabled and set to a high or low state.

EA 29 I External Access Enable

When held at high level, instructions are fetched from the internal ROM (C504-2R only) when the PC is less than 4000H.When held at low level, the C504 fetches all instructions from external program memory. For the C504-L this pin must be tied low.

P0.0-P0.7 37-30 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impendance inputs.Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup resistors when issuing 1 s. Port 0 also outputs the code bytes during program verification in the C504-2R. External pullup resistors are required during program (ROM) verification.

AREF

AGND

*) I = Input

O = Output

38 – Reference voltage for the A/D converter. 39 – Reference ground for the A/D converter. 16 – Ground (0V) 17 – Power Supply (+5V)

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C504

Functional Description

The C504 basic architecture is fully compatible to the standard 8051 microcontroller family. While maintaining all architectural and operational characteristics of the SAB 80C52 / C501, the C504 incorporates some enhancements such as on-chip XRAM, A/D converter, fail save mechanisms, and a versatile capture/compare unit.

Figure 3 shows a block diagram of the C504.

Figure 3 Block Diagram of the C504

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C504

CPU

The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % threebyte instructions. With a 12 MHz crystal, 58 % of the instructions are executed in 1.0µs (24 MHz: 500 ns, 40 MHz : 300 ns).

Special Function Register PSW (Address D0H) Reset Value : 00

Bit No. MSB LSB

Bit Function

CY Carry Flag

AC Auxiliary Carry Flag

F0 General Purpose Flag RS1

RS0

CY AC

Used by arithmetic instruction.

Used by instructions which execute BCD operations.

RS1 RS0 Function

RS1 RS0 OV F1 PD0

PSW

0 0 Bank 0 selected, data address 00H-07 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F

OV Overflow Flag

Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

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H H H H

Memory Organization

The C504 CPU manipulates operands in the following four address spaces:

– up to 64 Kbyte of external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – 256 bytes of internal XRAM data memory – a 128 byte special function register area

Figure 4 illustrates the memory address spaces of the C504.

C504

Figure 4 C504 Memory Map

The XRAM in the C504 is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types (MOVX instructions) must be used for accessing the XRAM. The XRAM can be enabled and disabled by the XMAP bit in the SYSCON register.

ROM Protection

The C504-2R ROM version allows to protect the content of the internal ROM against read out by non authorized people. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C504-2R ROM version has to define whether ROM protection has to be selected or not.

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C504

Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 63 special function register (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. The SFRs of the C504 are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C504. Table 3 illustrates the contents of the SFRs in numeric order of their addresses.

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C504

Table 2 Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B DPH DPL PSW SP

SYSCON

Interrupt System

IEN0 IEN1 CCIE IP0 IP1 ITCON

Ports P0

P1 P1ANA P2 P3 P3ANA

A/DConverter

ADCON0 ADCON1

ADDATH ADDATL P1ANA P3ANA

Serial Channels

PCON SBUF SCON

Timer 0/ Timer 1

TCON TH0 TH1 TL0 TL1 TMOD

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer System Control Register

Interrupt Enable Register 0 Interrupt Enable Register 1

Capture/Compare Interrupt Enable Reg. Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Trigger Condition Register

Port 0 Port 1

Port 1 Analog Input Selection Register Port 2 Port 3

Port 3 Analog Input Selection Register A/D Converter Control Register 0

A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte

Port 1 Analog Input Selection Register

Port 3 Analog Input Selection Register

Power Control Register Serial Channel Buffer Register Serial Channel Control Register

Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register

E0 F0

83 82

81 B1

A9 D6

B9 9A

80 90 90 A0 B0 B0

DC D9 DA 90 B0

87 99

98 88

8C 8D 8A 8B 89

H H

H H H

H H

H H H

H H H H

1) 4)

XX10XXX0 0X000000

XX000000 00

XX000000 XX000000 00101010

XXXX1111 FF

XX1111XX XX000000

01XXX000 00

00XXXXXX XXXX1111 XX1111XX

000X0000

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