Siemens HYB314171BJ-50, HYB314171BJ-60, HYB314171BJ-70, HYB314171BJL-50, HYB314171BJL-60 Datasheet

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3.3V 256 K x 16-Bit Dynamic RAM

HYB 314171BJ-50/-60/-70

3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh

Preliminary Information

• 262 144 words by 16-bit organization

• 0 to 70 °C operating temperature

• Fast access and cycle time

• RAS access time:

50 ns (-50 version) 60 ns (-60 version) 70 ns (-70 version)

• CAS access time:

15ns (-50,-60 version) 20 ns (-70 version)

• Cycle time:

95 ns (-50 version) 110 ns (-60 version) 130 ns (-70 version)

• Fast page mode cycle time

35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version)

• Single + 3.3 V (± 0.3 V) supply with a built-

in VBB generator

HYB 314171BJL-50/-60/-70

• Low Power dissipation

max. 450 mW active (-50 version) max. 378 mW active (-60 version) max. 306 mW active (-70 version)

• Standby power dissipation

7.2 mW standby (TTL)

3.6 mW max. standby (CMOS)

0.72 mW max. standby (CMOS) for Low Power Version

• Output unlatched at cycle end allows two-

dimensional chip selection

• Read, write, read-modify write, CAS-

before-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability

• 2 CAS / 1 WE control

• Self Refresh (L-Version)

• All inputs and outputs TTL-compatible

• 512 refresh cycles / 16 ms

• 512 refresh cycles / 128 ms

Low Power Version only

• Plastic Packages:

P-SOJ-40-1 400mil width

The HYB 314171BJ/BJL is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The HYB 314171BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 314171BJ/BJL to be packed in a standard plastic 400mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include Self Refresh (LVersion), single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance logic device families.

Semiconductor Group 1

7.96

HYB 314171BJ/BJL-50/-60/-70

3.3V 256 K x 16-DRAM

Ordering Information Type Ordering Code Package Description

HYB 314171BJ-50 on request P-SOJ-40-1 3.3V 50ns 256 K x 16 DRAM HYB 314171BJ-60 on request P-SOJ-40-1 3.3V 60 ns 256 K x 16 DRAM HYB 314171BJ-70 on request P-SOJ-40-1 3.3V 70 ns 256 K x 16 DRAM HYB 314171BJL-50 on request P-SOJ-40-1 3.3V 50 ns 256 K x 16 DRAM HYB 314171BJL-60 on request P-SOJ-40-1 3.3V 60 ns 256 K x 16 DRAM HYB 314171BJL-70 on request P-SOJ-40-1 3.3V 70 ns 256 K x 16 DRAM

Truth Table RAS LCAS UCAS WE OE I/O1-I/O8 I/O9-I/O16 Operation

High-Z

Dout

High-Z

Dout

Din

Don't care

Din

High-Z

Pin Names

A0-A8 Address Inputs

High-Z

Dout

Don't care

Din

High-Z

Standby

Refresh

Lower byte read

Upper byte read

Word read

Lower byte write

Upper byte write

Word write

RAS Row Address Strobe UCAS, LCAS Column Address Strobe WE Read/Write Input OE Output Enable I/O1 – I/O16 Data Input/Output

Power Supply (+ 3.3 V) Ground (0 V)

N.C. No Connection

Semiconductor Group 2

Pin Configuration

(top view)

HYB 314171BJ/BJL-50/-60/-70

3.3V 256 K x 16-DRAM

P-SOJ-40-1

Semiconductor Group 3

HYB 314171BJ/BJL-50/-60/-70

3.3V 256 K x 16-DRAM

Block Diagram

Semiconductor Group 4

HYB 314171BJ/BJL-50/-60/-70

3.3V 256 K x 16-DRAM

Absolute Maximum Ratings

Operating temperature range ........................................................................................ 0 to + 70 °C

Storage temperature range..................................................................................... – 55 to + 150 °C

Input/output voltage ....................................................................................– 1 to (VCC + 0.5, 4.6) V

Power supply voltage..................................................................................................– 1 to + 4.6 V

Data out current (short circuit) ................................................................................................50 mA

Note:

Stresses above those listed under“Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics

= 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 5 ns

Parameter Symbol Limit Values Unit Notes

min. max.

Input high voltage Input low voltage

OUT

LVTTL Output high voltage ( LVTTL Output low voltage ( LVCMOS Output high voltage ( LVCMOS Output low voltage ( Input leakage current, any input

(0 V <

< VCC + 0.3 V, all other inputs = 0 V)

Output leakage current

(DO is disabled, 0 V < Average

supply current: -50 version

< VCC+ 0.3 V )

OUT

= – 2.0 mA) V

= 2 mA) V

= – 100 µA) V

OUT

= 100 µA) V

OUT

-60 version

-70 version

V V

I(L)

O(L)

CC1

2.0 VCC + 0.5 V 1 – 1.0 0.8 V 1

2.4 – V 1 – 0.4 V 1

2.4 – V 1 – 0.4 V 1 – 10 10 µA1

– 10 10 µA1

– 125

mA 2, 3, 4 105 85

Standby

supply current

(RAS = LCAS = UCAS = WE = VIH)

Average

supply current during

RAS-only refresh cycles: -50 version

-60 version

-70 version

Semiconductor Group 5

CC2

CC3

–2 mA

–

125

2, 4

105 85

HYB 314171BJ/BJL-50/-60/-70

3.3V 256 K x 16-DRAM

DC Characteristics (cont’d) Parameter Symbol Limit Values Unit Notes

min. max.

Average

supply current during

fast page mode operation: -50 version

-60 version

-70 version

Standby

supply current

(RAS = LCAS = UCAS = WE = VCC – 0.2 V) Average

supply current during

CAS-before-RAS refresh mode:

-50 version

-60 version

-70 version

Standby

current (L-version)

(RAS = LCAS = UCAS = WE= VCC– 0.2 V) Self Refresh Current (L-version)

RAS, LCAS, UCAS = 0.2 V

( A0–A8=VCC – 0.2 V or 0.2 V)

CC4

CC5

CC6

CC5

CCS

–

2, 3, 4

65 60

–1mA1

–

125

2, 4

105 85

– 200 µA

– 250 µA

Capacitance

= 0 to 70 °C; VCC = 3.3 V ± 0.3 V, f = 1 MHz

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A8) Input capacitance (

RAS, UCAS, LCAS, WE, OE) C

Output capacitance (l/O1 to l/O16)

–6pF –7pF –7pF

Semiconductor Group 6

HYB 314171BJ/BJL-50/-60/-70

3.3V 256 K x 16-DRAM

AC Characteristics

= 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 5 ns

Parameter

5)6)

Symbol

-50 - 60 - 70

min. max. min. max. min. max.

Common Parameters

Random read or write cycle time t RAS precharge time t RAS pulse width t CAS pulse width t Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time t RAS to column address delay

t t t t

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

95 – 110 – 130 – ns 35 – 40 – 50 – ns 50 10k 60 10k 70 10k ns 15 10k 15 10k 20 10k ns 0–0–0–ns 10 – 10 – 10 – ns 0–0–0–ns 10 – 15 – 15 – ns 20 35 20 45 20 50 ns 15 25 15 30 15 35 ns

time

Limit Values

Unit

Note

RAS hold time t CAS hold time t CAS to RAS precharge time t Transition time (rise and fall) Refresh period Refresh period (L-version)

Read Cycle

Access time from RAS t Access time from CAS t Access time from column address t OE access time t Column address to

RAS lead time t Read command setup time Read command hold time Read command hold time ref. to

RAS

t t t

RSH

CSH

CRP

REF

RAC

CAC

OEA

RAL

RCS

RCH

RRH

15 – 15 – 20 – ns 50 – 60 – 70 – ns 5–5–5–ns 350350350ns7 –16–16–16ms – 128 – 128 – 128 ms

–50–60–70ns –15–15–20ns –25–30–35ns

8, 9 8, 9 8,10

–15–15–20ns 25 – 30 – 35 – ns 0–0–0–ns 0–0–0–ns11 0–0–0–ns11

CAS to output inlow-Z t

CLZ

0–0–0–ns8

Semiconductor Group 7

HYB 314171BJ/BJL-50/-60/-70

3.3V 256 K x 16-DRAM

Parameter

Output buffer turn-off delay from CAS

Output buffer turn-off delay from OE

Data to

OE low delay t CAS high to datadelay t OE high to data delay t

Write Cycle

Write command hold time t Write command pulse width Write command setup time Write command to Write command to

RAS lead time t

CAS lead time t Data setup time Data hold time Data to

CAS lowdelay t

Symbol

OFF

OEZ

DZO

CDD

ODD

WCH

WCS

RWL

CWL

DZC

Note

Limit Values

Unit

-50 - 60 - 70

min. max. min. max. min. max.

015020020ns12

0–0–0–ns13 15 – 20 – 20 – ns 14 15 - 20 – 20 – ns 14

10 – 10 – 15 – ns 10 – 10 – 15 – ns 0–0–0–ns15 15 – 15 – 20 – ns 15 – 15 – 20 – ns 0–0–0–ns16 10 – 15 – 15 – ns 16 0–0–0–ns13

Read-modify-Write Cycle

Read-write cycle time t RAS to WE delay time t CAS to WE delay time t Column address to

WE delay

time OE command hold time t

Fast Page Mode Cycle

Fast page mode cycle time t CAS precharge time t Access time from

CAS precharge t RAS pulse width t RAS hold time from CAS

precharge

RWC

RWD

CWD

AWD

OEH

CPA

RASP

RHCP

140 – 160 – 185 – ns 75 – 90 – 100 – ns 15 40 – 45 – 50 – ns 15 50 – 60 – 65 – ns 15

15 – 20 – 20 – ns

35 – 40 – 45 – ns 10 – 10 – 10 – ns –30–35–40ns7 50 200k 60 200k 70 200k ns 30 – 35 – 40 – ns

Semiconductor Group 8

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