Richtek RT8812AGQW Schematic [ru]

RT8812A

Dual-Pha se PWM Controller with PWM-VID Reference

General Description

The RT8812A is a 2/1 phase synchronous Buck PWM controller which is optimized for high performa nce gra phic microprocessor and computer applications. The IC integrates a Constant-On-T ime (COT) PWM controller , two MOSFET drivers with internal bootstrap diodes, as well as channel current balance and protection functions including Over Voltage Protection (OVP), Under Voltage Protection (UVP), current limit, and thermal shutdown into the WQFN-20L 3x3 package.

The RT8812A adopts R Current limit is accomplished through continuous inductorcurrent-sense, while R accurate channel current balance. Using the method of current sampling utilizes the best advantages of each technique.

The RT8812A fe atures external reference input and PWMVID dyna mic output voltage control, in which the feedba ck voltage is regulated and tracks external input reference voltage. Other features include adjustable switching frequency , dynamic pha se number control, internal/external soft-start, power good indicator, a nd enable function s.

current sensing technique.

DS(ON)

current sensing is used for

DS(ON)

Features



Dual-Phase PWM Controller





 Two Embedded MOSFET Drivers and Embedded



Switching Boot Diode



 External Reference Input Control



 PWM-VID Dynamic Voltage Control



 Dynamic Phase Number Control



 Lossless R



 Internal Fixed and External Adjustable Soft-Start



 Adjustable Current Limit Threshold



 Adjustable Switching Frequency



 UVP/OVP Protection



 Shoot Through Protection and Short Pulse Free



Current Sensing for Current Balance

DS(ON)

Technology



 Support an Ultra-Low Output Voltage as Standby



Voltage



 Thermal Shutdown



 Power Good Indicator



 RoHS Compliant and Halogen Free



Applications

 CPU/GPU Core Power Supply  Notebook PC Memory Power Supply  Chipset/RAM Power Supply  Generic DC/DC Power Regulator

Simplified Application Circuit

RT8812A

PVCC

BOOT1

UGATE1 PHASE1

TON

PGOOD

PSI

UGATE2 PHASE2

VID

EN GND

RGND

VSNS

DS8812A-04 November 2013 www.richtek.com

OUT

GND_SNS

OUT_SNS

RT8812A

Ordering Information

RT8812A

Package Type QW : WQFN-20L 3x3 (W-Type)

Lead Plating System G : Green (Halogen Free and Pb Free)

Note : Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

Marking Information

0Z= : Product Code

0Z=YM

YMDNN : Date Code

DNN

Function Pin Description

Pin Configurations

(TOP VIEW)

PHASE1

LGATE1

BOOT1

UGATE1

1 2 3

EN PSI VID SS

GND

REFIN

REFADJ

WQFN-20L 3x3

LGATE2

PVCC

17181920

9876

TON

VREF

PHASE2

RGND

BOOT2

UGATE2

PGOOD

VSNS

115

Pin No. Pin Name Pin Function

1 BO OT 1 Boo tstrap Suppl y for PWM 1. T his pin powe rs the high sid e MOS FET driv er.

2 UGATE1

Hig h Side G ate Dri ver of PW M 1. This pi n provi des t he gate driv e for t he conv ert er's high side MOSFET. Connect this pin to the Gate of high side MOSFET .

3 EN Enable Control Input. Active high input.

Power Sav i ng Interfac e. Wh en t h e vol tag e is pul led below 0. 8V, th e dev ice will o per a te

4 PSI

int o 1 p hase DEM . W hen t he volt age is between 1.2V to 1.8 V, the dev ice wi ll operat e into 1 phase force CCM . When the voltag e is between 2.4V to 5.5V, the device will operate into 2 phase force CCM.

5 VID

Programming Output Voltage Control Input. Refer to PWM-VID Dynamic Voltage

Control. 6 REF ADJ Reference Adjustment Outp ut. Refer to PWM-VID Dynami c Voltage Control. 7 REFIN External Reference Input.

8 VREF

9 TON

Reference Voltage Output. This is a high precision voltage ref erence (2V) from the

VRE F pin to RGND pin.

ON -Ti me/Sw itchi ng Freque ncy A djustm ent In put. Con nect a 1 00pF cerami c capac itor

betw een C

and ground is optional for noise immunity enhancement.

TON

10 RGND Negative Remote Sense Input. Connect this pin to the ground of output load. 11 SS

Soft-Start Time Setting. Connect an external capacitor to adjust soft-start time. When the external capacitor is removed, the internal soft-start function will be chose.

12 VSNS Positive Remote Sense Input. Connect this pin to the positive terminal of output load. 13 PGOOD Po w er Good Indi cator Outpu t. Active high open d rain output.

14 UGATE2

Hig h Side G ate Dri ver of PW M 2. This pi n provi des t he gate driv e for t he conv ert er's

high side MOSFET. Connect this pin to the Gate of high side MOSFET .

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Pin No. Pin Name Pin Function

15 BOOT2 Bootstrap Supply for PWM 2. This pin powers the hi gh side MOSFET driver.

Switch Node for PWM2. This pin is return node of the high side driver of PWM 2.

16 PHASE2

Connect this pin to the Source of high side MOSFET together with the Drain of low side MOSFET and the inductor.

17 LGATE2

18 PVCC

19 LGATE1

Low Side Gate Driver of PWM 2. This pin provides the gate drive for the converter's low side MOSFET. Connect this pin to the Gate of low side MOSFET.

Suppl y Voltage Input. Connect this pi n to a 5V bias supply. Place a high quality bypass capacitor from this pin to GND.

Low Side Gate Driver of PWM 1. This pin provides the gate drive for the converter's low side MOSFET. Connect this pin to the Gate of low side MOSFET.

Switch Node for PWM1. This pin is return node of the high side driver of PWM 1.

20 PHASE1

Connect this pin to the Source of high side MOSFET together with the Drain of low side MOSFET and the inductor.

21 (Exposed Pad) GND

Ground. The Exposed pad should be soldered to a large PCB and connected to GND for maximum thermal dissipation.

Function Block Diagram

RT8812A

VID

REFADJ

PSI

REFIN

VSNS

RGND

VREF

Threshold

Select

40% REFIN

Soft-Start

& Slew Rate

Control

Enable

Logic

To Power On Reset

Reference

Output Gen.

Mode Select

PWM

CMP

To Driver Logic To Power On Reset

Power On Reset

& Central Logic

Control & Protection Logic

TON

Gen 1

TON

Gen 2

Boot-Phase Detection 1

Boot-Phase Detection 2

PWM1

Driver

Logic

PWM2

PVCC

PGOOD

BOOT1 UGATE1 PHASE1

LGATE1

BOOT2 UGATE2

PHASE2 LGATE2

TON

VIN

Detection

Current

To Driver LogicZCDPHASE1

To Protection Logic

Balance

Current

Limit

S/H

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RT8812A

Operation

The RT8812A is a 2/1 phase synchronous Buck PWM controller with integrated drivers which are optimized for high performance gra phic microprocessor a nd computer application s. The IC integrates a COT (Constant-On-T ime) PWM controller with two MOSFET drivers, as well as output current monitoring and protection functions. Referring to the function block diagra m of TON Genx, the synchronous UGA TE driver is turned on at the beginning of each cycle. After the internal one-shot timer expires, the UGATE driver will be turned off. The pulse width of this one-shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly consta nt over the input voltage range a nd output voltage. Another one-shot sets a minimum off-time.

The RT8812A also features a PWM-VID dyna mic voltage control circuit driven by the pulse width modulation method. This circuit reduces the device pin count and enables a wide dyna mic voltage ra nge.

Soft-Start (SS)

For internal soft-start function, an internal current source charges an internal capacitor to build the soft-start ra mp voltage. The output voltage will track the internal ramp voltage during soft-start interval. For external soft-start function, an additional capacitor connected from SS pin to the GND will be charged by a current source and determines the soft-start time.

PGOOD

The power good output is an open drain architecture.

Current Balance

The RT8812A implements internal current balance mechanism in the current loop. The R T8812A sens es per phase current a nd compares it with the average current. If the sensed current of any particular pha se is higher tha n average current, the on-time of this pha se will be adjusted to be shorter.

Current Limit

The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle. Thus, the current to the load exceeds average output inductor current, the output voltage falls and eventually crosses the under voltage protection threshold, inducing IC shutdown.

Over Voltage Protection (OVP) & Under Voltage Protection (UVP)

The output voltage is continuously monitored for over voltage and under voltage protection. When the output voltage exceeds its set voltage threshold (If V OV = 2V, or V

> 1.33V, OV = 1.5 x V

REFIN

≤ 1.33V,

), UGATE goes low and LGATE is forced high; when it is less than 40% of its set voltage, under voltage protection is triggered and then both UGA TE a nd LGATE gate drivers are f orced low. The controller is latched until PVCC is re-supplied and exceeds the POR rising threshold voltage or EN is reset.

When the soft-start is finished, the PGOOD open drain output will be high impedance.

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RT8812A

Absolute Maximum Ratings (Note 1)

 TO N to G ND------------------------------------------------------------------------------------------------------------------ −0.3V to 30V  RGN D t o G ND --------------------------------------------------------------------------------------------------------------- −0.7V to 0.7V  BOOTx to PHASEx-------------------------------------------------------------------------------------------------------- −0.3V to 6V  PHASEx to GND

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 30V <20ns ------------------------------------------------------------------------------------------------------------------------- −8V to 36V

 UGATEx to PHASEx

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 6V <20ns ------------------------------------------------------------------------------------------------------------------------- −5V to 7.5V

 LGA TEx to GND

 Other Pins-------------------------------------------------------------------------------------------------------------------- −0.3V to 6V  Power Dissipation, P

WQFN-20L 3x3 ------------------------------------------------------------------------------------------------------------- 3.33W

 Package Thermal Resistance (Note 2)

WQF N-20L 3x3, θJA-------------------------------------------------------------------------------------------------------- 30°C/W WQFN-20L 3x3, θJC------------------------------------------------------------------------------------------------------- 7.5°C/W

 Lead T e mperature (Soldering, 10 sec.)-------------------------------------------------------------------------------- 26 0°C  Junction T emperature------------------------------------------------------------------------------------------------------ 150°C  Storage T emperature Range --------------------------------------------------------------------------------------------- −65°C to 150°C  ESD Susceptibility (Note 3)

HBM (Human Body Model)----------------------------------------------------------------------------------------------- 2kV

@ T

= 25°C

Recommended Operating Conditions (Note 4)

 Input V oltage, V  Supply Voltage, V  Junction T emperature Range--------------------------------------------------------------------------------------------- −40°C to 125°C  Ambient T emperature Range--------------------------------------------------------------------------------------------- −40°C to 85°C

----------------------------------------------------------------------------------------------------------- 7V to 26V

---------------------------------------------------------------------------------------------------- 4.5V to 5.5V

PVCC

Electrical Characteristics

= 25°C unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

PWM Controlle r

PVCC Supply Voltage V PVCC Supply Current I PVCC Shu tdown Curre nt I PVCC POR Threshold 3.8 4.1 4.4 V POR Hysteresis -- 0.3 -- V Switching Frequency fSW R

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4.5 -- 5.5 V

PVCC SUPPLY SHDN

EN = 3.3V, Not Switching -- 1.5 2 mA

EN = 0V -- -- 10 A

= 500k (Note 5) 270 300 330 kHz

TON

RT8812A

Parameter Symbol Test Conditions Min Typ Max Unit

Minimum On-Time t M inimu m O ff-Time t

ON(MIN) OFF(MIN)

-- 70 -- ns

-- 300 -- ns

EN Input Voltage

Logic-High V Logic-Low V

1.6 -- --

ENH

-- -- 0.8

ENL

Mode Decision

PSI High Threshold V PSI Intermediate Threshold V PSI Low Threshold V

High-Level V

VID Input Voltage

Low-Level V

Enables Two Phases with FCCM 2.4 -- -- V

PSIH

Enables One Phases with FCCM 1.2 -- 1.8 V

PSIM

Enables One Phases with DEM -- -- 0.8 V

PSIL

2 -- --

VIDH

-- -- 1

VIDL

Protection Function

Zero Current Crossing Threshold

Current Limit Setting Current I Current Limit Setting Current

Temperature Coefficient Current Limit Threshold R Absolute Over Voltage

Protection Threshold Relative Over Voltage Protection Threshold

8 -- 8 mV

9 10 11 A

OCS ET

OCS ET_TC

OVP, Ab sol u te

OVP, Relat i ve

-- 6300 -- ppm/C = 10k -- 60 -- mV

OCS ET

 1. 33V 1.9 2 2.1 V

REFIN

> 1.33V 145 150 155 %

REFIN

OV Fault Delay FB forced above OV threshold -- 5 -- s Rel ative Under V oltage

Protection Threshold

UVP 35 40 45 %

UVP

UV Fault Delay FB forced above UV threshold -- 3 -- s Thermal Shutdown Threshold TSD -- 150 -- C PGOOD Blanking Time

(Internal)

From EN = high to PGOOD = high with VSNS within regulation point

-- 2.5 -- ms

From first UGAT E t o VSNS

VSNS Soft-Start (Internal)

regu lati on point, V

REFIN

= 1V and

-- 0.7 -- ms

VSNS ini tial = 0V

Soft-Start Current Source ISS -- 5 -- A

Er ror Amp l i f ier

VSNS Error Comparator Threshold (Valley)

= 1V 17.5 12.5 7.5 mV

REFIN

Reference

Reference Voltage V

VREF

Sourcing Current = 1mA, VID no Switching

1.98 2 2.02 V

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Parameter Symbol Test Conditions Min Typ Max Unit

Driver On-Resistance

RT8812A

UGATE Dri ver Source R UGATE Dri ver Sink R LGATE Driver Source R LGATE Driver Sink R

UGATEsr UGATEsk LGATEsr LGATEsk

Dead-Time

Internal Boost Charging Switch On-Resistance

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Not production tested. Test condition is V

is measured at T

measured at the exposed pad of the package.

BOOT

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

BOOTx  PHAS Ex Force d to 5V -- 2 4 

BOOTx  PHASEx Forced to 5V -- 1 2 

LG ATEx, Hi gh State -- 1.5 3 

LGATEx, Low State -- 0.7 1.5 

From LGATE Falling to UGATE Rising

From UGATE Falling to LGATE Rising

PVCC to BOOTx, I

= 8V, V

OUT

BOOT

= 1V, I

= 10mA -- 40 80 

= 20A using application circuit.

OUT

-- 30 --

-- 20 --

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RT8812A

Typical Application Circuit

TON

500k

Optional

PSI

VID

Enable

20k

REFADJ

2k 2.7nF

RGND

REF2

18k

100k

RGND

STANDBY

2.2

STANDBY

5.1k

REF1

BOOT

RGND

PVCC

1µF

PGOOD

RGND

2.2µF

0.1µF

20k

REFADJ

REFIN

TON

4 5

PVCC

TON

PGOOD PSI VID

EN VREF

REFADJ

REFIN

RT8812A

UGATE1 PHASE1

LGATE1

UGATE2 PHASE2

LGATE2

GND

21 (Exposed pad)

BOOT1

BOOT2

RGND

VSNS

1 2

20 19

14 16

10 12

Figure 1. 2 Active Pha se Configuration

0 0

47pF

0 0

0.1µF

OCSET

10k

0.1µF

0.36µH/1.05m

10µF x 2

NC NC

10µF x 2

NC NC



470µF/50V

22µF x 15

330µF/2V x 4

470µF/50V

1010

OUT

GND_SNS

OUT_SNS

STANDBY

2.2

5.1k

REF1

BOOT

RGND

PVCC

500k

1µF

RGND

TON

Optional

PGOOD

Enable

20k

RGND

REF2

18k

PSI VID

REFADJ

2.7nF

2.2µF

PVCC

BOOT1

RT8812A

UGATE1

RGND

TON

100k

0.1µF

20k

REFADJ

4 5

TON

PGOOD PSI

VID EN

VREF

REFADJ

PHASE1 LGATE1

RGND

VSNS

BOOT2 UGATE2 PHASE2

C NC

REFIN

LGATE2

GND

21 (Exposed pad)

RGND

Figure 2. 1 Active Pha se Configuration

0.1µF

20 19

OCSET

10k

47pF

10µF x 2

0.36µH/1.05m

NC NC

470µF/50V



22µF x 15

330µF/2V x 4

OUT

1010

10 12

GND_SNS

OUT_SNS

14 16

Floating

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Typical Operating Characteristics

RT8812A

Eff iciency (%)

(ns)

Efficiency vs. Load Current

100%

100

90%

80%

70%

60%

50%

40%

30%

20%

10%

0 5 10 15 20 25 30 35 40 45 50 55 60

VIN = 19V, V

= 0.9V, 2 Phase Operation

OUT

Load Curren t (A)

TON vs. Temperature

185.0

182.5

180.0

177.5

175.0

172.5

PVCC

= 5V,

Effic iency vs. Load Current

100%

100

90%

80%

70%

60%

50%

40%

Eff iciency (%)

30% 20%

20 10

10%

0.01 0.1 1 10

= 0.9V, 1 Phase with DEM Operation

OUT

Load Current (A)

vs. Temperature

2.04

2.03

2.02

2.01

(V)

2.00

REF

1.99

REF

VIN = 19V, V

PVCC

= 5V,

170.0

167.5

165.0

VIN = 19V, V

-50 -25 0 25 50 75 100 125

= 5V, No Load

PVCC

Temperatur e (°C)

Inductor Current vs. Output Current

Induct or Current (A)

0 102030405060

Phase 1

Phase 2

VIN = 19V, V

Output Current (A)

PVCC

= 5V

1.98

1.97

1.96

(5V/Div)

OUT

(1V/Div)

UGATE1

(50V/Div)

UGATE2

(50V/Div)

VIN = 19V, V

-50 -25 0 25 50 75 100 125

= 5V, No Load

PVCC

Temperatur e (°C)

Power On from EN

VIN = 19V, V

Time (1ms/Div)

PVCC

= 5V, I

OUT

= 50A

DS8812A-04 November 2013 www.richtek.com

RT8812A

(5V/Div)

OUT

(1V/Div)

UGATE1

(50V/Div)

UGATE2

(50V/Div)

PVCC

(5V/Div)

Power Off from EN

VIN = 19V, V

Time (1ms/Div)

PVCC

= 5V, I

Power Off from VCC

OUT

= 50A

PVCC

(5V/Div)

OUT

(1V/Div)

UGATE1

(50V/Div)

UGATE2

(50V/Div)

DVID

(2V/Div)

Power On from VCC

VIN = 19V, V

Time (1ms/Div)

PVCC

= 5V, I

Dynamic Output Voltage Control

VIN = 19V, V

PVCC

= 5V

OUT

= 50A

OUT

(1V/Div)

UGATE1

(50V/Div)

UGATE2

(50V/Div)

DVID

(2V/Div)

OUT

(1V/Div)

UGATE1

(50V/Div)

UGATE2

(50V/Div)

VIN = 19V, V

PVCC

= 5V, I

OUT

= 50A

Time (1ms/Div)

Dynamic Output Voltage Control

OUT

VIN = 19V, V

= 50A, V

= 1.2V to 0.6V

REFIN

PVCC

= 5V

OUT

(1V/Div)

UGATE1

(50V/Div)

UGATE2

(50V/Div)

OUT

(100mV/Div)

OUT

(50A/Div)

UGATE2

(50V/Div)

UGATE1

(50V/Div)

= 50A, V

OUT

= 0.6V to 1.2V

REFIN

Time (50μs/Div)

Load Transient Response

VIN = 19V, V

PVCC

= 5V

Time (50μs/Div)

Time (20μs/Div)

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RT8812A

OUT

(100mV/Div)

OUT

(50A/Div)

UGATE2

(50V/Div)

UGATE1

(50V/Div)

VSNS

(1V/Div)

UGATE1

(20V/Div)

Load Transient Response

VIN = 19V, V

Time (20μs/Div)

PVCC

UVP

= 5V

VSNS

(1V/Div)

UGATE1

(20V/Div)

LGATE1 (5V/Div)

(20A/Div)

UGATE1

(50V/Div)

OVP

VIN = 19V, V

Time (100μs/Div)

PVCC

OCP

= 5V, No Load

LGATE1 (5V/Div)

VIN = 19V, V

PVCC

Time (20μs/Div)

= 5V, I

OUT

= 40A

LGATE1

(10V/Div)

VIN = 19V, V

Time (20μs/Div)

PVCC

= 5V

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RT8812A



Application Information

The RT8812A is a dual-phase synchronous Buck PWM controller with integrated drivers which is optimized for high performance gra phic microprocessor a nd computer application s. A COT (Consta nt-On-Time) PWM controller and two MOSFET drivers with internal bootstrap diodes are integrated so that the external circuit can be easily designed and the number of component is reduced.

The topology solves the poor load tran sient response timing problems of fixed-frequency mode PWM and avoids the problems caused by widely varying switching frequencies in conventional constant on-time and constant off-time PWM schemes.

The IC supports dynamic mode transition function with various operating states, which include dual-phase with CCM operation and single phase with diode emulation mode. These different operating states ma ke the system efficiency as high as possible.

The RT8812A provides a PWM-VID dynamic control operation in which the feedback voltage is regulated a nd tracks external input reference voltage. It also features complete fault protection functions including over voltage, under voltage and current limit.

PWM Operation

The RT8812A integrates a Con stant-On-Ti me (COT) PWM controller, and the controller provides the PWM signal which relies on the output ripple voltage comparing with internal reference voltage a s shown in Figure 4. Referring to the function block diagram of TON Genx, the synchronous UGA TE driver is turned on at the beginning of each cycle. After the internal one-shot timer expires, the UGATE driver will be turned off. The pulse width of this one-shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly consta nt over the input voltage and output voltage ra nge. Another one-shot sets a minimum off-time.

OUT

PEAK

OUT

VALLEY

REF

Figure 4. Constant On-T ime PWM Control

On-Time Control

Remote Sense

The RT8812A uses the remote sense path (VSNS and RGND) to overcome voltage drops in the power lines by sensing the voltage directly at the end of GPU. Normally , to protect remote sense path disconnecting, there are two resistors (R

) connecting between local sense path

Local

and remote sense path. That is, in application with re mote sense, the R no need of remote sense, the R

is recommended to be 10Ω to 100Ω. If

Local

is recommended to

Local

be 0Ω.

BOOT

UGATE PHASE

LGATE

RGND

VSNS

Local Sense Path

OUT

+ R

Local

Remote Sense Path

Local

GPU GPU

Figure 3. Output Voltage Sensing

The on-time one-shot comparator has two inputs. One input monitors the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this ca pa citor to charge from zero volts to V

, thereby making the on-time of the

OUT

high side switch directly proportional to output voltage and inversely proportional to input voltage. The implementation results in a nearly constant switching frequency without the need for a clock generator .

2 V 3.2p



T = R

ON TON

OUT

V0.5





And then the switching frequency FS is :

F= V V T

SOUT INON

TON

value of R



is a resistor connected from the VIN to TON pin. The

can be selected a ccording to Figure 5.

TON

The recommend operation frequency range is 150kHz to 600kHz.

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RT8812A

800

700

600

500

400

Frequency (kHz) 1

300

200

150 250 350 450 550 650 750

(k )

TON

Figure 5. Frequency vs. R

TON

Active Phase Circuit setting

The RT8812A operates as active phase being 2 phase, and 1 phase. When programming active phase being 1 phase, The UGATE2, BOOT2, PHASE2, and LGATE 2 pins are floating. As programming active phase being 1 phase, the voltage setting at PSI pin can't higher than

1.8V.

Mode Selection

The RT8812A ca n operate into 2 pha ses with force CCM, 1 phase with f orce CCM, and 1 pha se with DEM a ccording to PSI voltage setting. If PSI voltage is pulled below 0.8V , the controller will operate into 1 phase with DEM. In DEM operation, the RT8812A automatically reduces the operation frequency at light load conditions for saving power loss. If PSI voltage is pulled between 1.2V to 1.8V, the controller will switch operation into 1 phase with force CCM. If PSI voltage is pulled between 2.4V to 5.5V, the controller will switch operation into 2 phase with force CCM. The operation mode is summarized in Table 1. Moreover, the PSI pin is valid after POR of VR.

Table 1

Operation Phase Number PSI Voltage Setting

1 phase with DEM 0V to 0.8V 1 phase with CCM 1.2V to 1.8V 2 phase with CCM 2.4V to 5.5V

Diode-Emulation Mode

In diode-emulation mode, the RT8812A automatically reduces switching frequency at light-load conditions to maintain high efficiency . As the output current decrea ses from heavy-load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low side MOSFET allows only partial of negative current when the inductor freewheeling current reaches negative value. As the load current is further decreased, it takes a longer time to discharge the output capacitor to the level that requires the next “ON” cycle. In reverse, when the output current increases from light load to heavy load, the switching frequency increa ses to the preset value as the inductor current reaches the continuous conduction condition. The transition load point to the light load operation is shown in Figure 6 and ca n be calculated as follows :

(V V )



LOAD(SKIP) ON

IN OUT



where tON is on-time.

Slope = (V

- V

OUT

) / L

PEAK

LOAD

= I

PEAK/2

Figure 6. Boundary condition of CCM/DEM

The switching waveforms may be noisy and a synchronous in light loading diode-emulation operation condition, but this is a normal operating condition that results in high light-load efficiency . T rade-off in DEM noise vs. light-load efficiency is made by varying the inductor value. Generally , low inductor values produce a broad high efficiency ra nge vs. load curve, while higher values result in higher full load efficiency (a ssuming that the coil resistance remains f ixed) and less output voltage ripple. The disadvantages for using higher inductor values include larger physical size and degraded load-tran sient response (especially at low input voltage levels).

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RT8812A

Forced-CCM Mode

The low noise, forced-CCM mode disables the zerocrossing comparator, which controls the low side switch on-time. This causes the low side gate drive waveform to be the complement of the high side gate drive waveform. This in turn causes the inductor current to reverse at light loads a s the PWM loop to maintain a duty ratio V

OUT/VIN

The benefit of forced-CCM mode is to keep the switching frequency fairly constant.

Enable and Disable

The EN pin is a high impedance input that allows power sequencing between the controller bia s voltage and another voltage rail. The RT8812A remains in shutdown if the EN pin is lower than 800mV . When the EN voltage rises above the 1.6V high level threshold, the RT8812A will begin a new initialization and soft-start cycle.

Power On Reset (POR), UVLO

Power On Reset (POR) occurs when V

rises above

PVCC

to approximately 4.1V (typical), the RT8812A will reset the fault latch circuit and prepare for PWM operation. When the V

is lower than 3.8V (typical), the U nder Voltage

PVCC

Lockout (UVLO) circuitry inhibits switching by keeping UGATE a nd LGA TE low.

Soft-Start

The RT8812A provides both intern al soft-start function and external soft-start function. The soft-start function is used to prevent large inrush current and output voltage overshoot while the converter is being powered up. The soft-start function automatically begins once the chip is enabled. There is a delay time around 1.1ms from EN goes high to V

begins to ra mp-up.

OUT

signal as well a s the input current at power up are li mited. The soft-start process is finished until both the internal SSOK and external SSOK go high and protection is not triggered. Figure 7 shows the internal soft-start sequence.

PVCC

OUT

Internal SS

External SS

Internal SSOK

External SSOK

LGATE

UGATE

PGOOD

Current Limit

Programming

Soft-Start

Normal

Figure 7. Internal Soft-Start Sequence

The RT8812A also provide s an external soft-start function, and the external soft-start sequence is shown in Figure

8. The external ca pa citor connected from SS pin to GND is charged by a 5μA current source to build a soft-start voltage ramp. If the extern al soft-start function is chosen, the external soft-start time should be set longer than internal soft-start time to avoid output voltage tra cking the internal soft-start ra mp. The recommend external soft-start slew rate is from 0.1V/ms to 0.4V/ms.

Soft

Discharged

If the external ca pacitor between the SS pin a nd ground is removed, the internal soft-start function will be chosen. An internal current source charges the internal soft-start ca pacitor so that the internal soft-start voltage ramps up linearly The output voltage will track the intern al soft-start voltage during the soft-start interval. After the internal softstart voltage exceeds the REFIN voltage, the output voltage no longer tracks the internal soft-start voltage but f ollows the REFIN voltage. Theref ore, the duty cycle of the UGA TE

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Power Good Output (PGOOD)

RT8812A

PVCC

OUT

Internal SS

External SS

Internal SSOK

External SSOK

LGATE

UGATE

PGOOD

VCC

Current Limit

Programming

Soft-Start

Normal

Discharged

Figure 8. External Soft-Start Sequence

OUT

Soft

REFIN

The PGOOD pin is a n open drain output, and it requires a pull-up resistor. During soft-start, the PGOOD is held low and is allowed to be pulled high after V

achieved over

OUT

UVP threshold and under OVP thre shold. In additional, if any protection is triggered during operation, the PGOOD will be pulled low immediately.

PWM VID and Dynamic Output Voltage Control

The RT8812A fe atures a PWM VID input f or dynamic output voltage control as shown in Figure 10, which reduces the number of device pin and enable s a wide dynamic voltage range. The output voltage is determined by the applied voltage on the REFIN pin. The PWM duty cycle determines the variable output voltage at REFIN.

VID VREF

REFADJ

Buffer

RGND

REFIN

STANDBY

Standby

Mode Control

RGND

BOOT

REF2

PWM IN

REF1

RGND

REFADJ

Figure 10. PWM VID Analog Circuit Diagram

Figure 9. External Soft-Start Time Setting

With the external circuit and VID control signal, the controller provides three operation modes shown as Figure

The soft-start time can be calculated as :

(C V )



t =

Where ISS = 5μA (typ.), V

SS REFIN

is the voltage of REFIN

REFIN

pin, and CSS is the external capacitor placed from SS to GND.

11.

REFIN

PWM VID

STANDBY

CONTROL

VREF

BOOT

MODE

NORMAL

MODE

BOOT

MODE

STANDBY

MODE

Figure 1 1. PWM VID T i me Diagra m

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RT8812A

Boot Mode

V = V

min VREF

VID is not driven, a nd the buffer output is tri-state. At this time, turn off the switch Q1 a nd connect a resistor divider as shown in Figure 11 that can set the REFIN voltage to be V

V = V

BOOT VREF

Where V Choose R

and R

REF1 BOOT

BOOT REF1

a s the following equation :

BOOT







RRR

REF1 REF2 BOOT



= 2V (typ.)

VREF

to be approximately 10kΩ, and the R

REF2

can be calculated by the following equations :

BOOT

RVV



RVV

REF2 VREF BOOT



RVV

REF2 VREF BOOT



REF2 VREF BOOT





BOOT





BOOT

REF2



REF1





BOOT

V = V

By choosing R calculated by the following equation :

The relationship between VID duty an d V Figure 12, and V below :

V = V NV

where V

V =

Standby Mode

An external control can provide a very low voltage to meet V

operating in standby mode. If the VID pin is floating

OUT

and switch Q1 is ena bled as shown in Figure 1 1, the REFIN pin can be set for standby voltage according to the

where Nmax is the number of total availa ble voltage steps and N is the number of step at a specific V voltage VID period (T unit pulse width (Tu) and the available step number (N The recommended Tu is 27ns.

calculation below :

V = V

STANDBY VREF

R// R

By choosing R



R R (R // R )

REF1 BOOT REF2 STANDBY

, R

REF1

REF2 STANDBY



REF2

, and R

BOOT

, the R

STANDBY

can

be calculated by the following equation :

STANDBY

RVV RRR

REF2 REF STANDBY REF1 REF2 BOOT



RRR V

 



REF2 REF1 BOOT STANDBY

   





R R // (R R )

REF1 REFADJ BOOT REF2

max VREF

min

N = 1



STEP

(V V )

REFIN

N = 1

REFADJ

OUT min STEP

STEP



R // (R R )



REF1

REF1 min

max min

REF2



REF2 BOOT

REFADJ BOOT REF2





(R // R ) R R

REF1 REFADJ BOOT REF2

, R

REF2

, and R



REF2



, the R

BOOT

REFADJ

can be





is shown in

REFIN

can be set a ccording to the calculation

OUT



is the resolution of each voltage step 1 :



max min

max

. The dynamic

OUT

N = 2

= Tu x N

vid

0.5

) is determined by the

max

N = N

max

VID Duty

VID Input

max



REF1

N = 2

VID Input

= N

max

x T

vid

Normal Mode

If the VID pin is driven by a PWM sign al and switch Q1 is disabled a s shown in Figure 11, the V from V PWM duty cycle and V percent PWM duty cycle. The V

min

to V

, where V

max

is the voltage at zero percent

min

is the voltage at one hundred

max

min

can be adjusted

REFIN

and V

max

can be set

Figure 12. PWM VID Analog Output

by the following equations :

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RT8812A



VID Slew Rate Control

In RT8812A, the V

slew rate is proportional to PWM

REFIN

VID duty, the rising time and falling time are the sa me. In In normal mode, the V by C

When choose C

SR = R = (R // R ) // (R +R )

SR REF1 REFADJ BOOT REF2

When choose C

SR = R = R // R R // R

SR REF1 REFADJ BOOT REF2

or C

REFADJ

(V V ) 80%

REFIN_Final REFIN_initial

REFIN

REFADJ

2.2R C



REFIN

(V V ) 80%

REFIN_Final REFIN_initial

2.2R C







The recommend SR is estimated by C

slew rate SR can be estimated

REFIN

as the following equation :



SR REFADJ



SR REFIN



REFADJ

Current Limit

The RT8812A provides cycle-by-cycle current limit control by detecting the PHASE voltage drop across the low side MOSFET when it is turned on. The current limit circuit employs a unique “valley” current sensing algorithm as shown in Figure 13. If the magnitude of the current sense signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle.

In order to provide both good accura cy and a cost effective solution, the RT8812A supports temperature compensated MOSFET R

DS(ON)

sensing.

L,PEAK

LOAD

L,VALLEY

Figure 13. “Valley” Current Limit

In an over current condition, the current to the load exceeds the average output inductor current. Thus, the output voltage falls and eventually crosses the under voltage protection threshold, inducing IC shutdown.

Current Limit Setting

Current limit threshold can be set by a resistor (R

OCSET

between LGATE1 and GND. Once PVCC exceeds the POR threshold and chip is enabled, an internal current source I R

OCSET

. The threshold range of V

OCSET

flows through R

OCSET

. The voltage across

OCSET

is stored as the current li mit protection threshold

is 50mV to 400mV .

OCSET

After that, the current source is switched off. R

where I (valley inductor current) and I

can be determined using the following equation :

OCSET

R =

OCSET

VALLEY

IR 40mV



VALLEY LGATEDS(ON)

represents the desired inductor limit current



OCSET

is current limit setting

OCSET

current which has a temperature coef ficient to compensate the temperature dependency of the R

If R

is not present, there is no current path for I

OCSET

DS(ON)

OCSET

to build the current limit threshold. In this situation, the current limit threshold is internally preset to 400mV.

Negative Current Limit

The RT8812A supports cycle-by-cycle negative current limiting. The absolute value of negative current limit threshold is the same with the positive current limit threshold. If negative inductor current is rising to trigger negative current limit, the low side MOSFET will be turned off and the current will flow to in put side through the body diode of the high side MOSFET . At this time, output voltage tends to rise because this protection limits current to discharge the output cap acitor . In order to prevent shutdown because of over voltage protection, the low side MOSFET is turned on again 400ns after it is turned off. If the device hits the negative over current threshold again before output voltage is discharged to the target level, the low side MOSFET is turned off and process repeats. It ensures maximum allowable discharge ca pa bility when output voltage continues to rise. On the other hand, if the output is discharged to the target level before negative current threshold is reached, the low side MOSFET is turned off, the high side MOSFET is then turned on, and the device keeps normal operation.

)

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RT8812A

Current Balance

The RT8812A i mplements current balance mecha nism in the current loop. The RT8812A senses per pha se current signal and compares it with the average current. If the sensed current of any particular pha se is higher tha n the

average current, the on-time of this phase will be decreased.

The current balance accuracy is major related with onresistance of low side MOSFET (R practical application, using lower R

LG,DS(ON)

). That is, in

will reduce

the current balance a ccuracy.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over voltage protection. If REFIN voltage is lower tha n 1.33V, the over voltage threshold follows to absolute over voltage 2V . If REFIN voltage is higher tha n 1.33V , the over voltage threshold follows relative over voltage 1.5 x V

REFIN

. When OVP is triggered, UGA TE goes low a nd LGA TE is forced high. The RT8812A is latched once OVP is triggered and can only be released by PVCC or EN power on reset. A 5μs delay is used in OVP detection circuit to prevent false trigger.

Output Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under voltage protection. When the output voltage is less than 40% of its set voltage, under voltage protection is triggered and then all UGATE and LGATE gate drivers are forced low. There is a 3μs delay built in the UVP circuit to prevent false transitions. During soft-start, the UVP bla nking time is equal to PGOOD bla nking ti me.

RT8812A employs ada ptive dead time control scheme to ensure safe operation without sacrificing efficiency. Furthermore, elaborate logic circuit is implemented to prevent cross conduction. For high output current application s, two power MOSFET s are usually paralleled to reduce R

. The gate driver needs to provide more

DS(ON)

current to switch on/off these paralleled MOSFET s. Gate driver with lower source/sink current cap ability results in longer rising/falling time in gate signals and higher switching loss. The RT8812A embeds high current gate drivers to obtain high efficiency power conversion.

Inductor Selection

Inductor plays an importa nce role in step-down converters because the energy from the input power rail is stored in it and then released to the load. From the viewpoint of efficiency, the DC Resistance (DCR) of inductor should be as small as possible to minimize the copper loss. In additional, the inductor occupies most of the board spa ce so the size of it is important. Low profile inductors can save board space especially when the height is limited. However, low DCR and low profile inductors are usually not cost effective.

Additionally, higher inductance results in lower ripple current, which means the lower power loss. However , the inductor current rising time increa ses with inductance value. This means the tra nsient response will be slower. Therefore, the inductor design is a trade-off between performance, size and cost.

In general, inductance is designed to let the ripple current ranges between 20% to 40% of full load current. The inductance ca n be calculated using the following equation :



VV V

MOSFET Gate Driver

L =

min

IN OUT OUT



fkI V

SW OUT_rated IN



The RT8812A integrates high current gate drivers for the MOSFETs to obtain high efficiency power conversion in synchronous Buck topology. A dead-time is used to prevent

where k is the ratio between inductor ripple current and rated output current.

the crossover conduction for high side and low side MOSFETs. Because both the two gate signals are off during the dead-time, the inductor current freewheels through the body diode of the low side MOSFET. The freewheeling current and the forward voltage of the body diode contribute power losses to the converter. The

Input Capacitor Selection

V oltage rating a nd current rating are the key parameters in selecting input ca pacitor . Generally , input capa citor ha s a voltage rating 1.5 times greater tha n the maximum input voltage is a conservatively safe design.

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RT8812A

The input capacitor is used to supply the input RMS current, which can be a pproximately calculated using the following equation :

I = I 1

RMS OUT





OUT OUT



IN IN



The next step is to select proper ca pacitor f or RMS current rating. Use more than one capacitor with low Equivalent Series Resistance (ESR) in parallel to form a capacitor bank is a good design. Besides, pla cing cera mic cap acitor close to the drain of the high side MOSFET is helpful in reducing the input voltage ripple at heavy load.

Output Capacitor Selection

The output filter ca pacitor must have ESR low enough to meet output ripple and loa d transient requirement, yet have high enough ESR to satisfy stability requirements. Also, the cap acitance must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the OVP circuit. Organic semiconductor capacitor(s) or special polymer capacitor(s) are recommended.

MOSFET Selection

The majority of power loss in the step-down power conversion is due to the loss in the power MOSFET s. For low voltage high current applications, the duty cycle of the high side MOSFET is small. Therefore, the switching loss of the high side MOSFET is of concern. Power MOSFETs with lower total gate charge are preferred in such kind of application.

However, the small duty cycle mea ns the low side MOSFET is on for most of the switching cycle. Therefore, the conduction loss tends to dominate the total power loss of the converter. To improve the overall efficiency, the MOSFETs with low R

are preferred in the circuit

DS(ON)

design. In some cases, more than one MOSFET are connected in parallel to further decrease the on-state resistance. However, this depends on the low side MOSFET driver ca pability and the budget.

Thermal Considerations

For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and a mbient temperature. The maximum power dissipation can be calculated by the following formula :

P where T

the ambient temperature, a nd θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

is the maximum junction temperature, TA is

is the junction to ambient

thermal resistance. For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to ambient thermal re sistance, θJA, is layout dependent. For WQFN-20L 3x3 package, the thermal resistance, θJA, is 30°C/W on a standard JEDEC 51-7 f our-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula :

= (125°C − 25°C) / (30°C/W) = 3.33W for

D(MAX)

WQF N-20L 3x3 pa ckage The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. The derating curve in Figure 14 allows the designer to see the effect of rising a mbient temperature on the maximum power dissipation.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Maximum Power Dissipation ( W ) 1

0.0 0 25 50 75 100 125

Ambient Temperature ( °C)

Four-Layer PCB

Figure 14. Derating Curve of Maxi mum Power

Dissipation

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RT8812A

Layout Considerations

Layout is very important in high frequency switching converter design. If designed improperly , the PCB could radiate excessive noise and contribute to the converter instability . Following layout guidelines must be considered before starting a layout for RT8812A.

 Place the RC filter as close as possible to the PVCC

pin.

 Keep current limit setting network a s close as possible

to the IC. Routing of the network should avoid coupling to high voltage switching node.

 Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as short as possible to reduce stray inductance.

 All sensitive analog traces and components such as

VSNS, RGND, EN, PSI, VID, PGOOD, VREF, TON VREF ADJ, VREFIN and TSNS should be placed away from high voltage switching nodes such as PHASE, LGA TE, UGATE, or BOOT nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback tra ce from power traces a nd components.

 Power sections should connect directly to ground

plane(s) using multiple vias as required for current handling (including the chip power ground connection s). Power components should be placed to minimize loops and reduce losses.

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Outline Dimension

RT8812A

1 2

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dimension s In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010

D 2.900 3.100 0.114 0.122 D2 1.650 1.750 0.065 0.069

E 2.900 3.100 0.114 0.122

E2 1.650 1.750 0.065 0.069

e 0.400 0.016

L 0.350 0.450

0.014 0.018

W-Type 20L QFN 3x3 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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Richtek RT8812AGQW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual