richtek RT8241D Datasheet

RT8241D

High Efficiency Single Synchronous Buck PWM Controller

General Description

The RT8241D PWM controller provides high efficiency, excellent transient response, a nd high DC output a ccuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers.

The RT8241D supports on chip voltage programming function between 0.675V and 0.9V by controlling GX digital inputs.

The constant-on-time PWM control sche me handles wide input/output voltage ratios with ea se and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency .

The RT8241D a chieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs and enter diode emulation mode at light load condition. The buck conversion allows this device to directly step down high voltage batteries at the highest possible efficiency . The RT8241D is intended for CPU core, chipset, DRAM, or other low voltage supplies as low as

0.675V.

Features

z Meet Intel VCCSA Voltage Slew Rate z Built-in 1% Reference Voltage z 2-Bit Programma ble Output V oltage with Integrated

Tra n sition Support

z Quick Load-Step Response within 100ns z 4700ppm/

Side R

z 4.5V to 26V Battery Input Range z Internal Ramp Current Limit Soft-Start Control z Drives Large Synchronous Rectifier FET s z Integrated Boost Switch z Over/Under Voltage Protection z Thermal Shutdown z Power Good Indicator z RoHS Compliant and Halogen Free

°°

°C Programmable Current Limit by Low

°°

Sensing

DS(ON)

Applications

z Notebook Computers z CPU/GPU Core Supply z Chipset/RAM Supply z Generic DC/DC Power Regulator

Pin Configurations

The RT8241D is availa ble in a WQF N-12L 2x2 package.

Ordering Information

RT8241D

Package Type QW : WQFN-12L 2x2 (W-Type)

Lead Plating System

LGATE PGOOD

PHASE UGATE

(TOP VIEW)

GND

12 1011

GND

2 3

654

9 8

G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free)

Note : Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

DS8241D-03 January 2014 www.richtek.com

WQFN-12L 2x2

VCC

BOOT

RT8241D

Marking Information

RT8241DGQW

38 : Product Code

38W

Typical Application Circuit

For Fixed V oltage Regulator :

W : Date Code

RT8241DZQW

38W

38 : Product Code W : Date Code

Chip Enable

* : Optional

12, 13 (Exposed Pad)

For Adjustable Voltage Regulator :

Chip Enable

* : Optional

12, 13 (Exposed Pad)

BYPASS

RT8241D

VCC

PGOOD

GND

RT8241D

VCC

PGOOD

GND

BOOT

UGATE

PHASE

LGATE

G0 G1 FB

BOOT

UGATE

PHASE

LGATE

G0 G1 FB

1 7

8 10

1 7

8 10

R5*

C2*

R5*

C2*

OUT

FB1

FB2

C3*

OUT

Table 1. VID Table

G0 G1 VFB

0 0 0.9V 0 1 0.8V 1 0 0.725V 1 1 0.675V

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Functional Pin Description

Pin No. Pin Name Pin Function

1 LGATE Gate Drive Output for Low Side External MOSFET.

External Inductor Connection Pin for PWM Converter. It behaves as the

2 PHASE

3 UGATE Gate Drive Output for the High Side External MOSFET. 4 BOOT

5 VCC

6 EN Chip Enable (Active High). 7 G0 2-Bit Input Pin. 8 G1 2-Bit Input Pin.

9 PGOOD Open Drain Power Good Indicator. High impedance indicates power is good.

10 FB Output Voltage Feedback Input. 11 CS

12, 13 (Exposed Pad) GND

cur rent se nse co mpar ator inp ut for lo w sid e MOSFET R reference voltage for on time generation.

Su pply In put for High S ide Dr iver. C onnec t a capa citor t o the f loating node (PHASE) pin.

Control Voltage Input. Provides the power for the buck controller, the low side dr iver a nd t he bo otstr ap c ircuit for high s ide d river . Bypa ss to GN D with a

4.7μF ceramic capacitor .

Cu r rent L im it T hre sh old Sett in g Inp ut. C on nec t a se tt in g res ist or to G ND an d the current limit threshold is equal to 1/8 of the voltage seen at this pin.

Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissip ation.

RT8241D

sensi ng and

DS(ON)

Function Block Diagram

TRIG

On-time compute

1.1V

0.45V

85% V

REF

One shot

PHASE

(Internal)

Voltage

Programmer

REF

COMP

Latch

S1 Q

Latch

S1 Q

TON

Shutdown

Thermal

Min toff

One shot

Emulation

TRIGQ

Diode

ZCD

BST switch resistance

DRV

1/8

OC threshold

UG R

LG R

leakage

DS(ON)

10µA

BOOT UGATE PHASE

VCC LGATE GND

PGOOD

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RT8241D

Absolute Maximum Ratings

z VCC, FB, PGOOD, EN, CS, G0, G1 to GND ----------------------------------------------------------------------- −0.3V to 6V z PHASE to GND

(Note 1)

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 32V <20ns ------------------------------------------------------------------------------------------------------------------------ −8V to 38V

z BOOT to PHASE ----------------------------------------------------------------------------------------------------------- −0.3V to 6V z UGATE to PHASE

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V <20ns ------------------------------------------------------------------------------------------------------------------------ −5V to 7.5V

z LGA TE to GND

z Power Dissipation, P

@ T

= 25°C

WQFN-12L 2x2 ------------------------------------------------------------------------------------------------------------ 0.606W

z Package Thermal Re sistance (Note 2)

WQFN-12L 2x2, θJA------------------------------------------------------------------------------------------------------- 165 °C/W

z Junction T emperature----------------------------------------------------------------------------------------------------- 150°C z Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------- 260°C z Storage T emperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ---------------------------------------------------------------------------------------------- 2kV MM (Ma chine Mode)------------------------------------------------------------------------------------------------------ 200V

Recommended Operating Conditions (Note 4)

z Supply Input V oltage, V z Control Voltage, V z Junction T emperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C z Ambient T emperature Range-------------------------------------------------------------------------------------------- −40°C to 85°C

------------------------------------------------------------------------------------------------ 4.5V to 26V

------------------------------------------------------------------------------------------------------ 4.5V to 5.5V

Electrical Characteristics

= 5V, V

PWM Controller

VCC Quiescent Supply Current IQ VCC Shutdown Current I

CS Shutdown Curr ent CS pull to GND -- -- 1 μA FB Error Comparator Threshold VFB V

Voltage Range V

OUT

On -Time, Pulse Width tON VFB = 0.9V (f

Minimum Off-Time t

= 8V, V

= 5V, V

= 1V, T

= 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

FB forced above the regulation point, V

VCC curren t , V

SHDN

= 5 V

= 0V -- -- 1 μA

TA = 25°C −1 0 1 T

= −40°C to 85°C (Note 5) −1.5 0 1.5

0.675 -- 3.3 V

OUT

= 300kHz) -- 40 0 -- ns

OFF

-- 500 1250 μA

250 400 550 ns

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RT8241D

Parameter Symbol Test Conditions Min Typ Max Unit

Current Se nsing

CS Source Current 9 10 11 μA CS Source Current

Temperature Coefficient Zero Crossing Threshold

Protection Function

Curr ent Limit Threshold Offset Negative Current Limit Threshold Offset

Under Voltage Protection UVP Detect, Falling Edge 0.41 0.45 0.49 V UVP Fault Delay VFB = 0.375V -- 3.5 -- μs Over Voltage Protection OVP Detect, Rising Edge 1.065 1.1 1.133 V OVP Fault Delay VFB = 1.183V -- 5 -- μs

VCC Under Voltage Lockout (UVLO) Threshold

VCC UVLO Hysteresis ΔV VOUT Soft-Start F rom EN = High to V Dynamic VID Slew Rate SGX G0/G1 Transition 1.75 -- 10 mV/μs

-- 4700 -- ppm/°C PHASE − GND −10

-- 5 mV

GND − PHASE = VCS/ 8 −20 0 20 mV

PHASE − GND = VCS/8 -- 3 -- mV

Falling edge, PWM disabled below

UVLO

this le v el

-- 100 -- mV

UVLO

= 95% -- 0.8 -- ms

OUT

3.5 3.7 3.9 V

UVP Blank Time From EN sig nal going h igh -- 3 - ms Therma l Shutdow n TSD -- 150 --

Therma l Shutdow n Hysteresis

-- 10 --

ΔT

°C

Driver On-Resistance

UGATE Driver Source

UGATE Driv er Sink LGATE Driver Source

LGATE Driver Sink

Dead Time Internal Boost Charging

Switch On-Resistance

UGATEsr

UGATEsk

LGATEsr

LGATEsk

VCC to BOOT, 10mA

BOOT−PHASE forced to 5V, UGATE High State BOOT−PHASE forced to 5V, UGATE Low State

LGATE, High State LGATE, Low State LGATE Rising (V

= 1.5V) --

PHASE

UGATE Rising

-- 1.8 3.6

-- 1.2 2.4 Ω

-- 1.8 3.6

-- 0.8 1.34 30

EN Threshold EN Threshold

Voltage

Logic-High Logic-Low

1.8 -- --

-- -- 0.5

Voltag e Programming (G0, G1) G0, G1 Input

Threshold Voltage

Logic-High 750 -- --

Logic-Low -- -- 300

Ω Ω

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RT8241D

Parameter Symbol Test Conditions Min Typ Max Unit

PGOOD (upper side threshold determined by OVP threshold)

Falling edge, measur ed at FB,

Trip Threshold

Trip Hysteresis -- 3 -Fault Propagation Del ay Output Low Vol t age

Leakage Current High S tate, forced to 5V -- -- 1

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by Design.

is measured in natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3

thermal measurement standard.

with respect to refere nce, no load.

Falling edge, FB forced below PGOOD trip threshold

= 1m A

SINK

−19 −15 −11 %

-- 2.5 --

μs

-- -- 0.4 V μA

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Typical Operating Characteristics

RT8241D

Efficiency vs. Output Current

100

95 90 85 80 75

Eff iciency (%)

70 65

= 8V, V

0.001 0.01 0.1 1 10

= V

= 5V, V

OUT

Output Current (A)

Efficiency vs . Output Current

100

95 90 85 80 75

Eff iciency (%)

70 65 60

0.001 0.01 0.1 1 10

= 12V, V

= V

Output Current (A)

= 5V, V

OUT

= 0.9V

Switching Frequency vs. Output Curre nt

350

= 8V, V

325 300 275 250 225 200 175 150 125 100

Swit ching Frequency (kHz) 1

50 25

0.001 0.01 0.1 1 10

= V

= 5V, V

OUT

= 0.9V

Output Current (A)

Switching Frequency vs. Output Current

350

= 12V, V

325 300 275 250 225 200 175 150 125 100

Swit ching Frequency (kHz) 1

50 25

0.001 0.01 0.1 1 10

= V

= 5V, V

Output Current (A)

OUT

= 0.9V

Effic iency vs. Output Current

100

95 90 85 80 75

Efficiency (%)

70 65

= 20V, V

0.001 0.01 0.1 1 10

Output Current (A)

= V

= 5V, V

OUT

= 0.9V

Switching Frequency vs . Output Current

350

= 20V, V

325 300 275 250 225 200 175 150 125 100

Swit ching Frequency (kHz) 1

50 25

0.001 0.01 0.1 1 10

= V

= 5V, V

Output Current (A)

OUT

= 0.9V

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RT8241D

730

720

710

700

690

Quiescent Current (µA) 1

680

670

OUT

(1V/Div)

PGOOD

(10V/Div)

Quiescent Current vs. Input Voltage

No Load, V

5 7 9 1113151719212325

Inp ut Volta ge (V)

= 5V

Power On from EN

VIN = 12V, VCC = VEN = 5V, V I

= 0.1A

LOAD

OUT

= 0.9V,

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

Shutdown Cur rent (µA) 1

0.2

0.1

0.0

OUT

(1V/Div)

PGOOD

(10V/Div)

Shutdown Current vs . Input Voltage

No Load, EN = GND

5 7 9 1113151719212325

Input Voltage (V)

Power Off from V

VIN = 12V, VCC = VEN = 5V, V

OUT

= 0.9V, I

LOAD

= 0.1A

(5V/Div)

PHASE

(10V/Div)

OUT

(50mV/Div)

(5V/Div)

UGATE

(20V/Div)

LGATE

(10V/Div)

0.9V

0.8V

Time (400μs/Div)

Dynamic VID Up

No Load, VIN = 12V, VCC = VEN = 5V, V

= 0.8V to 0.9V

OUT

Time (20μs/Div)

(5V/Div)

PHASE

(10V/Div)

OUT

(50mV/Div)

G1 (5V/Div) UGATE

(20V/Div)

LGATE

(10V/Div)

0.9V

0.8V

Time (1ms/Div)

Dynamic VIN Down

No Load, VIN = 12V, VCC = VEN = 5V, V

= 0.9V to 0.8V

OUT

Time (20μs/Div)

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RT8241D

OUT

(500mV/Div)

PGOOD (5V/Div)

LGATE

(5V/Div)

OUT_ac

(20mV/Div)

Over Voltage Protection

No Load, VIN = 12V, VCC = VEN = 5V, V

Time (100μs/Div)

Load Transient Response

VIN = 12V, VCC = VEN = 5V, V

= 0.9V, I

OUT

LOAD

= 0.9V

OUT

= 0A to 6A

OUT

(1V/Div)

PGOOD (5V/Div)

UGATE

(20V/Div)

LGATE

(5V/Div)

Under Voltage Protection

No Load, VIN = 12V, VCC = VEN = 5V, V

Time (100μs/Div)

OUT

= 0.9V

LOAD

(5A/Div)

UGATE

(20V/Div)

LGATE

(10V/Div)

Time (100μs/Div)

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RT8241D

Application Information

The RT8241D is of a constant on-time PWM controller which provides four DC feedback voltages by controlling the G0 and G1 digital input. The constant on-time PWM control scheme handles wide input/output ratios with ea se and provides 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The topology circumvents the poor load tra nsient timing problems of fixed-frequency current mode PWMs, while avoiding the problems caused by widely varying switching frequencies in conventional constant on-time and consta nt of f-ti me PWM schem es. The DRVTM mode PWM modulator is specifically designed to have better noise immunity for such a single output application.

PWM Operation

The Mach ResponseTM, DRVTM mode controller relies on the output filter capacitor's Effective Series Resistance (ESR) to act as a current sense resistor, so the output ripple voltage provides the PWM ra mp signal. Referring to the function diagra ms of the RT8241D, the synchronous high side MOSFET is turned on at the beginning of ea ch cycle. After the internal one-shot timer expires, the high side MOSFET is turned off. The pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the input voltage range. Another one-shot sets a minimum off-time (400ns typ.).

Diode-Emulation Mode

RT8241D automatically reduces switching frequency at light-load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly a nd without increasing V

ripple or load regulation. As the output

OUT

current decreas es from heavy load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low side MOSFET allows only partial negative current when the inductor freewheeling current becomes negative. As the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level that is required for the next “ON” cycle. The on-time is kept the same as that in the heavy-load condition. In reverse, when the output current increa ses from light load to heavy load, the switching frequency increases to the preset value a s the inductor current reaches the continuous condition. The transition load point to the light-load operation can be calculated a s f ollows (Figure 1) :

(V V )

−

LOAD ON

IN OUT

≈×

where tON is the on-time.

Slope = (VIN-V

OUT

) / L

L_Peak

On-Time Control (TON)

LOAD

= I

L_Peak

The on-time one-shot comparator has two inputs. One input monitors the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge

Figure 1. Boundary Condition of CCM/DCM

an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to V

, thereby making the on-time of the high

OUT

side switch directly proportional to the output voltage and inversely proportional to the input voltage. The implementation results in a nearly constant switching frequency without the need of a clock generator.

The switching waveforms may appear noisy and asynchronous when light loa ding causes diode-emulation operation, but this is a normal operating condition that results in high light-load efficiency . T rade-offs in DEM noise vs. light-load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance

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RT8241D

remains fixed) and less output voltage ripple. The disadvantages for using higher inductor values include larger physical size and degraded load-tra nsient response (especially at low input voltage levels).

Output V oltage Setting (FB)

As Figure 2 shows, the output voltage can be adjusted from 0.675V to 3.3V by setting the feedback resistors R

and R

FB1

and solve for R

VV(1 )

=×+

OUT FB

. Choose R

FB2

using the equation :

FB1

FB2

to be approximately 20k Ω,

FB2

where VFB is as shown in Table 2.

Table 2. Feedback Voltage Selection

G0 State G1 State Feedback Voltage

0 0 VFB = 0.9V 0 1 VFB = 0.8V 1 0 VFB = 0.725V 1 1 VFB = 0.675V

UGATE

BOOT

PHASE

LGATE

G0 G1 FB

G0 G1

OUT

FB1

FB2

OUT

MOSFET remains on until VFB reaches the new internal V

. Thus, the negative inductor current will be increa sed.

REF

If the negative current become large enough to trigger NOCP , the low side MOSFET will be turned of f to prevent large negative current from damaging the component. Refer to the Negative Over Current Li mit section for a full description.

GND

Initia l V Final V

Initia l V

Final V

REF

OUT

REF

UGATE

LGATE

OUT

Figure 3. Output V oltage Down T ransition

For an upward transition (from lower to higher V

OUT

) as shown in Figure 4, Gx cha nges from low to high and causes VFB to rise to a new internal V

. This quickly trips the

REF

VFB comparator regardless of whether DEM is active or not, generating an UGATE on-time and causing a subsequent LGATE to be turned on. At the end of the minimum off-time (400ns), if VFB is still below the new internal V

, another UGA TE on-time will be started. This

REF

sequence continues until the FB pin exceeds the new internal V

REF

Figure 2. Setting V

with a Resistor-Divider

OUT

Output Voltage Transition Operation

The digital input control pin Gx allows V

to transition

OUT

to both higher and lower values. For a downward tra nsition, the rapid cha nge of Gx from high to low will suddenly cause VFB to drop to a new internal V

. At this ti me the LGA TE

REF

will drive high to turn on the low side MOSFET and draw current from the output cap acitor via the inductor . LGA TE will remain on until VFB falls to the new internal V

REF

, at which point a normal UGA TE switching cycle begins, as shown in Figure 3. For a down transition, the low side

REF

UGATE

LGATE

OUT

Figure 4. Output V oltage Up T ra nsition

GND

Final V Initial V

REF

OUT

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RT8241D

If the V consecutive cycle of UGA TE on-time followed by minimum LGA TE time. This ca n cause a rapid increase in inductor current: typically it only takes a few switching cycles for inductor current to rise up to the current limit. At some

point the VFB will rise up to the new internal V UGATE pulses will cease, but the inductor's LI2 energy must then flow into the output capacitor. This can cre ate a significant overshoot, a s shown in Figure 5.

UGATE

LGATE

change is significant, there can be several

OUT

REF

GND

REF

Final V

Initia l V

and the

REF

V(mV) = R(k)10(A)

CS CS

Ω×

The Inductor current can be monitored by the voltage between GND and the PHASE pin. Hence, the PHASE pin should be connected to the drain terminal of the low side MOSFET. ICS has temperature coefficient to compensate the temperature dependency of the R GND is used as the positive current sensing node, so GND should be connected to the source terminal of the bottom MOSFET .

While the comparison is being done during the OFF state, VCS sets the valley level of the inductor current. Thus, the load current at over current threshold, I

LOAD_OC

calculated as f ollows :

LOAD_OC

8R 2

DS(ON)

V(VV)V

=+×

CS IN OUT OUT

8R 2Lf V

×××

DS(ON) SW IN

ripple

−×

In an over current condition, the current to the load exceeds

Final V

OUT

Initia l V

OUT OUT

Figure 5. Output V oltage Up Tr an sition with

Overshooting

This overshoot can be approximated by the following equation, where ICL is the current limit, V desired set point for the final voltage, L is in μH and C

FINAL

is the

OUT

is in μF.

V()V

MAX FINAL

OUT

the current to the output capa citor , thus causing the output voltage to fall. Eventually the voltage crosses the under voltage protection threshold and the device shuts down.

L_Peak

LOAD

LIM

Figure 6. “Valley” Current Limit

Current Limit Setting (OCP)

The RT8241D has a cycle-by-cycle current limiting control. The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense signal at the CS pin is above the current limit threshold, the PWM is not allowed to initiate a new cycle (Figure.

6). In order to provide both good accuracy and a cost effective solution, the RT8241D supports temperature compensated MOSFET R

sensing. The CS pin

DS(ON)

should be connected to GN D through the trip voltage setting resistor, RCS. The 10μA CS terminal source current , ICS, and the trip voltage setting resistor, RCS, set the CS trip voltage, VCS, as in the f ollowing equation.

Negative Over Current Limit (PWM Only Mode)

The RT8241D supports cycle-by-cycle negative over current limiting in CCM Mode only . The over current li mit is set to be negative but is the same absolute value as the positive over current limit. If output voltage continues to rise, the low side MOSEFT remains on. Thus, the inductor current is reduced and reverses direction after it reaches zero. When there is too much negative current in the inductor, the low side MOSFET is turned off and the current flows towards VIN through the body diode of the high side MOSFET. Because this protection limits the discharge current of the output capa citor , the output voltage

DS8241D-03 January 2014www.richtek.com

DS(ON)

, can be

RT8241D

tends to rise, eventually hitting the over voltage protection threshold and shutting down the device. If the device hits the negative over current threshold again before output voltage is discharged to the target level, the low side MOSFET is turned off a nd the process repeats. It ensures maximum allowable discharge capability when output voltage continues to rise. On the other hand, if the output is discharged to the target level before negative current threshold is reached, the low side MOSFET is turned off, the high side MOSFET is then turned on, and the device resumes normal operation.

MOSFET Gate Driver (UGATE, LGA TE)

The high side driver is designed to drive high current, low R

N-MOSFET(s). When configured as a floating

DS(ON)

driver, 5V bias voltage is delivered from the VCC supply. The average drive current is proportional to the gate charge at VGS = 5V times switching frequency . The insta ntaneous drive current is supplied by the flying cap acitor between the BOOT and PHASE pins. A dead time to prevent shoot through is internally generated between high side MOSFET off to low side MOSFET on, and low side MOSFET off to high side MOSFET on. The low side driver is designed to drive high current, low R

DS(ON)

NMOSFET(s). The internal pull-down tran sistor that drives LGA TE low is robust, with a 0.8Ω typical on resistance. A 5V bias voltage is delivered from the VCC supply. The instantaneous drive current is supplied by the flying cap acitor between VCC a nd GND.

For high current application s, some combinations of high and low side MOSFETs might be encountered that will cause excessive gate drain coupling, which can lead to efficiency killing, EMI-producing shoot through currents. This is often remedied by adding a resistor in series with BOOT, which increases the turn-on time of the high side MOSFET without degrading the turn-off time, a s shown in Figure 7.

UGATE

BOOT

PHASE

Figure 7. Reducing the UGA TE Rise T ime

Power Good Output (PGOOD)

The power good output is an open-drain output and requires a pull-up resistor. When the feedback voltage is above

1.1V or below 0.45V , PGOOD will be pulled low . PGOOD is allowed to be high until soft-start ends and the output reaches 89% of its set voltage. There is a 2.5μs delay built into PGOOD circuitry to prevent false tra n sition.

When Gx cha nges, PGOOD remains in its present state for 32 clock cycles. Mea nwhile, V

or VFB regulates to

OUT

the new level.

POR, UVLO and Soft-Start

Power On Reset (POR) occurs when VCC rises above

3.7V (typ.). After POR is triggered, the RT8241D will reset the fault latch and prepare the PWM for operation. Below

3.6V (typ.), the VCC Under Voltage Lockout (UVLO) circuitry inhibits switching by keeping UGA TE and LGA TE low. A built-in soft-start is used to prevent surge current from the power supply input after EN is en abled. It cla mps the ramping of the internal reference voltage which is compared with the FB signal. The typical soft-start duration is 0.8ms.

Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over voltage protection. When VFB exceeds 1.1V , over voltage protection is triggered and the low side MOSFET is latched on. This activates the low side MOSFET to discharge the output capacitor. The RT8241D is latched once OVP is triggered and ca n only be released by VCC or EN power on reset. There is a 5μs delay built into the over voltage protection circuit to prevent false transitions.

Under Voltage Protection (UVP)

The output voltage can be continuously monitored for under voltage protection. When VFB is less than 0.45V, under voltage protection is triggered and then both UGA TE a nd LGA TE gate drivers are forced low . In order to remove the residual charge on the output cap a citor during the under voltage period, if PHASE is greater than 1V, the LGATE is forced high until PHASE is lower than 1V. There is a

3.5μs delay built into the under voltage protection circuit to prevent false transitions. During soft-start, the UVP blanking time is 3ms.

DS8241D-03 January 2014 www.richtek.com

RT8241D

Output Inductor Selection

The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value a s follows :

LIR I

LOAD(MAX)

×−

t(VV)

ON IN OUT

where LIR is the ratio of peak-to-pea k ripple current to the maximum average inductor current. Select a low pass inductor having the lowest possible DC resistance that fits in the allowed dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (I

II I

=+×

PEAK LOAD(MAX) LOAD(MAX)

LIR

PEAK

) :

Output Capacitor Selection

The output filter ca pacitor must have ESR low enough to meet output ripple and loa d transient requirement, yet have high enough ESR to satisfy stability requirements. Also, the capa citance must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the OVP circuit. For CPU core voltage converters and other a pplications where the output is subject to violent load tran sient, the output capa citor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite ca pa citance :

ESR

≤

−

LOAD(MAX)

Do not put high value ceramic capacitors directly a cross the outputs without taking precautions to ensure sta bility . Large ceramic capacitors can have a high ESR zero

frequency and cause erratic and unstable operation. However, it is easy to add sufficient series resistance by placing the ca pacitors a couple of inche s downstream from the inductor and connecting FB divider close to the inductor. There are two related but distinct ways including double pulsing and feedback loop instability to identify the unstable operation. Double pulsing occurs due to noise on the output or because the ESR is too low such that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a

new cycle immediately after the 400ns minimum off-time period has expired. Double-pulsing is more a nnoying than harmful, resulting in nothing worse than increa sed output ripple. However , it may indicate the possible presence of loop instability , which is caused by insufficient ESR. Loop instability can result in oscillation at the output after line or load perturbations that can trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for stability checking is to apply a very zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It helps to si multaneously monitor the inductor current with an AC probe. Do not allow more than one ringing cycle after the initial step-response underor overshoot.

Thermal Considerations

In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain at an accepta ble level of output voltage ripple :

ESR

≤

LIR I

−

LOAD(MAX)

Organic semiconductor capacitor(s) or special polymer

For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and a mbient temperature. The maximum power dissipation can be calculated by the following formula :

cap acitor(s) are recommended.

Output Capacitor Stability

Stability is determined by the value of the ESR zero relative to the switching frequency . The point of instability is given

P where T

the ambient temperature, a nd θ thermal resistance.

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

is the maximum junction temperature, T

is the junction to ambient

by the following equation :

=≤

ESR

2ESRC 4

××

OUT

For recommended operating condition specifications of the RT8241D, the maximum junction temperature is 125°C

DS8241D-03 January 2014www.richtek.com

RT8241D

(W)

and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WQF N12L 2x2 pa ckages, the thermal resistance, θJA, is 165°C/ W on a standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula :

= (125°C − 25°C) / (165°C/W) = 0.606W for

D(MAX)

WQF N-12L 2x2 pa ckage The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. For the RT8241D package, the derating curve in Figure 8 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

ower

0.25

0.20

0.15

mum

0.10

0.05

0.00 0 25 50 75 100 125

Ambient Temperature ( °C)

Four-Layer PCB

Layout Considerations

Layout is very important in high frequency switching converter design. If designed improperly , the PCB could radiate excessive noise and contribute to converter instability. For best performance of the RT8241D, the following guidelines should be strictly followed.

` Connect an RC low-pa ss filter from VCC, (1μF a nd 10Ω

are recommended). Place the filter capacitor close to the IC.

` Keep current limit setting network a s close as possible

to the IC. Routing of the network should be kept away from high voltage switching nodes to prevent it from coupling.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as short as possible to reduce stray inductance.

` All sensitive analog traces and components pertaining

to V

, FB, GND, EN, PGOOD, CS and VCC should

OUT

be placed away from high voltage switching nodes such as PHASE, LGA TE, UGA TE, or BOOT nodes to prevent it from coupling. Use internal layer(s) as ground pla ne(s) and shield the feedback trace from power traces and components.

` Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device.

Figure 8. Derating Curves for the RT8241D Package

` Power sections should connect directly to ground

plane(s) using multiple vias as required for current handling (including the chip power ground connection s). Power components should be placed to minimize loops and reduce losses.

DS8241D-03 January 2014 www.richtek.com

RT8241D

Outline Dimension

1 2

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010 D 1.900 2.100 0.075 0.083 E 1.900 2.100 0.075 0.083

e 0.400 0.016

D2 0.850 0.950 0.033 0.037

1 2

E2 0.850 0.950 0.033 0.037

L 0.250 0.350

W-Type 12L QFN 2x2 Package

0.010 0.014

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8241D-03 January 2014www.richtek.com

richtek RT8241D Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual