Richtek RT8856GQW Schematic

®

RT8856

Multi-Phase PWM Controller for CPU Core Power Supply

General Description

The RT8856 is a single/dual pha se PWM controller with two integrated MOSFET drivers. Moreover, it is compli ant with Intel IMVP6.5 V oltage Regulator Specification to fulfill its mobile CPU Vcore power supply requirements. The

TM

RT8856 adopts NAVP proprietary topology derived from finite DC gain compensator peak current mode, ma king it an ea sy setting PWM controller that meets all Intel AVP (Active Voltage Positioning) mobile CPU requirements.

The output voltage of the RT8856 is set by 7-bit VID code. The built-in high accuracy DAC converts the VID code ranging from 0V to 1.5V with 12.5mV per step. The system accuracy of the controller can reach 1.5%. The part supports VID on-the-fly and mode change on-the-fly functions that are fully compliant with IMVP6.5 specification. It operates in single pha se, dual pha se and RFM. It can rea ch up to 90% efficiency in different modes according to different loa ding conditions. The droop load line can be easily programmed by setting the DC gain of the error amplifier. With proper compensation, the load transient can achieve optimized AVP performance. This chip controls soft-start and output tra nsition slew rate vi a a capacitor. It supports both DCR and sense resistor current sensing. The current mode NA VPTM topology with high accura cy current sensing a mplifier well balances the RT8856's channel currents.

The RT8856 provides power good, clock enabling and thermal throttling output signals for IMVP6.5 specification. It also features complete fault protection functions including over voltage, under voltage, negative voltage, over current, thermal shutdown, and under voltage lockout.

The RT8856 is available in a WQFN-40L 6x6 small foot print package.

(Native AVP) which is Richtek's

Features



1/2 Phase PWM Controller with 2 Integrated





MOSFET Drivers



 IMVP6.5 Compatible Power Management States



(DPSRLVR, PSI, Extended Deeper Sleep Mode)



 NAVP (Native AVP) Topology



 7-bit DAC



 0.8% DAC Accuracy



 Fixed V



 Differential Remote Voltage Sensing



 Programma ble Output Tra nsition Slew Rate Control



 Accurate Current and Thermal Balance



 System Thermal Compensation AVP



 Ringing Free Mode at Light Load Conditions



 Fast T ran sient Respon se



 Power Good



 Clock Enable Output



 Thermal Throttling



 Current Monitor Output



 Switching Frequency up to 1MHz Per Phase



 OVP, UVP, NVP, OCP, OTP, UVLO



 40-Lead WQFN Package



 RoHS Compliant and Halogen Free



BOOT

(1.1V)

Ordering Information

RT8856

Package Type QW : WQFN-40L 6X6 (W-Type) (Exposed Pad-Option 1)

Lead Plating System G : Green (Halogen Free and Pb Free)

Note :

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

Applications

 IMVP6.5 Core Supply  Multi-phase CPU Core Supply  A VP Step-Down Converter  Notebook/ Des ktop Computer/ Servers

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1

RT8856

Marking Information

RT8856GQW : Product Number

RT8856

YMDNN : Date Code

GQW YMDNN

Typical Application Circuit

V

C

3

V

I

0

D

V

I

D

1

V

I

D

2

V

I

D

.

V

3

R

7

V

p

c

R

1

P

W

R

G

D

L

C

K

E

N

T

V

R

T

C

M

C

1

2

C

U

P

S

V

E

N

S

E

S

R

2

0

R

V

U

O

T

C

U

P

S

V

E

N

S

E

C

2

R

8

D

1

R

5

C

1

4

1

R

2

T

N

C

2

4

3

V

I

D

4

V

I

D

5

V

I

D

6

P

S

I

R

P

L

S

V

P

R

V

R

O

N

1

R

8

C

R

2

3

1

C

1

8

Pin Configurations

(TOP VIEW)

2

C

P

V

T

2

E

N

S

E

C

S

O

I

41

SOFT

RGND

L

R

6

1

V

L

R

1

4

V

U

C

1

2

S

N

_

2 N E S

I

ISEN1

C

S

2 T

O O B

31323334353637383940

30

UGATE2

29

PHASE2

28

PGND2

27

LGATE2

26

PVCC

25

LGATE1

24

PGND1 PHASE1

23 22

UGATE1

21

BOOT1

20191817161514131211

ISEN1_N

6

C

7

V

O

U

1

0

C

1

6

E

N

S

E

T

1

C

1

D

N

DPRSLPVR

VRON

FS

CM

M

C

S

VID6 VID5 VID4 VID3 VID2

O

E

O

K

G

L

P

C

1 2 3 4 5

T

E

6 7 8 9

10

VID1

VID0

C C V

I S P

T

N

T R

O T

V

GND

FB

COMP

C T N

VSEN

WQFN-40L 6x6

V

I

5

R

1

8

T

R

5

3

8

V

C

1

2

V

D

I

1

V

D

I

1

0

D

V

I

9

D

V

I

8

D

V

I

7

D

V

I

6

D

V

I

1

3

P

I

S

1

P

D

R

2

V

R

O

4

0

P

G

O

3

9

L

C

K

3

6

V

R

T

4

M

C

5

S

M

C

1

6

E

S

V

1

5

B

F

1

5

1

4

O

C

M

3

F

S

2

R

5

6

0 1

U

2

P

3 4 5 6

L

S

I

S

L

P

V

R

U

N

P

D

O

E

N

L

T

E

N

I

S

P

G

D

N

4

1

(

E

2

6

P

V

C

2

B

G H G

P

E

B

G H

G

P

E

O

x

1

O

T

O

1

2

T

A

1

E

2

3

A

S

E

1

2

5

T

A

E

1

2

4

N

G

1

D

1

9

I

E

S

1

N

2

0

N

1

_

N

3

1

O

T

2

O

3

0

T

A

E

2

9

A

S

E

2

7

A

T

2

E

2

8

N

G

2

D

3

7

T

N

O

3

I

E

S

2

N

3

2

N

_

N

1

8

O

S

F

T

1

7

G

N

R

D

3

5

N

T

C

3

4

C

S

T

E

p

o

s

e

d

p

a

d

)

V

C

1

R

2

C

R

3

R

4

C

R

9

1

R

0

R

1

2

R

1

6

C

1

7

R

2

6

R

2

9

N

7

V

o

t

2

4

V

C

4

1

Q

2

9

3

Q

4

1

R

7

1

3

R

2

7

2

5

R

C

R

C

V

N

I

R

1

9

R

2

N

T

1

D

5

V

I

N

7

V

o

t

C

8

1

3

2

D

9

8

2

C

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DS8856-04 August 2014www.richtek.com

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Table 1. IMVP6.5 VID code table

RT8856

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output

0 0 0 0 0 0 0 1.5000V 0 0 0 0 0 0 1 1.4875V 0 0 0 0 0 1 0 1.4750V 0 0 0 0 0 1 1 1.4625V 0 0 0 0 1 0 0 1.4500V 0 0 0 0 1 0 1 1.4375V 0 0 0 0 1 1 0 1.4250V 0 0 0 0 1 1 1 1.4125V 0 0 0 1 0 0 0 1.4000V 0 0 0 1 0 0 1 1.3875V 0 0 0 1 0 1 0 1.3750V 0 0 0 1 0 1 1 1.3625V 0 0 0 1 1 0 0 1.3500V 0 0 0 1 1 0 1 1.3375V 0 0 0 1 1 1 0 1.3250V

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output

0 1 0 0 0 0 1 1.0875V 0 1 0 0 0 1 0 1.0750V 0 1 0 0 0 1 1 1.0625V 0 1 0 0 1 0 0 1.0500V 0 1 0 0 1 0 1 1.0375V 0 1 0 0 1 1 0 1.0250V 0 1 0 0 1 1 1 1.0125V 0 1 0 1 0 0 0 1.0000V 0 1 0 1 0 0 1 0.9875V 0 1 0 1 0 1 0 0.9750V 0 1 0 1 0 1 1 0.9625V 0 1 0 1 1 0 0 0.9500V 0 1 0 1 1 0 1 0.9375V 0 1 0 1 1 1 0 0.9250V

0 1 0 1 1 1 1 0.9125V 0 0 0 1 1 1 1 1.3125V 0 0 1 0 0 0 0 1.3000V

0 0 1 0 0 0 1 1.2875V 0 0 1 0 0 1 0 1.2750V 0 0 1 0 0 1 1 1.2625V 0 0 1 0 1 0 0 1.2500V 0 0 1 0 1 0 1 1.2375V 0 0 1 0 1 1 0 1.2250V 0 0 1 0 1 1 1 1.2125V 0 0 1 1 0 0 0 1.2000V 0 0 1 1 0 0 1 1.1875V 0 0 1 1 0 1 0 1.1750V 0 0 1 1 0 1 1 1.1625V 0 0 1 1 1 0 0 1.1500V 0 0 1 1 1 0 1 1.1375V 0 0 1 1 1 1 0 1.1250V

0 1 1 0 0 0 0 0.9000V

0 1 1 0 0 0 1 0.8875V

0 1 1 0 0 1 0 0.8750V

0 1 1 0 0 1 1 0.8625V

0 1 1 0 1 0 0 0.8500V

0 1 1 0 1 0 1 0.8375V

0 1 1 0 1 1 0 0.8250V

0 1 1 0 1 1 1 0.8125V

0 1 1 1 0 0 0 0.8000V

0 1 1 1 0 0 1 0.7875V

0 1 1 1 0 1 0 0.7750V

0 1 1 1 0 1 1 0.7625V

0 1 1 1 1 0 0 0.7500V

0 1 1 1 1 0 1 0.7375V

0 1 1 1 1 1 0 0.7250V

0 1 1 1 1 1 1 0.7125V 0 0 1 1 1 1 1 1.1125V 0 1 0 0 0 0 0 1.1000V

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1 0 0 0 0 0 0 0.7000V

1 0 0 0 0 0 1 0.6875V

3

RT8856

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output

1 0 0 0 0 1 0 0.6750V 1 0 0 0 0 1 1 0.6625V 1 0 0 0 1 0 0 0.6500V 1 0 0 0 1 0 1 0.6375V 1 0 0 0 1 1 0 0.6250V 1 0 0 0 1 1 1 0.6125V 1 0 0 1 0 0 0 0.6000V 1 0 0 1 0 0 1 0.5875V 1 0 0 1 0 1 0 0.5750V 1 0 0 1 0 1 1 0.5625V 1 0 0 1 1 0 0 0.5500V 1 0 0 1 1 0 1 0.5375V 1 0 0 1 1 1 0 0.5250V 1 0 0 1 1 1 1 0.5125V 1 0 1 0 0 0 0 0.5000V

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output

1 1 0 0 0 0 1 0.2875V 1 1 0 0 0 1 0 0.2750V 1 1 0 0 0 1 1 0.2625V 1 1 0 0 1 0 0 0.2500V 1 1 0 0 1 0 1 0.2375V 1 1 0 0 1 1 0 0.2250V 1 1 0 0 1 1 1 0.2125V 1 1 0 1 0 0 0 0.2000V 1 1 0 1 0 0 1 0.1875V 1 1 0 1 0 1 0 0.1750V 1 1 0 1 0 1 1 0.1625V 1 1 0 1 1 0 0 0.1500V 1 1 0 1 1 0 1 0.1375V 1 1 0 1 1 1 0 0.1250V

1 1 0 1 1 1 1 0.1125V 1 0 1 0 0 0 1 0.4875V 1 0 1 0 0 1 0 0.4750V 1 0 1 0 0 1 1 0.4625V 1 0 1 0 1 0 0 0.4500V 1 0 1 0 1 0 1 0.4375V 1 0 1 0 1 1 0 0.4250V 1 0 1 0 1 1 1 0.4125V 1 0 1 1 0 0 0 0.4000V 1 0 1 1 0 0 1 0.3875V 1 0 1 1 0 1 0 0.3750V 1 0 1 1 0 1 1 0.3625V 1 0 1 1 1 0 0 0.3500V 1 0 1 1 1 0 1 0.3375V 1 0 1 1 1 1 0 0.3250V 1 0 1 1 1 1 1 0.3125V 1 1 0 0 0 0 0 0.3000V

1 1 1 0 0 0 0 0.1000V

1 1 1 0 0 0 1 0.0875V

1 1 1 0 0 1 0 0.0750V

1 1 1 0 0 1 1 0.0625V

1 1 1 0 1 0 0 0.0500V

1 1 1 0 1 0 1 0.0375V

1 1 1 0 1 1 0 0.0250V

1 1 1 0 1 1 1 0.0125V

1 1 1 1 0 0 0 0.0000V

1 1 1 1 0 0 1 0.0000V

1 1 1 1 0 1 0 0.0000V

1 1 1 1 0 1 1 0.0000V

1 1 1 1 1 0 0 0.0000V

1 1 1 1 1 0 1 0.0000V

1 1 1 1 1 1 0 0.0000V

1 1 1 1 1 1 1 0.0000V

4

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DS8856-04 August 2014www.richtek.com

Functional Pin Description

Pin No. Pin Name Pin Function

1 DPRSLPVR 2 VRON Voltage Regulator Enabler. 3 FS

4 CM

5 CMSET

6 to 12 VID[6:0]

13 14 COMP Compensation. This pin is the output node of the error amplifier.

15 FB Feedback. This is the negative input node of the error amplifier. 16 VSEN

17 RGND

18 SOFT

19 ISEN1 Positive Input of Phase1 Current Sense. 20 ISEN1_N Negative Input of Phase1 Current Sense.

21 BOOT1

22 UGATE1 Upper Gate Drive of Phase1. This pin drives the gate of the high side MOSFETs. 23 PHASE1 24 PGND1 Dr ive r Ground of Phase1.

25 LGATE1 Lower Gate Drive of Phase1. This pin drives the gate of the low side MOSFETs. 26 PVCC Driver Power. 27 LGATE2 Lower Gate Drive of Phase2. This pin drives the gate of the low side MOSFETs. 28 PGND2 Dr ive r Ground of Phase2.

29 PHASE2

PSI

Deep er Sle ep Mod e S ig nal . Togeth er wit h PSI, the com b ination o f the se t wo pin s indicates the power management states.

Fre quen c y Se t ting . C on nec t t h is p in w ith a res is tor t o g r oun d to set the oper ati ng frequency.

Current Monitor Output. This pin outputs a voltage proportional to the output current.

Curr e nt Mo nit or Ou tpu t Ga in Ex t ern all y S et ting . Conn ec t this pin wit h o ne res is tor to VSE N while C M pin is connec ted to grou nd wit h a not her resis tor. Th e curre nt mo nitor ou tput gain can be set by the ratio of these two resist ors.

Voltage ID. DAC voltage identification inputs for IMVP6.5. The logic threshold is 30% of VCCP as the maximum value for low state and 70% of VCCP as the minimum value for the high state. VCCP is 1.05V. Power Status Indicator II. Together with DPRSLPVR, the combination of these two pins indicates the power management states.

Positive Voltage Sensing Pin. This pin is the positive node of the differential v oltage sensing. Return Gro und. This pin is the n egative node of the differential remote voltage sensing. Soft-Start. This pin provides soft-start function and slew rate control. The capac it an ce of t he s le w rat e c on trol ca paci t or is restrict ed to be lar g er than 10n F. The feedback voltage of the converter follows the ramping voltage on the SOFT pin during soft-start and other voltage transitions according to different modes of operation and VID change.

Boo tstra p Power Pin of Phase1 . T his p in powe rs the high s ide MOSFE T drivers . Conn ec t this pin t o t he j unc tio n of the boo t st rap c ap ac itor wi th t he c ath ode of the bootstrap diode. Connect the anode of the bootstrap diode to the PVCC pin.

Retu r n Node o f P ha se 1 H ig h Sid e D ri ver . C onn ect thi s pin to h i gh si de MO SFE T sources together with the low side MOSFET drains and the inductor.

Retu r n Node o f P ha se 2 H ig h Sid e D ri ver . C onn ect thi s pin to h i gh si de MO SFE T sources together with the low side MOSFET drains and the inductor.

RT8856

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RT8856

Pin No. Pin Name Pin Function

30 UGATE2

31 BOOT2

32 ISEN2_N Negative Input of Phase2 Current Sense. 33 ISEN2 Positive input of Phase2 Curr ent Sense.

34 OCSET

35 NTC

36

37 TON 38 VCC Chip Power. 39 40 PGOOD Power Good Indicator.

41 (Exposed Pad) GND

VRTT

CLKEN

Upper Gate Drive of Phase2. This pin drives the gate of the high side

MOSFETs. Bootstrap Power Pin of Phase2. This pin powers the high side MOSFET drivers. Connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. Connect the anode of the bootstrap diode to the PVCC pin.

Over Current Protection Setting. Connect a resistive voltage divider from VCC to ground and connect the joint of the voltage divider to the OCSET pin. The voltage, V Thermal Detection Input for VRTT Circuit. Connect this pin with a resistive voltage divider from VCC using NTC on the top to set the thermal management thre s h old le ve l. Voltage Regul ator Thermal Throttling. This open-dr ain output pin indi cates the tem per ature exceeding the preset level when it is pulled low. Connect this pin to VIN with one resistor. This resistor value sets the ripple size in ringing free mode.

In verted Clock Enable. This open-drain pi n is an output indic ating the start of the PLL locking of the clock chip.

Ground. The exposed pad m ust be soldered to a larg e PCB and connected to GND for maximum power dissipation.

, determines the over current threshold, I

OCSE T

LIM

.

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DS8856-04 August 2014www.richtek.com

Function Block Diagram

RT8856

FS

TON

OCSET

I S P

DPRSLPVR

VRON

FB

Ringing

OCP

Mode

Power On Reset

OSC

Free

Setting

Selection

&

Mode

Central Logic

BOOT1

PHASE1

UGATE1

-

+

LGATE1

PVCC

PGND1

Driver

+

Logic

-

UGATE2

BOOT2

Control

+

OTP

-

PHASE2

PWMCP

LGATE2

PWMCP

-

+

ISEN1

ISEN2_N

-

+

20

1/2

+

ONE_PHASE

ISEN1_N

PGND2

ISEN2

-

20

CM

CMSET

CM

+

Offset Cancellation

PGOOD VCC

N E K

L C

T T R V

NTC

-

+

Point

OVP Trip

MUX

VID0

VID1

+

AMP

ERROR

-

UVP Trip

VID2

Point

DAC

VID3

VID4

VID5

VID6

SOFT

RGND

+

START

FB

SOFT

VSEN

COMP

-

+

Point

NVP Trip

-

+

1.2V

VCC

GND

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RT8856

Absolute Maximum Ratings (Note 1)

 VCC to GND ------------------------------------------------------------------------------------------------ −0.3V to 6.5V  RGND, PGNDx to GND ---------------------------------------------------------------------------------- −0.3V to 0.3V  VIDx to GND------------------------------------------------------------------------------------------------ −0.3V to (V  PSI, VRON to GN D --------------------------------------------------------------------------------------- −0.3V to (V  PGOOD, CLKEN, VRTT to GND----------------------------------------------------------------------- −0.3V to (V  VSEN, FB, COMP, SOFT , FS, OCSET, CM, CMSET, NTC to GND--------------------------- −0.3V to (V  ISENx, ISEN1_N, ISEN2_N to GND ----------------------------------------------------------------- −0.3V to (V  PVCC to PGNDx ------------------------------------------------------------------------------------------ −0.3V to 6.5V  LGA TEx to PGNDx --------------------------------------------------------------------------------------- −0.3V to (PVCC + 0.3V)  PHASEx to PGNDx -------------------------------------------------------------------------------------- −3V to 28V  BOOTx to PHASEx--------------------------------------------------------------------------------------- −0.3V to 6.5V  UGATEx to PHASEx ------------------------------------------------------------------------------------- −0.3V to (BOOTx − PHASEx)  PGOOD------------------------------------------------------------------------------------------------------ −0.3V to (V  Power Dissipation, P

@ T

D

= 25°C

A

WQFN−40L 6x6-------------------------------------------------------------------------------------------- 2.941W

 Package Thermal Re sistance (Note 2)

WQF N-40L 6x6, θJA--------------------------------------------------------------------------------------- 34°C/W WQFN-40L 6x6, θJC-------------------------------------------------------------------------------------- 6°C/W

 Junction T emperature------------------------------------------------------------------------------------- 150°C  Lead T e mperature (Soldering, 10 sec.)--------------------------------------------------------------- 26 0°C  Storage T emperature Range ---------------------------------------------------------------------------- −65°C to 150°C  ESD Susceptibility (Note 3)

HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV MM (Ma chine Mode)-------------------------------------------------------------------------------------- 200V

+ 0.3V)

CC

+ 0.3V)

CC

+ 0.3V)

CC

+ 0.3V)

CC

+ 0.3V)

CC

+ 0.3V)

CC

Recommended Operating Conditions (Note 4)

 Supply Voltage, V  Battery Voltage, V  Junction T emperature Range---------------------------------------------------------------------------- −40°C to 125°C  Ambient T emperature Range----------------------------------------------------------------------------

-------------------------------------------------------------------------------------- 4.5V to 5.5V

CC

-------------------------------------------------------------------------------------- 7V to 24V

IN

−40°C to 85°C

Electrical Characteristics

(V

= 5V, TA = 25°C, unless otherwise specified)

CC

Parameter Symbol Test Conditions Min Typ Max Unit

Supply Input

R

= 33k, V

Supply Current I Shutdown Curr ent I

VCC

CC

+ I

PVCC

FS

Not Switching

V

VRON

= 0V -- -- 5 A

Soft-Start/Slew Rate Control (based on 10nF CSS)

Soft-Start / Soft-Shutdown I Deeper Sleep Exit/VID

Change Slew Current

V

SS1

I

V

SS2

SOFT

= 1.5V 16 20 24 A = 1.5V 80 100 120 A

8

©

VRON

= 3.3V,

-- -- 10 mA

DS8856-04 August 2014www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

Oscillator

RT8856

Frequency

Frequency f Variation R

R

OSC

= 33k, V

FS

= 5k to 50k  20 -- 20 %

FS

> 1 .05 270 300 330 kH z

DAC

Frequency Range Per phase 200 -- 1000 kHz Maximum Duty Cycle Per phase -- 50 -- % FS pin Output Voltage VFS R

= 33k, V

FS

> 1 . 05 1 1.05 1.1 V

DAC

Reference and DAC

V

= 0.7500  1.5000

DC Accuracy VFB

Boot Voltage V

BOOT

DAC

(No Load, Active Mode )

= 0.5000 0.7500 7.5 0 7.5 mV

V

DAC

1.089 1.1 1.111 V

0.8 0 0.8 %VID

Error Amplifier

DC Gain RL = 47k 70 80 -- dB Gain-Bandwidth Product GBW C

Slew Rate SR Output Volta ge Ra nge V

MAX Source/Sink Current I

RL = 47k 0.5 -- 3.6 V

COMP

V

OUTEA

= 5pF -- 10 -- MHz

LOAD

C R

= 10pF (Gain = 4,

LOAD

= 47k, V

F

= 2V -- 250 -- A

COMP

= 0.5V 3V)

OUT

-- 5 -- V/s

Current Sense Amplifier

Input Offset Voltage V Impedance at Neg. Input R Impedance at Pos. Input R

1 -- 1 mV

OSCS ISENx_N ISENx

1 -- -- M

1 -- -- M DC Gain AI -- 10 -- V/V Input Range V

ISENx_IN

50 -- 100 mV

RFM TON Setting

TON Pin Output Voltage V DEM ON- Tim e Se ttin g tON I R

Current Range I

TON

R

TON

25 -- 280 A

RTON

= 80k, V

TON

= 80A -- 350 -- ns

RTON

TON

= V

= 0 . 75V 5 0 5 %

DAC

Protection

Under Voltage Lo c kout Threshold Under Voltage Lo c kout Threshold Hysteresis Absolute Over Vol tage Protection Threshold Rel ati ve Ov er Vo lta ge Protection Threshold

Under Voltag e Pr otection Threshold

Negative Voltage Protection Threshold

Falling edge 4.1 4.3 4.5 V

V

UVLO

V

V

-- 200 -- mV

UVLO

(With respect to 1.5V, ±50mV) 1.45 1.5 1.55 V

OVABS

(With respect to V

OV

, ±50mV) 150 200 250 mV

VID

Measured at VSEN with respect to

V

UV

un loaded output vo ltage (UOV)

350 300 250 mV

(for 0.8 < UOV < 1.5)

V

NV

Measured at VSEN with respect to GND

100 -- -- mV

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9

RT8856

Parameter Symbol Test Conditions Min Typ Max Unit

Current Limit Threshold Voltage (Average)

Current Limit Threshold Voltage (per phase)

V

ILIM

V

ILIM_PH

 (V V

OCSET

V

ILIMT(nom)

V

ILIMITPH

T herm al S hutd own Th resh old TSD -- 160 -- °C T herm al S hutd own Hys ter es is TSD -- 10 -- °C

Logic Inputs

VRON Input Threshold Voltage

Logic-High VIH With respect to 3.3V, 70% 2 .31 -- -Logic-Low V

W ith respec t to 3.3V, 30% -- -- 0 .99

IL

Leakage Current of VRON 1 -- 1 A DAC (VID0  VID6),

PSI and DPR SLPV R Input Threshold Voltage Leakage Current of DAC (VID0  VID6 ), PSI and DP RSLPVR

Logic-High VIH With respect to 1.1V, 70% 0 .77 -- -Logic-Low V

W ith respec t to 1.1V, 30% -- -- 0 .33

IL

1 -- 1 A

Power Good

PGOOD Threshold V PGOOD Low Voltage V PGOOD Dela y t

TH_PGOOD

PGOOD

-- 1 -- V

I

PGOOD

CLKEN Low to PGOOD High

Clock E nable

CLKEN Low Voltage V

CLKEN

I

CLKEN

Thermal Throttling

Thermal Throttling Threshold VOT

Thermal Throttling Threshold Hysteresis

VRTT Output Voltage

V

OT_HY

V

VRTT

I

Measure at NTC with respect to V

At V

VRTT

Current Monitor

Current Moni tor Maximum Output Voltage in Operating Range

Current Moni tor Maximum Output Voltage

-- -- 1.15 V

V R

DAC

CM

Gate Driver

V

UGA TE Driver Source R UGA TE Driver Sink R L G ATE D r iv er So u r ce R L G ATE D r iv er Si n k R UGATE Driver Source/Sink Current I LGATE Driver Source Current I

UGATEsr

UGATEsk

LGATEsr

LGATEsk

UGATE

LGATEsr

V

BOOTx

V

BOOTx

V

UGATE

V

PVCC

V

PVCC

V

LGATE

V

BOOT

V

UGATE LGATE

V

ISEN x

= 0.625V,

ISENx_N

) / N,

23 25 27 mV

= 25mV

/ V

-- 150 -- %

ILIMIT

V

= 4mA -- -- 0.4 V

3 -- 20 ms

= 4mA -- -- 0.4 V

CC

= 5V -- 100 -- mV

CC

-- 80 -- %V

= 40mA -- -- 0.4 V

= 1V, V

RCMSET

= 50k, R

 V

PHASEx

V

UGATEx

CMSET

= 5V

= 1V

= 90mV,

= 10k

0.855 0.9 0.945 V

-- 0.7 -- 

= 1V -- 0.6 -- 

= 5V ,

 V

LGATE

= 1V

-- 0.7 -- 

= 1V -- 0.3 -- 

 V

= 2.5V

PHASE

= 5V

-- 3 -- A

= 2.5V -- 3 -- A

DD

10

©

DS8856-04 August 2014www.richtek.com

RT8856

Parameter Symbol Test Conditions Min Typ Max Unit

LGATE Driver Sink Current I Internal Boost Charging Switch

On-Resistance

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.

is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of

JA

JEDEC 51-7 thermal measurement standard. The measured case position of θ package.

LGATEsk

R

V

PVCC to BOOTx -- 30 -- 

BOOT

= 2 .5V -- 5 -- A

LGATE

is on the exposed pad of the

JC

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11

RT8856

Typical Operating Characteristics

CCM Efficiency vs. Load Current

100

90 80 70 60 50 40

Efficiency (%)

30 20 10

0

0 1020304050

VIN = 8V

V

= 12V

IN

= 19V

V

IN

VID = 1.15V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High

Load Current (A)

DEM Efficiency vs. Load Current

95 90 85 80 75 70 65

Efficiency (% )

60 55 50

00.511.522.53

VIN = 8V

= 12V

V

IN

V

= 19V

IN

VID = 0.85V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High

Load Curren t (A)

CCM Efficiency vs. Loa d Current

100

90 80 70 60 50 40

Efficiency (% )

30 20 10

0

0 1020304050

VIN = 8V

V

= 12V

IN

VIN = 19V

VID = 0.9375V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High

Load Current (A)

CCM VCC_SENSE vs. Load Current

1.16

1.14

1.12

1.1

1.08

VCC_SENSE (V)

1.06

1.04

VIN = 8V

V

= 12V

IN

= 19V

V

IN

VID = 1.15V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High

0 1020304050

Load Current (A)

CCM VCC_SENSE vs. L oad Current

0.96

0.94

0.92

VIN = 8V

= 12V

V

0.90

0.88

IN

V

IN

= 19V

VCC_SENSE (V)

0.86

0.84 0 1020304050

VID = 0.9375V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High

Load Current (A)

©

1.1

1.0

0.9

0.8

0.7

0.6

(mV)

0.5

CM

V

0.4

0.3

0.2

0.1

0.0 0 1020304050

VCM vs. Load Current

VIN = 8V

V

= 12V

IN

= 19V

V

IN

VID = 0.9375V, RFS = 33 kΩ, DPRSLPVR = GND, PSI = High

Load Current (A)

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12

RT8856

V

SENSE

CC

(500mV/Div)

PGOOD

(1V/Div)

VRON

(5V/Div)

UGATE

(20V/Div)

V

SENSE

CC

(100mV/Div)

Power On from VRON

VIN = 12V, VID = 0.9375V

DPRSLPVR = GND, PSI = High, No Load

Time (1ms/Div)

CCM VID Change Up

VIN = 12V, VID change from 0.85V to 0.9375V

V

SENSE

CC

(500mV/Div)

PGOOD (1V/Div)

VRON

(5V/Div)

UGATE

(2V/Div)

V

SENSE

CC

(100mV/Div)

Power Off from VRON

VIN = 12V, VID = 0.9375V

DPRSLPVR = GND, PSI = High, No Load

Time (1ms/Div)

CCM VID Change Down

VIN = 12V, VID change from 0.9375V to 0.85V

UGATE1

(20V/Div)

LGATE1

(1V/Div)

VID0

(2V/Div)

V

SENSE

CC

(100mV/Div)

UGATE1

(20V/Div)

LGATE1

(5V/Div)

VID0

(2V/Div)

DPRSLPVR = GND, PSI = High, No Load

Time (20μs/Div)

RFM VID Change Down

VIN = 12V, VID change 0.9375V to 0.85V,

DPRSLPVR = High, No Load

UGATE1

(20V/Div)

LGATE1

(5V/Div)

VID0

(2V/Div)

V

SENSE

CC

(50mV/Div)

UGATE1

(20V/Div)

LGATE1 (5V/Div)

DPRSLPVR = GND, PSI = High, No Load

Time (20μs/Div)

CCM Load Transient Response

VIN = 12V, VID = 0.95V, I DPRSLPVR = GND, PSI = High

LOAD =

12A to 51A,

Time (40μs/Div)

©

Time (4μs/Div)

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13

RT8856

V

SENSE

CC

(50mV/Div)

UGATE1

(20V/Div)

LGATE1 (5V/Div)

V

SENSE

CC

(1V/Div)

CCM Load Transient Response

VIN = 12V, VID = 0.95V, I

DPRSLPVR = GND, PSI = High

Time (4μs/Div)

LOAD =

51A to 12A,

Over Voltage Protection

V

SENSE

CC

(500mV/Div)

PGOOD (1V/Div)

I

LOAD

(50A/Div)

LGATE1

(10V/Div)

V

SENSE

CC

(1V/Div)

Over Current Protection

VIN = 12V , VID = 0.9375V, DPRSLPVR = GND

Time (10μs/Div)

Under Voltage Protection

PGOOD

(2V/Div)

UGATE1

(20V/Div)

LGATE1

(5V/Div)

VIN = 12V , VID = 0.9375V, DPRSLPVR = GND

Time (10μs/Div)

PGOOD (2V/Div)

UGATE1

(20V/Div)

LGATE1 (5V/Div)

VIN = 12V , VID = 0.9375V, DPRSLPVR = GND

Time (10μs/Div)

©

DS8856-04 August 2014www.richtek.com

14

Application Information

RT8856

The RT8856 is a 1/2-pha se DC/DC controller a nd includes embedded gate drivers for reduced system cost and board area. The number of phases is not only user selectable, but also dynamically changeable based on Intel's IMVP6.5 control signals to optimize efficiency. Phase currents are continuously sensed for loop control, droop tuning, and over current protection. The internal 7-bit VID DAC and a low offset differential amplifier allow the controller to maintain high voltage regulating accuracy to meet Intel's IMVP6.5 specification.

Design Tool

To reduce the efforts and errors caused by manual calculations, a user friendly design tool is now available on request.

This design tool calculates all necessary design parameters by entering user's requirements. Please contact Richtek's representatives for details.

Phase Selection and Operation Modes

The maximum number of operating pha se is programmable by setting ISEN2_N. After the initi al turn-on of the RT8856, an internal comparator check s the voltage at the ISEN2_N pin. To set the RT8856 as a pure single phase PWM controller, connect ISEN2_N to a voltage higher than (V

CC

- 1V) at power on. The controller will then disable pha se 2 (hold UGA TE2 and LGA TE2 low) and operate a s a single phase PWM controller .

The RT8856 also works in conjunction with Intel's IIMVP6.5 control signals, such as PSI and DPRSLPVR. Table 2 shows the control signal truth table for operation modes of the RT8856.

For high current demand, the controller will operate with both phases active. These two phase gate signals are interleaved. This achieves mini mal output voltage ri pple and best tra nsient performa nce.

For reduced current demand, only one phase is active. For 1-phase operation, the power stage can minimize switching losses and maintain transient response capability.

At lowest current levels, the controller enters single phase Ringing-Free Mode (RFM) to achieve highest eff iciency .

Table 2. Control signal truth table for operation

modes

DPRSLPVR PSI Operation mode

0 1 0 0

1 1 1 0

Multi-phase CCM Single-phase CCM S Single-phase RFM,

sl ow C4E Single-phase RFM, sl ow C4E

Differential Remote Sense Setting

The RT8856 includes differential, remote sense inputs to eliminate the effects of voltage drops along the PC board traces, CPU internal power routes and socket contacts. The CPU contains on-die sense pin voltages, V and V V

CC_SENSE

SS_SENSE

. V

SS_SENSE

is connected to RGND pin. The

is connected to FB pin with a resistor to build

CC_SENSE

the negative input path of the error a mplifier. Connect VSEN to V

CC_SENSE

for CLKEN, PGOOD, OVP, and UVP sense. The 7-bit VID DAC a nd the precision voltage reference are referred to RGND f or accurate remote sensing.

Current Sense Setting

The RT8856 continuously sense the output current of ea ch phase. Therefore, the controller can be less noise sensitive and get more a ccurate current sharing between phases. Low offset a mplifiers are used for loop control a nd current limit. The internal current sense a mplifier gain (AI) is fixed to be 10. The ISENx and ISENx_N denote the positive and negative input of the current sense amplifier of each phase, respe ctively. Users ca n either use a current-sense resistor or the inductor's DCR f or current sensing.

Using inductor's DCR allows higher efficiency as shown in Figure 1. If

L

RC

DCR



X

(1)

then the current sense performa nce will be optimum. For example, choosing L = 0.36μH with 1mΩ DCR and CX = 100nF, yields RX :



X



1.0m 100nF

0.36 H



R3.6k

(2)

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15

RT8856

V

OUT

L

R

X

ISENx

DCR

C

X

+ V

V

C2 C1

-

X

IN

HS_FET

LS_FET

C

BYPASS

) of the current

ESL

, will decrease

OUT

L

R

X

C

X

V

OUT

R

C

PHASEx

ISENx

ISENx_N

Figure 1. Lossless Inductor Sensing

Since the inductance tolerances are normally observed to be 20%, the resistor, RX, has to be tuned on board by examining the transient voltage. If the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery , RX is chosen too small. Vice versa, with a resistance too large, the output voltage transient has only a small initial dip and the recovery is too fast, thus causing a ring-back.

Using current sense resistor in series with the inductor can have better a ccuracy , but the ef ficiency is a trade-off. Considering the equivalent inductance (L sense resistor , an RC filter is recommended. The RC f ilter calculation method is similar to the above-mentioned inductor DCR sensing method .

Loop Control

The RT8856 adopts Richtek's proprietary NAV PTM topology . NAVPTM is based on the finite-gain peak current mode PWM topology. The output voltage, V with increasing output load current. The control loop consists of PWM modulator with power stage, current sense a mplifier and error a mplif ier a s shown in Figure 2.

RT8856

CMP

COMP2

Clock

-

S

R

+

V

CS

PWM Logic

A

+

I

-

UGATEx

LGATEx

ISENx_N

Similar to the peak current mode control with finite compensator gain, the HS_FET on-time is determined by both the internal clock and the PWM comparator which compares the EA output with the output of current sense amplifier. When load current increases, VCS increases, the steady state COMP voltage also increa ses and ma kes the V (V

decrea se, hence achieving A VP . A near-DC of fset

OUT

) is added to the output EA to cancel the inherent

OFS

output offset of finite-gain pea k current mode controller. In RFM, HS_FET is turned on with constant TON when

VCS is lower than V

. Once the HS_FET is turned off,

COMP2

LS_FET is turned on automatically. By Ringing-Free Technique, the LS_FET allows only partial of negative current when the inductor free-wheeling current reaches negative. The switching frequency will be proportionately reduced, thus the conduction and switching losses will be greatly reduced.

Droop Setting (with Temperature Compensation)

It's very ea sy to achieve Active V oltage Positioning (A VP) by properly setting the error amplif ier gain with respect to the native droop characteristics. The target is to have Equation (3)

V

= V

OUT

then solving the switching condition V

SOFT

− I

LOAD

x R

DROOP

COMP2

(3)

= VCS in

Figure 2 yields the desired error a mplifier gain a s

AR

R2

A



V

R1 R

where AI is the internal current sense a mplifier gain. R



I SENSE

DROOP

(4)

SENSE

is the current sense resistor. If there is no extern al sense resistor, it is the DCR of the inductor. R

DROOP

is the resistive slope value of the converter output and is the desired static output impedance, e.g. −1.9mΩ or −3mΩ for IMVP6.5 specification. Increasing AV can make load line more shallow as shown in Figure 3.

V

OUT

A

> A

V2

V1

FB

R2 R1

C

SOFT

V

CC_SENSE

V

SS_SENSE

A

V2

A

V1

0

Load Current

Figure 3. Error Amplifier Gain (AV) Influence on V

Accuracy

COMP

-

EA

+

SOFT

-

+

V

OFS

DAC

RGND

Figure 2. Simplified Schematic for Droop a nd Remote

Sense in CCM

©

DS8856-04 August 2014www.richtek.com

16

OUT

RT8856





Since the DCR of inductor is highly temperature dependent,

it affects the output accuracy at hot conditions.

Temperature compensation is recommended for the lossless inductor DCR current sense method. Figure 4 shows a simple but effective way of compensating the temperature variations of the sense resistor using a n NTC thermistor placed in the feedba ck path.

FB

C2 C1

R2

R1b

C

SOFT

10nF

R1a

NTC

V

CC_SENSE

SS_SENSE

EA

+

V

DAC

RT8856

+

-

COMP

SOFT

RGND

Figure 4. Loop Setting with T emperature Compen sation

Usually , R1a is set to equal R

(25°C). R1b is selected

NTC

to linearize the NTC's temperature characteristic. For a given NTC, design is to get R1b a nd R2 and then C1 a nd C2. According to Equation (4), to compensate the temperature variations of the sense resistor, the error amplifier gain (AV) should have the same temperature coefficient with R

AR

V, HOT SENSE, HOT

AR

V, COLD SENSE, COLD



SENSE

. Hence,

(5)

where the 0.00393 is the temperature coefficient of the copper. For a given NTC thermistor , solving Equation (6) at room temperature (25°C) yields

R2 = A where A

x (R1b + R1a // R

V, 2 5

is the error amplif ier gain at room temperature

V, 25

) (9)

NTC, 25

and ca n be obtained from Equation (4). R1b can be obtained by substituting Equation (9) to (5),

R1 b



R

SENSE, HOT

R

SENSE, COLD

(R1a//R ) (R1a//R )



 



NTC, HOT NTC, HOT

R

SENSE, HOT

1



R

SENSE, COLD

(10)

Loop Compensation

Optimized compensation of the RT8856 allows for best possible load step response of the regulator's output. A type-II compensator with one pole and one zero is adequate for a proper compensation. Figure 4 shows the compensation circuit. Prior design procedure shows how to select the resistive feedback components for the error amplif ier gain. Next, the C1 a nd C2 must be calculated for the compensation. The target is to achieve constant resistive output impedance over the widest possible frequency range.

From Equation (4), A v can be obtained at a ny temperature (T) as shown below :

A



V, T

R1 a// R R1 b

R2

NTC, T



(6)

The pole frequency of the compensator must be set to compensate the output ca pacitor ESR zero :

f



P

1

2CR

 

C

(11)

where C is the cap acita nce of output ca pa citor , a nd RC is

The standard formula f or the resistance of NTC thermistor a s a function of temperature compensation is given by :



11









T+273 298

RR e



NTC, T 25



(7)

where R25 is the thermistor's nominal resistance at room temperature, β (beta) is the thermistor's material constan t in Kelvins, and T is the thermistor's actual temperature in Celsius.

T o calculate DCR value at different te mperature, use the

the ESR of output capacitor. C2 can be calculated as follows :

CR



C2



R2

C

(12)

The zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. such that,

C1



R1 b R1a// R f





1

NTC, 25 SW

(13)

equation below : DCRT = DCR25 x [1 + 0.00393 x (T − 25)] (8)

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17

RT8856

Frequency Setting

High frequency operation optimizes the application for smaller component size, but trads off efficiency due to higher switching losses. This may be accepta ble in ultraportable devices where the load currents are lower and the controller is powered from a lower voltage supply . Low frequency operation offers the best overall efficiency at the expense of component size and board spa ce.

Connect a resistor (RFS) between FS and ground to set the switching frequency (fSW) per phase :

Power Up Sequence

With the controller's VCC voltage above the POR threshold (typ. 4.3V), the power-up sequence begins when VRON exceeds the 3.3V logic high threshold. Approximately 20μs later, SOFT and V

starts ramping up to boot

CORE

voltage (1.1V) with maximum pha ses. The slew rate during power-up is 20μA/C after V

rises above 1V for 73μs. Right after CLKEN

VSEN

goes low, SOFT and V

. The RT8856 pulls CLKEN low

SOFT

starts ramping to first DAC

CORE

value. After CLKEN goes low for approximate 4.7ms, PGOOD is a sserted HIGH. DPRSLPVR and PSI are valid

R(k)

FS

300(kHz) 33(k )



A resistor of 5kΩ to 50kΩ corresponds to switching frequency of 1MHz to 200kHz, respectively .

Soft-Start and Mode Change Slew Rates

The RT8856 uses 2 slew rates for various modes of operation. These two slew rates are internally determined by commanding one of two bi-directional current sources on to the SOFT pin (ISS). The 7-bit VID DAC and the precision voltage reference are referred to RGND for accurate remote sensing. Hence, connect a capacitor (C

) from SOFT pin to RGND for controlling the slew

SOFT

rate as shown in Figure 4. The cap acita nce of capa citor is restricted to be larger than 10nF. The voltage on SOFT pin (V

) is higher than the reference voltage of the error

SOFT

amplif ier at about 0.9V. The first current of typically 20μA is used to charge or

discharge the C second current of typically 100μA is used during other voltage transitions, including VID cha nge a nd transitions between operation modes.

The IMVP6.5 specification specifies the critical timing associ ated with regulating the output voltage. The symbol, SLEWRATE, as given in the IMVP6.5 specification will determine the choice of the SOFT ca pacitor , C following equation :

C(nF)

SOFT



SLEWRATE(mV / s)



f(kHz)

SW

during soft-start, soft-shutdown. The

SOFT

SOFT,



I(A)

SS



(14)

by the

(15)

right after PGOOD is asserted. UVP is masked as long as V

DPRSLPVR

CLKEN

PGOOD

is less than 1V.

SOFT

4.3V

VCC POR

VRON

VID Valid

V

CORE

PWM

PSI

Hi-Z

XX

1V

MAX Phases

73µs typ.4.7ms typ.

1.1V

DPRSLPVR/PSI

Defined

MAX Phases ValidXX XX ValidXX XX

0.2V Pull Low

Figure 5. Ti ming Di agram f or Power-Up and Power-Down

Power Down

When VRON goes low, the RT8856 enters low-power shutdown mode. PGOOD is pulled low i mmedi ately and V

ramps down with slew rate of 20μA/C

SOFT

also ramps down f ollowing V After V

falls below 200mV , the RT8856 turns of f both

VSEN

with maximum pha ses.

SOFT

high side and low side MOSFETs. A discharging re sistor at VSEN will be en abled and the a nalog part will be turned off.

Deeper Sleep Mode Transitions

After DPRSLPVR goes high, the RT8856 immediately disables pha se 2 (UGA TE2 and LGA TE2 forced low) a nd enters 1-phase deeper slee p mode operation. If the VIDs are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. The internal target V

still ramps as before, and UVP,

SOFT

OCP and OVP are masked for 73μs.

18

©

DS8856-04 August 2014www.richtek.com

. V

x x

VSEN

4.1V

RT8856

The RT8856 provides 2 slew rates for deeper sleep mode entry/ exit. For standard deeper sleep exit, the RT8856 immediately a ctivates all en a bled phases and ramps the output voltage to the DAC code provided by the processor at the slew rate of 100μA/C

. The RT8856 remains in

SOFT

1-phase ringing free mode a nd ramps the output voltage to the DAC code provided by the processor at the slew rate of 20μA/C

SOFT

.

Current Limit Setting

The RT8856 compares a progra mmable current limit set point to the voltage from the current sense a mplifier output for Over Current Protection (OCP). The voltage a pplied to OCSET pin defines the desired current limit threshold, I

:

LIM

V

OCSET

= 25 x I

LIM

x R

(16)

SENSE

Connect a resistive voltage divider from VCC to GND, with the joint of the voltage divider connected to OCSET pin a s shown in Figure 6. For a given R

V



RR 1

 

OC1 OC2

CC



V

OCSET



RT8856

OCSET

V

OC2

CC

,

(17)

R

OC1

R

OC2

Figure 6. OCP Setting Without Temperature

Compensation

The OCP works in two stages :

 Stage 1 : A verage inductor current exceeds the current

limit threshold, I smaller than 150% of I

, defined by V

LIM

If the over current condition

LIM

, but remains

OCSET

remains valid for 16 cycles, the OCP latches and the system shuts down.

 Stage 2 : Any inductor current exceeds 150% of I

LIM

then OCP latches instantaneously.

Latched OCP forces driver high impedance with UGA TEx = 0 and LGA TEx = 0. After latched OCP ha ppens, V

will be monitored. When V

VSEN

falls below 200mV ,

VSEN

a discharging resistor at VSEN will be enabled.

temperature compensation is recommended to protect under all conditions. Figure 7 shows a typical OCP setting with temperature compensation.

V

CC

RT8856

OCSET

R

OC1a

R

NTC

OC1b

OC2

Figure 7. OCP Setting with Temperature Compensation

Usually, select R resistance at room temperature. Ideally, V have same temperature coefficient as R

equal to thermistor's nominal

OC1a

OCSET

SENSE

should

(Inductor

DCR) :

VR

OCSET, HOT SENSE, HOT

VR

OCSET, COLD SENSE, COLD

According to the basic circuit calculation, V



OCSET

(18)

can be

obtained at any temperature :

R

V

OCSET, T



R//R R R

OC1a NTC, T OC1b OC2

OC2



Re-write Equation (18) from (19), and get V

OCSET

(19)

at room

temperature

R//R R R R

OC1a NTC, COLD OC1b OC2 SENSE, HOT

R//R R R R

OC1a NTC, HOT OC1b OC2 SENSE, COLD





(20)

R

V

OCSET, 25



R//R R R

OC1a NTC, 25 OC1b OC2

Solving Equation (20) and (21) yields R

R



OC2

RR (1)R

    

EQU, HOT EQU, COLD EQU, 25

V

CC

V

OCSET, 25

R



OC1b

(1)R R R

   

OC2

EQU, HOT EQU, COLD

(1 )



OC2



(1 )



OC1b

and R

(21)

OC2

(22)

(23)

where



R

SENSE, HOT

R DCR [1 0.00393 (T 25 )]

SENSE, COLD 25 COLD

DCR [1 0.00393 (T 25)]



  

25 HOT

  

If inductor DCR is used a s current sense component, then

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(24)

19

RT8856

R

EQU, T

= R1a // R

(25)

NTC, T

For example, the f ollowing design parameters are given : DCR =1mΩ, V R

= R

OC1a

NTC, 25

= 5V, I

CC

= 10kΩ, β

L, Ripple

NTC

= 5A

= 2400

For −20°C to 100°C operation range, to set OCP trip current I

= 57A when operating with maxi mum phases :

TRIP

57A

I5A33.5A



LIM

V 25 33.5A 1m 0.8375V

R R



R

2

OCSET, 25

NTC, −20

SENSE, −20

=41.89kΩ, R

= 2.437kΩ, R

OC2

 

SENSE, 100

= 7.113kΩ

OC1b

= 1.98kΩ

NTC, 100

=0.82 mΩ, R

=1.29mΩ

Over Voltage Protection (OVP)

The OVP circuit is triggered under two conditions :

 Condition 1 : When V  Condition 2 : When V

exceeds 1.55V.

VSEN

exceeds V

VSEN

by 200mV.

DAC

If either condition is valid, the RT8856 latches the LGATEx =1 and UGATEx = 0 as crowbar to the output voltage of VR. Turning on all LS_FETs can lead to very large reverse inductor current and potentially result in negative output voltage of VR. To prevent damage of the CPU by negative voltage, the RT8856 turns off all LS_FET s when V

has fallen below −100mV.

VSEN

Under Voltage Protection (UVP)

If V

is less than V

VSEN

by 300mV or more, a UVP fault

DAC

is latched and the RT8856 turns of f both upper side and lower side MOSFETs. V valid. When V

falls below 200mV, a discharging

VSEN

is monitored after UVP is

VSEN

resistor at VSEN will be enabled.

Negative Voltage Protection (NVP)

During shutdown or protection state, when V

VSEN

is lower than −100mV, the controller will force LGATEx = 0 and UGA TEx = 0 for preventing negative voltage. Once V

VSEN

recovers to be more than 0mV, NVP will be suspended and LGATEx = 1 will be enabled again.

Over Temperature Protection (OTP)

Over Temperature Protection prevents the VR from da mage. OTP is considered to be the final protection stage against overheating of the VR. The thermal throttling VRTT should be set to assert prior to OTP to manage the VR power. When this measure is insufficient to keep the die temperature of the controller below the OTP threshold, OTP will be a sserted and latched. The die temperature of the controller is monitored internally by a temperature sensor. As a result of OTP triggering, a soft shutdown will be launched and V

will be monitored. When V

VSEN

is less than 200mV, the driver remains in high impedance state and the discharging resistor at VSEN pin will be enabled. A reset can be executed by cycling VCC or VRON.

Thermal Throttling Control

Intel IMVP6.5 technology supports thermal throttling of the processor to prevent catastrophic thermal damage. The RT8856 includes a thermal monitoring circuit to detect an exceeded user defined temperature on a VR point. The thermal monitoring circuit senses the voltage change across the NTC pin. Figure 8 shows the principle of setting the temperature threshold. Connect an external re sistive voltage divider between Vcc and GND. This divider uses a Negative T emperature Coef ficient (NTC) thermistor and a resistor. The joint of the voltage divider is connected to the NTC pin in order to generate a voltage that is proportional to the temperature. The RT8856 pulls VRTT low if the voltage on the NTC pin is greater tha n 0.8 x VCC. The internal VR TT comparator ha s a hysteresis of 100mV to prevent high frequency VRTT oscillation when the temperature is near the setting point. The minimum a ssertion/de-assertion time for VRT T toggling is 1.5ms.

RT8856

T

R

V

CC

R

CMP

0.8 x V

NTC

+

-

CC

R

OC1b

OC2

Figure 8. Thermal Throttling Setting Principle

20

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RT8856

Users can use the sa me NTC thermistor for both thermal throttling and current limit setting as shown in Figure 9. Just divide the R V

equation at thermal throttling temperature TT°C :

NTC

R

TT a

+ R

TTb

= R

RR

RR R//R



OC2 OC1b OC1a NTC, TT C

0.8 V



CC

Solving (26) and (27) for R R

= 4 x (R

TTb

R

= R

TTa

OC1b

into R

OC1b

(26)

OC1b



OC2 TTb

// R

OC1a

− R

NTC, TT°C

(29)

TTb

RT8856

+

CMP

-

0.8 x V

CC

TTa

NTC

and R

TT a

and R

)−R

R

OC1a

TTb

V





as :

TTb

(28)

OC2

T

R

V

CC

R

, and write the

CC

(27)

T

NTC

OC1b

OC2

Figure 9. Using single NTC Thermistor f or Thermal

Throttling and Current Limit Setting

Current Monitor

The current monitor allows the system to accurately monitor the CPU's current dissipation and quickly predict whether the system is about to overheat before the significantly slower temperature sensor signals an over temperature alert. The voltage output of CM pin is proportional to the output current. This pin is connected to ground with one resistor while CMSET pin is connected to V

with another resistor . By choosing the appropri ate

VSEN

ratio of these two resistors, current monitor gain can be set and VCM will be 1V with maximum output current. Maximum value of VCM is clamped at 1.15V.

R

 

VI R 2

CM LOAD DROOP

R

CM

CMSET

(30)

Inductor Selection

The switching frequency and ripple current determine the inductor value as f ollows :

V(1D)

LN

MIN

OUT(MIN) MIN



where N is the total number of pha ses. D



fI



SW Ripple

is the minimum

MIN

(31)

duty at highest input voltage VIN. Higher inductance yields in less ripple current a nd hence

in higher efficiency. The flaw is the slower transient response of the power stage to load tran sients. This might increa se the need f or more output capacitors driving the cost up. Find a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The core must be large enough not to saturate at the peak inductor current.

Output Capacitor Selection

Output cap acitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. Usually, the CPU manufacturer recommends a capacitor configuration. Two different kinds of output capacitors can be found, bulk capacitors closely located to the inductors and ceramic output capacitors in close proximity to the load. The latter ones are for mid frequency decoupling with especially small ESR and ESL values while the bulk ca pacitors have to provide enough stored energy to overcome the low frequency bandwidth gap between the regulator and the CPU.

Thermal Considerations

For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and a mbient temperature. The maximum power dissipation can be calculated by the following formula :

P where T

the ambient temperature, a nd θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

JA

is the maximum junction temperature, T

is the junction to ambient

JA

A

thermal resistance.

is

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21

RT8856

For recommended operating condition specifications of RT8856, the maximum junction temperature is 125°C a nd TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WQF N-40L 6x6 pa ckages, the thermal resista nce, θJA, is 34°C/W on a standard JEDEC 51-7 f our-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula :

P

= (125°C − 25°C) / (34°C/W) = 2.941W for

D(MAX)

WQF N-40L 6x6 pa ckage The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. For RT8856 package, the derating curve in Figure 10 allows the designer to see the effect of rising ambient temperature on the maxi mum power dissipation.

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

Maximum Power Dissipation (W) 1

0.0 0 25 50 75 100 125

Ambient Temperature (°C)

Four Layers PCB

Layout Considerations

Careful PC board layout is critical to achieve low switching losses and clea n, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for optimum PC board layout :

 Keep the high current paths short, especially at the

ground terminals.

 Keep the power trace s and load connections short. This

is essential for high efficiency.

 Connect slew rate control capacitor at SOFT pin to

RGND.

 When trade offs in trace lengths must be made, it's

preferable to allow the inductor charging path to be made longer than the discharging path.

 Place the current sense component close to the

controller. ISENx a nd ISENx_N conne ctions for current limit and voltage positioning must be made using Kelvin sense connections to guarantee the current sense accuracy. PCB trace from the sense nodes should be paralleled back to controller .

 Route high speed switching nodes away from sensitive

analog areas (SOFT, COMP, FB, VSEN, ISENx, ISENx_N, CM, CMSET, etc...)

Figure 10. Derating Curves f or RT8856 Packages

22

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Outline Dimension

RT8856

Symbol

D2

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dime nsions In Inches

Min. Max. Min. Max.

A A1 A3

b

D

0.700 0.800 0.028 0.031

0.000 0.050 0.000 0.002

0.175 0.250 0.007 0.010

0.180 0.300 0.007 0.012

5.950 6.050 0.234 0.238 Option1 4.000 4.750 0.157 0.187 Option2 3.470 3.570 0.137 0.141

E

5.950 6.050 0.234 0.238

1 2

DETAIL A

1

2

E2

Option1 4.000 4.750 0.157 0.187 Option2 2.570 2.670 0.101 0.105

e L

0.350 0.450 0.014 0.018

0.500 0.020

W-Type 40L QFN 6x6 Package

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23

RT8856

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8856-04 August 2014www.richtek.com

24

Richtek RT8856GQW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual