Richtek RT8820A Datasheet

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RT8820A

Dual-Pha se PWM Controller with PWM-VID Reference

General Description

The RT8820A is a 2/1 phase synchronous Buck PWM

controller which is optimized for high performance graphic

microprocessor and computer applications. The IC

integrates a Constant-On-Time (COT) PWM controller, two

MOSFET drivers with internal bootstrap diodes, as well

as channel current balance and protection functions

including Over-Voltage Protection (OVP), Under-Voltage

Protection (UVP), current limit, and thermal shutdown into

the WQFN-20L 3x3 package.

The RT8820A adopts R

Current limit is accomplished through continuous inductor-

current-sense, while R

accurate channel current balance. Using the method of

current sampling utilizes the best advantages of each

technique.

The RT8820A features external reference input and PWM-

VID dynamic output voltage control, in which the feedback

voltage is regulated and tracks external input reference

voltage. Other features include adjustable switching

frequency, dynamic phase number control, internal soft-

start, power good indicator, and enable functions.

current sensing technique.

DS(ON)

current sensing is used for

DS(ON)

Features



Dual-Phase PWM Controller





 Power State Indicator





 1P-CCM/2P-CCM/1P-DEM/2P-DEM





 Two Embedded MOSFET Drivers and Embedded



Switching Boot Diode



 Support 1.8V PWM-VID Interface



 External Reference Input Control



 PWM-VID Dynamic Voltage Control



 Dynamic Phase Number Control



 Lossless R



 Internal/External Soft-Start



 Adjustable Current Limit Threshold



 Adjustable Switching Frequency



 UVP/OVP Protection



 Shoot Through Protection and Short Pulse Free



Current Sensing for Current Balance

DS(ON)

Technology



 Support an Ultra-Low Output Voltage as Standby



Voltage



 Thermal Shutdown



 Power Good Indicator (EN to PG high = 500



μμ

μs)

μμ

Applications

Ordering Information

RT8820A

Package Type QW : WQFN-20L 3x3 (W-Type)

Lead Plating System G : Green (Halogen Free and Pb Free)

Note :

 CPU/GPU Core Power Supply

 Desktop PC Memory, VTT Power

 Chipset/RAM Power Supply

 Generic DC-DC Power Regulator

Pin Configuration

(TOP VIEW)

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

Marking Information

KP= : Product Code

KP=YM

DNN

YMDNN : Date Code

PHASE1

BOOT1

UGATE1

EN PSI VID VSNS

GND

REFADJ

PHASE2

LGATE1

LGATE2

PVCC

17181920

BOOT2

UGATE2

PGOOD

TON

OCSET/SS

115

RGND

9876

VREF

REFIN

WQFN-20L 3x3

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RT8820A

Functional Pin Description

Pin No. Pin Name Pin Function

1 BOOT1 Bootstrap supply for PWM1. This pin powers the high-side MOSFET driver.

2 UGATE1

3 EN

4 PSI

5 VID

6 REFADJ Reference adjustment output. Refer to PWM-VID Dynamic Voltage Control.

7 REFIN External reference input.

8 VREF

9 TON

10 RGND Negative remote sense input. Connect this pin to the ground of output load.

11 VSNS

12 OCSET/SS

13 PGOOD Power good indicator output. Active high open-drain output.

14 UGATE2

High-side gate driver of PWM1. This pin provides the gate drive for the converter's high-side MOSFET. Connect this pin to the gate of high-side MOSFET.

Enable control input. Active high input. When PVCC POR, the input voltage must not be over PVCC.

Power saving interface. When the voltage is pulled below 0.4V, the device operates into 1 phase DEM. When the voltage is between 0.7V to 0.88V, the device operates into 1 phase forced CCM. When the voltage is between 1.08V to

1.35V, the device operates into 2 phase DEM. W hen the voltage is between 1.6V to 5.5V, the device operates into 2 phase forced CCM.

Programming output voltage control input. Refer to PWM-VID Dynamic Voltage Control.

Reference voltage output. This is a high precision voltage reference (2V) from the VREF pin to RGND pin.

On-time/switching frequency adjustment input. Connecting a 100pF ceramic capacitor between C

Positive remote sense input. Connect this pin to the positive terminal of output load.

Current limit setting. Connect a resistor from OCSET/SS to GND to set the current limit threshold. The external soft start time also can be set through by connecting a capacitor from OCSET/SS pin to GND.

High-side gate driver of PWM2. This pin provides the gate drive for the converter's high-side MOSFET. Connect this pin to the gate of high-side MOSFET.

and ground is optional for noise immunity enhancement.

TON

15 BOOT2 Bootstrap supply for PWM2. This pin powers the high-side MOSFET driver.

Switch node for PWM2. This pin is return node of the high-side driver of PWM 2.

16 PHASE2

17 LGATE2

18 PVCC

19 LGATE1

20 PHASE1

(Exposed Pad)

GND

Connect this pin to the source of high-side MOSFET together with the drain of low-side MOSFET and the inductor.

Low-side gate driver of PWM2. This pin provides the gate drive for the converter's low-side MOSFET. Connect this pin to the gate of low-side MOSFET.

Supply voltage input. Connect this pin to a 5V bias supply. Place a high quality bypass capacitor from this pin to GND.

Low-side gate driver of PWM1. This pin provides the gate drive for the converter's low-side MOSFET. Connect this pin to the gate of low-side MOSFET.

Switch node for PWM1. This pin is return node of the high-side driver of PWM 1. Connect this pin to the Source of high-side MOSFET together with the drain of low-side MOSFET and the inductor.

Ground. The Exposed pad should be soldered to a large PCB and connected to GND for maximum thermal dissipation.

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Functional Block Diagram

VREF

VID

REFADJ

PSI

REFIN

RGND

150% REFIN

or 2V

40% REFIN

Mode Select

Reference

Output Gen.

Power On Reset

& Central Logic

Control & Protection Logic

Boot-Phase Detection 1

RT8820A

PVCC

PGOOD

VSNS

TON

OCSET/SS

Soft-Start

& Slew Rate

Control

Enable

Logic

To Power On Reset

ICS 10µ

To Driver Logic To Power On Reset

VIN

Detection

ICS 40µ

PWM

CMP

To Protection Logic

To SSOK

X(-1/12)

TON

Gen 1

TON

Gen 2

Current

Balance

Current

Limit

Boot-Phase Detection 2

PWM1

PWM2

S/H

Driver

Logic

BOOT1 UGATE1 PHASE1

LGATE1

BOOT2 UGATE2 PHASE2

LGATE2

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RT8820A

Operation

The RT8820A is a dual-phase synchronous Buck PWM

controller with integrated drivers which are optimized for

high performance graphic microprocessor and computer

applications. The IC integrates a COT (Constant-On-Time)

PWM controller with two MOSFET drivers, as well as

output current monitoring and protection functions.

Referring to the function block diagram of TON Genx, the

synchronous UGATE driver is turned on at the beginning

of each cycle. After the internal one-shot timer expires,

the UGATE driver is turned off. The pulse width of this

one-shot is determined by the converter's input voltage

and the output voltage to keep the frequency fairly constant

over the input voltage range and output voltage. Another

one-shot sets a minimum off-time.

The RT8820A also features a PWM-VID dynamic voltage

control circuit driven by the pulse width modulation

method. This circuit reduces the device pin count and

enables a wide dynamic voltage range.

Soft-Start (SS)

For soft-start function, an internal current source charges

an internal capacitor to build the soft-start ramp voltage.

The output voltage will track the internal ramp voltage during

soft-start interval.

PGOOD

The power good output is an open-drain architecture.

When the soft-start is finished, the PGOOD open-drain

output is high impedance.

Current Balance

The RT8820A implements internal current balance

mechanism in the current loop. The RT8820A senses per

phase current and compares it with the average current. If

the sensed current of any particular phase is higher than

average current, the on-time of this phase is adjusted to

be shorter.

Current Limit

The current limit circuit employs a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at PHASE is above the current limit threshold, the

PWM is not allowed to initiate a new cycle. Thus, the

current to the load exceeds average output inductor

current, the output voltage falls and eventually crosses

the under-voltage protection threshold, inducing IC

shutdown.

Over-Voltage Protection (OVP) & Under-Voltage Protection (UVP)

The output voltage is continuously monitored for over-

voltage and under-voltage protection. When the output

voltage exceeds its set voltage threshold (If V

OV = 2V, or V

> 1.33V, OV = 1.5 x V

REFIN

≤ 1.33V,

), UGATE

goes low and LGATE is forced high; when it is less than

40% of its set voltage, under voltage protection is triggered

and then both UGATE and LGATE gate drivers are forced

low. The controller is latched until PVCC is re-supplied

and exceeds the POR rising threshold voltage or EN is

reset.

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RT8820A

Absolute Maximum Ratings (Note 1)

 TON to GND ------------------------------------------------------------------------------------------------------------------ −0.3V to 30V

 RGND to GND --------------------------------------------------------------------------------------------------------------- −0.7V to 0.7V

 BOOTx to PHASEx

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 6V

<100ns ------------------------------------------------------------------------------------------------------------------------ −5V to 7.5V

 BOOTx to GND

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 36V

<100ns ------------------------------------------------------------------------------------------------------------------------ −5V to 42V

 PHASEx to GND

DC------------------------------------------------------------------------------------------------------------------------------ −5V to 30V

<100ns ------------------------------------------------------------------------------------------------------------------------ −10V to 42V

 UGATEx to GND

DC------------------------------------------------------------------------------------------------------------------------------ −5V to 36V

<100ns ------------------------------------------------------------------------------------------------------------------------ −10V to 42V

 UGATEx to PHASEx

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 6V

<100ns ------------------------------------------------------------------------------------------------------------------------ −5V to 7.5V

 LGATEx to GND

DC------------------------------------------------------------------------------------------------------------------------------ −0.3V to 6V

<100ns ------------------------------------------------------------------------------------------------------------------------ −5V to 7.5V

 Other Pins-------------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V

 Power Dissipation, P

WQFN-20L 3x3 ------------------------------------------------------------------------------------------------------------- 2.67W

 Package Thermal Resistance (Note 2)

WQFN-20L 3x3, θJA-------------------------------------------------------------------------------------------------------- 30°C/W

WQFN-20L 3x3, θJC------------------------------------------------------------------------------------------------------- 7.5°C/W

 Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------- 260°C

 Junction Temperature ------------------------------------------------------------------------------------------------------ 150°C

 Storage Temperature Range --------------------------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Model)----------------------------------------------------------------------------------------------- 2kV

@ T

= 25°C

Recommended Operating Conditions (Note 4)

 Input Voltage, VIN ---------------------------------------------------------------------------------------------------------- 2.5V to 26V

 Supply Voltage, PVCC ---------------------------------------------------------------------------------------------------- 4.5V to 5.5V

 Junction Temperature Range --------------------------------------------------------------------------------------------- −10°C to 105°C

DS8820A-01 February 2020 www.richtek.com

RT8820A

Electrical Characteristics

= 5V, typical values are referenced to TA = TJ = 25°C, Min and Max values are referenced to TA = TJ from −10°C to

PVCC

105°C, unless other noted)

Parameter Symbol Test Conditions Min Typ Max Unit

PWM Controller

PVCC Supply Voltage V

PVCC Supply Current I

PVCC Shutdown Current I

PVCC POR Threshold 3.8 4.1 4.4 V

POR Hysteresis -- 0.3 -- V

Switching Frequency fSW R

Minimum On-Time t

Minimum Off-Time t

EN Inpu t Voltage

Logic-High V

EN Input Voltage

Logic-Low V

Mode Decision

2 Phase CCM V

2 Phase DEM V

1 Phase CCM V

1 Phase DEM V

PWM-VID Input Vol t age for 1. 8V G PIO Set t ing

4.5 -- 5.5 V

PVCC

= 3.3V, 1phase DEM mode,

SUPPLY

not switching, VREF external R =

-- 0.4 -- mA

40k

SHDN

ON(MIN)

OFF(MIN)

-- 70 -- ns

1.2 -- 5.5

EN_H

-- -- 0.55

EN_L

1.6 1.8 5.5 V

PSI

1.08 1.2 1.35 V

PSI

0.7 0.8 0.88 V

PSI

-- 0 0.4 V

PSI

= 0V -- -- 10 A

= 500k (Note 5) 270 300 330 kHz

TON

-- 300 -- ns

Logic H V

Logic L V

PWM-VID_H

PWM-VID_L

1.2 -- -- V

-- -- 0.6 V

Protect io n Function

Zero Current Crossing Threshold

Current Limit Setting Current I

Current Limit Setting Current Temperature Coefficient

Current Limit Threshold R

Absolute Over-Voltage Protection Threshold Relative Over-Voltage Protection Threshold

8 -- 8 mV

OCSET

OCSET_TC

OVP, Absolute

OVP, Relative

-- 4700 -- ppm/C

= TJ = 25C 9 10 11 A

= 120k -- 100 -- mV

OCSET

 1.33V 1.9 2 2.1 V

REFIN

> 1.33V 145 150 155 %

REFIN

OV Fault Delay FB forced above OV threshold -- 5 -- s

Relative Under-Voltage Protection Threshold

UVP 35 40 45 %

UVP

UV Fault Delay FB forced above UV threshold -- 3 -- s

Thermal Shutdown Threshold

-- 150 -- C

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RT8820A

Parameter Symbol Test Conditions Min Typ Max Unit

VOUT Soft-Start (PGOOD Blanking Time)

From VEN = high to VOUT regulation point, V

REFIN

= 1V

-- 0.5 -- ms

Error Amplifier

VSNS Error Comparator Threshold (Valley)

= 1V 11 6 1 mV

REFIN

Reference

Reference Voltage V

VREF

Sourcing current = 1mA, VID no switching

1.98 2 2.02 V

Driver On-Resistance

UGATE Driver Source R

UGATE Driver Sink R

LGATE Driver Source R

LGATE Driver Sink R

UGATEsr

UGATEsk

LGATEsr

LGATEsk

BOOTx  PHASEx forced to 5V -- 2 4 

BOOTx  PHASEx forced to 5V -- 1 2 

LGATEx, high state -- 1.5 3 

LGATEx, low state -- 0.7 1.5 

From LGATE falling to UGATE rising -- 30 --

Dead-Time

From UGATE falling to LGATE rising -- 20 --

Internal Boost Diode Resistance

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Not production tested. Test condition is V

is measured under natural convection (still air) at T

thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θ

exposed pad of the package.

BOOT

PVCC to BOOTx, I

= 25°C with the component mounted on a high effective-

= 8V, V

OUT

= 1V, I

= 10mA -- 80 -- 

BOOT

is measured at the

= 20A using application circuit.

OUT

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RT8820A

Typical Application Circuit

TON

500k

Optional

PSI VID

Enable

20k

REFADJ

2k 2.7nF

RGND

REF2

18k

100k

RGND

STANDBY

2.2

STANDBY

5.1k

REF1

BOOT

RGND

PVCC

1µF

PGOOD

RGND

2.2µF

0.1µF

20k

REFADJ

REFIN

TON

4 5

PVCC

TONV

PGOOD PSI VID

VREF

REFADJ

REFIN

BOOT1

RT8820A

UGATE1

PHASE1

LGATE1

OCSET/SS

BOOT2

UGATE2

PHASE2

LGATE2

RGND

GND

21 (Exposed pad)

VSNS

OCSET

0.36µH/1.05m

10µF x 2

0.36µH/1.05m

10µF x 2



470µF/50V

22µF x 15

330µF/2V x 4

470µF/50V

1010

OUT

GND_SNS

OUT_SNS

0.1µF

STANDBY

2.2

STANDBY

5.1k

REF1

BOOT

RGND

PVCC

500k

1µF

RGND

TON

Optional

PGOOD

Enable

20k

RGND

REF2

18k

PSI

VID

2.7nF

RGND

REFADJ

Figure 1. 2 Active Phase Configuration

2.2µF

100k

0.1µF

RGND

TON

20k

REFADJ

REFIN

PVCC

TONV

PGOOD

PSI

VID

VREF

REFADJ

REFIN

RT8820A

UGATE1

PHASE1

LGATE1

OCSET/SS

UGATE2

PHASE2

LGATE2

GND

21 (Exposed pad)

BOOT1

RGND

VSNS

BOOT2

C NC

0.1µF

OCSET

Floating

10µF x 2

0.36µH/1.05m

470µF/50V



22µF x 15

330µF/2V x 4

1010

OUT

GND_SNS

OUT_SNS

Figure 2. 1 Active Phase Configuration

DS8820A-01 February 2020www.richtek.com

Typical Operating Characteristics

)

RT8820A

Effic iency vs. Load Current

VIN = 5V

Efficiency (%)

VIN = 19V

0.01 0.1 1 10 100

VIN = 12V

= 1.2V, V

PSI

OUT

= 1V

Load Current (A)

Current Limit Setting Current vs. Temperature

Current Limit Setting Current (μA

-50 -25 0 25 50 75 100 125

Temperature (°C)

= 5V, No load

PVCC

Inductor Valley Current vs. Load Current

PVCC

= 5V

Inductor Valley Current (A

-5 0 102030405060

VIN = 19V, V

Load Current (A)

Reference Voltage vs. Temperature

2.010

2.005

2.000

1.995

1.990

Reference Voltage (V)

1.985

= 5V, No load

1.980

-50 -25 0 25 50 75 100 125

Temperature (°C)

PVCC

(5V/Div)

OUT

Power On from EN

(5V/Div)

OUT

(1V/Div)

Power Off from EN

(1V/Div)

UGATE1

(20V/Div)

UGATE2

(20V/Div)

VIN = 12V, V

PVCC

= 5V, I

OUT

= 40A

Time (200μs/Div)

UGATE1

(20V/Div)

UGATE2

(20V/Div)

VIN = 12V, V

PVCC

Time (200μs/Div)

= 5V, I

OUT

= 40A

DS8820A-01 February 2020 www.richtek.com

RT8820A

PVCC

(5V/Div)

OUT

(1V/Div)

UGATE1

(20V/Div)

UGATE2

(20V/Div)

REFIN

(600mV/Div)

OUT

(600mV/Div)

UGATE1

(20V/Div)

Power On from PVCC

VIN = 12V, V

Time (1ms/Div)

PVCC

= 5V, I

OUT

= 40A

Dynamic Output Voltage Control

REFIN

OUT

PVCC

(5V/Div)

OUT

(1V/Div)

UGATE1 (20V/Div)

UGATE2

(20V/Div)

REFIN

(600mV/Div)

OUT

(600mV/Div)

UGATE1

(20V/Div)

Power Off from VCC

PVCC

VIN = 12V, V

PVCC

= 5V, I

OUT

Time (20ms/Div)

Dynamic Output Voltage Control

REFIN

OUT

= 40A

UGATE2

(20V/Div)

= 0.6V to 1.2V, I

REFIN

OUT

= 40A

Time (50μs/Div)

Load Transient Response

OUT

(40mV/Div)

OUT

(20A/Div)

UGATE1

(20V/Div)

UGATE2

(20V/Div)

VIN = 12V, V

OUT

= 1V

UGATE2

(20V/Div)

OUT

(40mV/Div)

OUT

(20A/Div)

UGATE1

(20V/Div)

UGATE2

(20V/Div)

= 1.2V to 0.6V, I

REFIN

OUT

= 40A

Time (50μs/Div)

Load Transient Response

VIN = 12V, V

OUT

= 1V

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RT8820A

OUT

(500mV/Div)

(10A/Div)

UGATE1 (20V/Div)

LGATE1 (5V/Div)

Current Limit and UVP

VIN = 12V, V

Time (100μs/Div)

PVCC

= 5V

SNS

(500mV/Div)

UGATE1

(20V/Div)

LGATE1 (5V/Div)

OVP

VIN = 12V, V

Time (100μs/Div)

PVCC

= 5V, No Load

DS8820A-01 February 2020 www.richtek.com

RT8820A



Application Information

The RT8820A is a dual-phase synchronous Buck PWM

controller with integrated drivers which is optimized for

high performance graphic microprocessor and computer

applications. A COT (Constant-On-Time) PWM controller

and two MOSFET drivers with internal bootstrap diodes

are integrated so that the external circuit can be easily

designed and the number of component is reduced.

The topology solves the poor load transient response timing

problems of fixed-frequency mode PWM and avoids the

problems caused by widely varying switching frequencies

in conventional constant on-time and constant off-time

PWM schemes. The IC supports dynamic mode transition

function with various operating states, which include single

phase with CCM, dual-phase with CCM, single phase with

diode emulation mode and dual-phase with diode emulation

mode operation. These different operating states make

the system efficiency as high as possible.

The RT8820A provides a PWM-VID dynamic control

operation in which the feedback voltage is regulated and

tracks external input reference voltage. It also features

complete fault protection functions including over voltage,

under voltage and current limit.

PWM Operation

The RT8820A integrates a Constant-On-Time (COT) PWM

controller, and the controller provides the PWM signal

which relies on the output ripple voltage comparing with

internal reference voltage as shown in Figure 4. Referring

to the function block diagram of TON Genx, the

synchronous UGATE driver is turned on at the beginning

of each cycle. After the internal one-shot timer expires,

the UGATE driver is turned off. The pulse width of this

one-shot is determined by the converter input voltage and

the output voltage to keep the frequency fairly constant

over the input voltage and output voltage range. Another

one-shot sets a minimum off-time.

OUT

PEAK

OUT

VALLEY

REF

Figure 4. Constant On-Time PWM Control

On-Time Control

Remote Sense

The RT8820A uses the remote sense path (VSNS and

RGND) to overcome voltage drops in the power lines by

sensing the voltage directly at the end of GPU. Normally,

to protect remote sense path disconnecting, there are

two resistors (R

) connecting between local sense path

Local

and remote sense path. That is, in application with remote

sense, the R

no need of remote sense, the R

is recommended to be 10Ω to 100Ω. If

Local

is recommended to

Local

be 0Ω.

BOOT

UGATE

PHASE

LGATE

RGND

VSNS

Local Sense Path

OUT

Local

+ R

Local

GPU

Remote Sense Path

Figure 3. Output Voltage Sensing

The on-time one-shot comparator has two inputs. One

input monitors the output voltage, while the other input

samples the input voltage and converts it to a current.

This input voltage proportional current is used to charge

an internal on-time capacitor. The on-time is the time

required for the voltage on this capacitor to charge from

zero volts to V

, thereby making the on-time of the high-

OUT

side switch directly proportional to output voltage and

inversely proportional to input voltage. The implementation

results in a nearly constant switching frequency without

the need for a clock generator.

2 V 3.2p



T = R

ON TON

OUT

V0.5





and then the switching frequency FS is :

F= V V T

SOUT INON

TON



is a resistor connected from the VIN to TON pin.

The recommended operation frequency range is from

250kHz to 750kHz.

DS8820A-01 February 2020www.richtek.com

RT8820A

Active Phase Circuit Setting

The RT8820A can be set for 2 phase or 1 phase operation

by hardware circuit. When set to 1 phase operation,

UGATE2, BOOT2, PHASE2, LGATE2 pins are floating,

and the voltage of PSI pin must be set to the 1 phase

operation threshold. Refer to Table 1 for detail.

Mode Selection

The RT8820A can operate into 2 phases with forced

CCM, 1 phase with forced CCM, 1 phase with DEM and

2 phases with DEM according to PSI voltage setting. If

PSI voltage is pulled below 0.4V, the controller operates

into 1 phase with DEM. In DEM operation, the RT8820A

automatically reduces the operation frequency at light

load condition for saving power loss. If PSI voltage is

pulled between 0.7V to 0.88V, the controller switches

operation into 1 phase with forced CCM. If PSI voltage

is pulled between 1.08V to 1.35V, the controller

switches operation into 2 phase with DEM. If PSI voltage

is pulled between 1.6V to 5.5V, the controller switches

operation into 2 phase with forced CCM. The operation

mode is summarized in Table 1. Moreover, the PSI pin

is valid after POR of VR.

Table 1

Operation Phase Number PSI Voltage Setting

1phase with DEM 0V to 0.4V

1phase with CCM 0.7V to 0.88V

2phase with DEM 1.08V to 1.35V

2phase with CCM 1.6V to 5.5V

Diode-Emulation Mode

In diode-emulation mode, the RT8820A automatically

reduces switching frequency at light-load condition to

maintain high efficiency. As the output current decreases

from heavy-load condition, the inductor current is also

reduced, and eventually comes to the point that its valley

touches zero current, which is the boundary between

continuous conduction and discontinuous conduction

modes. By emulating the behavior of diodes, the low side

MOSFET allows only partial of negative current when the

inductor freewheeling current reaches negative value. As

the load current is further decreased, it takes a longer

time to discharge the output capacitor to the level that

requires the next “ON” cycle. In reverse, when the output

current increases from light load to heavy load, the

switching frequency increases to the preset value as the

inductor current reaches the continuous conduction

condition. The transition load point to the light load

operation is shown in Figure 5 and can be calculated as

follows:

(V V )



LOAD(SKIP) ON

IN OUT



where tON is on-time.

Slope = (V

- V

OUT

) / L

PEAK

LOAD

= I

PEAK/2

Figure 5. Boundary Condition of CCM/DEM

The switching waveforms may be noisy and asynchronous

in light loading diode-emulation operation condition, but

this is a normal operating condition that results in high

light-load efficiency. Trade-off in DEM noise vs. light-load

efficiency is made by varying the inductor value. Generally,

low inductor values produce a broad high efficiency range

vs. load curve, while higher values result in higher full load

efficiency (assuming that the coil resistance remains fixed)

and less output voltage ripple. The disadvantages for using

higher inductor values include larger physical size and

degraded load-transient response (especially at low input

voltage levels).

Forced-CCM Mode

The low noise, forced-CCM mode disables the zero-

crossing comparator, which controls the low-side switch

on-time. This causes the low-side gate drive waveform to

be the complement of the high-side gate drive waveform.

This in turn causes the inductor current to reverse at light

loads as the PWM loop to maintain a duty ratio V

OUT/VIN

The benefit of forced-CCM mode is to keep the switching

frequency fairly constant.

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RT8820A

Enable and Disable

The EN pin is a high impedance input that allows power

sequencing between the controller bias voltage and

another voltage rail. The RT8820A remains in shutdown if

the EN pin is lower than 550mV. When the EN voltage

rises above the 1.2V high level threshold, the RT8820A

begins a new initialization and soft-start cycle.

Power On Reset (POR), UVLO

Power On Reset (POR) occurs when V

rises above

PVCC

approximately 4.1V (typical), the RT8820A resets the fault

latch circuit and prepare for PWM operation. When the

is lower than 3.8V (typical), the Under Voltage

PVCC

Lockout (UVLO) circuitry inhibits switching by keeping

UGATE and LGATE low.

Soft-Start

The RT8820A provides internal soft-start function and

external soft-start function. The soft-start function is used

to prevent large inrush current and output voltage overshoot

while the converter is being powered up. The soft-start

function automatically begins once the chip is enabled.

There is a delay time around 200us from EN goes high to

begins to ramp-up.

OUT

If external capacitor from OCSET/SS pin to GND is

removed, the internal soft-start function is chosen. An

internal current source charges the internal soft-start

capacitor so that the internal soft-start voltage ramps

up linearly. The output voltage will track the internal

soft-start voltage during the soft-start interval. After the

internal soft- start voltage exceeds the REFIN voltage,

the output voltage no longer tracks the internal soft-

start voltage but follows the REFIN voltage. Therefore,

the duty cycle of the UGATE signal as well as the input

current at power up are limited.

The soft-start process is finished when the internal SSOK

goes high and protection is not triggered. Figure 6 shows

the internal soft-start sequence.

PVCC

VOUT

VREFIN

Internal SS

Internal SSOK

UGATE

LGATE

PGOOD

Enable

delay time

NormalSoft-start

Soft

Discharged

Figure 6. Internal Soft-Start Sequence

The RT8820A also provides external soft-start function,

and the external soft-start sequence is shown in Figure

7, connecting an additional capacitor from OCSET/SS pin

to GND. The external capacitor is charged by internal

current source to build soft-start voltage ramp. If external

soft-start function is chosen, the external soft-start time

should be set longer than internal soft-start time to avoid

output voltage tracking the internal soft-start ramp. The

external soft-start time setting is shown in Figure 8 and

the recommended external soft-start slew rate is from

0.1V/ms to 0.4V/ms.

PVCC

VOUT

120% VREFIN

External SS

External SSOK

UGATE

LGATE

PGOOD

Enable

delay time

Soft-start

Normal

Soft

Discharged

Figure 7. External Soft-Start Sequence

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RT8820A

The soft-start time can be calculated as:



t= (C R ) 1

 

SS SS OCSET

where ISS = 50μA (typ.), V

pin, R

is the current limit setting resistor, and CSS is

OCSET

 

REFIN



REFIN





SS OCSET



is the voltage of REFIN

the external capacitor placed from OCSET/SS pin to GND.

VCC

OCSET/SS

OCSET

OUT

REFIN

Figure 8. External Soft-Start Time Setting

Power Good Output (PGOOD)

The PGOOD pin is an open-drain output, and it requires

a pull-up resistor. During soft-start, the PGOOD is held

low and is allowed to be pulled high after V

OUT

goes

over UVP threshold and under OVP threshold. In

addition, if any protection is triggered during operation,

the PGOOD is pulled low immediately.

PWM VID and Dynamic Output Voltage Control

The RT8820A features a PWM VID input for dynamic

output voltage control as shown in Figure 9, which

reduces the number of device pin and enables a wide

dynamic voltage range. The output voltage is determined

by the applied voltage on the REFIN pin. The PWM duty

cycle determines the variable output voltage at REFIN.

With the external circuit and VID control signal, the

controller provides three operation modes shown as

Figure 10.

VREF

BOOT

MODE

REFIN

PWM VID

STANDBY

CONTROL

NORMAL

MODE

BOOT

MODE

STANDBY

MODE

Figure 10. PWM VID Time Diagram

Boot Mode

VID is not driven, and the buffer output is tri-state. At this

time, turn off the switch Q1 and connect a resistor divider

as shown in Figure 9 that can set the REFIN voltage to be

as the following equation :

BOOT



V = V

BOOT VREF

where V

VREF

Choose R

and R

BOOT



REF1 BOOT

BOOT REF1

RVV



RVV







RRR

REF1 REF2 BOOT



= 2V (typ.)

to be approximately 10kΩ, and the R

REF2

can be calculated by the following equations :

RVV

REF2 VREF BOOT





REF2 VREF BOOT

BOOT





REF2 VREF BOOT

BOOT

REF2



REF1





BOOT

STANDBY

Standby

Mode Control

RGND

REF1

BOOT

REF2

PWM IN

RGND

REFADJ

VID

VREF

REFADJ

Buffer

RGND

REFIN

Standby Mode

An external control can provide a very low voltage to

meet V

operating in standby mode. If the VID pin is

OUT

floating and switch Q1 is enabled as shown in Figure 9,

the REFIN pin can be set for standby voltage according

to the calculation below :

V = V

STANDBY VREF

R// R

By choosing R



R R (R // R )

REF1 BOOT REF2 STANDBY

, R

REF1

REF2 STANDBY



REF2

, and R

BOOT

, the R

STANDBY

can

be calculated by the following equation :

Figure 9. PWM VID Analog Circuit Diagram

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RT8820A

R =

STANDBY

RRR V

RV V RRR

  

REF2 VREF STANDBY REF1 REF2 BOOT

Normal Mode

If the VID pin is driven by a PWM signal and switch Q1 is

disabled as shown in Figure 9, the V

from V

min

to V

PWM duty cycle and V

percent PWM duty cycle. The V

by the following equations :

V = V

min VREF

V = V



max VREF

By choosing R

calculated by the following equation :

 



REF2 REF1 BOOT STANDBY



can be adjusted

REFIN

, where V

max



REF2 BOOT

R // (R R )

REFADJ BOOT REF2

R R // (R R )





REF1 REFADJ BOOT REF2



(R // R ) R R

REF1 REFADJ BOOT REF2

, R

REF1

is the voltage at zero percent

min

is the voltage at one hundred

max

REF2

min

and V

can be set

max



REF2



REF2

, and R

BOOT

, the R

REFADJ

can be

min

N = 1

N = 2

REFIN

N = 1

N = 2

0.5

= N

max

x T

vid

N = N

max

VID Duty

VID Input

Figure 11. PWM VID Analog Output

VID Slew Rate Control

In the RT8820A, the V

slew rate is proportional to

REFIN

PWM VID duty, the rising time and falling time are the

same. In normal mode, the V

estimated by C

When choose C

REFADJ

or C

REFIN

slew rate SR can be

REFIN

as the following equation :



REFADJ

The relationship between VID duty and V

Figure 11, and V

REF1 min





max min

can be set according to the calculation

OUT

is shown in

REFIN

below :

V = V NV

OUT min STEP

where V

V =

STEP



is the resolution of each voltage step 1 :

STEP



(V V )

max min

max

where Nmax is the number of total available voltage

steps and N is the number of step at a specific V

The dynamic voltage VID period (T

= Tu x N

vid

max

OUT

) is

determined by the unit pulse width (Tu) and the available

step number (N

). The recommended Tu is 27ns.

max

(V V ) 80%

SR =

R = (R // R ) // (R +R )

REFIN_Final REFIN_initial



SR REF1 REFADJ BOOT REF2

When choose C

(V V ) 80%

SR =

R = R // R R // R

REFIN_Final REFIN_initial





SR REF1 REFADJ BOOT REF2



The recommended SR is estimated by C



2.2R C

SR REFADJ

REFIN



2.2R C

SR REFIN



REFADJ

Current Limit

The RT8820A provides cycle-by-cycle current limit

control by detecting the PHASE voltage drop across

the low-side MOSFET when it is turned on. The current

limit circuit employs a unique “valley” current sensing

algorithm as shown in Figure 12. If the magnitude of

the current sense signal at PHASE is above the current

limit threshold, the PWM is not allowed to initiate a

new cycle.

In order to provide both good accuracy and a cost

effective solution, the RT8820A supports temperature

compensated MOSFET R

DS(ON)

DS8820A-01 February 2020www.richtek.com

sensing.

RT8820A

L,PEAK

LOAD

L,VALLEY

Figure 12. “Valley” Current Limit

In an over-current condition, the current to the load exceeds

the average output inductor current. Thus, the output

voltage falls and eventually crosses the under-voltage

protection threshold, inducing IC shutdown.

Current Limit Setting

The RT8820A adopts per-phase current limiting protection.

The current limit threshold can be set by a resistor (R

OCSET

between OCSET/SS pin and GND. Once PVCC exceeds

the POR threshold and chip is enabled, an internal current

source I

OCSET

flows through R

OCSET

. The voltage across

OCSET

is stored as the current limit protection threshold

. The threshold range of V

is 30mV to 200mV.

OCSET

It can be calculated according to the following equation :

I x R

V =

OCSET

R =

OCSET

where I

limit current (valley inductor current) and I

OCSET OCSET

can be determined using the following equation :

I x R x 12

VALLEY DS_ON

OCSET

represents the desired per-phase inductor

VALLEY

is current

OCSET

limit setting current which has a temperature coefficient

to compensate the temperature dependency of the

SSOK), the I

. During soft-start period (EN is pulled high to

DS(ON)

is 50μA. Once soft-start finishes, the

OCSET

switches to 10μA.

OCSET

For ensuring the soft-start and current limit functions work

normally, below setting limitation must be followed.

If R

x 50μA > 1.2 x V

OCSET

is not present, there is no current path for I

OCSET

REFIN

OCSET

to build the current limit threshold. In this situation, the

current limit threshold is internally preset to 200mV.

Negative Current Limit

The RT8820A supports cycle-by-cycle negative current

limit. The absolute value of negative current limit

threshold is the same as the positive current limit

threshold. If negative inductor current is rising to trigger

negative current limit, the low-side MOSFET is turned

off and the current flows to input side through the body

diode of the high-side MOSFET. At this time, output

voltage tends to rise because this protection limits

current to discharge the output capacitor. In order to

prevent shutdown because of over-voltage protection,

the low-side MOSFET is turned on again 400ns after it

is turned off. If the device hits the negative current limit

threshold again before output voltage is discharged to

the target level, the low-side MOSFET is turned off and

process repeats. It ensures maximum allowable

)

discharge capability when output voltage continues to

rise. On the other hand, if the output is discharged to

the target level before negative current limit threshold

is reached, the low-side MOSFET is turned off, the high-

side MOSFET is then turned on, and the device keeps

normal operation.

Current Balance

The RT8820A implements current balance mechanism in

the current loop. The RT8820A senses per phase current

signal and compares it with the average current. If the

sensed current of any particular phase is higher than the

average current, the on-time of this phase is decreased.

The current balance accuracy is mainly related with on-

resistance of low-side MOSFET (R

practical application, using lower R

LG,DS(ON)

the current balance accuracy.

Output Over-V oltage Prote ction (OVP)

The output voltage can be continuously monitored for over-

voltage protection. If REFIN voltage is lower than 1.33V,

the over voltage threshold follows absolute over voltage

2V. If REFIN voltage is higher than 1.33V, the over voltage

threshold follows relative over voltage 1.5 x V

OVP is triggered, UGATE goes low and LGATE is forced

high. The RT8820A is latched once OVP is triggered and

). That is, in

will reduce

. When

REFIN

DS8820A-01 February 2020 www.richtek.com

RT8820A

can only be released by PVCC or EN power on reset. A

5μs delay is used in OVP detection circuit to prevent false

trigger.

Output Under-Voltage Protection (UVP)

The output voltage can be continuously monitored for under-

voltage protection. When the output voltage is less than

40% of its set voltage, under voltage protection is triggered

and then all UGATE and LGATE gate drivers are forced

low. There is a 3μs delay built in the UVP circuit to prevent

false transitions. During soft-start, the UVP blanking time

is equal to PGOOD blanking time.

MOSFET Gate Driver

The RT8820A integrates high current gate drivers for the

MOSFETs to obtain high efficiency power conversion in

synchronous Buck topology. A dead-time is used to prevent

the cross conduction for high-side and low-side MOSFETs.

Because both the two gate signals are off during the dead-

time, the inductor current freewheels through the body

diode of the low-side MOSFET. The freewheeling current

and the forward voltage of the body diode contribute power

losses to the converter. The RT8820A employs adaptive

dead time control scheme to ensure safe operation without

sacrificing efficiency. Furthermore, elaborate logic circuit

is implemented to prevent cross conduction. For high

output current applications, two power MOSFETs are

usually paralleled to reduce R

. The gate driver needs

DS(ON)

to provide more current to switch on/off these paralleled

MOSFETs. Gate driver with lower source/sink current

capability results in longer rising/falling time in gate signals

and higher switching loss. The RT8820A embeds high

current gate drivers to obtain high efficiency power

conversion.

MOSFET Selection

However, the small duty cycle means the low-side

MOSFET is on for most of the switching cycle. Therefore,

the conduction loss tends to dominate the total power

loss of the converter. To improve the overall efficiency, the

MOSFETs with low R

are preferred in the circuit

DS(ON)

design. In some cases, more than one MOSFET are

connected in parallel to further decrease the on-state

resistance. However, this depends on the low-side

MOSFET driver capability and the budget.

Inductor Selection

Inductor plays an importance role in step-down converters

because the energy from the input power rail is stored in

it and then released to the load. From the viewpoint of

efficiency, the DC Resistance (DCR) of inductor should

be as small as possible to minimize the copper loss. In

addition, the inductor occupies most of the board space

so the size of it is important. Low profile inductors can

save board space especially when the height is limited.

However, low DCR and low profile inductors are usually

not cost effective.

Additionally, higher inductance results in lower ripple

current, which means the lower power loss. However, the

inductor current rising time increases with inductance value.

This means the transient response will be slower. Therefore,

the inductor design is a trade-off between performance,

size and cost.

In general, inductance is designed to let the ripple current

ranges between 20% to 40% of full load current. The

inductance can be calculated using the following equation :

L =

min

IN OUT OUT



fkI V

SW OUT_rated IN





VV V

where k is the ratio between inductor ripple current and

rated output current.

The majority of power loss in the step-down power

conversion is due to the loss in the power MOSFETs. For

low voltage high current applications, the duty cycle of

the high-side MOSFET is small. Therefore, the switching

loss of the high-side MOSFET is of concern. Power

MOSFETs with lower total gate charge are preferred in

such kind of application.

Input Capacitor Selection

Voltage rating and current rating are the key parameters

in selecting input capacitor. Generally, input capacitor

voltage rating should be 1.5 times greater than the

maximum input voltage for a conservatively safe design.

The input capacitor is used to supply the input RMS

current, which can be approximately calculated using the

DS8820A-01 February 2020www.richtek.com

RT8820A

following equation :

I = I 1

RMS OUT





OUT OUT



IN IN



The next step is to select proper capacitor for RMS current

rating. Using more than one capacitor with low Equivalent

Series Resistance (ESR) in parallel to form a capacitor

bank is a good design. Besides, placing ceramic capacitor

close to the Drain of the high-side MOSFET is helpful in

reducing the input voltage ripple at heavy load.

Output Capacitor Selection

The output filter capacitor must have ESR low enough

to meet output ripple and load transient requirement,

yet have high enough ESR to satisfy stability

requirements. Also, the capacitance must be high

enough to absorb the inductor energy going from a full

load to no load condition without tripping the OVP

circuit. Organic semiconductor capacitor(s) or special

polymer capacitor(s) are recommended.

= (105°C − 25°C) / (30°C/W) = 2.67W for a

D(MAX)

WQFN-20L 3x3 package

The maximum power dissipation depends on the operating

ambient temperature for the fixed T

and the thermal

J(MAX)

resistance, θJA. The derating curves in Figure 13 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Maximum Power Dissipation (W) 1

0.0 0 102030405060708090100110

Ambient Temperature (°C)

Four-Layer PCB

Thermal Considerations

The junction temperature should never exceed the

absolute maximum junction temperature T

J(MAX)

, listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

where T

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

is the maximum junction temperature, TA is

the ambient temperature, and θJA is the junction-to-ambient

thermal resistance.

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 105°C. The junction-to-ambient thermal

resistance, θJA, is highly package dependent. For a

WQFN-20L 3x3 package, the thermal resistance, θJA, is

30°C/W on a standard JEDEC 51-7 high effective-thermal-

conductivity four-layer test board. The maximum power

dissipation at TA = 25°C can be calculated as below :

Figure 13. Derating Curve of Maximum Power

Dissipation

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RT8820A

Layout Considerations

Layout is very important in high frequency switching

converter design. If designed improperly, the PCB could

radiate excessive noise and contribute to the converter

instability. Following layout guidelines must be considered

before starting a layout for the RT8820A.

 Place the RC filter as close as possible to the PVCC

pin.

 Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high voltage switching node.

 Connections from the drivers to the respective gate of

the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance.

 All sensitive analog traces and components such as

VSNS, RGND, EN, PSI, VID, PGOOD, VREF, TON

REFADJ and REFIN should be placed away from high

voltage switching nodes such as PHASE, LGATE,

UGATE, or BOOT nodes to avoid coupling. Use internal

layer(s) as ground plane(s) and shield the feedback trace

from power traces and components.

 Power sections should connect directly to ground

plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed to minimize loops

and reduce losses.

DS8820A-01 February 2020www.richtek.com

Outline Dimension

RT8820A

1 2

DETAIL A

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010

D 2.900 3.100 0.114 0.122

D2 1.650 1.750 0.065 0.069

E 2.900 3.100 0.114 0.122

1 2

E2 1.650 1.750 0.065 0.069

e 0.400 0.016

L 0.350 0.450

0.014 0.018

W-Type 20L QFN 3x3 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8820A-01 February 2020 www.richtek.com

Richtek RT8820A Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual