Richtek RT8243AZQW, RT8243BZQW, RT8243CZQW Schematic

®

RT8243A/B/C

High Efficiency, Main Power Supply Controller for Notebook Computers

General Description

The RT8243A/B/C is a dual step down, Switch Mode Power

Supply (SMPS) controller which generates logic supply

voltages for battery powered systems. It includes two

Pulse Width Modulation (PWM) controllers adjustable

from 2V to 5.5V and also two fixed 5V/3.3V linear

regulators. One of the controllers (LDO5) provides

automatic switch over to the BYP1 input connected to

the main SMPS1 output for maximized efficiency. An

optional external charge pump can be monitored through

SECFB (RT8243B/C). Other features include on board

power up sequencing, a power good output, internal soft-

start, and a soft discharge output that prevents negative

voltage during shutdown.

A constant on-time PWM control scheme operates without

sense resistors and assures fast load transient response

while maintaining nearly constant switching frequency. To

eliminate noise in audio applications, an ultrasonic mode

is included, which maintains the switching frequency

above 25kHz. Moreover, a diode emulation mode

maximizes efficiency for light load applications. The

SMPS1/SMPS2 switching frequency can be adjustable

from 200kHz/233kHz to 400kHz/466kHz respectively.

The RT8243A/B/C is available in a WQFN-20L 3x3

package, and operates over an extended temperature range

from −40°C to 85°C.

Features



 5.5V to 25V Input Voltage Range



 2V to 5.5V Output Voltage Range



 No Current Sense Resistor Needed



 5V/3.3V Linear Regulators



 4700ppm/



 Internal Current Limit Soft-Start and Soft Discharge



°°

°C R

°°

Current Sensing

DS(ON)

Output



 Built In OVP/UVP/OCP



 Selectable Operation Mode with Switcher Enable



Control (RT8243A)



 SECFB Input Maintains Charge Pump Voltage



(RT8243B/C)



 Power Good Indicator (RT8243B/C includes SECFB)



 RoHS Compliant and Halogen Free



Applications

 Notebook computers

 System Power Supplies

 3- and 4- Cell Li+ Battery-Powered Device

Ordering Information

RT8243A/B/C

Package Type QW : WQFN-20L 3x3 (W-Type)

Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free)

Pin Function With A : ENM B : SECFB C : SECFB, Ultrasonic Mode

Note :

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

©

DS8243A/B/C-07 November 2014 www.richtek.com

1

RT8243A/B/C

Pin Configurations

BYP1

BOOT1

1

FB1

TON

FB2

2

3

GND

4

ENTRIP1

ENTRIP2

UGATE1

(TOP VIEW)

LGATE1

17181920

16

15

LDO3

14

LDO5

13

ENM

12

21

9876

ENLDO

115

VIN

10

FB1

ENTRIP1

TON

ENTRIP2

FB2

BYP1

BOOT1

PHASE1

UGATE1

LGATE1

17181920

16

1

2

3

GND

4

15

LDO3

14

LDO5

13

SECFB

12

21

9876

ENLDO

115

VIN

10

BOOT2

PGOOD

UGATE2

Marking Information

RT8243AZQW

8A : Product Code

8A YM

DNN

RT8243CZQW

0B YM

DNN

YMDNN : Date Code

0B : Product Code

YMDNN : Date Code

LGATE2

PHASE2 PHASE1

WQFN-20L 3x3

RT8243BZQW

7A YM

DNN

BOOT2

PGOOD

PHASE2

UGATE2

RT8243B/CRT8243A

7A : Product Code

YMDNN : Date Code

LGATE2

©

DS8243A/B/C-07 November 2014www.richtek.com

2

Typical Application Circuit

V

I

5

.

V

T

O

U

1

5

V

N

V

o

t

2

5

V

1

C

1

0

µ

F

N1

1

L

+

3

C

5

C

l

a

n

t

i

p

o

O

3

R

k

5

1

4

R 1

k

0

N2

Chip Enable

R

2

C

µ

.

1

0

2

R

4

C

.

1

0

R

TON

21 (Exposed Pad)

RT8243A/B/C

RT8243A

BOOT2

FB2

LDO3

LDO5

8

7

9

10

5

4

2

15

14

6

N3

R

5

C

7

0

1

.

µ

F

N4

8

R

k

0

1

9

R

k

0

1

C

9

4

7

.

µ

F

C

0

1

R

k

0

1

4

7

.

11

VIN

12

F

µ

18

19

17

16

1

3

20

13

ENLDO

UGATE1

BOOT1

PHASE1

LGATE1

FB1

TON

BYP1

ENM

GND

UGATE2

PHASE2

LGATE2

ENTRIP2

ENTRIP1

PGOOD

C

6

1

0

F

µ

L

2

R

6

5

.

k

7

R

k

0

1

l

A

w

V

.

3

l

a

w

V

A

5 0 µ

F

V

O

U

T

+

C

8

O

s

y

a

n

s

y

O

2

3

.

3

V

n

Figure 1. RT8243A NB Main Supply Typical Application Circuit

©

DS8243A/B/C-07 November 2014 www.richtek.com

3

RT8243A/B/C

V

I

5

.

5

V

U

O

T

1

V

5

C

a

t

n

i

o

p

O

N

V

o

t

2

5

V

C

1

0

µ

F

N1

1

L

+

3

C

5

l

3

1

C

0

µ

1

.

1

C

1

0

.

µ

N2

3

R

k

5

1

4

R

k

0

1

F

4

F

C

V

CP

Figure 2. RT8243B/C NB Main Supply Typical Application Circuit

1

R

11

2

C

.

1

0

12

F

µ

18

2

R

4

C

.

0

19

F

µ

1

17

16

1

R

TON

3

20

1

C

0

1

.

F

µ

2

1

C

0

1

.

µ

F

1

R

2

0

k

5

1

13

2

1

R

9

k

3

VIN

ENLDO

UGATE1

BOOT1

PHASE1

LGATE1

FB1

TON

BYP1

SECFB

RT8243B/C

ENTRIP2

ENTRIP1

UGATE2

BOOT2

PHASE2

LGATE2

FB2

LDO3

LDO5

PGOOD

GND

8

R

7

9

5

C 0

10

5

4

2

15

C

9

4

7

.

µ

14

0

1

R

k

0

6

1

21 (Exposed Pad)

C

6

1

0

µ

N3

7

1

.

µ

F

L

N4

8

R

k

0

1

9

R

k

0

1

F

2

R

6

5

.

k

7

R

k

0

1

V

O

U

T

+

C

8

2

3

.

V

On

Off

n

O

s

y

a

l

w

A

V

.

3

F

n

s

O

y

l

a

w

V

A

C 4

5

1

0

7

.

µ

F

©

DS8243A/B/C-07 November 2014www.richtek.com

4

Functional Pin Description

Pin No. Pin Name Pin Function

RT8243A/B/C

1 FB1

2 ENTRIP1

3 TON ON-Time/Frequency Adjustment Input. Connect to GND with 56k to 100k.

4 ENTRIP2

5 FB2

6 PGOOD

7 BOOT2

8 UGATE2

9 PHASE2

SMPS1 Feedback Input. Connect FB1 to a resistive voltage divider from SMPS1 output to GND for adjustable output from 2V to 5.5V.

Channel 1 Enable and Current Limit Setting Input. Connect resistor to GND to set the threshold for Channel 1 synchronous R cur rent limit threshold is 1/10th the voltage seen at ENTRIP1 over a 0.5V to 3V range. There is an internal 10A current source from LD O5 to ENT RIP1. Leave ENTRIP1 floating or drive it above 4.5V to shut down channel 1.

Channel 2 Enable and Current Limit Setting Input. Connect resistor to GND to set the threshold for Channel 2 synchronous R cur rent limit threshold is 1/10th the voltage seen at ENTRIP2 over a 0.5V to 3V range. There is an internal 10A current source from LD O5 to ENT RIP2. Leave ENTRIP2 floating or drive it above 4.5V to shut down channel 2.

SMPS2 Feedback Input. Connect FB2 to a resistive voltage divider from SMPS2 output to GND for adjustable output from 2V to 5.5V.

Power Good Output for Channel 1 and Channel 2 (RT8243A).

Power Good Output for Channel 1, Channel 2 and SECFB (RT8243B/C).

Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the typical application circuits.

Upper Gate Driver Output for SMPS2. UGATE2 swings between PHASE2 and BOOT2.

Switch Node for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high side gate driver. PHASE2 is also the current sense input for the SMPS2.

sense. The GND-PHASE1

DS(ON)

sense. The GND-PHASE2

DS(ON)

10 LGATE2 Lower Gate Drive Output for SMSP2. LGATE2 swings between GND and LDO5.

11 VIN Supply Input for LDO5.

Master Enable Input. LDO5/LDO3 is enabled if it is within logic high level and

12 ENLDO

ENM (RT8243A)

13

14 LDO5

15 LDO3

SECFB (RT8243B/C)

disabled if it is less than the logic low level. Leave ENLDO floating to default enable LDO5/LDO3.

Mode Selection with Enable Input. Pull up to LDO5 (Ultrasonic mode) or LDO3 (DEM) to turn on both switch Channels. Short to GND for shutdown.

Change Pump Feedback Pin. The SECFB is used to monitor the optional external charge pump. Connect a resistive divider from the change pump output to GND to detect the output. If SECFB drops below its feedback threshold, an ultrasonic pulse occurs to refresh the charge pump driven by LGATE1 or LGATE2. If SECFB drops below its UV threshold, the switcher channels stop working and enter into discharge-mode. Pull up to LDO5 or LDO3 to disable SECFB UVP function.

5V Linear Regulator Output. LDO5 is the supply voltage for the low side MOSFET driver and also the analog supply voltage for the device. Bypass a minimum 4.7F ceramic capacitor to GND

3.3V Linear Regulator Output. Bypass a minimum 4.7F ceramic capacitor to GND.

DS8243A/B/C-07 November 2014 www.richtek.com

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5

RT8243A/B/C

Pin No. Pin Name Pin Function

16 LGATE1

17 PHASE1

18 UGATE1

19 BOOT1

20 BYP1 Switch Over Source Voltage Input for LDO5.

21 (Exposed Pad) GND

Function Block Diagram

BOOT1

UGATE1

PHASE1

LGATE1

FB1

ENTRIP1

TON

BYP1

LDO5

10µA

Switch Over Threshold

+

-

Lower Gate Driver Output for SMPS1. LGATE1 swings between GND and LDO5.

Switch Node SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high side gate driver. PHASE1 is also the current sense input for the SMPS1.

Upper Gate Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT 1.

Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the typical application circuits.

Analog Ground and Power Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

BOOT2

UGATE2

PHASE2

LGATE2

FB2 ENTRIP2

ENM (RT8243A) SECFB (RT8243B/C)

PGOOD

SMPS1

PWM

Buck

Controller

On Time

SMPS2

PWM

Buck

Controller

LDO5

10µA

GND

LDO5

VIN

ENLDO

©

Power On

Sequence

Clear Fault Latch

REF

LDO3

DS8243A/B/C-07 November 2014www.richtek.com

6

RT8243A/B/C

Absolute Maximum Ratings (Note 1)

 VIN, ENLDO to GND ------------------------------------------------------------------------------------------------------ −0.3V to 30V

 BOOTx to PHASEx

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −2.5V to 6.3V

 ENTRIPx, FBx, TON, BYP1, PGOOD, LDO5, LDO3, ENM/SECFB to GND ------------------------------- −0.3V to 6V

 PHASEx to GND

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 30V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −8V to 38V

 UGATEx to PHASEx

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −5V to 7.5V

 LGATEx to GND

DC----------------------------------------------------------------------------------------------------------------------------- −0.3V to 6V

< 20ns ----------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

 Power Dissipation, P

WQFN-20L 3x3 ------------------------------------------------------------------------------------------------------------ 3.33W

 Package Thermal Resistance (Note 2)

WQFN-20L 3x3, θJA------------------------------------------------------------------------------------------------------- 30°C/W

WQFN-20L 3x3, θJC------------------------------------------------------------------------------------------------------ 7.5°C/W

 Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C

 Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C

 Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Model)---------------------------------------------------------------------------------------------- 2kV

@ TA = 25°C

D

Recommended Operating Conditions (Note 4)

 Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- 5.5V to 25V

 Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C

 Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C

DS8243A/B/C-07 November 2014 www.richtek.com

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7

RT8243A/B/C

Electrical Characteristics

(VIN = 12V, V

Parameter Symbol Test Conditions Min Typ Max Unit

Input Supply

VIN Power On Reset

ENLDO

= 5V, V

ENTRIPx

= 2V, V

= 5V, No Load on LDO5, LDO3, T

BYP1

= 25°C, unless otherwise specified)

A

Rising Threshold -- 5.1 5.5

Falling Threshold 3.5 -- 4.5

V

VIN Shutdown Current

VIN Standby Supply Current

Quiescent Power Consumption

I

VIN_SHDN

I

VIN_SBY

I

Q

SMPS Output and FB Voltage

FBx Regulation Voltage

Output Voltage Adjustable Range

SECFB Voltage

V

FBx

SMPS1, SMPS2 2 -- 5.5

SECFB

V

On Time

ON-Time Pulse Width

Minimum Off-Time

Frequency Range

Ultrasonic Mode Frequency

t

UGATEx

t

LGATEx

f

SMPS1

f

SMPS2

f

ASM

V

RT8243C, V

Soft-Start

Soft-Start Time

t

SSx

Current Sense

Current Limit Current Source

Temperature Coefficient of I

ENTRIPx

Current Limit Adjustment Range

Current Limit Threshold

Zero-Current Threshold

I

ENTRIPx

V

ENTRIPx

V

ZC

Internal Regulator and Reference

LDO5 Output Voltage

V

LDO5

V

ENLDO

= GND

-- 20 40

A

Both SMPS Off -- 250 350

Both SMPSs on, FBx = 2.1V, BYP1 = 5V, ENM = 3.3V (RT8243A)

-- 5 7 mW

FBx, CCM Operation -- 2 --

V

FBx, DEM Operation 1.98 2.006 2.03

V

RT8243B 1.92 2 2.08

V R

IN

TON

FBx

= 20V

= 56k

= 1.8V

V

PHASE1

V

PHASE2

= 2V

SMPS1 Operating Frequency 200 -- 400

SMPS2 Operating Frequency 233 -- 466

PHASEx

= 50mV

Zero to 200mV Current Limit Threshold from ENTRIPx Enable

V

ENTRIPx

= 0.9V

On The Basis of 25C

V

ENTRIPx

= I

ENTRIPx

GND  PHASEx, V

x R

ENTRIPx

= 2V

GND  PHASEx, FBx = 2.1V

= 0V, I

V

BYP1

V

= 0V, I

BYP1

6.5V < V V

= 0V, I

BYP1

5.5V < V

< 25V

IN

< 25V

IN

LDO5

< 100mA

< 100mA ,

< 50mA,

-- 256 --

-- 220 --

ns

-- -- 400 ns

kHz

25 -- -- kHz

-- 2 -- ms

9.4 10 10.6

-- 4700 --

A

ppm/C

0.5 -- 2.7 V

180 200 225 mV

-- 3 -- mV

4.9 5 5.1

4.75 -- 5.25 V

4.75 -- 5.25

8

©

DS8243A/B/C-07 November 2014www.richtek.com

Parameter Symbol Test Conditions Min Typ Max Unit

LDO5 Output Current I

5V Switchover Threshold V

5V Switch R

R

DS(ON)

LDO3 Output Voltage V

LDO3 Output Current I

UVLO

LDO5 UVLO Threshold V

LDO3 UVLO Threshold V

Power Good

PGOOD Threshold V

PGOOD Propagation Delay

PGOOD Leakage Current I PGOOD Output Low

Voltage SECFB Power Good Threshold

Fault Detection

Over Voltage Protection Trip Threshold Over Voltage Protection Propagation Delay

Under Voltage Protection Trip Threshold

Under Voltage Protection Shutdown Blanking Time

Thermal Shutdown

RT8243A/B/C

SHORT5

SHORT3

t

PD_PGOOD

LK_PGOOD

V

t

DLY_OVP

V

t

SSHx

V

BYP1TH

BYPSW

LDO3

V

UVLO5

Both SMPS Off 1.9 2.2 2.5

UVLO3

PGOOD

Falling Edge -- 5 -- s

High State, Forced to 5.5V -- -- 1 A

SINK_PGOOD ISINK

SFB_PGOOD

OVP Detect, FBx Rising Edge 108 112 116 %

OVP

Rising Edge -- 5 -- s

UVP Detect, FBx Falling Edge. 53 58 63 %

UVP

SFB_UVP

UVP Detect, SECFB Falling Edge. 0.8 -- 1.2 V

From ENTRIPx or ENM Enable -- 5 -- ms

= 0V, V

BYP1

Falling Edge, Rising Edge with FB1 Regulation Point

= 5V, I

BYP1

= 0V, I

V

BYP1

V

= 5V, I

BYP1

= 0V, V

BYP1

= 4.5V 150 225 300 mA

LDO5

4.53 4.66 4.79 V

= 50mA -- 1.5 3 

LDO5

< 100mA 3.234 3.3 3.366

LDO3

< 100mA 3.2 3.3 3.46

LDO3

= 2.9V 80 150 260 mA

LDO3

Rising Edge -- 4.35 4.5

Falling Edge 3.9 4.05 4.2

PGOOD Detect, Rising edge with soft-start delay time. Hysteresis = 2.5%

14 10 6 %

= 4mA -- -- 0.4 V

SECFB with Respect to 2V (RT8243B/C)

40 50 60 %

V

Thermal Shutdown TSD -- 150 -- °C

Thermal Shutdown Hysteresis

T

-- 10 -- °C

SD

Logic Input

ENTRIPx Input Voltage V

ENTRIPx

Clear Fault Level/SMPSx Off Level 4.5 -- -- V

Rising Edge Threshold 1.2 1.6 2

ENLDO Input Voltage V

ENLDO

Falling Edge Threshold 0.9 0.95 1 When ENLDO is Floating (Default

Enable)

2.1 -- --

V

Clear Fault Level/SMPSs Off Level -- -- 0.8

ENM Input Voltage (RT8243A)

V

ENM

SMPSs On, DEM Operation 2.3 -- 3.6

V

SMPSs On, Ultrasonic Mode Operation 4.5 -- --

DS8243A/B/C-07 November 2014 www.richtek.com

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9

RT8243A/B/C

Parameter Symbol Test Conditions Min Typ Max Unit

I

Input Leakage Current

V

FBx

I

P13

I

ENLDO = 0V or 5V 1 -- 3

EN LDO

= 0V or 5V 1

FBx

ENM/SECFB = 0V or 5V

1

Internal BOOT Switch

Internal Boost Charging Switch On-Resistance

R

BOOTx

LDO5 to BOOTx, 10mA -- -- 90

Power M OSFET Drivers

R

UGATEx On-Resistance

LGATEx On-Resistance

Dead Time

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.

is measured at T

JA

measured at the exposed pad of the package.

UGATEs r

R

UGATEs k

R

LGAT Esr

R

LGAT Esk

t

LGATERx

t

UGATERx

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

A

Source, V

Sink, V

UGATEx

Source, V

Sink, V

LGATEx

BOO Tx

LDO5

= 0.1V

 V

UGATEx

PHASEx

LGATEx

= 0.1V

UGATEx Off to LGATEx On -- 30 --

LGATEx Off to UGATEx On -- 40 --

-- 5 8

-- 2 4

-- 5 8

-- 1.5 3

-- 1

A



ns

10

©

DS8243A/B/C-07 November 2014www.richtek.com

Typical Operating Characteristics

V

Efficiency vs. Load Current

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

OUT1

DEM

ASM

VIN = 8V, R V

ENTRIP2

= 100kΩ, V

TON

= 5V, ENLDO = 5V

Load Current (A)

V

Efficiency vs. Load Current

OUT1

DEM

ASM

VIN = 20V, R V

ENTRIP2

= 100kΩ, V

TON

= 5V, ENLDO = 5V

Load Current (A)

ENTRIP1

= 1.5V

RT8243A/B/C

V

Efficiency vs. Load Current

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

OUT1

DEM

ASM

VIN = 12V, R V

ENTRIP2

= 100kΩ, V

TON

= 5V, ENLDO = 5V

Load Current (A)

V

Efficiency vs. Load Current

OUT2

DEM

ASM

VIN = 8V, R V

ENTRIP2

= 100kΩ, V

TON

= 1.5V, ENLDO = 5V

Load Current (A)

ENTRIP1

= 1.5V

= 5V,

V

Efficiency vs. Load Current

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0.001 0.01 0.1 1 10

OUT2

VIN = 12V, R V

= 1.5V, ENLDO = 5V

ENTRIP2

DEM

ASM

= 100kΩ, V

TON

ENTRIP1

100

Efficiency (%)

= 5V,

Load Current (A)

©

V

Efficiency vs. Load Current

OUT2

90

80

70

60

50

40

30

20

10

0

0.001 0.01 0.1 1 10

VIN = 20V, R V

ENTRIP2

DEM

ASM

= 100kΩ, V

TON

= 1.5V, ENLDO = 5V

ENTRIP1

= 5V,

Load Current (A)

DS8243A/B/C-07 November 2014 www.richtek.com

11

RT8243A/B/C

V

Switching Frequency v s. Load Current

OUT1

240

VIN = 8V, R

220

ENLDO = VIN, V

200

V

ENTRIP2

180

160

140

120

100

80

60

40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

V

Switching Frequency v s . Loa d Current

OUT1

260

VIN = 20V, R

240

ENLDO = VIN, V

220

V

ENTRIP2

200

180 160

140

120

100

80

60

40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

= 100kΩ,

TON

ENTRIP1

= 5V

Load Current (A)

= 100kΩ,

TON

ENTRIP1

= 5V

Load Current (A)

= 1.5V,

ASM

DEM

= 1.5V,

ASM

DEM

V

Switching Frequency vs. Load Current

OUT1

260

VIN = 12V, R

240

ENLDO = VIN, V

220

V

ENTRIP2

200

180 160

140

120

100

80

60

Switch Frequency (kHz) 1

40 20

0

0.001 0.01 0.1 1 10

= 5V

= 100kΩ,

TON

ENTRIP1

= 1.5V,

ASM

DEM

Load Current (A)

V

Switching Frequency v s . Loa d Current

OUT2

280

VIN = 8V, R

260

ENLDO = VIN, V

240

V

ENTRIP2

220 200 180 160 140 120 100

80 60 40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

TON

= 1.5V

= 100kΩ,

ENTRIP1

= 5V,

ASM

DEM

Load Current (A)

V

Switching Frequency v s. Loa d Current

OUT2

300

VIN = 12V, R

280

ENLDO = VIN, V

260

V

ENTRIP2

240 220 200 180 160 140 120 100

80 60 40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

TON

= 1.5V

= 100kΩ,

ENTRIP1

= 5V,

ASM

DEM

Load Current (A)

©

V

Switching Frequency v s . Loa d Current

OUT2

300

VIN = 20V, R

280

ENLDO = VIN, V

260

V

ENTRIP2

240 220 200 180 160 140 120 100

80 60 40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

TON

= 1.5V

= 100kΩ,

= 5V,

ENTRIP1

ASM

DEM

Load Current (A)

DS8243A/B/C-07 November 2014www.richtek.com

12

5.034

)

V

Output Voltage vs. Load Current

OUT1

3.420

RT8243A/B/C

V

Output Voltage vs. Load Current

OUT2

5.031

5.028

5.025

5.022

5.019

Output Voltage (V)

5.016

5.013

5.010

0.001 0.01 0.1 1 10

VIN = 12V, R V

= 1.5V, V

ENTRIP1

ASM

DEM

= 100kΩ, ENLDO = VIN,

TON

ENTRIP2

= 5V

Load Current (A)

LDO5 Output Voltage vs. Output Current

5.072

5.068

5.064

5.060

5.056

Output Voltage (V)

5.052

5.048

VIN = 12V, V

0 102030405060708090100

ENTRIP1

= V

= 5V, ENLDO = VIN

ENTRIP2

Output Current (mA)

3.414

3.408

3.402

3.396

3.390

Output Voltage (V)

3.384

3.378

3.372

0.001 0.01 0.1 1 10

VIN = 12V, R V

ENTRIP1

ASM

DEM

= 100kΩ, ENLDO = VIN,

TON

= 5V, V

ENTRIP2

= 1.5V

Load Current (A)

LDO3 Output Volta ge vs. Output Current

3.354

3.352

3.350

3.348

3.346

3.344

3.342

3.340

Output Voltage (V)

3.338

3.336

3.334

VIN = 12V, V

0 102030405060708090100

ENTRIP1

= V

= 5V, ENLDO = VIN

ENTRIP2

Output Current (mA)

No Load Battery Current vs. Input Voltage

100

10

ASM

DEM

1

Battery Current (mA

R

= 100kΩ, V

TON

0.1 6 7 8 9 10111213141516171819202122232425

EVLDO = VIN

Input Voltage (V)

©

ENTRIP1

= V

ENTRIP2

=1.5V,

Standby Input Current vs. Input Voltage

240

238

236

234

232

230

228

Standby Input Current (μA) 1

226

V

= V

ENTRIP1

6 8 10 12 14 16 18 20 22 24 26

= 5V, ENLDO = VIN, No Load

ENTRIP2

Input Voltage (V)

DS8243A/B/C-07 November 2014 www.richtek.com

13

RT8243A/B/C

22

21

20

19

18

17

16

15

14

13

12

Shutdown Input Current (μA) 1

11

10

V

OUT1

(2V/Div)

V

OUT2

(2V/Div) PGOOD

(5V/Div)

Shutdown Input Current vs. Input Voltage

V

6 8 10 12 14 16 18 20 22 24 26

ENTRIP1

= V

= 5V, ENLDO = GND, No Load

ENTRIP2

Input Voltage (V)

Power On from ENM

RT8243A

LDO5

(2V/Div)

LDO3

(2V/Div)

CP

(10V/Div)

ENLDO

(10V/Div)

V

OUT1

(5V/Div)

V

OUT2

(5V/Div)

PGOOD (5V/Div)

RT8243A

Power On from ENLDO

VIN = 12V, V

ENLDO = VIN, R

Time (2ms/Div)

= V

ENTRIP1

= 100kΩ, No Load

TON

ENTRIP2

Power Off from ENM

VIN = 12V, V

= 5V, R

ENM

V

ENTRIP1

ENLDO = VIN, No Load

= V

TON

ENTRIP2

= 1.5V

= 100kΩ,

= 1.5V,

ENM

(5V/Div)

V

OUT1

(2V/Div)

PGOOD (5V/Div)

ENTRIP1

(5V/Div)

V

ENTRIP1

VIN = 12V, V

= V

ENTRIP2

= 1.5V, ENLDO = VIN, No Load

Time (1ms/Div)

Power On from ENTRIP1

RT8243B/C

VIN = 12V, V ENLDO = VIN, R

Time (1ms/Div)

= 5V, R

ENM

= V

ENTRIP1

= 100kΩ, No Load

TON

ENTRIP2

= 100kΩ

= 1.5V,

ENM

(5V/Div)

V

OUT1

(2V/Div)

PGOOD

(5V/Div)

ENTRIP1

(5V/Div)

Time (10ms/Div)

Power Off from ENTRIP1

RT8243B/C

VIN = 12V, V

ENLDO = VIN, R

Time (4ms/Div)

= V

ENTRIP1

= V

ENTRIP1

= 100kΩ, No Load

TON

= 100kΩ, No Load

TON

RT8243B/C

ENTRIP2

= 1.5V,

©

DS8243A/B/C-07 November 2014www.richtek.com

14

RT8243A/B/C

V

OUT2

(1V/Div)

PGOOD

(5V/Div)

ENTRIP2

(5V/Div)

V

OUT1

V

OUT1_AC

(50mV/Div)

UGATE1

(20V/Div)

Power On from ENTRIP2

RT8243B/C

VIN = 12V, V ENLDO = VIN, R

= V

ENTRIP1

= 100kΩ, No Load

TON

ENTRIP2

= 1.5V,

Time (1ms/Div)

DEM-MODE Load Transient Response

V

OUT2

(1V/Div)

PGOOD

(10V/Div)

ENTRIP2

(5V/Div)

V

OUT2

V

OUT2_AC

(50mV/Div)

UGATE2

(20V/Div)

Power Off from ENTRIP2

RT8243B/C

VIN = 12V, V ENLDO = VIN, R

= V

ENTRIP1

= 100kΩ, No Load

TON

ENTRIP2

= 1.5V,

Time (20ms/Div)

DEM-MODE Load Transient Response

LGATE1 (5V/Div)

Inductor

Current (5A/Div)

V

OUT1

(2V/Div)

PGOOD (5V/Div)

V

OUT2

(2V/Div)

VIN = 12V, R ENLDO = VIN, I

VIN = 12V, R

= 100kΩ,

TON

=1A to 8A

OUT1

Time (20μs/Div)

OVP

= 100kΩ, ENLDO = VIN, No Load

TON

Time (10ms/Div)

LGATE2

(5V/Div)

Inductor

Current (5A/Div)

V

OUT1

(2V/Div) PGOOD

(5V/Div)

UGATE1

(50V/Div)

LGATE1

(10V/Div)

VIN = 12V, R ENLDO = VIN, I

TON

Time (20μs/Div)

UVP

VIN = 12V, R

Time (100μs/Div)

TON

= 100kΩ,

=1A to 8A

OUT2

= 100kΩ, ENLDO = VIN

©

DS8243A/B/C-07 November 2014 www.richtek.com

15

RT8243A/B/C

Application Information

The RT8243A/B/C is a dual, Mach Response

TM

mode synchronous buck controller targeted for notebook

system power supply solutions. Richtek's Mach

ResponseTM technology provides fast response to load

steps. The topology circumvents the poor load transient

timing problems of fixed frequency current mode PWMs

while avoiding the problems caused by widely varying

switching frequency in conventional constant on-time and

constant off-time PWM schemes. A special adaptive on-

time control trades off the performance and efficiency over

wide input voltage range. The RT8243A/B/C includes 5V

(LDO5) and 3.3V (LDO3) linear regulators. The LDO5 linear

regulator steps down the battery voltage to supply both

internal circuitry and gate drivers. The synchronous switch

gate drivers are directly powered by LDO5. When V

rises above 4.66V, an automatic circuit disconnects the

linear regulator and allows the device to be powered by

V

via the BYP1 pin.

OUT1

PWM Operation

TM

The Mach ResponseTM DRV

mode controller relies on

the output filter capacitor's Effective Series Resistance

(ESR) to act as a current sense resistor, so that the output

ripple voltage provides the PWM ramp signal. Referring to

the RT8243A/B/C's Function Block Diagram, the

synchronous high side MOSFET will be turned on at the

beginning of each cycle. After the internal one-shot timer

expires, the MOSFET will be turned off. The pulse width

of this one-shot is determined by the converter's input

voltage and the output voltage to keep the frequency fairly

constant over the entire input voltage range. Another one-

shot sets a minimum off-time (400ns typ.). The on-time

one-shot will be triggered if the error comparator is high,

the low side switch current is below the current limit

threshold, and the minimum off-time one-shot has timed

out.

PWM Frequency and On-time Control

For each specific input voltage range, the Mach

ResponseTM control architecture runs with pseudo constant

frequency by feed forwarding the input and output voltage

into the on-time one-shot timer. The high side switch

DRV

TM

OUT1

on-time is inversely proportional to the input voltage as

measured by VIN and proportional to the output voltage.

There are two benefits of a constant switching frequency.

First, the frequency can be selected to avoid noise

sensitive regions such as the 455kHz IF band. Second,

the inductor ripple current operating point remains

relatively constant, resulting in easy design methodology

and predictable output voltage ripple. The frequency for

3V SMPS is set higher than the frequency for 5V SMPS.

This is done to prevent audio frequency “beating” between

the two sides, which switch asynchronously for each side.

The TON pin is connected to GND through the external

resistor, R

, to set the switching frequency.

TON

The RT8243A/B/C adaptively changes the operation

frequency according to the input voltage. Higher input

voltage usually comes from an external adapter, so the

RT8243A/B/C operates with higher frequency to have

better performance. Lower input voltage usually comes

from a battery, so the RT8243A/B/C operates with lower

switching frequency for lower switching losses. For a

specific input voltage range, the switching cycle period is

given by :

For 5.5V < V

tS1 = 61.28p x R

tS2 = 44.43p x R

For 6.5V < V

tS1 = 51.85p x R

tS2 = 44.43p x R

For 12V < V

tS1 = 45.75p x R

tS2 = 39.2p x R

< 6.5V :

IN

< 12V :

IN

< 25V :

IN

TON

The on-time guaranteed in the Electrical Characteristics

table is influenced by switching delays in the external

high side power MOSFET. Two external factors that

influence switching frequency accuracy are resistive drops

in the two conduction loops (including inductor and PC

board resistance) and the dead time effect. These effects

are the largest contributors to the change of frequency

with changing load current. The dead time effect increases

16

©

DS8243A/B/C-07 November 2014www.richtek.com

RT8243A/B/C

the effective on-time by reducing the switching frequency

as one or both dead times. It occurs only in PWM mode

when the inductor current reverses at light or negative

load currents. With reversed inductor current, the

inductor's EMF causes PHASEx to go high earlier than

normal, hence extending the on-time by a period equal to

the low to high dead time. For loads above the critical

conduction point, the actual switching frequency is :

f = (V V ) / (t x (V V V ))

where V



OUT DROP1 ON IN DROP1 DROP2

is the sum of the parasitic voltage drops in

DROP1

the inductor discharge path, including synchronous

rectifier, inductor, and PC board resistances; V

the sum of the resistances in the charging path; and t

DROP2

ON

is the on-time calculated by the RT8243A/B/C.

Operation Mode Selection

The RT8243A/B supports two operation modes : Diode

Emulation Mode and Ultrasonic Mode. The RT8243C only

supports Ultrasonic Mode. The operation mode can be

set via the ENM pin for RT8243A or SECFB pin for

RT8243B.

Table 1. Operation Mode Setting

Part Number RT8243A RT8243B RT8243C

Pin Name ENM SECFB SECFB

Pin-13

Voltage Range

Mode State

4.5V to 5V ASM ASM ASM

2.3V to 3.6V DEM DEM ASM

1.2V to 1.8V ASM ASM ASM

Below 0.8V Shutdown UVP UVP

Diode Emulation Mode

In Diode Emulation Mode, the RT8243A/B automatically

reduces switching frequency at light load conditions to

maintain high efficiency. This reduction of frequency is

achieved smoothly. As the output current decreases from

heavy-load condition, the inductor current is also reduced,

and eventually comes to the point that its current valley

touches zero, which is the boundary between continuous

conduction and discontinuous conduction modes. By

emulating the behavior of diodes, the low side MOSFET

allows only partial negative current to flow when the

inductor free wheeling current becomes negative. As the

load current is further decreased, it takes longer and longer

time to discharge the output capacitor to the level that

requires the next “ON” cycle. The on-time is kept the

same as that in the heavy load condition. In reverse, when

the output current increases from light load to heavy load,

the switching frequency increases to the preset value as

the inductor current reaches the continuous conduction.

The transition load point to the light load operation is shown

in Figure 3. and can be calculated as follows :

I

L

Slope = (VIN-V

OUT

)/L

I

PEAK

is

I

LOAD = IPEAK

0

t

ON

t

Figure 3. Boundary condition of CCM/DEM

(V V )



It

LOAD(SKIP) ON

IN OUT



2L

where tON is the on-time.

The switching waveforms may appear noisy and

asynchronous when light loading causes diode emulation

operation. This is normal and results in high efficiency.

Trade offs in PFM noise vs. light load efficiency is made

by varying the inductor value. Generally, low inductor values

produce a broader efficiency vs. load curve, while higher

values result in higher full load efficiency (assuming that

the coil resistance remains fixed) and less output voltage

ripple. Penalties for using higher inductor values include

larger physical size and degraded load transient response

(especially at low input voltage levels).

Ultrasonic Mode

The RT8243A/B/C activates a unique type of Diode

Emulation Mode with a minimum switching frequency of

25kHz, called Ultrasonic Mode. This mode eliminates

audio-frequency modulation that would otherwise be

present when a lightly loaded controller automatically

skips pulses. In Ultrasonic Mode, the low side switch gate

driver signal is “OR”ed with an internal oscillator

(>25kHz). Once the internal oscillator is triggered, the

ultrasonic controller pulls LGATEx high and turns on the

/2

DS8243A/B/C-07 November 2014 www.richtek.com

©

17

RT8243A/B/C

low side MOSFET to induce a negative inductor current.

After the output voltage falls below the reference voltage,

the controller turns off the low side MOSFET (LGATEx

pulled low) and triggers a constant on-time (UGATEx driven

high). When the on-time has expired, the controller re-

enables the low side MOSFET until the controller detects

that the inductor current dropped below the zero crossing

threshold.

Linear Regulators (LDOx)

The RT8243A/B/C includes 5V (LDO5) and 3.3V (LDO3)

linear regulators. The regulators can supply up to 100mA

for external loads. Bypass LDOx with a minimum 4.7μF

ceramic capacitor. When V

is higher than the switch

OUT1

over threshold (4.66V), an internal 1.5Ω P-MOSFET switch

connects BYP1 to the LDO5 pin while simultaneously

disconnects the internal linear regulator.

Current Limit Setting (ENTRIPx)

The RT8243A/B/C has cycle-by-cycle current limit control.

The current limit circuit employs a unique “valley” current

sensing algorithm. If the magnitude of the current sense

signal at PHASEx is above the current limit threshold,

the PWM is not allowed to initiate a new cycle (Figure 4).

The actual peak current is greater than the current limit

threshold by an amount equal to the inductor ripple current.

Therefore, the exact current limit characteristic and

maximum load capability are a function of the sense

resistance, inductor value, and battery and output voltage.

I

L

I

PEAK

I

LOAD

10μA (typ.) at room temperature. The current source has

a 4700ppm/°C temperature slope to compensate the

temperature dependency of the R

. When the voltage

DS(ON)

drop across the sense resistor or low side MOSFET

equals 1/10 the voltage across the R

resistor, positive

ILIM

current limit will be activated. The high side MOSFET will

not be turned on until the voltage drop across the MOSFET

falls below 1/10 the voltage across the R

resistor.

ILIM

Choose a current limit resistor according to the following

equation :

V

R

ILIM

= (R

= (I

x 10μA) / 10 = I

ILIM

x R

ILIM

DS(ON)

ILIM

) x 10 / 10μA

x R

DS(ON)

Carefully observe the PC board layout guidelines to ensure

that noise and DC errors do not corrupt the current sense

signal at PHASEx and GND. Mount or place the IC close

to the low side MOSFET.

Charge Pump (SECFB)

The external 14V charge pump is driven by LGATEx. When

LGATEx is low, C1 will be charged by V

C1 voltage is equal to V

minus the diode drop. When

OUT1

through D1.

OUT1

LGATEx becomes high, C1 transfers the charge to C2

through D2 and charges C2 voltage to V

LGATEX

plus C1

voltage. As LGATEx transitions low on the next cycle, C3

is charged to C2 voltage minus a diode drop through D3.

Finally, C3 charges C4 through D4 when LGATEx switches

high. Thus, the total charge pump voltage, VCP, is :

V

= V

CP

where V

+ 2 x V

OUT1

is the peak voltage of the LGATEx driver

LGATEx

− 4 x V

D

which is equal to LDO5 and VD is the forward voltage

dropped across the Schottky diode.

The SECFB pin in the RT8243B/C is used to monitor the

I

LIMIT

charge pump via a resistive voltage divider to generate

approximately 14V DC voltage and the clock driver uses

t

Figure 4. “Valley” Current Limit

The RT8243A/B/C uses the on resistance of the

synchronous rectifier as the current sense element and

supports temperature compensated MOSFET R

sensing. The R

resistor between the ENTRIPx pin and

ILIM

GND sets the current limit threshold. The resistor, R

DS(ON)

ILIM

is connected to a current source from ENTRIPx which is

18

©

V

as its power supply. In the event where SECFB

OUT1

drops below its feedback threshold, an ultrasonic pulse

will occur to refresh the charge pump driven by LGATEx.

If there's an overload on the charge pump in which SECFB

can not reach more than its feedback threshold, the

controller will enter Ultrasonic Mode. Special care should

be taken to ensure that enough normal ripple voltage is

,

present on each cycle to prevent charge pump shutdown.

DS8243A/B/C-07 November 2014www.richtek.com

RT8243A/B/C

The robustness of the charge pump can be increased by

reducing the charge pump decoupling capacitor and placing

a small ceramic capacitor, CF (47pF to 220pF), in parallel

with the upper leg of the SECFB resistor feedback network,

R

, as shown below in Figure 5.

CP1

SECFB

LGATE1

VOUT1

C1

D1 D2 D3C3D4

C2

C

F

R

CP1

C4

R

CP2

Charge Pump

Figure 5. Charge pump circuit connected to SECFB

MOSFET Gate Driver (UGATEx, LGA TEx)

The high side driver is designed to drive high current, low

R

N-MOSFET(s). When configured as a floating driver,

DS(ON)

5V bias voltage is delivered from the LDO5 supply. The

average drive current is also calculated by the gate charge

at VGS = 5V times switching frequency. The instantaneous

drive current is supplied by the flying capacitor between

BOOTx and PHASEx pins. A dead time to prevent shoot

through is internally generated from high side MOSFET

off to low side MOSFET on and low side MOSFET off to

high side MOSFET on.

The low side driver is designed to drive high current low

R

N-MOSFET(s). The internal pull down transistor

DS(ON)

that drives LGATEx low is robust, with a 1.5Ω typical on-

resistance. A 5V bias voltage is delivered from the LDO5

supply. The instantaneous drive current is supplied by an

input capacitor connected between LDO5 and GND.

For high current applications, some combinations of high

and low side MOSFETs may cause excessive gate drain

coupling, which leads to efficiency killing, EMI producing,

shoot through currents. This is often remedied by adding

a resistor in series with BOOTx, which increases the turn

on time of the high side MOSFET without degrading the

turn-off time. See Figure 6.

V

IN

UGATEx

BOOTx

PHASEx

R

BOOT

Soft-Start

The RT8243A/B/C provides an internal soft-start function

to prevent large inrush current and output voltage overshoot

when the converter starts up. The soft-start (SS)

automatically begins once the chip is enabled. During soft-

start, the internal current limit circuit gradually ramps up

the inductor current from zero. The maximum current limit

value is set externally as described in previous section.

The soft-start time is determined by the current limit level

and output capacitor value. The current limit threshold ramp

up time is typically 2ms from zero to 200mV after

ENTRIPx is enabled. A unique PWM duty limit control

that prevents output over voltage during soft-start period

is designed specifically for FBx floating.

UVLO Protection

The RT8243A/B/C has LDO5 under voltage lock out

protection (UVLO). When the LDO5 voltage is lower than

4.05V (typ.) and the LDO3 voltage is lower than 2.2V (typ.),

both switch power supplies are shut off. This is a non-

latch protection.

Power Good Output (PGOOD)

PGOOD is an open-drain type output and requires a pull

up resistor. PGOOD is actively held low in soft-start,

standby, and shutdown. It is released when both output

voltages are above 90% of the nominal regulation point

for RT8243A. For RT8243B/C, besides requiring both

output voltages to be above 90% of nominal regulation

point, the SECFB threshold must also be above 50% of

nominal regulation point in order for PGOOD to be released.

The PGOOD signal goes low if either output turns off or is

10% below its nominal regulation point.

Output Over Voltage Protection (OVP)

The output voltage can be continuously monitored for over

voltage. If the output voltage exceeds 12% of its set voltage

threshold, the over voltage protection is triggered and the

LGATEx low side gate drivers are forced high. This

activates the low side MOSFET switch, which rapidly

discharges the output capacitor and pulls the input voltage

downward.

Figure 6. Increasing the UGATEx Rise Time

DS8243A/B/C-07 November 2014 www.richtek.com

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19

RT8243A/B/C

The RT8243A/B/C is latched once OVP is triggered and

can only be released by either toggling ENLDO, ENTRIPx

or cycling VIN. There is a 5μs delay built into the over

voltage protection circuit to prevent false transition.

Note that latching LGATEx high will cause the output

voltage to dip slightly negative due to previously stored

energy in the LC tank circuit. For loads that cannot tolerate

a negative voltage, place a power Schottky diode across

the output to act as a reverse polarity clamp.

If the over voltage condition is caused by a short in high

side switch, turning the low side MOSFET on 100% will

create an electrical short between the battery and GND,

hence blowing the fuse and disconnecting the battery from

the output.

Output Under voltage Protection (UVP)

The output voltage can be continuously monitored for under

voltage. If the output is less than 58% of its set voltage

threshold, the under voltage protection will be triggered

and then both UGATEx and LGATEx gate drivers will be

forced low. The UVP is ignored for at least 5ms (typ.)

after a start up or a rising edge on ENTRIPx. Toggle

ENTRIPx or cycle VIN to reset the UVP fault latch and

restart the controller.

Thermal Protection

The RT8243A/B/C features thermal shutdown to prevent

damage from excessive heat dissipation. Thermal

shutdown occurs when the die temperature exceeds

150°C. All internal circuitry is inactive during thermal

shutdown. The RT8243A/B/C triggers thermal shutdown

if LDOx is not supplied from V

, while input voltage on

OUTx

VIN and drawing current from LDOx are too high.

Nevertheless, even if LDOx is supplied from V

OUTx

overloading LDOx can cause large power dissipation on

automatic switches, which may still result in thermal

shutdown.

Discharge Mode (Soft Discharge)

When ENTRIPx is low and a transition to standby or

shutdown mode occurs, or the output under voltage fault

latch is set, the output discharge mode will be triggered.

During discharge mode, an internal switch creates a path

for discharging the output capacitors' residual charge to

GND.

Shutdown Mode

SMPS1, SMPS2, LDO3 and LDO5 all have independent

enabling control. Drive ENLDO, ENTRIP1 and ENTRIP2

below the precise input falling edge trip level to place the

RT8243A/B/C in its low power shutdown state. The

RT8243A/B/C consumes only 20μA of input current while

in shutdown. When shutdown mode is activated, the

reference turns off. The accurate 0.95V falling edge

threshold on ENLDO can be used to detect a specific

analog voltage level and to shutdown the device. Once in

shutdown, the 1.6V rising edge threshold activates,

providing sufficient hysteresis for most applications.

Power Up Sequencing and On/Off Controls (ENTRIPx, ENM)

ENTRIP1 and ENTRIP2 control SMPS power up

sequencing. When the RT8243A/B/C is applied in the

single channel mode, ENTRIPx disables the respective

output when ENTRIPx voltage rises above 4.5V.

Furthermore, when the RT8243A is applied in the dual

channel mode, the outputs are enabled when ENM voltage

rises above 2.3V.

,

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DS8243A/B/C-07 November 2014www.richtek.com

RT8243A/B/C

Table1. Operation Mode Truth Table

Mode Condition Comment

Transitions to discharge mode after VIN POR and

Power Up LDOx

Run

Over Voltage Protection

Under Voltage Protection

Disch arge

Stan dby Shutdown ENLDO = low All circuitry are off.

Thermal Shutdown

< UVLO threshold

ENLDO = high, V enabled

Either output >112% of the nominal level.

Either output < 58% of the nominal level after 3ms time-out expires and output is enabled

Either output is still high in standby mode or shutdown mode

ENTRIPx or ENM < startup threshold, ENLDO = high.

T

> 150°C

J

OUT 1

or V

OUT2

are

after REF becomes valid. LDO5 and LDO3 remain active.

Normal Operation.

LGATEx is forced high. LDO3 and LDO5 are active. Exit by VIN POR or by toggling ENLDO, ENTRIPx, and ENM. Both UGATEx and LGATEx are forced low and enter discharge mode. LDO3 and LDO5 are active. Exit by VIN POR or by toggling ENLDO, ENTRIPx, and ENM. During discharge mode, there is one path to discharge the output capacitors’ residual charge to GND via an internal switch.

LDO3 and LDO5 are active.

All circuitry are off. Exit by VIN POR or by toggling ENLDO, ENTRIPx, and ENM.

Table 2. Power Up Sequencing (RT8243A)

ENLDO (V) ENM (V)

Low Low X X Off Off Off Off

“>1.6V”

=> High

“>1.6V”

=> High

“>1.6V”

=> High

“>1.6V”

=> High

“>1.6V”

=> High

Low X X On On Off Off

“>2.3 V”

=> High

“>2.3 V”

=> High

“>2.3 V”

=> High

“>2.3 V”

=> High

ENTRIP1

(V)

Off Off On On Off Off

Off On On On Off On

On On On On On On

On Off On On On Off

ENTRIP2

(V)

LDO5 LDO3 SMPS1 SMPS2

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21

RT8243A/B/C

Output Voltage Setting (FBx)

Connect a resistive voltage divider at the FBx pin between

V

and GND to adjust the output voltage between 2V

OUTx

and 5.5V (Figure 7). Choose R2 to be approximately 10kΩ,

and solve for R1 using the equation :



R1



VV x 1

OUT FBx

where V

is 2V (typ.).

FBx

UGATEx

PHASEx

LGATEx

PGND

Figure 7. Setting V





R2



V

IN

FBx

GND

with a resistive voltage divider

OUTx

VOUTx

R1

R2

Output Inductor Selection

The switching frequency (on-time) and operating point (%

ripple or LIR) determine the inductor value as shown

below :

t x (V V )

ON IN OUTx



L

LIR x I



LOAD(MAX)

where LIR is the ratio of the peak-to-peak ripple current to

the average inductor current.

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite cores

are often the best choice, although powdered iron is

inexpensive and can work well at 200kHz. The core must

be large enough not to saturate at the peak inductor

current, I

I

= I

PEAK

:

PEAK

LOAD(MAX)

+ [ (LIR / 2) x I

LOAD(MAX)

]

The calculation above shall serve as a general reference.

To further improve transient response, the output

inductance can be further reduced. Of course, besides

the inductor, the output capacitor should also be

considered when improving transient response.

Output Capacitor Selection

The capacitor value and ESR determine the amount of

output voltage ripple and load transient response. Thus,

the capacitor value must be greater than the largest value

calculated from below equations.

(I ) L (t t )

V



SAG

2 x C V t V (t + t )

V

V LIR x I ESR +

where V



SOAR

P P LOAD(MAX)



2C V



SAG





OUT IN ON OUTx ON OFF(MIN)

()

IL



LOAD



OUT OUTx

and V

2

LOAD ON OFF(MIN)

 

2

  

are the allowable amount of

SOAR

1

8 x C f

OUT



undershoot and overshoot voltage during load transient,

V

is the output ripple voltage, and t

p-p

OFF(MIN)

is the

minimum off-time.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

P

where T

the ambient temperature, and θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

JA

is the maximum junction temperature, TA is

is the junction to ambient

JA

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θJA, is layout dependent. For

WQFN-20L 3x3 package, the thermal resistance, θJA, is

30°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at TA = 25°C can

be calculated by the following formula :

P

= (125°C − 25°C) / (30°C/W) = 3.33W for

D(MAX)

WQFN-20L 3x3 package

22

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DS8243A/B/C-07 November 2014www.richtek.com

RT8243A/B/C

The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. The derating curve in Figure 8 allows the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

3.6

3.0

2.4

1.8

1.2

0.6

Maximum Power Dissipation (W) 1

0.0 0 25 50 75 100 125

Ambient Temperature (°C)

Four-Layer PCB

Figure 8. Derating Curve of Maximum Power Dissipation

Layout Considerations

Layout is very important in high frequency switching

converter design. Improper PCB layout can radiate

excessive noise and contribute to the converter’s

instability. Certain points must be considered before

starting a layout with the RT8243A/B/C.

 Place the filter capacitor close to the IC, within 12mm

(0.5 inch) if possible.

 Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high-voltage switching node.

 Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as

short as possible to reduce stray inductance. Use

0.65mm (25 mils) or wider trace.

 All sensitive analog traces and components such as

FBx, ENTRIPx, PGOOD, and TON should be placed

away from high voltage switching nodes such as

PHASEx, LGATEx, UGATEx, or BOOTx nodes to avoid

coupling. Use internal layer(s) as ground plane(s) and

shield the feedback trace from power traces and

components.

 Place ground terminal of VIN capacitor(s), V

capacitor(s), and source of low side MOSFETs as close

to each other as possible. The PCB trace of PHASEx

node, which connects to source of high side MOSFET,

drain of low side MOSFET and high voltage side of the

inductor, should be as short and wide as possible.

OUTx

DS8243A/B/C-07 November 2014 www.richtek.com

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23

RT8243A/B/C

Outline Dimension

1 2

DETAIL A

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010

D 2.900 3.100 0.114 0.122

D2 1.650 1.750 0.065 0.069

E 2.900 3.100 0.114 0.122

E2 1.650 1.750 0.065 0.069

1

2

e 0.400 0.016

L 0.350 0.450

0.014 0.018

W-Type 20L QFN 3x3 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8243A/B/C-07 November 2014www.richtek.com

24

Richtek RT8243AZQW, RT8243BZQW, RT8243CZQW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual