richtek RT8223P Datasheet

High Efficiency, Main Power Supply Controller
for Notebook Computer

RT8223P

General Description

The RT8223P is a dual step-down, switch-mode power
supply controller generating logic-supply voltages in
battery-powered systems. It includes two Pulse Width
Modulation (PWM) controllers adjustable from 2V to 5.5V,
and also features fixed 5V/3.3V linear regulators. Each
linear regulator provides up to 100mA output current with
automatic linear regulator bootstrapping to the PWM
outputs. The RT8223P includes on-board power up
sequencing, a power good output, internal soft-start, and
soft-discharge output that prevents negative voltage during
shutdown.

The constant on-time PWM sche me can operate without
sense resistors a nd provide 100ns load tran sient response
while maintaining nearly constant switching frequency . To
eliminate noise in audio a pplications, a n ultra sonic mode
is included, which maintains the switching frequency
above 25kHz. Moreover, the diode-emulation mode
maximizes efficiency for light load applications. The
RT8223P is available in a WQF N-24L 4x4 pa ck age.

Features

zz

z Constant On-time Control with 100ns Load Step

zz

Response

zz

z Wide Input Voltage Range : 6V to 25V

zz

zz

z Dual Adjustable Outputs from 2V to 5.5V

zz

zz

z Fixed 3.3V and 5V LDO Output : 100mA

zz

zz

z 2V Reference Voltage

zz

zz

z Frequency Selectable via TONSEL Setting

zz

zz

z 4700ppm/

zz

zz

z Programmable Current Limit Combined with

zz

°°

°C R

°°

Current Sensing

DS(ON)

Enable Control

zz

z Selectable PWM, DEM, or Ultrasonic Mode

zz

zz

z Internal Soft-Start and Soft-Discharge

zz

zz

z High Efficiency up to 97%

zz

zz

z 5mW Quiescent Power Dissipation

zz

zz

z Thermal Shutdown

zz

zz

z RoHS Compliant and Halogen Free

zz

Applications

z Notebook and Sub-Notebook Computers
z 3-Cell and 4-Cell Li+ Battery-Powered Devices

Ordering Information

RT8223P

Package Type
QW : WQFN-24L 4x4 (W-Type)

Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Marking Information

20 : Product Code

20 YM

DNN

YMDNN : Date Code

Pin Configurations

(TOP VIEW)

VOUT1

PGOOD

BOOT1

FB1

REF

FB2

1
2
3

GND

4
5
6

78910 1211

VOUT2

VREG3

BOOT2

WQFN-24L 4x4

ENTRIP1

TONSEL

ENTRIP2

UGATE1

LGATE1

PHASE1

21 20 1924 2223

18

ENC

17

VREG5

16

VIN

15

25

UGATE2

GND

14

SKIPSEL

13

EN

LGATE2

PHASE2

DS8223P-01 June 2011 www.richtek.com

1

RT8223P

Typical Application Circuit

1

C

0

µ

F

1

Q1

BSC119

N03S

L

1
µ

H

.

8

V

1

T

U

O

5

V

C

2

µ

2

0

1

C

.

1

0

6

F

M

r

q

e
/

D

Q3

BSC119

N03S

V

c

u

n

y

e

E

M

l

/

U

OFF

REF

2V

C

t

r

o

a

3
F

1

C

8

9

µ

F

5

R

4

C

1

2

R

5

1

k

1

3

R

0

1

k

W

P

R

R

2

C

.

0

1

µ

F

1

C

.

0

2

µ

2

t

r

l

n

o

o

i

s

n

c

ON

ON

OFF

V

I

N

V

6

V

2

o

5

t

8

R

.

9

3

16

0

1

C

.

0

1

µ

F

4

0

21

0

22

O

1

B

T

O

20
19

24

5
F

14
13

18

VIN

UGATE1

BOOT1

PHASE1
LGATE1

VOUT1

2

FB1

3

REF

4

TONSEL
SKIPSEL
EN

ENC

RT8223P

UGATE2

BOOT2

PHASE2
LGATE2

GND

VOUT2

FB2

ENTRIP1

ENTRIP2

GND

VREG5

PGOOD

VREG3

R

1

0

0

10

0

9

R

2

T

B

O

O

11
12
15

7
5

R

1

L

M

I

I

1

5

0

1

6
25 (Exposed Pad)

17

23
8

k

R

M

2

I

L

I

5

0

1

k

C

9

µ

.

7

4

6

C

1

7

µ

.

4

Q2
BSC119

N03S

C

1

1

0

.

1

F

µ

Q4
BSC119

N03S

5

R

6

F

0

0

1

k

P
3

F

3

C

1

1

0

F

µ

2

L

µ

7

4

.

H

R

1

1

C

1

4

R

.

6

R

0

1

V

G

3

.

n

O

y

w

s

a

A

l

O

O

n

I

D

o

r

t

c

d

i

a

V

A

l

w

a

O

s

y

n

C

1

2

0

µ

1

F

V

U

T

O

2

3

3

.

V

C

1

7

2

F

µ

2

0

1

2

C

1

4

k

5

1

5

k

0

2

C

F

µ

.

1

0

Functional Pin Description

P in No. Pin Name Pin Function

Chan nel 1 Ena ble an d Curre nt Li mi t Sett ing Inp ut. Co nnec t a r esisto r to GND to
set the threshold for channel 1 synchronous R

1 ENTRIP1

2 FB1

3 REF

4 TONSEL

5 FB2

6 ENTRIP2

7 VOUT2
8 VREG3 3.3V Linear Regulator Output.

current limit threshold is 1/10th the voltage seen at ENTRIP1 over a 0.515V to 3V
range. There is an internal 10μA c urren t sou r ce from V REG5 to ENT R IP1. Lea ve
ENTRIP1 floating or short ENTRIP1 to GND to shut down channel 1.

SMPS 1 Feedbac k Input. Connect FB1 t o a re sisti ve v olt a ge div ide r fr om VOU T1
to GND to adjust output from 2V to 5.5V.

2V Reference Output. Bypass to GND with a minimum 0.22μF c apac i to r. RE F can
so urce up to 10 0μA for exte rnal loa ds. Loadin g REF d egrades FBx and output
accuracy according to the REF load-regulation error .

Frequency Selectable Input for VOUT1/VOUT2 respectively.
400kHz/500kHz : Connect to VREG5 or VREG3
300kHz/375kHz : Connect to REF
200kHz/250kHz : Connect to GND

SMPS 2 Feedbac k Input. Connect FB2 t o a re sisti ve v olt a ge div ide r fr om VOU T2
to GND to adjust output voltage from 2V to 5.5V.

Chan nel 2 Ena ble an d Curre nt Li mi t Sett ing Inp ut. Co nnec t a r esisto r to GND to
set the threshold for channel 2 synchronous R
current limit threshold is 1/10th the voltage seen at ENTRIP2 over a 0.515V to 3V
range. There is an internal 10μA curr ent sourc e from VREG5 to ENT RIP2. Lea ve
ENTRIP2 floating or short ENTRIP2 to GND to shut down channel 2.

Byp ass Pi n for SMP S2. Co nn ect to t h e SM P S2 o ut p ut to bypas s effici ent pow er
for VREG3 pin. VOUT2 is also for the SMPS2 output soft-discharge.

sense. The GND − PHASE1

DS(ON)

sense. The GND − PHASE2

DS(ON)

T o be continued

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Pin No. Pin Name Pin Function

9 BOOT2

10 UGATE2

11 PHASE2

12 LGATE2

13 EN

14 SKIPSEL

16 VIN Supply Input for 5V/3.3V LDO and Feed Forward On-Time circuitry.
17 VREG5

18 ENC
19 LGATE1

20 PHASE1

21 UGATE1

22 BOOT1
23 PGOOD Power Good Output for Channel 1 and Channel 2. (Logical AND).
24 VOUT1

15, 25

(Exposed Pad)

GND

Boos t Flyin g C ap aci t or C on nec tio n f o r SM PS 2. Conne ct to an ex te r nal cap ac itor
ac co rding to the typic al ap p lic ati on cir c ui ts.
Upper Gate Dri ver Output for S MPS 2. U GAT E2 swings between PHASE2 and
BOOT2.
Switch Node for SMPS2. PHASE2 is the internal lower supply rail for the
UGAT E2 hi gh s ide gate driv er. PH ASE2 is also the cur rent -sense inp ut for the
SMPS2.
Lower Gate Driver Output for SMPS2. LGATE2 swings between GND and
VREG5.
Ma ster E nabl e In put. The REF/V REG 5/VR EG3 ar e e na bled if it is wit hin l ogic
high level and disabled if it is less than the logic low level.
Operation Mode Selectable Input.
Conn ec t to VREG5 or VRE G3 : Ultras on ic Mod e
Connect to REF : PWM Mode
Connect to GND : DEM Mode

5V Linear Regulator Output. VREG5 is also the supply voltage for the lower gate
driver and analog supply voltage for the device.
SMPS Enable Input. Pull up to VREG3 or VREG5 to turn on both switch channels.
Short to GND to shutdown them.
Lower Gate Driver Output for SMPS1. LGATE1 swings between GND and
VREG5.
Switch Node for SMPS1. PHASE1 is the internal lower supply rail for the
UGAT E1 hi gh s ide gate driv er. PH ASE1 is also the cur rent -sense inp ut for the
SMPS1.

Upper Gate Dri ver Output for S MPS 1. U GAT E1 swings between PHASE1 and
BOOT1.

Boos t Flyin g C ap aci t or C on nec tio n f o r SM PS 1. Conne ct to an ex te r nal cap ac itor
ac co rding to the typic al ap p lic ati on cir c ui ts.

Byp ass Pin f or SMPS 1. Co nn ect t o th e SM P S1 outp ut to by pas s effici ent pow er
for VREG5 pin. VOUT1 is also for the SMPS1 output soft-discharge.

Gr ound for SMP S C ont rol l er. The exp os ed pad mu st be s olde r ed to a lar ge PCB
and con nected to GND for maxi mum power dissipati on.

RT8223P

DS8223P-01 June 2011 www.richtek.com

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RT8223P

Function Block Diagram

BOOT1

UGATE1
PHASE1

LGATE1

FB1

ENTRIP1

EN

ENC

VOUT1

VREG5

VREG5

10µA

SW5 Threshold

TONSEL SKIPSEL

SMPS1

PWM Buck

Controller

Power-On
Sequence

Clear Fault Latch

SMPS2

PWM Buck

Controller

SW3 Threshold

VREG5

BOOT2

UGATE2
PHASE2

VREG5

LGATE2

10µA

VOUT2
FB2

ENTRIP2
PGOOD

GND

VREG5

VIN

VREG5

Thermal

Shutdown

REF

REF

VREG3

VREG3

DS8223P-01 June 2011www.richtek.com

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RT8223P

Absolute Maximum Ratings (Note 1)

z VIN, EN to GND ----------------------------------------------------------------------------------------------- −0.3V to 30V
z PHASEx to GND

D C---------------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 20ns----------------------------------------------------------------------------------------------------------- −8V to 38V

z BOOTx to PHASEx ------------------------------------------------------------------------------------------ −0.3V to 6V
z ENTRIPx, SKIPSEL, TONSEL, PGOOD to GND------------------------------------------------------ −0.3V to 6V
z VREG5, VREG3, FBx, VOUTx, ENC, REF to GND -------------------------------------------------- −0.3V to 6V
z UGA TEx to PHASEx

D C---------------------------------------------------------------------------------------------------------------- −0.3V to (VREG5 + 0.3V)
< 20ns----------------------------------------------------------------------------------------------------------- −5V to 7.5V

z LGA TEx to GND

D C---------------------------------------------------------------------------------------------------------------- −0.3V to (VREG5 + 0.3V)
< 20ns----------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

z Power Dissipation, P

WQFN-24L 4x4------------------------------------------------------------------------------------------------ 1.923W

z Package Thermal Resistance (Note 2)

WQF N-24L 4x4, θJA------------------------------------------------------------------------------------------ 52°C/W
WQF N-24L 4x4, θJC------------------------------------------------------------------------------------------ 7°C/W

z Lead T emperature (Soldering, 10 sec.) ------------------------------------------------------------------ 260°C
z Junction T emperature ---------------------------------------------------------------------------------------- 150°C
z Storage T emperature Range -------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)

HBM (Human Body Mode)---------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------- 200V

@ TA = 25°C

D

Recommended Operating Conditions (Note 4)

z Supply V oltage, V

z Junction T emperature Range ------------------------------------------------------------------------------- −40°C to 125°C
z Ambient T emperature Range ------------------------------------------------------------------------------- −40°C to 85°C

------------------------------------------------------------------------------------------ 6V to 25V

IN

DS8223P-01 June 2011 www.richtek.com

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RT8223P

Electrical Characteristics

(V

= 12V, V

IN

Parameter Symbol Test Conditions Min Typ Max Unit

Input Supply

VIN Standby Current I
VIN Shutdown Supply

Current
Quiesce nt Power

Consumption

SMPS Output and FB Voltage

EN

= V

ENC

= 5V, V

VIN_SBY

I

VIN_SHDN

P
+P

ENTRIP1

= V

= 2V, No Load, TA = 25°C, unless otherwise specified)

ENTRIP2

VIN = 6V to 25V, ENTRIPx = GND -- 200 -- μA

= 6V to 25V,

V

VIN

PVCC

IN

ENTRIPx = EN = GND
Both SMPS On, V

SKIPSEL = GND, V
(Note 5)

= 2. 1V,

FBx

OUT1

= 5V, V

OUT2

= 3. 3 V

-- 20 40 μA

-- 5 7 mW

DEM Mod e 1 .97 5 2 2.02 5

FBx Voltage V

Out p ut Vol ta ge Ad ju st
Range

V

Discharge

OUTx

Current

V

V

On-Time

On-Time Pulse Width tON

Minimum Off-Time t
Ultrasonic Mode

Frequency

SKIPSEL = VREG5 or VREG3 22 33 -- kHz

Soft-Start

Soft-S t art Time t

Cur r ent S ens e

ENTRIPx Source
Current

I

ENTRIPx Current
Temperature

TC
Coefficient
ENT RIP x Ad ju stme n t
Range
Current Limit
Threshold
Zero-Current
Threshold

V

GND − PHASEx, V

GND − PHASEx in DEM -- 3 -- mV

FBx

PWM Mode (Note 6) -- 2 --

V

Ultrasonic Mode -- 2.032 --

SMPS1, SMPS2 2 -- 5.5 V

OUTx

= 0.5V, V

OUTx

ENTRIPx

TONSEL = GND

TONSEL = REF

TONSEL = REG5

V

OFF

Internal Soft-Start -- 2 -- ms

SSx

ENTRIPx

V

IENTRIPx

= 1.9V 200 300 4 00 ns

FBx

ENTRIPx

= 0.9V 9.4 10 10.6 μA

In Comparison with 25°C (Note 6) -- 4700 -- ppm/°C

ENTRIPx

= I

ENTRIPx

= 0V 10 45 -- mA

V

= 5.05 V (200k H z) 189 5 2105 2 315

OUT1

= 3.33V (250kH z ) 9 99 1110 1221

V

OUT2

V

= 5.05 V (300k H z) 122 7 1403 1 579

OUT1

= 3.33 V (375k H z) 647 740 8 33

V

OUT2

V

= 5.05 V (400k H z) 895 1052 1 209

OUT1

V

= 3.33 V (500k H z) 475 555 6 35

OUT2

x R

ENTRIPx

ENTRIPx

0.515 -- 3 V

= 2V 180 200 220 mV

ns

T o be continued

DS8223P-01 June 2011www.richtek.com

6

Parameter Symbol Test Conditions Min Typ Max Unit

Internal Regulator and Reference

VREG5 Outpu t Volta g e V

VREG3 Outpu t Volta g e V

VREG5 Outpu t Cu rrent I

VREG5

VREG3

VREG5

V

OUT1

V

OUT1

I

VREG5

V

OUT1

I

VREG5

V

OUT2

V

OUT2

I

VREG3

V

OUT2

I

VREG3

V

VREG5

= GND, I

< 100mA 4.8 5 5.2

VREG5

= GND, 6.5V < VIN < 25V,

< 100mA

= GND, 5.5V < VIN < 25V,

< 50mA

= GND, I
= GND, 6.5V < VIN < 25V,

< 100mA

= GND, 5.5V < VIN < 25V,

< 50mA

= 4.5V , V

< 100mA 3.2 3.33 3.46

VREG3

= GND 100 175 250 mA

OUT1

RT8223P

4.75 5 5.25

4.75 5 5.25

3.13 3.33 3.5

3.13 3.33 3.5

V

V

VREG3 Outpu t Cu rrent I
VR EG5 Switc h-o v er

Threshold to V

OUT1

VR EG3 Switc h-o v er
Threshold to V

OUT2

VREGx Switch-over
Equi vale nt Resistance

REF Output Voltage V
REF Load Reg ulation 0 < I

V

VREG3

V

V

SW5

V
V

V

SW3

VREGx to V

R

SWx

No External Load 1.98 2 2.02 V

REF

V

= 3V, V

VREG3

Rising Edge 4.6 4.75 4.9

OUT1

Falling Edge 4.3 4. 4 4.5

OUT1

Rising Edge 2.975 3.125 3.25

OUT2

Falling Edge 2.775 2.875 2.975

OUT2

OUTx

< 100μA -- 10 -- mV

LOAD

= GND 100 175 250 mA

OUT2

, 10mA -- 1.5 3 Ω

V

V

REF Sink Current REF in Reg ulation 5 -- -- μA

UVLO

VREG5 Under Volt age
Lockout Threshol d

VREG3 Under Volt age
Lockout Threshol d

SMPSx off -- 2.5 -- V

Rising Edge -- 4.2 4.45

V

Falli ng Edge 3.7 3. 9 4.1

Powe r Go od

PGOO D Detect, FBx falling Edge 82 85 88

PGOOD Threshold

PGOO D Prop agat ion
Delay

Hy s tere s is , Rising Edge with SS De lay
Time

-- 6 --

Falling Edge, 50mV Overdrive -- 10 -- μs

%

PGOO D Lea kage Current High State, Forc ed to 5.5V -- -- 1 μA
PGOOD Output Low

Voltage

I

= 4mA -- -- 0.3 V

SINK

Fault Detection

Over Voltage Protection
Tr ip Thresh old

Over Voltage Protection
Propagation Delay

Unde r Vol tage Protection
Tr ip Thresh old

V

FB_OVP

FBx = 2.35V -- 5 -- μs

V

FB_UVP

OVP Detect, FBx Rising Edg e 109 112 1 16 %

U VP Detect , FBx Fall ing Edge 49 52 56 %

T o be continued

DS8223P-01 June 2011 www.richtek.com

7

RT8223P

Parameter Symbol Test Conditions Min Typ Max Unit

UVP Shutdown Blanking Time t

SHDN_UVP

Thermal Shutdown

Thermal Shutdown T

SHDN

Thermal Shutdown Hysteresis -- 10 -- °C

Logic Input

SKIPSEL Input Volt age

ENTR IPx

ENTRIPx Low Level Threshold

EN Threshold
Voltage

Logic-High VIH 2.4 -- -­Logic-Low V

-- -- 0.4

IL

EN Voltage VEN Floating, Default Enable 2.4 3. 3 4.2 V
EN Current IEN

ENC Threshold
Voltage

Logic-High V
Logic-Low V

IH_ENC

IL_ENC

From ENTRIPx Enable -- 5 -- ms

-- 150 -- °C

Low Level (DEM Mode) -- -- 0.8
REF Level ( PW M Mode) 1. 8 -- 2.3
High Level (Ultrasonic Mode) 2.7 -- -­Low Level (SMPS Off) -- -- 0.25
On Level (SMPS On) 0.515 -- 3 ENTRIPx Input Voltage V
High Level (SMPS Off) 4.5 -- -­Rising Edge -- 0.4 0.515
Falling Edge 0.25 0.36 --

V

= 0.2V , Source 1.5 3 5

EN

= 5V, Sink -- 3 8

V

EN

2 -- --

-- -- 0.6

V

V

V

V

μA

V

Input Leakage Current

Inter nal BOOT Switch

Internal Boost Switch
On-Resistance

Power MOSFET Dri vers

UGATE x On-Resistance

LGATE x On-Resistance

Dead Time

V

/ V

OUT1

V

/ V

OUT1

/ V

V

OUT1

V

TONSEL

V

= 0V or 5V −1 -- 1

ENC

VREG5 to BOOTx, 10mA -- 40 80 Ω

UGA TEx, High State,
BOOTx to PHASEx F orced to 5V
UGATEx, Low St at e,
BOOTx to PHASEx F orced to 5V

LGATEx , High St ate -- 4 8

= 200kHz/250kHz -- -- 0.8

OUT2

= 300kHz/375kHz 1.8 -- 2.3 TONSEL Sett i ng Voltage

OUT2

= 400kHz/500kHz 2.7 -- --

OUT2

, V

SKIPSEL

= 0V or 5V −1 -- 1

-- 4 8

-- 1.5 4

V

μA

Ω

Ω

LGATEx , Low State -- 1. 5 4
LGA TEx Ri sing -- 30 --

ns

UGATE x Rising -- 40 --

DS8223P-01 June 2011www.richtek.com

8

RT8223P

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.

Note 2. θ

Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. P
Note 6. Guaranteed by Design.

is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of

JA

JEDEC 51-7 thermal measurement standard. The measurement case position of θ
package.

+ P

VIN

VREG5

is on the exposed pad of the

JC

DS8223P-01 June 2011 www.richtek.com

9

RT8223P

Typical Operating Characteristics

VOUT1 Efficiency vs. Load Current

100

90

DEM Mode

80
70
60
50
40

Efficiency (%) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 8V , T ONSEL = GND, EN = FLOA TING,

Ultrasonic Mode

PWM Mode

V

ENTRIP1

= 1.5V, V

ENTRIP2

Load Cu rrent (A)

VOUT1 Efficiency vs. Load Current

100

90

DEM Mode

80
70
60
50
40

Efficiency (%) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 20V

TONSEL = GND, EN = FLOA TING,

V

ENTRIP1

Load C urrent (A)

Ultrasonic Mode

PWM Mode

= 1.5V, V

ENTRIP2

= 5V

= 5V

VOUT1 Efficiency vs. Load Current

100

90

DEM Mode

80
70

PWM Mode

= 1.5V, V

ENTRIP1

Ultrasonic Mode

ENTRIP2

60
50
40

Eff i ciency (%) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 12V
TONSEL = GND, EN = FLOATING,

V

Load Current (A)

VOUT2 Efficiency vs. Load Current

100

90

DEM Mode

80
70
60
50
40

Efficiency (%) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 8V
TONSEL = GND, EN = FLOA TING,
V

Load C urrent (A)

PWM Mode

ENTRIP1

Ultrasonic Mode

= 5V, V

ENTRIP2

= 1.5V

= 5V

10

VOUT2 Efficiency vs. Load Current

100

90
80

DEM Mode

70
60
50
40

Eff i ci ency (%) 1

30
20
10

0

0.001 0.01 0.1 1 10

VIN = 12V

TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

Load C urrent (A)

Ultrasonic Mode

PWM Mode

= 5V, V

ENTRIP2

= 1.5V

VOUT2 Efficiency vs. Load Current

100

90
80
70
60
50
40

Efficiency (%) 1

30
20
10

0

DEM Mode

Ultrasonic Mode

PWM Mode

VIN = 20V
TONSEL = GND,EN = FLOA TING,
V

0.001 0.01 0.1 1 10

ENTRIP1

= 5V, V

ENTRIP2

= 1.5V

Load Current (A)

DS8223P-01 June 2011www.richtek.com

RT8223P

VOUT1 Switching Frequency vs. Load Current

220
200
180
160
140
120
100

80
60
40

Switching Freque ncy (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 8V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 1.5V, V

ENTRIP2

= 5V

Ultrasonic Mode

DEM Mode

Load C urrent (A)

VOUT1 Switching Frequency vs. Load Current

220
200
180
160
140
120
100

80
60
40

Switching Freque ncy (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 20V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 1.5V, V

ENTRIP2

= 5V

Ultrasonic Mode

DEM Mode

Load Cu rrent (A)

VOUT1 Switching Frequency vs. Load Current

220
200
180
160
140
120
100

80
60
40

Switching Fr equency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 12V

TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 1.5V, V

ENTRIP2

= 5V

Ultrasonic Mode

DEM Mode

Load Cu rrent (A)

VOUT2 Switching Frequency vs. Load Current

280
260
240
220
200
180
160
140
120
100

80
60
40

Swi t c hing Frequency (kH z) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 8V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 5V, V

ENTRIP2

= 1.5V

Ultrasonic Mode

DEM Mode

Load C urrent (A)

VOUT2 Switching Frequency vs. Load Current

280
260
240
220
200
180
160
140
120
100

80
60
40

Switching Frequency (kHz) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 12V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 5V, V

ENTRIP2

= 1.5V

Ultrasonic Mode

DEM Mode

Load Current (A)

VOUT2 Switching Frequency vs. Load Current

280
260
240
220
200
180
160
140
120
100

80
60
40

Swi t c hing Frequency ( kHz ) 1

20

0

0.001 0.01 0.1 1 10

PWM Mode

VIN = 20V
TONSEL = GND, EN = FLOA TING,
V

ENTRIP1

= 5V, V

ENTRIP2

= 1.5V

Ultrasonic Mode

DEM Mode

Load C urrent (A)

DS8223P-01 June 2011 www.richtek.com

11

RT8223P

VOUT1 Output Voltage vs. Load Current

5.090

5.084

5.078

5.072

5.066

5.060

5.054

5.048

5.042

5.036

5.030

5.024

Output Voltage (V) 1

5.018

5.012

5.006

5.000

0.001 0.01 0.1 1 10

VIN = 12V , TONSEL = GND, EN = FLOATING,

Ultrasonic Mode

PWM Mode

DEM Mode

V

ENTRIP1

= 1.5V, V

Load Cu rrent (A)

VREG5 Output Voltage vs. Output Current

5.006

5.000

4.994

4.988

4.982

Output Voltage (V) 1

4.976

VIN = 12V , TONSEL = GND, EN = FLOA TING,

V

ENTRIP1

= V

ENTRIP2

ENTRIP2

= 5V

= 5V

VOUT2 Output Voltage vs. Load Current

3.446

3.440

3.434

3.428

3.422

3.416

3.410

3.404

3.398

Outpu t V oltage (V) 1

3.392

3.386

3.380

0.001 0.01 0.1 1 10

VIN = 12V , T ONSEL = GND, EN = FLOA TING,

Ultrasonic Mode

PWM Mode

DEM Mode

V

ENTRIP1

= 5V, V

ENTRIP2

Load C urrent (A)

VREG3 Output Voltage vs. Output Current

3.358

3.354

3.350

3.346

3.342

3.338

Outp ut Voltage (V) 1

3.334

VIN = 12V , TONSEL = GND, EN = FLOA TING,

V

ENTRIP1

= V

= 1.5V

ENTRIP2

= 5V

12

4.970

2.0080

2.0072

2.0064

2.0056

2.0048

2.0040

2.0032

2.0024

2.0016

Reference Voltage (V) 1

2.0008

2.0000

0 20406080100

Output Current (mA)

Reference Voltage vs. Output Current

VIN = 12V , TONSEL = GND, EN = FLOA TING,

-10 0 10 20 30 40 50 60 70 80 90 100

Output Current (µA)

V

ENTRIP1

= V

ENTRIP2

= 5V

3.330
0 10203040506070

Output Current (mA)

Battery Current vs. Input Voltage

100.0

Battery Current (mA) 1

No Load

PWM Mode

10.0

Ultrasonic Mode

1.0

DEM Mode

TONSEL = GND, EN = FLOA TING,

V

= V

0.1
6 7 8 9 10111213141516171819202122232425

ENTRIP1

ENTRIP2

Input Volt age (V)

DS8223P-01 June 2011www.richtek.com

= 0.91V

RT8223P

Standby Input Current vs. Input Voltage

250
249
248
247
246
245
244
243
242

Standby Input Current (µ A ) 1

241
240

7 8 9 101112131415161718192021222324

No Load,
EN = FLOATING, V

ENTRIP1

= V

Input Volt age (V)

Reference Voltage v s. Temperature

2.011

2.008

2.005

2.002

1.999

1.996

1.993

ENTRIP2

= 5V

22
21
20
19
18
17
16
15
14
13
12
11
10

Shutdow n Input Current (µ A) 1

VREG5

(5V/Div)

VREG3

(2V/Div)

REF

(2V/Div)

Shutdown Input Current vs. Input Voltage

9
8

No Load, EN = GND, V

7 8 9 101112131415161718192021222324

ENTRIP1

= V

ENTRIP2

= 5V

Input Volt age (V)

VREG5, VREG3 and REF Start Up

1.990

Reference Voltage (V) 1

1.987

1.984

V

OUT1

(5V/Div)

V

OUT2

(2V/Div)

PGOOD

(5V/Div)

ENC

(5V/Div)

VIN = 12V, V

EN = FLOA TING, TONSEL = GND

-50 -25 0 25 50 75 100 125

ENTRIP1

= V

ENTRIP2

= 5V,

Temperature (°C)

Power On From ENC

No Load

VIN = 12V , TONSEL = GND,

SKIPSEL = REF , EN = FLOA TING,

V

= V

ENTRIP1

ENTRIP2

Time (1ms/Div)

= 1.5V, V

ENC

= 5V

EN

(2V/Div)

V

OUT1

(5V/Div)

V

OUT2

(2V/Div)

PGOOD

(5V/Div)

ENC

(5V/Div)

EN = FLOATING, V

No Load

No Load, VIN = 12V, TONSEL = GND,

= V

ENTRIP1

ENTRIP2

Time (400μs/Div)

Power Off From ENC

VIN = 12V , TONSEL = GND,

SKIPSEL = REF , EN = FLOA TING,

V

= V

ENTRIP1

ENTRIP2

Time (4ms/Div)

= 1.5V, V

ENC

= 5V

= 5V

DS8223P-01 June 2011 www.richtek.com

13

RT8223P

V

OUT1

(2V/Div)

PGOOD

(5V/Div)

ENTRIP1

(5V/Div)

V

OUT2

(2V/Div)

PGOOD

(5V/Div)

No Load

No Load

Power On from ENTRIP1

VIN = 12V , TONSEL = GND,

SKIPSEL = REF , EN = FLOA TING,

V

ENTRIP1

= V

ENTRIP2

Time (1ms/Div)

Power On from ENTRIP2

= 1.5V

V

OUT1

(2V/Div)

PGOOD
(5V/Div)

ENTRIP1

(5V/Div)

V

OUT2

(2V/Div)

PGOOD
(5V/Div)

Power Off from ENTRIP1

VIN = 12V , TONSEL = GND,

SKIPSEL = REF , EN = FLOA TING,

V

ENTRIP1

= V

ENTRIP2

Time (2ms/Div)

Power Off from ENTRIP2

No Load

= 1.5V

No Load

ENTRIP2

(5V/Div)

VIN = 12V , TONSEL = GND,

SKIPSEL = REF , EN = FLOA TING,

V

ENTRIP1

= V

ENTRIP2

= 1.5V

Time (1ms/Div)

VOUT1 PWM Mode Load Transient Response

V

OUT1_AC

(50mV/Div)

Inductor

Current
(5A/Div)

UGA TE1

(20V/Div)

LGA TE1

(5V/Div)

EN = FLOA TING, SKIPSEL = REF , I

VIN = 12V , T ONSEL = GND,

Time (20μs/Div)

OUT1

= 0A to 6A

ENTRIP2

(5V/Div)

VIN = 12V , TONSEL = GND,

SKIPSEL = REF , EN = FLOA TING,

V

ENTRIP1

= V

ENTRIP2

= 1.5V

Time (2ms/Div)

VOUT2 PWM Mode Load Transient Response

V

OUT2_AC

(50mV/Div)

Inductor

Current

(5A/Div)

UGA TE2

(20V/Div)

LGA TE2
(5V/Div)

EN = FLOA TING, SKIPSEL = REF , I

VIN = 12V , T ONSEL = GND,

Time (20μs/Div)

OUT2

= 0A to 6A

14

DS8223P-01 June 2011www.richtek.com

RT8223P

V

OUT1

(2V/Div)

V

OUT2

(2V/Div)

PGOOD
(5V/Div)

OVP

No Load, VIN = 12V, TONSEL = GND,

EN = FLOA TING, SKIPSEL = GND

Time (4ms/Div)

V

OUT1

(5V/Div)

PGOOD

(5V/Div)

UGA TE1

(20V/Div)

LGATE1

(5V/Div)

UVP

VIN = 12V , TONSEL = GND,

Time (100μs/Div)

EN = FLOA TING,

SKIPSEL = REF

DS8223P-01 June 2011 www.richtek.com

15

RT8223P

Application Information

The RT8223P is a dual, Ma ch Respon seTM DRVTM dual
ramp valley mode synchronous buck controller. The
controller is designed for low voltage power supplies for
notebook computers. Richtek's Mach Response

TM

technology is specifically designed for providing 100ns
“instant-on” response to load steps while maintaining a
relatively constant operating frequency and inductor
operating point over a wide range of input voltages. The
topology circumvents the poor load-transient timing
problems of fixed-frequency current mode PWMs while
avoiding the problems caused by widely varying switching
frequencies in conventional constant on-ti me and consta nt
off-time PWM schemes. The DRVTM mode PWM
modulator is specifically designed to have better noise
immunity for such a dual output application. The
RT8223P includes 5V (VREG5) and 3.3V (V REG3) linear
regulators. VREG5 linear regulator can step down the
battery voltage to supply both internal circuitry and gate
drivers. The synchronous-switch gate drivers are directly
powered from VREG5. When VOUT1 voltage is above

4.75V, an automatic circuit will switch the power of the
device from VREG5 linear regulator to VOUT1.

PWM Operation

TM

The Mach Respon seTM DRV

mode controller relies on
the output filter capacitor's Effective Series Resistance
(ESR) to act as a current sense resistor, so the output
ripple voltage provides the PWM ra mp signal. Refer to the
RT8223P's function block diagra m, the synchronous high
side MOSFET will be turned on at the beginning of each
cycle. After the internal one-shot timer expires, the
MOSFET will be turned off. The pulse width of this one
shot is determined by the converter's input voltage and
the output voltage to keep the frequency fairly constant
over the input voltage range. Another one shot sets a
minimum off-time (300ns typ.). The on-time one shot will
be triggered if the error comparator is high, the low side
switch current is below the current limit threshold, and
the minimum off-time one shot has timed out.

PWM Frequency and On-Time Control

The Mach ResponseTM control architecture runs with
pseudo constant frequency by feed-f orwarding the input
and output voltage into the on-time one-shot timer. The
high side switch on-time is inversely proportional to the
input voltage a s mea sured by VIN, and proportional to the
output voltage. There are two benefits of a constant
switching frequency . First, the frequency can be selected
to avoid noise-sensitive regions such as the 455kHz IF
band. Second, the inductor ri pple current operating point
remains relatively constant, resulting in easy design
methodology and predictable output voltage ripple.
Frequency for the 3V SMPS is set at 1.25 times higher
than the frequency for 5V SMPS. This is done to prevent
audio-frequency “Beating” between the two sides, which
switch asynchronously f or ea ch side. The frequencies are
set by the TONSEL pin connection as shown in Table 1.
The on-time is given by :

t= K(V V)×

ON OUT IN

/

where “K” is set by the TONSEL pin connection (Table

1). The on-time guara nteed in the Electrical Characteristics
table is influenced by switching delays in the external
high side power MOSFET. Two external factors that
influence switching frequency accura cy are resistive drops
in the two conduction loops (including inductor and PC
board resistance) a nd the dead time ef fect. These effects
are the largest contributors to the change in frequency
with changing load current. The dead-time ef fect increa ses
the effective on-time by reducing the switching frequency .
It occurs only in PWM mode (SKIPSEL= REF) when the
inductor current reverses at light or negative load currents.
With reversed inductor current, the inductor's EMF causes
PHASEx to go high earlier than normal, thus extending
the on-time by a period equal to the low-to-high dead time.
For loads above the critical conduction point, the actual
switching frequency is :

f = (V V ) (t (V V V ))+×+−

OUT DROP1 ON IN DROP1 DROP2

where V

is the sum of the parasitic voltage drops in

DROP1

/

the inductor discharge path, which includes the
synchronous rectifier , inductor, a nd PC board resista nces.
V

is the sum of the resistances in the charging path,

DROP2

and tON is the on-time.

16

DS8223P-01 June 2011www.richtek.com

Table 1. TONSEL Connection and Switching Frequency

RT8223P

TONSEL

SMPS 1

K-Fa cto r (μs)

SMPS 1

Frequency (kHz)

SM PS 2

K-Factor (μs)

SM PS 2

Frequency (kHz)

Approximate

K-Fac tor Error (%)
GND 5 200 4 250 ±10
REF 3.33 300 2.67 375 ±10

VREG5 or

VREG3

2.5 400 2 500 ±10

Operation Mode Selection (SKIPSEL)

(V V )

−

The RT8223P supports three operation modes : Diode­Emulation Mode, Ultrasonic Mode, and Forced-CCM
Mode. User can set operation mode vi a the SKIPSEL pin.

Diode-Emulation Mode (SKIPSEL=GND)

In Diode-Emulation Mode, the RT8223P automatically
reduces switching frequency at light-load conditions to
maintain high efficiency. This reduction of frequency is
achieved smoothly . As the output current decrea ses from
heavy-load condition, the inductor current is also reduced
and eventually comes to the point when its valley touches
zero current, which is the boundary between continuous
conduction and discontinuous conduction modes. By
emulating the behavior of diodes, the low side MOSFET
allows only partial negative current when the inductor free­wheeling current becomes negative. As the load current
is further decrea sed, it takes longer and longer to discharge
the output capacitor to the level that requires the next
“ON” cycle. The on-time is kept the same as that in the
heavy-load condition. In reverse, when the output current
increases from light load to heavy-load, the switching
frequency increases to the preset value as the inductor
current rea ches the continuous conduction. The tran sition
load point to the light-load operation is shown a s f ollows
(Figure 1) :

I

L

Slope = (VIN -V

0

T

ON

OUT

) / L

I

Load

I

L, PEAK

= I

L, PEAK

t

/ 2

Figure 1. Boundary Condition of CCM/DEM

It

LOAD (SKIP) ON

where tON is the On-time.
The switching waveforms may appear noisy and

asynchronous when light loa ding causes Diode-Emulation
Mode operation. However this is normal and results in
high efficiency. Trade-offs in PFM noise vs. light load
efficiency is made by varying the inductor value. Generally ,
low inductor values produce a broader efficiency vs. load
curve, while higher values result in higher full-load efficiency
(a ssuming that the coil resistance remains f ixed) and less
output voltage ripple.

Penalties for using higher inductor values include larger
physical size and degraded load transient response
(especially at low input-voltage levels).

Ultrasonic Mode (SKIPSEL = VREG5 or VREG3)

The RT8223P a ctivates a n unique Diode-Emulation Mode
with a minimum switching frequency of 25kHz, called the
Ultrasonic Mode. The Ultrasonic Mode avoids audio­frequency modulation that would otherwise be present
when a lightly loaded controller automatically skips
pulses. In Ultra sonic Mode, the high side switch gate driver
signal is OR with an internal oscillator (>25kHz). Once
the internal oscillator is triggered, the controller enters
constant off-time control. When output voltage reaches
the setting peak threshold, the controller turn s on the low
side MOSFET until the controller detects that the inductor
current dropped has below the zero-crossing thre shold.
The internal timer provides a consta nt off-time control a nd
it is effective to regulate the output voltage under light
load conditions.

IN OUT

≈×

2L

DS8223P-01 June 2011 www.richtek.com

17

RT8223P

Forced CCM Mode (SKIPSEL = REF)

The low noise, Forced CCM mode (SKIPSEL = REF)
disables the zero-crossing comparator , which controls the
low side switch on-time. This causes the low side gate­driver waveform to become the complement of the high
side gate-driver waveform. This in turn causes the inductor
current to reverse at light loads as the PWM loop to
maintain a duty ratio of V

OUT/VIN

. The benefit of Forced
CCM Mode is to keep the switching frequency fairly
constant, but it comes at a cost. The no load battery
current can be from 10mA to 40mA, depending on the
external MOSFET s.

Reference and linear Regulators (REF, VREGx)

The 2V reference (REF) is a ccurate within ±1% over the
entire operating temperature range, ma king REF useful
as a precision system reference. Bypass REF to GND
with a minimum 0.22μF cera mic ca pacitor . REF can supply
up to 100μA for external loads. Loading REF reduces the
VOUTx output voltage slightly because of the reference
load-regulation error .

The RT8223P includes 5V (V REG5) a nd 3.3V (V REG3)
linear regulators. The VREG5 regulator supplies a total of
100mA for internal and external loads, including the
MOSFET gate driver and PWM controller. The VREG3
regulator supplies up to 100mA f or external loads. Bypa ss
VREG5 and VREG3 with a minimum 4.7μF ceramic
capacitor.

When the 5V main output voltage is above the VREG5
switch over threshold (4.75V), an internal 1.5Ω P-Channel
MOSFET switch connects VOUT1 to VREG5, while
simultaneously shutting down the VREG5 linear regulator .
Similarly , when the 3.3V main output voltage is above the
VREG3 switch over threshold (3.125V), an intern al 1.5Ω
P-Channel MOSFET switch connects VOUT2 to VREG3,
while simultaneously shutting down the VREG3 linear
regulator. It ca n decrea se the power dissipation from the
same battery , be cause the converted efficiency of SMPS
is better than the converted efficiency of the linear
regulator.

Current-Limit Setting (ENTRIPx)

The RT8223P ha s a cycle-by-cycle current-limit control.
The current-limit circuit employs an unique “valley” current

sensing algorithm. If the magnitude of the current sense
signal at PHASEx is above the current-limit threshold, the
PWM is not allowed to initiate a new cycle (Figure 2).
The actual peak current is greater than the current-limit
threshold by an a mount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are functions of the sense
resistance, inductor value, a nd battery and output voltage.

I

L

I

L, PEAK

I

LOAD

I

LIM

0

t

Figure 2. “Valley” Current-Limit

The RT8223P uses the on-resista nce of the synchronous
rectifier as the current-sense element and supports
temperature compensated MOSFET R
R

resistor between the ENTRIP

ILIMX

X

the current-limit threshold. The resistor R
to a current source from ENTRIPx

which is 10μA typically

,

sensing. The

DS(ON)

pin and GND sets

is connected

ILIMX

at room temperature. The current source ha s a 4700ppm/
°C temperature slope to compensate the temperature
dependency of the R

. When the voltage drop across

DS(ON)

the sense resistor or low side MOSFET equals 1/10 the
voltage across the R

resistor, positive current limit

ILIMX

will be activated. The high side MOSFET will not be turned
on until the voltage drop across the MOSFET falls below
1/10 the voltage across the R

ILIMX

resistor.
Choose a current limit resistor by following equations
V
R

ILIMx

ILIMx

= (R

= (I

x10μA)/10 = I

ILIMx

x R

ILIMx

DS(ON)

x R

ILIMx

) x 10/10μA

DS(ON)

Carefully observe the PC board layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signal at PHASEx and GND. Mount or pla ce the IC close
to the low side MOSFET.

MOSFET Gate Driver (UGATEx, LGATEx)

The high side driver is designed to drive high-current, low
R

N-MOSFET(s). When configured as a floating driver ,

DS(ON)

a 5V bias voltage is delivered from the VREG5 supply.

18

DS8223P-01 June 2011www.richtek.com

RT8223P

The average drive current is calculated by the gate charge
at VGS = 5V times the switching frequency. The
instantaneous drive current is supplied by the flying
cap acitor between the BOOTx and PHASEx pins. A dead
time to prevent shoot through is internally generated
between high side MOSFET off to the low side MOSFET
on, and the low side MOSFET of f to the high side MOSFET
on.

The low side driver is designed to drive high current, low
R
that drives LGA TE

N-MOSFET(s). The internal pull-down tran sist or

DS(ON)

low is robust, with a 1.5Ω typical on-

X

resistance. A 5V bia s voltage is delivered from the VREG5
supply . The instanta neous drive current is supplied by an
input ca pa citor connected between VREG5 a nd GND.

For high current application s, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate-drain coupling, which can lea d to
efficiency killing, EMI-producing shoot-through currents.
This can be remedied by a dding a resistor in series with
BOOTx, which increa ses the turn-on time of the high side
MOSFET without degrading the turn-off time (Figure 3).

UVLO Protection

The RT8223P features VREG5 under voltage lockout
protection (UVLO). When the V REG5 voltage is lower than

3.9V (typ.) and the VREG3 voltage is lower than 2.5V
(typ.), both switch power supplies are shut off. This is
non-latch protection.

Power Good Output (PGOOD)

PGOOD is a n open-drain type output a nd requires a pull­up resistor. PGOOD is actively held low in soft-start,
standby, and shutdown. It is released when both output
voltages are above 91% of the nominal regulation point.
The PGOOD goes low if either output turns off or is 15%
below its nominal regulator point.

Output Over V oltage Protection (OVP)

The output voltage can be continuously monitored for over
voltage. If the output voltage exceeds 12% of its set voltage
threshold, the over voltage protection is triggered and the
LGATEx low side gate drivers are forced high. This a ctivates
the low side MOSFET switch, which rapidly discharges
the output ca pacitor a nd pulls the input voltage downward.

V

IN

R

BOOTx

UGATEx

PHASEx

BOOT

Figure 3. Increa sing the UGA TEx Rise Ti me

Soft-Start

The RT8223P provides an intern al soft-start function to
prevent large inrush current and output voltage overshoot
when the converter starts up. The soft-start (SS)
automatically begins once the chip is ena bled. During soft­start, it clamps the ramping of internal reference voltage
which is compared with FBx signal. The typical soft­start duration is 2 ms. A unique PWM duty limit control
that prevents output over voltage during soft-start period
is designed specifically for FBx floating.

The RT8223P is latched once OVP is triggered a nd ca n
only be relea sed by toggling EN, ENTRIPx or cycling VIN.
There is a 5μs delay built into the over voltage protection
circuit to prevent false alarm.

Note that the LGATEx latching high causes the output
voltage to dip slightly negative when energy has been
previously stored in the LC tank circuit. For loads that
cannot tolerate a negative voltage, pla ce a power Schottky
diode across the output to a ct a s a reverse polarity cla mp.

If the over-voltage condition is caused by a short in the
high side switch, completely turning on the low side
MOSFET can create an electrical short between the
battery and GND, which will blow the fuse and disconnect
the battery from the output.

Output Under V oltage Prote ction (UVP)

The output voltage can be continuously monitored f or under
voltage protection. If the output is less than 52% of its set
voltage threshold, under voltage protection will be triggered,
and then both UGATEx and LGA TEx gate drivers will be
forced low . The UVP will be ignored f or at lea st 5ms (typ.)
after start-up or a rising edge on ENTRIPx. Toggle

DS8223P-01 June 2011 www.richtek.com

19

RT8223P

ENTRIPx or cycle VIN to reset the UVP fault latch and
restart the controller.

Thermal Protection

The RT8223P features thermal shutdown protection to
prevent overheat damage to the device. Thermal shutdown
occurs when the die temperature exceeds 150°C. All
internal circuitry is ina ctive during thermal shutdown. The
RT8223P triggers thermal shutdown if VREGx is not
supplied from VOUTx, while the input voltage on VIN and
the drawing current from VREGx are too high. Even if
VREGx is supplied from VOUTx, large power dissipation
on automatic switches caused by overloading VREGx,
may also result in thermal shutdown.

Discharge Mode (Soft-Discharge)

When ENTRIPx is low and a transition to standby or
shutdown mode occurs, or the output under voltage fault
latch is set, the output discharge mode will be triggered.
During discharge mode, the output capacitors' residual
charge will be discharged to GND through an internal
switch.

Shutdown Mode

The RT8223P SMPS1, SMPS2, VREG3 a nd VREG5 have
independent enabling controls. Drive EN, ENTRIP1 a nd
ENTRIP2 below the precise input falling-edge trip level to
place the RT8223P in its low power shutdown state. The
RT8223P consumes only 20μA of input current while in
shutdown. When shutdown mode is activated, the
reference turns off. The a ccurate 0.4V falling-edge threshold
on the EN pin can be used to detect a specific analog
voltage level as well as to shutdown the device. Once in
shutdown, the 2.4V rising-edge threshold activates,
providing sufficient hysteresis for most a pplications.

Power Up Sequencing and On/Off Controls (ENC)

ENTRIP1 and ENTRIP2 control the SMPS power up
sequencing. When the RT8223P is in single cha nnel mode,
ENTRIP1 or ENTRIP2 enables the respective output when
ENTRIPx voltage descends below 3V . Furthermore, the
RT8223P ca n also be in dual channel mode. In this mode,
outputs are enabled when ENC voltage rises above 2V.

Table 2. Operation Mode Truth Table

MODE Condition Comment

Transit ion s to dischar ge mo de after a VI N POR and after

Power UP VR EGx < UVLO threshold

REF becomes valid. VR EG 5, VREG3, and RE F remain
active.

RUN

Over Voltage

Protection

Under

Voltage

Protection

Discharge

Standby

EN = high, VOUT1 or VOUT2
enabled

Either output > 111% of the nomin al
level.

Ei t he r outpu t < 52 % of the nom i na l
level after 3ms t ime-out expi res and
outpu t is enabled

Either SMPS out put is still high in
either stan dby mode or shutdown
mode

ENTRIP

< startup thresh old,

X

EN = high.

Normal Operat ion .
LGA TE x is forced high. VREG 3, VRE G5 and REF activ e.

Exited by VIN POR or by toggling EN, ENTRIPx, ENC
Both UGATEx and LGA TEx are fo rce d low and enter

discharge mode. V REG3, VREG5 and REF ar e active.
Exited by VIN POR or by toggling EN, ENTRIPx, ENC

During discharge mode, there is one path to dischar ge the
outputs capacitor residual charge. That is output capacitor
discharge to GND through an internal swi tch.

VREG3, VREG5 and RE F are active.

Shutdown EN = low All circuitry off.

Thermal

Shutdown

T

> 150°C

J

All circuitry off. Exit by VIN POR or by toggling EN, ENTRIPx,
ENC

20

DS8223P-01 June 2011www.richtek.com

Table 3. Power Up Sequencing

RT8223P

EN

(V)

ENC

(V)

ENTRIP1 ENTRIP2 REF VREG5 VREG3 SMPS1 SMPS2

Low Low X X Off Off Off Off Off

“>2.4V”

=> High

“>2.4V”

=> High

“>2.4V”

=> High

“>2.4V”

=> High

“>2.4V”

=> High

Output V oltage Setting (FBx)

Connect a resistor voltage-divider at the FBx pin between
VOUTx and GND to adjust the respe ctive output voltage
between 2V and 5.5V (Figure 4). Referring to Figure 4 a s
an example, choose R2 to be approximately 10kΩ, and
solve for R1 using the equation :

VV1

where V

=×+

OUTX FBX

is 2V .

FBX

Low X X On On On Off Off

“>2V”

=> High

“>2V”

=> High

“>2V”

=> High

“>2V”

=> High

Off Off On On On Off Off

Off On On On On Off On

On Off On On On On Off

On On On On On On On

where LIR is the ratio of the peak to pea k ripple current to
the average inductor current.

Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted di mensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and ca n work well at 200kHz. The core must

R1

⎛⎞

⎛⎞

⎜⎟

⎜⎟

R2

⎝⎠

⎝⎠

be large enough not to saturate at the peak inductor current
(I

) :

PEAK

II (LIR/2)I

=+×

PEAK LOAD(MAX) LOAD(MAX)

⎡⎤
⎣⎦

V

UGATEx
PHASEx

LGATEx

VOUTx

FBx

IN

V

OUTx

R1

R2

The calculation above shall serve a s a general reference.
To further improve the transient response, the output
inductance ca n be reduced even further . This needs to be
considered along with the selection of the output ca pacitor .

Output Capa citor Selection

The capacitor value and ESR determine the amount of
output voltage ripple and loa d tran sient response. Thus,
the capa citor value must be greater tha n the largest value

Figure 4. Setting V

Output Inductor Selection

The switching frequency (on-time) a nd operating point (%
ripple or LIR) determine the inductor value as shown in

with a Resistor V oltage Divider

OUTX

calculated from below equations :

2

()

⎡⎤

⎛⎞

VV

⎢⎥

⎜⎟
⎝⎠

⎣⎦

V

(I ) L K t

Δ×××+

LOAD OFF(MIN)

=

SAG

2C V K t

×× ×× −

OUT OUTx OFF(MIN)

V

OUTx

V

IN

−

IN OUTx

V

IN

the following equation :

(I ) L

()

tVV

×−

ON IN OUTx

L

=

LIR I

×

LOAD(MAX)

DS8223P-01 June 2011 www.richtek.com

V

SOAR

Δ×

=

CV

××

2

2

LOAD
OUT OUTx

21

RT8223P

=× × +

V LIR I ESR

P P LOAD(MAX)

−

⎛⎞
⎜⎟
⎝⎠

where V

SAG

and V

are the allowable amount of

SOAR

1

××

8C f

OUT

undershoot voltage the and overshoot voltage in load
transient, V

is the output ripple voltage, t

p-p

OFF(MIN)

is the

minimum off-time, and K is a factor listed in Table 1.

Thermal Considerations

For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and a mbient temperature. The
maximum power dissipation can be calculated by the
following formula :

P
where T

the ambient te mperature, and θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

JA

is the maximum junction temperature, T

is the junction to ambient

JA

A

thermal resistance.
For recommended operating condition specifications of

the RT8223P , the maxi mum junction temperature is 125°C
and TA is the a mbient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For WQF N­24L 4x4 packages, the thermal resistance, θJA, is 52°C/
W on a standard JEDEC 51-7 f our-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by the following formula :

P

= (125°C − 25°C) / (52°C/W) = 1.923W for

D(MAX)

WQF N-24L 4x4 pa ckage
The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. For the RT8223P pa ck age, the derating
curve in Figure 5 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.

2.1

1.8

1.5

1.2

0.9

0.6

0.3

Four-Layer PCB

Maximum Power Dissipation (W) 1

0.0
0 25 50 75 100 125

Ambient Temper ature ( °C)

Figure 5. Derating Curve f or the RT8223P Pa ckage

Layout Considerations

Layout is very important in high frequency switching
converter designs, the PCB could radiate excessive noise

is

and contribute to the converter instability with improper
layout. Certain points must be considered before starting
a layout using the RT8223P.

` Place the filter capacitor close to the IC, within 12mm

(0.5 inch) if possible.

` Kee p current limit setting network a s close a s possible

to the IC. Routing of the network should avoid coupling
to high voltage switching nodes.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as
short as possible to reduce stray inductance. Use

0.65mm (25mils) or wider trace.

` All sensitive analog traces and components such as

VOUTx, FBx, GND, ENTRIPx, PGOOD, a nd T ONSEL
should be placed away from high voltage switching
nodes such a s PHASEx, LGATEx, UGA TEx, or BOOTx
nodes to avoid coupling. Use internal layer(s) a s ground
plane(s) a nd shield the feedback tra ce from power traces
and components.

22

` Pla ce the ground terminal of VIN capa citor(s), VOUTx

capa citor(s), a nd source of low side MOSFET s a s close
a s possible. The PCB tra ce defined as PHASEX node,
which connects to source of high side MOSFET, drain
of low side MOSFET and high voltage side of the
inductor, should be a s short a nd wide a s possible.

DS8223P-01 June 2011www.richtek.com

Outline Dimension

RT8223P

D

E

A

A3

A1

D2

SEE DETAIL A

1

be

E2

L

1

2

1

2

DETAIL A

Pin #1 ID a nd T ie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 3.950 4.050 0.156 0.159
D2 2.300 2.750 0.091 0.108

E 3.950 4.050 0.156 0.159
E2 2.300 2.750 0.091 0.108

e 0.500 0.020
L 0.350 0.450

Richtek Technology Corporation

Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]

0.014 0.018

W-Type 24L QFN 4x4 Package

Richtek Technology Corporation

Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: [phone] Fax: [phone]
Email: [e-mail]

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

DS8223P-01 June 2011 www.richtek.com

23