QL6500 Eclipse Data Sheet
• • • • • • Combining Performance, Density and Embedded RAM
Device Highlights
Flexible Programmable Logic
•.25 m, Five layer metal CMOS Process
•2.5 V VCC, 2.5 V/3.3 V Drive Capable I/O
•3,032 Logic Cells
•488,064 Max System Gates
•Up to 444 I/O Pins
Embedded Dual Port SRAM
•Thirty six 2,304-bit Dual Port High Performance SRAM Blocks
•82,900 RAM Bits
•RAM/ROM/FIFO Wizard for Automatic Configuration
•Configurable and Cascadable
Programmable I/O
Advanced Clock Network
•Nine Global Clock Networks:
•One Dedicated
•Eight Programmable
•20 Quad-Net Networks: Five per Quadrant
•16 I/O Controls: Two per I/O Bank
Memory - Dual Port RAM
High Speed Logic Cells
488K Gates
Memory - Dual Port RAM
Figure 1: Eclipse Block Diagram
•High performance Enhanced I/O (EIO): Less than 3 ns Tco
•Programmable Slew Rate Control
•Programmable I/O Standards:
•LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3
•Eight Independent I/O Banks
•Three Register Configurations: Input, Output, and Output Enable
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© 2002 QuickLogic Corporation www.quicklogic.com •• 1
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QL6500 Eclipse Data Sheet Rev C
Electrical Specifications
AC Characteristics at VCC = 2.5 V, TA = 25° C (K = 0.74)
The AC Specifications are provided from Table 1 to Table 10. Logic Cell diagrams and waveforms are provided from Figure 2 to Figure 15.
Figure 2: Eclipse Logic Cell
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Table 1: Logic Cells |
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Value (ns) |
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Logic Cells |
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Min |
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Max |
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tPD |
Combinatorial Delay of the longest path: time taken by the combinatorial circuit to |
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0.257 |
output |
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tSU |
Setup time: time the synchronous input of the flip-flop must be stable before the |
0.22 |
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active clock edge |
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tHL |
Hold time: time the synchronous input of the flip-flop must be stable after the active |
0 |
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clock edge |
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tCO |
Clock to out delay: the amount of time taken by the flip-flop to output after the |
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0.255 |
active clock edge. |
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tCWHI |
Clock High Time: required minimum time the clock stays high |
0.46 |
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tCWLO |
Clock Low Time: required minimum time that the clock stays low |
0.46 |
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tSET |
Set Delay: time between when the flip-flop is ”set” (high) |
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0.18 |
and when the output is consequently “set” (high) |
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tRESET |
Reset Delay: time between when the flip-flop is ”reset” (low) and when the output |
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0.09 |
is consequently “reset” (low) |
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tSW |
Set Width: time that the SET signal remains high/low |
0.3 |
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tRW |
Reset Width: time that the RESET signal remains high/low |
0.3 |
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© 2002 QuickLogic Corporation |
• www.quicklogic.com |
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QL6500 Eclipse Data Sheet Rev C
SET
D
Q
CLK
RESET
Figure 3: Logic Cell Flip Flop
CLK
tCWHI (min) |
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tCWLO (min) |
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SET
RESET
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tRESET |
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tSET |
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tRW |
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tSW |
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Figure 4: Logic Cell Flip Flop Timings - First Waveform
CLK
D |
tSU |
tHL |
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Q
tCO
Figure 5: Logic Cell Flip Flop Timings - Second Waveform
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© 2002 QuickLogic Corporation |
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QL6500 Eclipse Data Sheet Rev C
Quad net
Figure 6: Eclipse Global Clock Structure
Table 2: Eclipse Clock Performance
Clock |
Parameters |
Clock Performance |
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Global |
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Dedicated |
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Logic Cells (Internal) |
Clock signal generated internally |
1.51 ns (max) |
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1.59 ns (max) |
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I/O’s (External) |
Clock signal generated externally |
2.06 ns (max) |
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1.73 ns (max) |
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Table 3: Eclipse Global Clock Performance |
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Clock Segment |
Parameter |
Value (ns) |
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tPGCK |
Global clock pin delay to quad net |
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1.34 |
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tBGCK |
Global clock buffer delay |
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0.56 |
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(quad net to flip flop) |
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Programmable Clock
External Clock
tPGCK
Global Clock Buffer
Global Clock
Clock
Select
tBGCK
Figure 7: Global Clock Structure Schematic
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4 • www.quicklogic.com © 2002 QuickLogic Corporation
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QL6500 Eclipse Data Sheet Rev C
[9:0] |
RE |
WA |
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RCLK |
WD |
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WE |
[9:0] |
RA |
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[17:0] |
WCLK |
RD |
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ASYNCRD |
RAM Module |
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Figure 8: RAM Module |
Table 4: RAM Cell Synchronous Write Timing
Symbol |
Parameter |
Value (ns) |
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RAM Cell Synchronous Write Timing |
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Max |
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tSWA |
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the |
0.675 |
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active edge of the WRITE CLOCK |
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tHWA |
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active |
0 |
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edge of the WRITE CLOCK |
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tSWD |
WD setup time to WCLK: time the WRITE DATA must be stable before the active |
0.654 |
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edge of the WRITE CLOCK |
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tHWD |
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge |
0 |
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of the WRITE CLOCK |
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tSWE |
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active |
0.623 |
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edge of the WRITE CLOCK |
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tHWE |
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active |
0 |
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edge of the WRITE CLOCK |
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tWCRD |
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the |
- |
4.38 |
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time when the data is available at RD |
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© 2002 QuickLogic Corporation |
www.quicklogic.com |
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• 5 |
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QL6500 Eclipse Data Sheet Rev C
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WCLK |
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WA |
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tSWA |
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tHWA |
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WD |
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tSWD |
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tHWD |
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WE |
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tSWE |
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tHWE |
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RD |
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old data |
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new data |
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tWCRD |
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Figure 9: RAM Cell Synchronous Write Timing |
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Table 5: RAM Cell Synchronous & Asynchronous Read Timing |
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Symbol |
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Parameter |
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Value (ns) |
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RAM Cell Synchronous Read Timing |
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Min |
Max |
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tSRA |
RA setup time to RCLK: time the READ ADDRESS must be stable before the active |
0.686 |
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edge of the READ CLOCK |
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tHRA |
RA hold time to RCLK: time the READ ADDRESS must be stable after the active |
0 |
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edge of the READ CLOCK |
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tSRE |
RE setup time to WCLK: time the READ ENABLE must be stable before the active |
0.243 |
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edge of the READ CLOCK |
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tHRE |
RE hold time to WCLK: time the READ ENABLE must be stable after the active |
0 |
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edge of the READ CLOCK |
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tRCRD |
RCLK to RD: time between the active READ CLOCK edge and the time when the |
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data is available at RD |
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RAM Cell Asynchronous Read Timing |
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rPDRD |
RA to RD: time between when the READ ADDRESS is input and when the DATA |
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2.06 |
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is output |
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•
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6 • www.quicklogic.com © 2002 QuickLogic Corporation
•
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•
QL6500 Eclipse Data Sheet Rev C
RCLK
RA
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tSRA |
tHRA |
RE |
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tSRE |
tHRE |
RD |
old data |
new data |
tRCRD
rPDRD
Figure 10: RAM Cell Synchronous & Asynchronous Read Timing
INPUT |
Q E |
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REGISTER |
D |
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OUTPUT |
Q |
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D |
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REGISTER |
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R |
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OUTPUT ENABLE |
E Q |
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D |
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REGISTER |
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R |
+
-
PAD
Figure 11: Eclipse Cell I/O
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© 2002 QuickLogic Corporation |
www.quicklogic.com |
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• 7 |
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QL6500 Eclipse Data Sheet Rev C
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tICLK |
tIN, tINI |
tISU |
+
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tSID
Q E
D
R
PAD
Figure 12: Eclipse Input Register Cell
Table 6: Input Register Cell
Symbol |
Parameter |
Value (ns) |
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Input Register Cell Only |
Min |
Max |
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tISU |
Input register setup time: time the synchronous input of the flip-flop must be stable |
3.12 |
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before the active clock edge |
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tIHL |
Input register hold time: time the synchronous input of the flip-flop must be stable |
0 |
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after the active clock edge |
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tICO |
Input register clock to out: time taken by the flip-flop to output after the active clock |
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1.08 |
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edge |
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tIRST |
Input register reset delay: time between when the flip-flop is “reset”(low) and when |
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0.99 |
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the output is consequently “reset” (low) |
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tIESU |
Input register clock enable setup time: time “enable” must be stable before the |
0.37 |
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active clock edge |
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tIEH |
Input register clock enable hold time: time “enable” must be stable after the active |
0 |
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•
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8 • www.quicklogic.com © 2002 QuickLogic Corporation
•
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QL6500 Eclipse Data Sheet Rev C
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R |
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CLK |
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D |
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tISU |
tIHL |
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Q |
tICO |
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E |
tIEH |
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tIESU |
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Table 7: Standard Input Delays |
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Value (ns) |
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Standard Input Delays |
To get the total input delay add this delay to tISU |
Min |
Max |
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tSID (LVTTL) |
LVTTL input delay: Low Voltage TTL for 3.3 V applications |
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0.34 |
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tSID (LVCMOS2) |
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower |
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0.42 |
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applications |
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tSID (GTL+) |
GTL+ input delay: Gunning Transceiver Logic |
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0.68 |
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tSID (SSTL3) |
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V |
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0.55 |
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tSID (SSTL2) |
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V |
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0.61 |
tIRST
Figure 13: Eclipse Input Register Cell Timing
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© 2002 QuickLogic Corporation |
www.quicklogic.com |
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• 9 |
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QL6500 Eclipse Data Sheet Rev C
PAD
OUTPUT
REGISTER
Figure 14: Eclipse Output Register Cell
Table 8: Eclipse Output Register Cell
Symbol |
Parameter |
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Value (ns) |
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Output Register Cell Only |
Min |
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Max |
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tOUTLH |
Output Delay low to high (90% of H) |
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0.40 |
tOUTHL |
Output Delay high to low (10% of L) |
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0.55 |
tPZH |
Output Delay tri-state to high (90% of H) |
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2.94 |
tPZL |
Output Delay tri-state to low (10% of L) |
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2.34 |
tPHZ |
Output Delay high to tri-State |
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3.07 |
tPLZ |
Output Delay low to tri-State |
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2.53 |
tCOP |
Clock to out delay (does not include clock tree delays) |
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3.15 (fast slew) |
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10.2 (slow slew) |
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•
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10 • www.quicklogic.com © 2002 QuickLogic Corporation
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QL6500 Eclipse Data Sheet Rev C
H |
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tOUTHL |
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tOUTLH |
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H |
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H |
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Z |
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tPZL |
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tPZH |
Z |
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L |
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tPLZ |
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Figure 15: Eclipse Output Register Cell Timing |
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Table 9: Output Slew Rates @ VCCIO = 3.3 V |
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Fast Slew |
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Slow Slew |
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Rising Edge |
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2.8 V/ns |
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1.0 V/ns |
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Falling Edge |
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2.86 V/ns |
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1.0 V/ns |
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Table 10: Output Slew Rates @ VCCIO = 2.5 V |
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Fast Slew |
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Slow Slew |
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Rising Edge |
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1.7 V/ns |
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0.6 V/ns |
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Falling Edge |
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1.9 V/ns |
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0.6 V/ns |
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• |
© 2002 QuickLogic Corporation |
www.quicklogic.com |
• |
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• 11 |
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• |
QL6500 Eclipse Data Sheet Rev C
DC Characteristics
The DC Specifications are provided in Table 11 through Table 13.
Table 11: Absolute Maximum Ratings
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Parameter |
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Value |
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Parameter |
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Value |
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VCC Voltage |
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-0.5 V to 3.6 V |
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DC Input Current |
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±20 mA |
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VCCIO Voltage |
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-0.5 V to 4.6 V |
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ESD Pad Protection |
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±2000 V |
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INREF Voltage |
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2.7 V |
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Leaded Package |
-65° C to + 150° C |
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Storage Temperature |
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Input Voltage |
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-0.5 V to VCCIO +0.5 V |
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Laminate Package (BGA) |
-55° C to + 125° C |
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Latch-up Immunity |
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±100 mA |
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Storage Temperature |
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Table 12: Operating Range |
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Symbol |
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Parameter |
Military |
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Industrial |
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Commercial |
Unit |
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Min |
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Max |
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Min |
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Max |
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Min |
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Max |
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VCC |
Supply Voltage |
2.3 |
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2.7 |
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2.3 |
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2.7 |
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2.3 |
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2.7 |
V |
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VCCIO |
I/O Input Tolerance Voltage |
2.3 |
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3.6 |
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2.3 |
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3.6 |
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2.3 |
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3.6 |
V |
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TA |
Ambient Temperature |
-55 |
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-40 |
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85 |
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0 |
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70 |
°C |
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TC |
Case Temperature |
- |
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125 |
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- |
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- |
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°C |
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-4 Speed Grade |
0.42 |
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2.3 |
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0.43 |
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2.16 |
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0.47 |
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2.11 |
n/a |
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K |
Delay Factor |
-5 Speed Grade |
0.42 |
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1.92 |
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0.43 |
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1.80 |
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0.46 |
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1.76 |
n/a |
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-6 Speed Grade |
0.42 |
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1.35 |
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0.43 |
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1.26 |
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0.46 |
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1.23 |
n/a |
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-7 Speed Grade |
0.42 |
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1.27 |
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0.43 |
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1.19 |
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0.46 |
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1.16 |
n/a |
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Table 13: DC Characteristics
Symbol |
Parameter |
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Conditions |
Min |
Max |
Units |
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II |
I or I/O Input Leakage Current |
VI = VCCIO or GND |
-10 |
10 |
µA |
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IOZ |
3-State Output Leakage Current |
VI = VCCIO or GND |
-10 |
10 |
µA |
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CI |
Input Capacitancea |
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- |
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- |
8 |
pF |
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I |
Output Short Circuit Currentb |
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Vo = GND |
-15 |
-180 |
mA |
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OS |
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Vo = VCC |
40 |
210 |
mA |
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I |
CC |
D.C. Supply Currentc |
V |
V = V |
CCIO |
or GND |
0.50 (typ) |
2 |
mA |
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I, |
o |
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ICCIO |
D.C. Supply Current on VCCIO |
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- |
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0 |
2 |
mA |
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ICCIO(DIF) |
D.C. Supply Current on VCCIO |
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- |
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- |
- |
mA |
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for Differential I/O |
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IREF |
D.C. Supply Current on INREF |
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- |
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-10 |
10 |
µA |
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IPD |
Pad Pull-down (programmable) |
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VCCIO = 3.6 V |
- |
150 |
µA |
a.Capacitance is sample tested only. Clock pins are 12 pF maximum.
b.Only one output at a time. Duration should not exceed 30 seconds.
c.For -4/-5/-6/-7 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices, and 5 mA for all military grade devices.
•
•
12 • www.quicklogic.com © 2002 QuickLogic Corporation
•
•
•