QUICK LOGIC QL6325-E-6PQ208C, QL6325-E-6PQ208I, QL6325-E-6PQ208M, QL6325-E-6PS484C, QL6325-E-6PS484I Datasheet

www.quicklogic.com

•

Preliminary

1

• • • • • •

Device Highlights

Flexible Programmable Logic

• 0.18

µ

m six layer metal CMOS Process

• 1.8/2.5/3.3 V Drive Capable I/O

• 1,536 Logic Cells

• 320,640 Max System Gates

•

Up to 310 I/O Pins

Embedded Dual Port SRAM

• Twenty-four 2,304-bit Dual Port High

Performance SRAM Blocks

• 55,300 RAM bits

• RAM/ROM/FIFO Wizard for Automatic

Configuration

• Configurable and Cascadable

Programmable I/O

• High performance Enhanced I/O (EIO)—

less than 3 ns Tco

• Programmable Slew Rate Control

• Programmable I/O Standards:

• LVTTL, LVCMOS, PCI, GTL+, SSTL2,

and SSTL3

• Eight Independent I/O Banks

• Three Register Configurations: Input,

Output, and Output Enable

Advanced Clock Network

• Nine Global Clock Networks:

• One Dedicated

• Eight Programmable

• 20 Quad-Net Networks—five per Quadrant

• 16 I/O Controls—two per I/O Bank

• Four phase locked loops

Embedded Computational Units

12 ECUs provide integrated Multiply, Add, and Accumulate Functions.

Figure 1: QL6325-E Eclipse-E Block

Diagram

Embedded RAM BlocksPLL PLL

Fabric

12 Embeded Computational Units

Embedded RAM BlocksPLL PLL

FPGA Combining Performance, Density, and Embedded RAM

QL6325-E Eclipse-E Data Sheet

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

2

Electrical Specifications

AC Characteristics*

*at VCC = 2.5 V, TA = 25° C, Worst Case Corner, Speed Grade = -7 (K = 1.16) The AC Specifications are provided from Table 1 to Table 10. Logic Cell diagrams and

waveforms are provided from Figure 2 to Figure 15.

Figure 2: Eclipse-E Logic Cell

Table 1: Logic Cells

Symbol Parameter Value

Logic Cells Min Max

t

PD

Combinatorial Delay of the longest path: time taken by th e combinatorial circuit to output

- 0.257 ns

t

SU

Setup time: time the synchronous input of the flip-flop must be stable before the active clock edge

0.22 ns -

t

HL

Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge

0 ns -

t

CO

Clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge.

- 0.255 ns

t

CWHI

Clock High Time: required minimum time the clock stays high 0.46 ns -

t

CWLO

Clock Low Time: required minimum time that the clock stays low 0.46 ns -

t

SET

Set Delay: time between when the flip-flop is ”set” (high) and when the output is consequently “set” (high)

- 0.18 ns

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

3

Figure 3: Logic Cell Flip-Flop

Figure 4: Logic Cell Flip-Flop Timings—First Waveform

t

RESET

Reset Delay: time between when the flip-flop is ”reset” (low) and when the output is consequently “reset” (low)

- 0.09 ns

t

SW

Set Width: time that the SET signal remains high/low 0.3 ns -

t

RW

Reset Width: time that the RESET signal remains high/low 0.3 ns -

Table 1: Logic Cells (Continued)

Symbol Parameter Value

Logic Cells Min Max

SET

D

CLK

RESET

Q

SET

RESET

Q

CLK

t

CWHI

(min)

t

CWLO

(min)

t

RESET

t

RW

t

SET

t

SW

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

4

Figure 5: Logic Cell Flip-Flop Timings—Second Waveform

Figure 6: Eclipse-E Global Clock Structure

Table 2: Eclipse-E Clock Delay

Clock Source Parameters Clock Performance

Global Dedicated

Logic Cells (Internal) Clock signal generated internally 1.51 ns (max)

Clock Pad Clock signal generated externally 2.06 ns (max) 1.73 ns (max)

CLK

D

Q

t

SU

t

HL

t

CO

Quad net

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

5

Figure 7: Global Clock Structure Schematic

Figure 8: RAM Module

Table 3: Eclipse-E Global Clock Delay

Clock Segment Parameter Value

Min Max

t

PGCK

a

a. When using a PLL, t

PGCK

and t

BGCK

are effectively zero due to delay adjustment by

Phase Locked Loop.

Global clock pin delay to quad net - 1.34 ns

t

BGCK

Global clock tree delay (quad net to flip-flop)

- 0.56 ns

Programmable Clock

External Clock

Global Clock Buffer

Global Clock

t

PGCK

t

BGCK

Clock Select

WA

WD

WE

WCLK

RE

RCLK

RA

RD

RAM Module

[9:0]

[17:0]

[9:0]

[17:0]

ASYNCRD

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

6

Figure 9: RAM Cell Synchronous Write Timing

Table 4: RAM Cell Synchronous Write Timing

Symbol Parameter Value

RAM Cell Synchronous Write Timing Min Max

t

SWA

WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK

0.675 ns -

t

HWA

WA hold t ime to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK

0 ns -

t

SWD

WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK

0.654 ns -

t

HWD

WD hold time to WCLK: time the WRITE DA T A must be stable after t he active edge of the WRITE CLOCK

0 ns -

t

SWE

WE setup time to WCLK: time the WRITE ENABLE must be stable before th e active edge of the WRITE CLOCK

0.623 ns -

t

HWE

WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK

0 ns -

t

WCRD

WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD

- 4.38 ns

t

SWA

t

SWD

t

SWE

t

HWA

t

HWD

t

HWE

t

WCRD

old data

new data

WCLK

WA

WD

WE

RD

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

7

Figure 10: RAM Cell Synchronous & Asynchronous Read Timing

Table 5: RAM Cell Synchronous & Asynchronous Read Timing

Symbol

RAM Cell Synchronous Read Timing Value

Parameter Min Max

t

SRA

RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK

0.686 ns -

t

HRA

RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK

0 ns -

t

SRE

RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK

0.243 ns -

t

HRE

RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK

0 ns -

t

RCRD

RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD

- 4.38 ns

RAM Cell Asynchronous Read Timing

r

PDRD

RA to RD: time between when the READ ADDRESS is input and when the DATA is output

- 2.06 ns

t

SRA

t

HRA

RCLK

RA

t

SRE

t

HRE

t

RCRD

old data

new data

RE

RD

r

PDRD

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

8

Figure 11: Eclipse-E Cell I/O

Figure 12: Eclipse-E Input Register Cell

E

R

Q

D

R

Q

E

R

Q

D

+

-

PAD

OUTPUT ENABLE

REGISTER

OUTPUT

REGISTER

INPUT

REGISTER

D

PAD

t

ISU

t

SID

+

-

Q

E

D

R

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

9

Table 6: Input Register Cell

Symbol Parameter: Input Register Cell Only

Value

Min Max

t

ISU

Input register setup time: the time the synchronous input of the flip-flop must be stable before the active clock edge

2.50 ns -

t

IHL

Input register hold time: the time the synchronous input of the flip-flop must be stable after the active clock edge

0 ns -

t

ICO

Input register clock-to-out: the time taken by the flip-flop to output after the active clock edge

- 1.08 ns

t

IRST

Input register reset delay: the time between when the flip-flop is “reset”(low) and when the output is consequently “reset” (low)

- 0.99 ns

t

IESU

Input register clock enable setup time: the time “enable” must be stable before the active clock edge

0.37 ns -

t

IEH

Input register clock enable hold time: the time “enable” must be stable after the active clock edge

0 ns -

Table 7: Standard Input Delays

Symbol Parameter Value

Standard Input Delays To get the total input delay add this delay to tISU Min Max

t

SID

(LVTTL) LVTTL input delay: Low Voltage TTL for 3.3 V applications - 0.34 ns

t

SID

(LVCMOS2)

LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications

- 0.42 ns

t

SID

(LVCMOS18) LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications - t

SID

(GTL+) GTL+ input delay: Gunning Transceiver Logic - 0.68 ns

t

SID

(SSTL3) SSTL3 input delay: Stub Series Terminated Logic for 3.3 V - 0.55 ns

t

SID

(SSTL2) SSTL2 input delay: Stub Series Terminated Logic for 2.5 V - 0.61 ns

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

10

Figure 13: Eclipse-E Input Register Cell Timing

Figure 14: Eclipse-E Output Register Cell

R

CLK

D

Q

ISU IHL

ICO

IESU

IEH

IRST

E

t

PAD

OUTPUT

REGISTER

www.quicklogic.com

•

QL6325-E Eclipse-E Data Sheet Rev A

Preliminary

11

Figure 15: Eclipse-E Output Register Cell Timing

Table 8: Eclipse-E Output Register Cell

Symbol Parameter Value

Output Register Cell Only Min Max

t

OUTLH

Output Delay low to high (90% of H) - 0.40 ns

t

OUTHL

Output Delay high to low (10% of L) - 0.55 ns

t

PZH

Output Delay tri-state to high (90% of H) - 2.94 ns

t

PZL

Output Delay tri-state to low (10% of L) - 2.34 ns

t

PHZ

Output Delay high to tri-State - 3.07 ns

t

PLZ

Output Delay low to tri-State - 2.53 ns

t

COP

Clock-to-out delay (does not include clock tree delays) -

3.15 ns (fast slew)

10.2 ns (slow slew)

Table 9: Output Slew Rates @ V

CCIO

= 3.3 V

Fast Slew Slow Slew

Rising Edge 2.8 V/ns 1.0 V/ns Falling Edge 2.86 V/ns 1.0 V/ns

Table 10: Output Slew Rates @ V

CCIO

= 2.5 V

Fast Slew Slow Slew

Rising Edge 1.7 V/ns 0.6 V/ns Falling Edge 1.9 V/ns 0.6 V/ns

L

H

L

H

t

OUTLH

t

OUTHL

L

H

Z

t

PZH

L

H

Z

t

PZL

L

H

Z

t

PLZ

L

H

Z

t

PHZ