QUICK LOGIC QL2003-2PF100I, QL2003-2PF144C, QL2003-2PF144I, QL2003-2PL84C, QL2003-2PL84I Datasheet

	QL2003
	3.3V and 5.0V pASIC® 2 FPGA
	Combining Speed, Density, Low Cost and Flexibility
	Rev. C
pASIC 2	Ultimate Verilog/VHDL Silicon Solution
HIGHLIGHTS	-Abundant, high-speed interconnect eliminates manual routing
	-Flexible logic cell provides high efficiency and performance
	-Design tools produce fast, efficient Verilog/VHDL synthesis
	Speed, Density, Low Cost and Flexibility in One Device
	-16-bit counter speeds exceeding 200 MHz
… 3,000	-3,000 usable ASIC gates, 5,000 usable PLD gates, 118 I/Os
usable ASIC gates,	-3-layer metal ViaLink® process for small die sizes
118 I/O pins	-100% routable and pin-out maintainable
	Advanced Logic Cell and I/O Capabilities
	-Complex functions (up to 16 inputs) in a single logic cell
	-High synthesis gate utilization from logic cell fragments
	-Full IEEE Standard JTAG boundary scan capability
	-Individually-controlled input/feedback registers and OEs on all I/O pins
	Other Important Family Features
	-3.3V and 5.0V operation with low standby power
	-I/O pin-compatibility between different devices in the same packages
	-PCI compliant (at 5.0V), full speed 33 MHz implementations
	-High design security provided by security fuses
QL2003
Block Diagram
192
Logic
Cells
	3-5

3

2 pASIC

QL2003

PRODUCT The QL2003 is a 3,000 usable ASIC gate, 5,000 usable PLD gate member of SUMMARY the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices.

The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.

The QL2003 contains 192 logic cells. With 118 maximum I/Os, the QL2003 is available in 84-PLCC, 100-pin TQFP and 144-pin TQFP packages.

Software support for the complete pASIC families, including the QL2003, is available through three basic packages. The turnkey QuickWorks® package provides the most complete FPGA software solution from design entry to logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The QuickToolsTM and QuickChipTM packages provide a solution for designers who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other thirdparty tools for design entry, synthesis, or simulation.

FEATURES

Total of 118 I/O Pins

-110 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades

-4 high-drive input-only pins

-4 high-drive input/distributed network pins

Four Low-Skew (less than 0.5ns) Distributed Networks

-Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin

-Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback

High Performance

-Input + logic cell + output delays under 6 ns

-Datapath speeds exceeding 225 MHz

-Counter speeds over 200 MHz

3-6

QL2003

PINOUT DIAGRAM

84-PIN PLCC

3

2 pASIC

3-7