QUICK LOGIC QL4058-1PB456M, QL4058-1PQ208C, QL4058-1PQ208I, QL4058-1PQ208M, QL4058-1PQ240C Datasheet

QL4058 QuickRAM Data Sheet

• • • • • •

58,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM

Device Highlights

High Performance & High Density

• 58,000 Usable PLD Gates with 252 I/Os

• 300 MHz 16-bit Counters, 400 MHz

Datapaths, 160+ MHz FIFOs

• 0.35 µm four-layer metal non-volatile

CMOS process for smallest die sizes

High Speed Embedded SRAM

• 18 dual-port RAM modules, organized in

user-configurable 1,152 bit blocks

• 5 ns access times, each port independently

accessible

• Fast and efficient for FIFO, RAM, and ROM

functions

Easy to Use / Fast Developm ent
Cycles

• 100% routable with 100% utilization and

complete pin-out stability

• Variable-grain logic cells provide high

performance and 100% utilization

• Comprehensive design tools include high

quality Verilog/VHDL synthesis

Advanced I/O Capabilities

• Interfaces with both 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V busses

for -1/-2/-3/-4 speed grades

• Full JTAG boundary scan

• I/O Cells with individually controlled

Registered Input Path and Output Enables

18

RA M

Blocks

Figure 1: QuickRAM Block Diagram

Hi gh Sp eed

Logic Cells

Interface

1,008

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

•

1

•

•

•

QL4058 QuickRAM Data Sheet Rev H

Architecture Overview

The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in
combination with Dual-Port SRAM modules. The QL4058 is a 58,000 usable PLD gate

member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35 µm

four-layer metal process using QuickLogic's patented ViaLink
unique combination of high performance, high density, low cost, and extreme ease-of-use.

The QL4058 contains 1,008 logic cells and 18 Dual Port RAM modules (see Figure 1). Each
RAM module has 1,152 RAM bits, for a total of 20,736 bits. RAM Modules are Dual Port
(one read port, one write port) and can be configured into one of four modes:
64 (deep) × 18 (wide), 128 × 9, 256 × 4, or 512 × 2 (see
252 I/Os, the QL4058 is available in 208-PQFP, 240-pin PQFP, and 456-pin PBGA
packages.

Designers can cascade multiple RAM modules to increase the depth or width allowed in
single modules by connecting corresponding address lines together and dividing the words
between modules (see
large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device.

TM

technology to provide a

Figure 4). With a maximum of

Figure 2). This approach allows up to 512-deep configurations as

Software support for the complete QuickRAM family, including the QL4058, is available
through two basic packages. The turnkey QuickWorks

TM

package provides the most
complete ESP software solution from design entry to logic synthesis, to place and route, to
simulation. The QuickTools package provides a solution for designers who use Cadence,
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for
design entry, synthesis, or simulation.

The QuickLogic

TM

variable grain logic cell features up to 16 simultaneous inputs and five
outputs within a cell that can be fragmented into five independent cells. Each cell has a fan­in of 29 including register and control lines (see

RAM

Module

(1,152 bits)

WADDR

RAM

Module

(1,152 bits)

WDATA

Figure 3).

RDATAWDATA

RADDR

RDATA

•

•

www.quicklogic.com

•

2

•

•

•

Figure 2: QuickRAM Module Bits

© 2002 QuickLogic Corporation

Product Summary

Total of 252 I/O Pins

• 244 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

• 8 high-drive input/distributed network pins

Eight Low-Skew Distributed Networks

• Two array clock/control networks available to the logic cell flip-flop clock, set and reset

inputs—each driven by an input-only pin

• Six global clock/control networks available to the logic cell F1, clock, set and reset inputs

and the input and I/O register clock, reset and enable inputs as well as the output enable
control—each driven by an input-only or I/O pin, or any logic cell output or I/O cell
feedback

High Performance Silicon

• Input + logic cell + output total delays = under 6 ns

• Data path speeds over 400 MHz

• Counter speeds over 300 MHz

• FIFO speeds over 160+ MHz

QL4058 QuickRAM Data Sheet Rev H

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

3

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

•

•

www.quicklogic.com

•

4

•

•

•

© 2002 QuickLogic Corporation

QL4058 QuickRAM Data Sheet Rev H

Electrical Specifications

AC Characteristic s at VCC = 3.3 V, TA = 25°C (K = 1.00)

To calculate delays, multiply the appropriate K factor from Table 10: Operating Range by the
following numbers in the tables provided.

QS

A1
A2
A3
A4
A5
A6

QS
OP
B1
B2
C1

C2
MP
MS

D1
D2
E1
E2
NP
NS

F1
F2
F3
F4
F5
F6

QC
QR

AZ

OZ

QZ

NZ

FZ

Figure 3: QuickRAM Logic Cell

Table 1: Logic Cell

Symbol Parameter

t

PD

t

SU

t

H

t

CLK

t

CWHI

t

CWLO

t

SET

t

RESET

t

SW

t

RW

Combinatorial Delay

Setup Time

a

Hold Time 0.0 0.0 0.0 0.0 0.0

Clock to Q Delay 0.7 1.0 1.2 1.5 2.5

Clock High Time 1.2 1.2 1.2 1.2 1.2

Clock Low Time 1.2 1.2 1.2 1.2 1.2

Set Delay 1.0 1.3 1.5 1.8 2.8

Reset Delay 0.8 1.1 1.3 1.6 2.6

Set Width 1.9 1.9 1.9 1.9 1.9

Reset Width 1.8 1.8 1.8 1.8 1.8

a

a. These limits are derived from a representative selection of the slowest paths through the

QuickRAM logic c ell incl uding ty pical ne t delays . Worst cas e delay values for spec ific path s should
be determined from timing analysis of your particular design.

Propagation Delays (ns)

Fanout (5)

1 2 3 4 5

1.4 1.7 1.9 2.2 3.2

1.7 1.7 1.7 1.7 1.7

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

5

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

[8:0]

[17:0]

[1:0]

Table 2: RAM Cell Synchronous Write Timing

Symbol Parameter

t

SWA

t

HWA

t

SWD

t

HWD

t

SWE

t

HWE

t

WCRD

WA Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0

WA Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0

WD Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0

WD Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0

WE Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0

WE Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0

WCLK to RD (WA=RA)

WA

WD

WE

WCLK

RE

RCLK

RA

RD

MODE ASYNCRD

Figure 4: QuickRAM Module

1 2 3 4 5

a

5.0 5.3 5.6 5.9 7.1

[8:0]

[17:0 ]

Propagation Delays (ns)

Fanout

•

•

www.quicklogic.com

•

6

•

•

•

a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and

TA = 25

°C. Multiply by the appropr iate Delay Factor, K, for speed gra de, volta ge and tempe ratu re

settings as specified in the Operating Range.

Table 3: RAM Cell Synchronous Read Timing

Symbol Parameter

Propagation Delays (ns)

Fanout

Logic Cells 1 2 3 4 5

t

SRA

t

HRA

t

SRE

t

HRE

t

RCRD

RA Setup Time to RCLK 1.0 1.0 1.0 1.0 1.0

RA Hold Time to RCLK 0.0 0.0 0.0 0.0 0.0

RE Setup Time to RCLK 1.0 1.0 1.0 1.0 1.0

RE Hold Time to RCLK 0.0 0.0 0.0 0.0 0.0

RCLK to RD

a

4.0 4.3 4.6 4.9 6.1

a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and

TA = 25

°C. Multiply by the appropr iate Delay Factor, K, for speed gra de, volta ge and tempe ratu re

settings as specified in the Operating Range.

© 2002 QuickLogic Corporation

QL4058 QuickRAM Data Sheet Rev H

Table 4: RAM Cell Asynchronous Read Timing

Symbol Parameter

Propagation Delays (ns)

Fanout

1 2 3 4 5

RPDRD RA to RD

a

3.0 3.3 3.6 3.9 5.1

a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and

TA = 25

°C. Multiply by the appropr iate Delay Factor, K, for speed gra de, volta ge and tempe ratu re

settings as specified in the Operating Range.

Table 5: Input-Only / Clock Cells

Symbol Parameter

Propagation Delays (ns)

Fanout

1 2 3 4 8 12 24

t

IN

t

INI

t

ISU

t

IH

t

ICLK

t

IRST

t

IESU

t

IEH

High Drive Input Delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4

High Drive Input, Inverting Delay 1.6 1.7 .19 2.0 2.5 3.0 4.5

Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1 3.1

Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0

Input Register Clock To Q 0.7 0.8 1.0 1.1 1.6 2.1 3.6

Input Register Reset Delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5

Input Register Clock Enable Setup Time 2.3 2.3 2.3 2.3 2.3 2.3 2.3

Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0

Symbol Parameter

t

ACK

t

GCKP

t

GCKB

a. The array dist ribu ted ne tw ork s co nsi st of 40 ha lf columns and the glo bal d is tributed networks con-

sist of 44 half columns, each driven by an independent buffer. The number of half columns used
does not affect clo ck buffer delay . The arra y clock has up to eight loads per ha lf column. The global
clock has up to 11 loads per half column.

© 2002 QuickLogic Corporati on

Table 6: Clock Cells

Propagation Delays (ns)

Fanout

a

1 2 3 4 8 10 11

Array Clock Delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7

Global Clock Pin Delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7

Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3

www.quicklogic.com

•

•

7

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

Table 7: I/O Cell Input Delays

Symbol Parameter

Propagation Delays (ns)

1 2 3 4 8 10

t

I/O

t

ISU

t

IH

t

IOCLK

t

IORST

t

IESU

t

IEH

Input Delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6

Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1

Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0

Input Register Clock to Q 0.7 1.0 1.2 1.5 2.5 3.0

Input Register Reset Delay 0.6 0.9 1.1 1.4 2.4 2.9

Input Register Clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3

Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0

a. Stated timing for worst case Propagation Delay over process variation at V

TA = 25

°C. Multiply by the appropr iate Delay Factor, K, for speed gra de, volta ge and tempe ratu re

settings as specified in the Operating Range.

Table 8: I/O Cell Output Delays

Symbol Parameter

Propagation Delays (ns)

Output Load Capacitance (pF)

3 50 75 100 150

t

OUTLH

t

OUTHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Output Delay Low to High 2.1 2.5 3.1 3.6 4.7

Output Delay High to Low 2.2 2.6 3.2 3.7 4.8

Output Delay Tri-state to High 1.2 1.7 2.2 2.8 3.9

Output Delay Tri-state to Low 1.6 2.0 2.6 3.1 4.2

Output Delay High to Tri-state

Output Delay High to Tri-state

a

a

2.0 - - - -

1.2 - - - -

Fanout

= 3.3 V and

CC

a

•

•

www.quicklogic.com

•

8

•

•

•

a. These loads are used for t

1ΚΩ

(see Figure 5)

PXZ

tPHZ

5 pF

Figure 5: Loads used for t

1ΚΩ

tPLZ

5 pF

PXZ

© 2002 QuickLogic Corporation

DC Characteristics

The DC specifications are provided in the tables below.

Parameter Value Parameter Value

VCC Voltage -0.5 V to 4.6 V DC Input Current ±20 mA

V

Voltage -0.5 V to 7.0 V ESD Pad Protection ±2000 V

CCIO

Input Voltage -0.5 V to V

Latch-up Immunity ±200 mA Lead Temperature 300°C

Symbol Parameter Military Industrial Commercial Unit

V

CC

V

CCIO

TA Ambient Temperature -55 - -40 85 0 70 °C

TC Case Temperature - 125 - - - - °C

Supply Voltage 3.0 3.6 3.0 3.6 3.0 3.6 V

I/O Input Tolerance Voltage 3.0 5.5 3.0 5.5 3.0 5.25 V

QL4058 QuickRAM Data Sheet Rev H

Table 9: Absolute Maximum Ratings

+0.5 V Storage Temperat ure -65°C to +150°C

CCIO

Table 10: Operating Range

Min Max Min Max Min Max

K Delay Factor

-0 Speed Grade 0.42 2.03 0.43 1.90 0.46 1.85 n/a

-1 Speed Grade 0.42 1.64 0.43 1.54 0.46 1.50 n/a

-2 Speed Grade 0.42 1.37 0.43 1.28 0.46 1.25 n/a

-3 Speed Grade 0.43 0.90 0.46 0.88 n/a

-4 Speed Grade 0.43 0.82 0.46 0.80 n/a

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

9

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

Symbol Parameter Conditions Min Max Units

Table 11: DC Characteristics

VIH Input HIGH Voltage 0.5 V

CCVCCIO

VIL Input LOW Voltage -0.5 0.3 V

+ 0.5 V

CC

V

IOH = -12 mA 2.4 V

VOH Output HIGH Voltage

IOH = -500 µA 0.9VCC V

IOL = 16 mA

a

0.45 V

VOL Output LOW Voltage

IOL = 1.5 mA 0.1 V

II I or I/O Input Leakage Current VI = V

IOZ 3-State Output Leakage Current VI = V

CI Input Capacitance

IOS Output Short Circuit Current

b

c

VO = GND -15 -180 mA

CC

or GND -10 10 µA

CCIO

or GND -10 10 µA

CCIO

10 pF

V

VO = VCC 40 210 mA

ICC D.C. Supply Current

d

VI, VIO = V

or GND 0.50 (typ) 2 mA

CCIO

ICCIO D.C. Supply Current on VCCIO 0 100 µA

a. Applies only to -1/-2/-3/-4 com mercial grade devices . These s peed gra des are also PCI-com plia nt. All

other devices have 8 mA IOL specifications.
b. Capacitance is sample tested only. Clock pins are 12 pF maximum.
c. Only one output at a time. Duration should not exceed 30 seconds.
d. For -1/-2/-3/-4 commerc ial gra de devices only. Ma xi mu m I CC is 3 m A for -0 commercial grade a nd all

industrial grade de vices and 5 m A for all mil itary grade d evices. For AC conditions, c ontact Qui ckLogic

customer applications group (see Contact Information)

•

•

www.quicklogic.com

•

10

•

•

•

© 2002 QuickLogic Corporation

Kv and Kt Graphs

1.1000

1.0800

1.0600

1.0400

1.0200

Kv

1.0000

0.9800

0.9600

0.9400

0.9200

QL4058 QuickRAM Data Sheet Rev H

Voltage Factor vs. Supply Voltage

3 3.1 3.2 3.3 3.4 3.5 3.6

Supply Voltage (V)

Figure 6: Voltage Factor vs. Supply Voltage

Temper ature Factor vs. Ope ra ting Te mpe ratur e

1.15

1.10

1.05

Kt

-60 -40 -20 0 20 40 60 80

1.00

0.95

0.90

0.85

Junction Tem per ature C

Figure 7: Temperature Factor vs. Operating Temperature

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

11

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

V

CC

V

CCIO

Internal Logic

Cells, RAM

blocks, etc

IO Cells

Power-up Sequencing

V

CCIO

V

CC

Voltage

(V

CCIO

-VCC)

MAX

400 us

Time

V

CC

Figure 8: Power-up Requirements

The following requirements must be met when powering up the device (see Figure 8):

• When ramping up the power supplies keep (V

CCIO

-VCC)

≤ 500 mV. Deviation from

MAX

this recommendation can cause permanent damage to the device.

• V

• The power supply must take greater than or equal to 400 µs to reach VCC. Ramping

An internal diode is present in-between VCC and V

must lead VCC when ramping the device.

CCIO

to VCC/V

earlier than 400 µs can cause the device to behave improperly.

CCIO

, as shown in Figure 9.

CCIO

•

•

www.quicklogic.com

•

12

•

•

•

Figure 9: Internal Diode Between VCC and VCCIO

© 2002 QuickLogic Corporation

JTAG

QL4058 QuickRAM Data Sheet Rev H

TCK

TMS

TRSTB

RDI

TAp Controller
State Machine

(16 States)

Mux

Instruction Decode

&

Control Logic

Instruction Register

Boundary-Scan Register

(Data Register)

Internal

Register

User Defined Data Register

I/O Registers

Figure 10: JTAG Block Diagram

Bypass

Register

Mux

TDO

Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design
challenges. One of these challenges concerns the accessibility of test points. The Joint Test
Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard

1149.1, the Standard Test Access Port and Boundary Scan Architecture.

The JTAG boundary scan test methodology allows complete observation and control of the
boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port
(TAP) controller works in concert with the Instruction Register (IR); these allow users to run
three required tests, along with several user-defined tests.

JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse
subsystem tests for fuller verification of higher level system elements.

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

13

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

The JTAG 1149.1 standard requires the following three tests:

• Extest Instruction. The Extest instruction performs a PCB interconnect test. This test

places a device into an external boundary test mode, selecting the boundary scan
register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO)
pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload
Instruction), and input boundary cells capture the input data for analysis.

• Sample/Preload Instruction. This instruction allows a device to remain in its

functional mode, while selecting the boundary scan register to be connected between
the TDI and TDO pins. For this test, the boundary scan register can be accessed via a
data scan operation, allowing users to sample the functional data entering and leaving
the device.

• Bypass Instruction. The Bypass instruction allows data to skip a device's boundary

scan entirely, so the data passes through the bypass register. The Bypass instruction
allows users to test a device without passing through other devices. The bypass register
connects the TDI and TDO pins, allowing serial data to be transferred through a device
without affecting the operation of the device.

•

•

www.quicklogic.com

•

14

•

•

•

© 2002 QuickLogic Corporation

Pin Descriptions

Pin Function Description

TDI/RSI

TRSTB/RRO

TMS Test Mode Select for JTAG

Table 12: Pin Descriptions

Test Data In for JTAG /RAM
init. Serial Data In

Active low Reset for JTAG
/RAM init. reset out

QL4058 QuickRAM Data Sheet Rev H

Hold HIGH during normal operation. Connects to
serial PROM data in for RAM initialization. Connect

if unused.

to V

CC

Hold LOW during normal operation. Connects to
serial PROM reset for RAM initialization. Connect to
GND if unused.

Hold HIGH during normal operation. Connect to
VCC if not used for JTAG.

TCK Test Clock for JTAG

TDO/RCO

STM Special Test Mode Must be grounded during normal operation.

I/ACLK

I/GCLK

I High-drive input Use for input signals with high fanout.

I/O Input/Output pin Can be configured as an input and/or output.

VCC Power supply pin Connect to 3.3 V supply.

VCCIO Input voltage tolerance pin

GND Ground pin Connect to ground.

GND/THERM Ground/Thermal pin

Test data out for JTAG /RAM
init. clock out

High-drive input and/or array
network driver

High-drive input and/or global
network driver

Hold HIGH or LOW during normal operation.
Connect to V

Connect to serial PROM clock for RAM
initialization. Must be left unconnected if not used for
JTAG or RAM initialization.

Can be configured as either or both.

Can be configured as either or both.

Connect to 5.0 V supply if 5 V input tolerance is
required, otherwise connect to 3.3 V supply.

Available on 456-PBGA only. Connect to ground
plane on PCB if heat sinking desired. Otherwise may
be left unconnected.

or ground if not used for JTAG.

CC

Ordering Information

QuickLogic device
QuickRAM device

part number

Speed Grade
0 = Quick
1 = Fast
2 = Faster
3 = Faster
*4 = Wow

* Contact QuickLogic regarding availabliity

© 2002 QuickLogic Corporati on

QL 4058 - 1 PQ208 C

Operating Range
C = Commercial
I = Industrial
M = Military

Package Code
PQ208 = 208-pin PQFP
PQ240 = 240-pin PQFP
PB456 = 456-pin PBGA

www.quicklogic.com

•

•

15

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

208 and 240 PQFP Pinout Diagrams

Pin 1

QuickRAM

QL4058-1PQ208C

Pin 53 Pin 105

Figure 11: Top View of 208 Pin PQFP

Pin 1

Pin 157

Pin 181

•

•

www.quicklogic.com

•

16

•

•

•

Pin 61

QuickRAM

QL4058-1PQ240C

Pin 121

Figure 12: Top View of 240 Pin PQFP

© 2002 QuickLogic Corporation

208 and 240 PQFP Pinout Table

Table 13: 208/240 PQFP Pinout Table

240

PQFP

PQFP

1208
2 1
32
4 3
54
6 5
7NC
8 6
97

10 8
11 9
12 10
13 11
14 12
15 13
16 14
17 NC
18 15
19 16
20 17
21 18
22 19
23 20
24 NC
25 21
26 22
27 23
28 24
29 25
30 26
31 27
32 28
33 29
34 30
35 31
36 32
37 NC
38 33
39 NC
40 34
41 35
42 36
43 NC
44 37
45 38
46 39
47 NC
48 40
49 41
50 42

208

Function

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

VCC

I/O

GND

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

GND

I/O

GCLK/I

ACLK/I

VCC
GCLK/I
GCLK/I

VCC

I/O
I/O

GND

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

VCC

I/O

240

PQFP

51 43
52 44
53 45
54 46
55 47
56 48
57 NC
58 49
59 50

60 51
NC 52
NC 53

61 54

62 NC

63 NC

64 55

65 56

66 NC

67 57

68 58

69 59

70 60

71 61

72 62

73 63

74 64

75 NC

76 65

77 66

78 67

79 NC

80 68

81 69

82 70

83 NC
NC 71

84 NC

85 72

86 73

87 74

88 NC

89 75

90 76

91 77

92 78

93 79

94 80

95 81

96 82

97 83

208

PQFP

Function

GND

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

TDI

I/O
I/O
I/O
I/O
I/O
I/O
I/O

GND

I/O

VCC

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

GND

I/O

VCC

I/O
I/O
I/O

GND

I/O
I/O
I/O
I/O

VCCIO

240

PQFP

98 84

99 85
100 86
101 87
102 88
103 89
104 90
105 91
106 92
107 NC
108 93
109 94
110 95

NC 96

111 97

NC 98

NC 99
112 100
113 NC
114 101
115 NC
116 102
117 NC
118 NC
119 103
120 104
121 105
122 NC
123 106
124 107
125 108
126 109
127 NC
128 110
129 111
130 112
131 113
132 114
133 115
134 116
135 117
136 NC
137 118
138 119
139 120
140 121
141 NC
142 122
143 123
144 124

208

PQFP

Function

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

GND

I/O

VCC

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

TRSTB

TMS

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

VCC

I/O

GND

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

QL4058 QuickRAM Data Sheet Rev H

240

PQFP

145 125
146 126
147 127
148 128
149 NC
150 129
151 130
152 131
153 132
154 133
155 134
156 135
157 136
158 NC
159 137
160 NC
161 138
162 139
163 140
164 141
165 142
166 NC
167 143
168 144
169 145
170 NC
171 146
172 147
173 148
174 149
175 150
176 151
177 152
178 153
179 154
180 155
NC 156
181 157
182 158
183 NC
184 159
185 160
186 161
187 162
188 163
189 164
190 165
191 166
192 NC
193 167

208

PQFP

Function

I/O
I/O

GND

I/O

I/O
GLCK/I
ACLK/I

VCC
GLCK/I
GLCK/I

VCC

I/O
I/O
I/O
I/O

GND

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

VCC

I/O
I/O

GND

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

TCK

STM

I/O
I/O
I/O
I/O
I/O

GND

I/O

VCC

I/O
I/O
I/O

240

PQFP

PQFP

194 168
195 169
196 NC
197 170
198 171
199 172
200 173
201 174
202 175
203 NC
204 176
205 177
206 178
207 179
208 NC
209 180
210 181
211 182
212 NC
213 183
214 184
215 185
216 186
217 187
218 188
219 NC
220 189
221 190
222 191
223 192
224 193
225 194
226 NC
227 195
228 196
229 197
230 198
231 NC
232 199
233 200
234 201
235 202
236 203
237 204
238 205
239 206
240 207

208

Function

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

GND

I/O
I/O
I/O
I/O

I/O
GND
VCC

I/O

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O
GND

I/O
VCC

I/O

I/O

I/O

I/O

I/O
TDO

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

17

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

208 and 240 PQFP Mechanical Drawing

•

•

www.quicklogic.com

•

18

•

•

•

Figure 13: 208 PQFP Mechanical Drawing

© 2002 QuickLogic Corporation

456 PBGA Pinout Diagram

QL4058-1PB456C

QL4058 QuickRAM Data Sheet Rev H

TOP View

QuickRAM

BOTTOM View

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W

Y
AA
AB
AC
AD
AE
AF

Figure 14: 456 PBGA Pinout Diagram

PIN A1
CORNER

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

19

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

456 PBGA Pinout Table

456 Function 456 Function 456 Function 456 Function 456 Function

A1
A2 I/O C2 I/O
A3 I/O C3 I/O
A4 I/O C4 TDO
A5 I/O C5 I/O
A6 I/O C6 I/O
A7 I/O C7 I/O
A8 I/O C8 I/O

A9 NC
A10 I/O
A11 I/O
A12 VCCIO
A13 I/O
A14 I/O
A15 NC
A16 I/O
A17 NC
A18 I/O
A19 I/O
A20 I/O
A21 NC
A22 I/O
A23 NC
A24 I/O
A25 I/O
A26 I/O

B1 I/O

B2 NC

B3 I/O

B4 NC

B5 NC

B6 NC

B7 NC

B8 NC

B9 I/O
B10 NC
B11 NC
B12 I/O
B13 I/O
B14 NC
B15 I/O
B16 I/O
B17 I/O
B18 I/O
B19 I/O
B20 I/O
B21 I/O
B22 I/O
B23 NC
B24 I/O
B25 I/O
B26 STM

I/O C1 I/O

C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25

TCK

C26

D1

D2

D3

D4

GND

D5

D6

D7

D8

D9

GND

D10
D11
D12

GND

D13
D14
D15

GND

D16
D17
D18

GND

D19
D20
D21
D22
D23

GND

D24
D25
D26

I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O

NC
I/O
I/O
I/O

NC
NC
I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O

I/O
NC
NC
I/O

I/O
I/O
I/O

Table 14: 456 PBGA Pinout Table

E1
E2
E3
E4
E5
E6
E7
E8

E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26

F1

F2

F3

F4

F5

F22
F23
F24
F25
F26

G1

G2

G3

G4

G5
G22
G23
G24
G25
G26

H1

H2

H3

H4

H5
H22

I/O
I/O
I/O
I/O

GND

VCC

GND

NC

GND

I/O
GND
GND

VCC
GND
GND
GND

NC

GND

NC

GND

VCC
GND

I/O
I/O
I/O
I/O
I/O
I/O
NC

NC
VCC
VCC

NC

I/O

I/O

I/O

I/O

I/O

I/O

I/O

NC

GND

NC

I/O

I/O

I/O

NC

I/O

NC

I/O

NC

NC

H23
H24
H25
H26

J1
J2
J3
J4

J5
J22
J23
J24
J25
J26

K1

K2

K3

K4

K5
K22
K23
K24
K25
K26

L1

L2

L3

L4

L5
L11
L12
L13
L14
L15
L16
L22
L23
L24
L25
L26

M1

M2

M3

M4

M5

M11
M12
M13
M14
M15
M16
M22

(Sheet 1 of 2)

NC
I/O
NC
I/O
I/O
I/O
I/O
NC

GND

NC
NC
I/O
I/O
I/O
NC
NC
I/O

I/O
VCC
GND

I/O

I/O

NC

I/O

I/O

I/O

I/O

I/O

NC

GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM

NC

I/O

I/O

NC

I/O

ACLK / I

GCLK/I

I/O

NC
GND

GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM

NC

M23
M24
M25
M26

N1
N2
N3
N4

N5
N11
N12
N13
N14
N15
N16
N22
N23
N24
N25
N26

P1

P2

P3

P4

P5
P11
P12
P13
P14
P15
P16
P22
P23
P24
P25
P26

R1

R2

R3

R4

R5
R11
R12
R13
R14
R15
R16
R22
R23
R24
R25
R26

NC
I/O
I/O
I/O

GCLK/I

I/O
I/O

GCLK/I

VCC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM

GND

I/O
I/O
NC
I/O
I/O
I/O
NC
I/O

NC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM

NC

GCLK / I
GCLK / I

NC

ACLK / I

NC

I/O

I/O

NC

NC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM

VCC

NC

NC

I/O

GCLK / I

•

•

www.quicklogic.com

•

20

•

•

•

© 2002 QuickLogic Corporation

QL4058 QuickRAM Data Sheet Rev H

Table 14: 456 PBGA Pinout Table (Continued)

456 Function 456 Function 456 Function 456 Function 456 Function

T1
T2
T3
T4

T5
T11
T12
T13
T14
T15
T16
T22
T23
T24
T25
T26

U1

U2

U3

U4

U5

U22
U23
U24
U25
U26

V1

V2

V3

V4

V5

V22
V23
V24
V25
V26

W1
W2
W3
W4

I/O
I/O
I/O
I/O

VCC
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM
GND/THERM

GND

I/O
I/O
NC
I/O
NC
I/O
I/O
I/O

GND

NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC

GND

NC
I/O
NC
I/O
I/O
I/O
I/O
I/O

W5
W22
W23
W24
W25
W26

Y1
Y2
Y3
Y4

Y5
Y22
Y23
Y24
Y25
Y26

AA1
AA2
AA3
AA4

AA5
AA22
AA23
AA24
AA25
AA26

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9
AB10
AB11
AB12
AB13
AB14

NC
NC
I/O
I/O
I/O
NC
NC
I/O
NC
I/O
I/O

GND

I/O
NC
I/O
I/O
I/O
I/O
NC

NC
VCC
VCC

NC

I/O

I/O

I/O

NC

I/O

I/O

I/O

GND

VCC

NC

NC

NC
VCC

GND

NC

I/O

GND

AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26

AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8

AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26

AD1

AD2

VCC

I/O
NC

VCC

GND

NC

VCC

GND

I/O
NC
I/O
I/O
I/O
I/O
NC

GND

NC
NC
NC
NC
NC
NC
I/O
NC
I/O

VCCIO

NC
NC
NC
NC
I/O
I/O
I/O
NC

GND

NC
I/O
I/O
I/O
NC

AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26

AE1

AE2

AE3

AE4

AE5

AE6

AE7

AE8

AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16

(Sheet 2 of 2)

I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O

TRSTB

NC
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26

AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8

AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26

I/O
I/O
I/O
I/O
I/O
NC
NC

TMS

I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
NC
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

21

•

•

•

•

QL4058 QuickRAM Data Sheet Rev H

456 PBGA Mechanical Drawing

•

•

www.quicklogic.com

•

22

•

•

•

Figure 15: 456 PBGA Mechanical Drawing

© 2002 QuickLogic Corporation

Contact Information

Telephone:[phone] (US)

416 497 8884 (Canada)

44 1932 57 9011 (Europe)

49 89 930 86 170 (Germany)

852 8106 9091 (Asia)

81 45 470 5525 (Japan)

E-mail: [e-mail]

Support:[e-mail]

Web site:http://www.quicklogic.com/

Revision History

Revision Date Comments

QL4058 QuickRAM Data Sheet Rev H

Table 15: Revision History

A not avail. First release.

B not avail.

C not avail.

D not avail.

E not avail.

F not avail.

G May 2000 Update of AC/DC Specs and reformat

H May 2002

Copyright Information

Copyright © 2002 QuickLogic Corporation.

All Rights Reserved.

The information contained in this product brief, and the accompanying software programs are pro­tected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation
reserves the right to make periodic modifications of this product without obligation to notify any per­son or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this
product without the prior written consent of an authorized representative of QuickLogic is prohib­ited.

Added Kfactor, Power-up, JTAG and mechanical

drawing information. Reformatted.

QuickLogic, pASIC, and ViaLink are registered trademarks, and SpDE and QuickWorks are trade­marks of QuickLogic Corporation.

Verilog is a registered trademark of Cadence Design Systems, Inc.

© 2002 QuickLogic Corporati on

www.quicklogic.com

•

•

23

•

•

•

•