-./012 ' 2
) # " " * " + " ,+ "
0.18 µm six layer metal CMOS Process
1.8/2.5/3.3 V Drive Capable I/O
960 Logic Cells
248,160 Max System Gates
Up to 250 I/O Pins
Twenty 2,304-bit Dual Port High Performance SRAM Blocks
46,100 RAM bits
RAM/ROM/FIFO Wizard for Automatic Configuration
Configurable and Cascadable
!
High performance Enhanced I/O (EIO)— less than 3 ns Tco
Programmable Slew Rate Control
Programmable I/O Standards:
LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3
Eight Independent I/O Banks
Three Register Configurations: Input, Output, and Output Enable
" #$% &$
Nine Global Clock Networks:
One Dedicated
Eight Programmable
20 Quad-Net Networks—five per Quadrant
16 I/O Controls—two per I/O Bank
Four phase locked loops
# ' " ("
10 ECUs provide integrated Multiply, Add, and Accumulate Functions.
PLL |
Embedded RAM Blocks |
PLL |
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10 Embeded Computational Units |
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Fabric |
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PLL |
Embedded RAM Blocks |
PLL |
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Preliminary
' * "
# # 3
*(at VCC = 2.5 V, TA = 25° C, Worst Case Corner, Speed Grade = -7 (K = 1.16))
The AC Specifications are provided from 4 to 4 1. Logic Cell diagrams and waveforms are provided from / to 0.
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tPD |
Combinatorial Delay of the longest path: time taken by the combinatorial circuit to |
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0.257 ns |
output |
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tSU |
Setup time: time the synchronous input of the flip-flop must be stable before the |
0.22 ns |
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active clock edge |
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tHL |
Hold time: time the synchronous input of the flip-flop must be stable after the active |
0 ns |
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clock edge |
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tCO |
Clock-to-out delay: the amount of time taken by the flip-flop to output after the |
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0.255 ns |
active clock edge. |
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tCWHI |
Clock High Time: required minimum time the clock stays high |
0.46 ns |
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tCWLO |
Clock Low Time: required minimum time that the clock stays low |
0.46 ns |
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tSET |
Set Delay: time between when the flip-flop is ”set” (high) |
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0.18 ns |
and when the output is consequently “set” (high) |
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/ Preliminary
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tRESET |
Reset Delay: time between when the flip-flop is ”reset” (low) and when the output |
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0.09 ns |
is consequently “reset” (low) |
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tSW |
Set Width: time that the SET signal remains high/low |
0.3 ns |
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tRW |
Reset Width: time that the RESET signal remains high/low |
0.3 ns |
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SET
D
Q
CLK
RESET
CLK
tCWHI (min) |
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RESET
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tRESET |
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tSET |
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tRW |
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tSW |
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! " #$%
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Preliminary |
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tSU |
tHL |
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Q
tCO
!& ' #$%
Quad net
( ) &" "
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Logic Cells (Internal) |
Clock signal generated internally |
1.51 ns (max) |
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Clock Pad |
Clock signal generated externally |
2.06 ns (max) |
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1.73 ns (max) |
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7 Preliminary
! "
#$" |
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a |
Global clock pin delay to quad net |
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1.34 ns |
tPGCK |
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tBGCK |
Global clock tree delay (quad net to |
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0.56 ns |
flip-flop) |
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#$% &%" ' (" ' ) ** + , ) -
%$
Programmable Clock |
Global Clock Buffer |
External Clock
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Global Clock |
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Clock |
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Select |
tPGCK |
tBGCK |
* ( ) &" " & + " |
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[9:0] |
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WA |
RE |
[17:0] |
RCLK |
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[9:0] |
WE |
RA |
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WCLK |
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ASYNCRD |
RAM Module |
,-./ / '
. /01 2 $) #)
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tSWA |
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the |
0.675 ns |
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active edge of the WRITE CLOCK |
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tHWA |
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active |
0 ns |
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edge of the WRITE CLOCK |
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tSWD |
WD setup time to WCLK: time the WRITE DATA must be stable before the active |
0.654 ns |
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edge of the WRITE CLOCK |
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Preliminary |
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. /01 2 $) #)
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tHWD |
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge |
0 ns |
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of the WRITE CLOCK |
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tSWE |
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active |
0.623 ns |
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edge of the WRITE CLOCK |
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tHWE |
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active |
0 ns |
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edge of the WRITE CLOCK |
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tWCRD |
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the |
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4.38 ns |
time when the data is available at RD |
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WCLK |
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WA |
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WD |
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tSWA |
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tHWA |
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WE |
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tSWD |
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tHWD |
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tSWE |
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tHWE |
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tWCRD |
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0-./ &1 + # " |
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3 /01 2 $) 4 0 $) / |
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# ," " 4 " |
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tSRA |
RA setup time to RCLK: time the READ ADDRESS must be stable before the active |
0.686 ns |
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edge of the READ CLOCK |
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tHRA |
RA hold time to RCLK: time the READ ADDRESS must be stable after the active |
0 ns |
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edge of the READ CLOCK |
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tSRE |
RE setup time to WCLK: time the READ ENABLE must be stable before the active |
0.243 ns |
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edge of the READ CLOCK |
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tHRE |
RE hold time to WCLK: time the READ ENABLE must be stable after the active |
0 ns |
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edge of the READ CLOCK |
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. |
Preliminary |
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3 /01 2 $) 4 0 $) / |
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# ," " 4 " |
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tRCRD |
RCLK to RD: time between the active READ CLOCK edge and the time when the |
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4.38 ns |
data is available at RD |
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# ," " 4 " |
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rPDRD |
RA to RD: time between when the READ ADDRESS is input and when the DATA |
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2.06 ns |
is output |
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RCLK
RA
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tSRA |
tHRA |
RE |
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tSRE |
tHRE |
RD |
old data |
new data |
tRCRD
rPDRD
-./ &1 + 2 . 1 + -'
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Preliminary |
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+ |
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INPUT |
Q E |
REGISTER |
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PAD |
OUTPUT |
Q |
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REGISTER |
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OUTPUT ENABLE |
E Q |
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REGISTER |
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345
tISU
+
-
tSID
Q E
D
R
PAD
3 "-"
9 Preliminary
5 6 / )
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5 |
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; "' # !" , |
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t |
Input register setup time: time the synchronous input of the flip-flop must be stable |
2.50 ns |
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ISU |
before the active clock edge |
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tIHL |
Input register hold time: time the synchronous input of the flip-flop must be stable |
0 ns |
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after the active clock edge |
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tICO |
Input register clock-to-out: time taken by the flip-flop to output after the active clock |
- |
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1.08 ns |
edge |
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tIRST |
Input register reset delay: time between when the flip-flop is “reset” (low) and when |
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0.99 ns |
the output is consequently “reset” (low) |
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tIESU |
Input register clock enable setup time: time “enable” must be stable before the |
0.37 ns |
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active clock edge |
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tIEH |
Input register clock enable hold time: time “enable” must be stable after the active |
0 ns |
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clock edge |
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7 2 ) 6
, |
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5 |
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" "' , |
4 "' , , ( |
" |
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tSID (LVTTL) |
LVTTL input delay: Low Voltage TTL for 3.3 V applications |
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0.34 ns |
tSID (LVCMOS2) |
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower |
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0.42 ns |
applications |
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tSID (LVCMOS18) |
LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications |
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tSID (GTL+) |
GTL+ input delay: Gunning Transceiver Logic |
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0.68 ns |
tSID (SSTL3) |
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V |
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0.55 ns |
tSID (SSTL2) |
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V |
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0.61 ns |
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Preliminary |
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R
CLK
D
tISU tIHL
Q |
tICO |
tIRST
E
tIESU tIEH
3 "-"
PAD
OUTPUT
REGISTER
5 " "-"
1 Preliminary
8 9 / )
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! ' # !" , |
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tOUTLH |
Output Delay low to high (90% of H) |
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tOUTHL |
Output Delay high to low (10% of L) |
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tPZH |
Output Delay tri-state to high (90% of H) |
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tPZL |
Output Delay tri-state to low (10% of L) |
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tPHZ |
Output Delay high to tri-State |
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tPLZ |
Output Delay low to tri-State |
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2.53 ns |
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tCOP |
Clock-to-out delay (does not include clock tree delays) |
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3.15 ns (fast slew) |
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10.2 ns (slow slew) |
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tOUTLH |
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tPLZ |
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5 " "-" |
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Rising Edge |
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2.8 V/ns |
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1.0 V/ns |
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Falling Edge |
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2.86 V/ns |
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> 9 2 / ; <69= 3 < |
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Rising Edge |
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1.7 V/ns |
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0.6 V/ns |
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Falling Edge |
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1.9 V/ns |
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0.6 V/ns |
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Preliminary |
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9 2 / ; <69= 8 <
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Rising Edge |
- V/ns |
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Falling Edge |
- V/ns |
- V/ns |
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/ Preliminary