-(.//0 *! . 1 *
02/// # ( 1 *! . 1 #
4,000 Usable PLD Gates with 82 I/Os
300 MHz 16-bit Counters,
400 MHz Datapaths
0.35 m four-layer metal non-volatile CMOS process for smallest die sizes
100% routable with 100% utilization and complete pin-out stability
Variable-grain logic cells provide high performance and 100% utilization
Comprehensive design tools include high quality Verilog/VHDL synthesis
' ( ) *+ ) #'
, ) +
Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin
Two global clock/control networks available to the logic cell; F1, clock, set and reset inputs and the data input, I/O register clock, reset and enable inputs as well as the output enable control — each driven by an inputonly or I/O pin, or any logic cell output or I/O cell feedback
Input + logic cell + output total delays under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
! " #
Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V buses for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled Registered Input Path and Output Enables
$%& ! "
74 bidirectional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for -1/-2/-3/-4 speed grades
Four High-Drive input-only pins
Four High-Drive/distributed network pins
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Preliminary
' " )
The QL3004E is a 4,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 m four-layer metal process using QuickLogic 's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.
The QL3004E contains 96 logic cells. With a maximum of 74 I/Os, the QL3004E is available 68-pin PLCC, 84-pin PLCC, and 100-pin TQFP packages.
Software support for the complete pASIC 3 family, including the QL3004E, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence , ExemplarTM, Mentor , Synopsys , Synplicity , ViewlogicTM, AldecTM, or other third-party tools for design entry, synthesis, or simulation.
& Preliminary
*
3 4 .5. 32$4 &6°78 4 5//9
To calculate delays, multiply the appropriate K factor from $# : by the numbers provided in $# through $# 6.
* # |
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7 9 ' |
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0 |
% |
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tPD |
Combinatorial Delay b |
1.4 |
1.7 |
1.9 |
2.2 |
3.2 |
tSU |
Setup Time b |
1.7 |
1.7 |
1.7 |
1.7 |
1.7 |
tH |
Hold Time |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
tCLK |
Clock to Q Delay |
0.7 |
1.0 |
1.2 |
1.5 |
2.5 |
tCWHI |
Clock High Time |
1.2 |
1.2 |
1.2 |
1.2 |
1.2 |
tCWLO |
Clock Low Time |
1.2 |
1.2 |
1.2 |
1.2 |
1.2 |
tSET |
Set Delay |
1.0 |
1.3 |
1.5 |
1.8 |
2.8 |
tRESET |
Reset Delay |
0.8 |
1.1 |
1.3 |
1.6 |
2.6 |
tSW |
Set Width |
1.9 |
1.9 |
1.9 |
1.9 |
1.9 |
tRW |
Reset Width |
1.8 |
1.8 |
1.8 |
1.8 |
1.8 |
! " # # !$" %&°' ( ) * +* * *
$# :
( ( ( ( ( (
$, #- ( (
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Preliminary |
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% , ./ 0
* # |
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% |
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&0 |
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tIN |
High Drive Input Delay |
1.5 |
1.6 |
1.8 |
1.9 |
2.4 |
2.9 |
4.4 |
tINI |
High Drive Input, Inverting Delay |
1.6 |
1.7 |
1.9 |
2.0 |
2.5 |
3.0 |
4.5 |
tISU |
Input Register Set-Up Time |
3.1 |
3.1 |
3.1 |
3.1 |
3.1 |
3.1 |
3.1 |
tIH |
Input Register Hold Time |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
tlCLK |
Input Register Clock To Q |
0.7 |
0.8 |
1.0 |
1.1 |
1.6 |
2.1 |
3.6 |
tlRST |
Input Register Reset Delay |
0.6 |
0.7 |
0.9 |
1.0 |
1.5 |
2.0 |
3.5 |
tlESU |
Input Register clock Enable Set-Up Time |
2.3 |
2.3 |
2.3 |
2.3 |
2.3 |
2.3 |
2.3 |
tlEH |
Input Register Clock Enable Hold Time |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
! " # # !$" %&°' ( ) * +* * *
$# :
#
* # |
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tACK |
Array Clock Delay |
1.2 |
1.2 |
1.3 |
1.3 |
1.5 |
1.6 |
1.7 |
tGCKP |
Global Clock Pin Delay |
0.7 |
0.7 |
0.7 |
0.7 |
0.7 |
0.7 |
0.7 |
tGCKB |
Global Clock Buffer Delay |
0.8 |
0.8 |
0.9 |
0.9 |
1.1 |
1.2 |
1.3 |
( %1 ( (
%2 ( * ( ( (
( ( ( ( (
( 3 (
0 Preliminary
1 , ./ ,0/
* # |
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tI/O |
Input Delay (bidirectional pad) |
1.3 |
1.6 |
1.8 |
2.1 |
3.1 |
3.6 |
tISU |
Input Register Set-Up Time |
3.1 |
3.1 |
3.1 |
3.1 |
3.1 |
3.1 |
tIH |
Input Register Hold Time |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
tlOCLK |
Input Register Clock To Q |
0.7 |
1.0 |
1.2 |
1.5 |
2.5 |
3.0 |
tlORST |
Input Register Reset Delay |
0.6 |
0.9 |
1.1 |
1.4 |
2.4 |
2.9 |
tlESU |
Input Register clock Enable Set-Up Time |
2.3 |
2.3 |
2.3 |
2.3 |
2.3 |
2.3 |
tlEH |
Input Register Clock Enable Hold Time |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
0.0 |
! " # # ! |
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$" %&°' ( ) * +* * * |
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$# : |
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tOUTLH |
Output Delay Low to High |
2.1 |
2.5 |
3.1 |
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3.6 |
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4.7 |
tOUTHL |
Output Delay High to Low |
2.2 |
2.6 |
3.2 |
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3.7 |
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4.8 |
tPZH |
Output Delay Tri-state to High |
1.2 |
1.7 |
2.2 |
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2.8 |
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3.9 |
tPZL |
Output Delay Tri-state to Low |
1.6 |
2.0 |
2.6 |
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3.1 |
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4.2 |
tPHZ |
Output Delay High to Tri-State a |
2.0 |
- |
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tPLZ |
Output Delay Low to Tri-State |
1.2 |
- |
- |
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(' & 45
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tPHZ |
1ΚΩ |
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1ΚΩ |
5 pF |
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tPLZ |
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5 pF |
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Preliminary |
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6 |
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The DC specifications are provided in $# ; through $# %.
6$' 7 8
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3 ' |
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VCC Voltage |
-0.5 V to 4.6 V |
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DC Input Current |
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±20 mA |
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VCCIO Voltage |
-0.5 V to 7.0 V |
ESD Pad Protection |
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±2000 V |
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Input Voltage |
-0.5 V to VCCIO +0.5 V |
Storage Temperature |
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-65°C to +150°C |
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Latch-up Immunity |
±200 mA |
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Lead Temperature |
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300°C |
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3 / 8 |
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* # |
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< |
< = |
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< = |
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< = |
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VCC |
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Supply Voltage |
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3.0 |
3.6 |
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3.0 |
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3.6 |
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3.0 |
3.6 |
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V |
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VCCIO |
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I/O Input Tolerance Voltage |
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3.0 |
5.5 |
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3.0 |
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5.5 |
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3.0 |
5.25 |
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V |
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TA |
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Ambient Temperature |
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-55 |
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-40 |
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85 |
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0 |
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70 |
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°C |
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TC |
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Case Temperature |
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- |
125 |
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°C |
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-0 Speed Grade |
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- |
- |
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0.43 |
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1.90 |
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0.46 |
1.85 |
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n/a |
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-1 Speed Grade |
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0.42 |
1.64 |
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0.43 |
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1.54 |
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0.46 |
1.50 |
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n/a |
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K |
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Delay Factor |
-2 Speed Grade |
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0.42 |
1.37 |
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0.43 |
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1.28 |
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0.46 |
1.25 |
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n/a |
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-3 Speed Grade |
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0.43 |
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0.90 |
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0.46 |
0.88 |
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n/a |
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-4 Speed Grade |
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0.43 |
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0.82 |
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0.46 |
0.80 |
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n/a |
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; Preliminary